amrreg.h revision 153409
1/*- 2 * Copyright (c) 1999,2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Copyright (c) 2002 Eric Moore 28 * Copyright (c) 2002 LSI Logic Corporation 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The party using or redistributing the source code and binary forms 40 * agrees to the disclaimer below and the terms and conditions set forth 41 * herein. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 44 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 46 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 47 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 49 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 * 55 * 56 * $FreeBSD: head/sys/dev/amr/amrreg.h 153409 2005-12-14 03:26:49Z scottl $ 57 */ 58 59/******************************************************************************** 60 ******************************************************************************** 61 Driver parameters 62 ******************************************************************************** 63 ********************************************************************************/ 64 65/* 66 * We could actually use all 17 segments, but using only 16 means that 67 * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 68 * maps crossing page boundaries. 69 * 70 * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 71 * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 72 * since we allocate the s/g maps contiguously anyway? 73 */ 74/* 75 * emoore - Oct 21, 2002 76 * firmware doesn't have sglist boundary restrictions. 77 * The sgelem can be set to 26 78 */ 79#define AMR_NSEG 26 80 81#define AMR_MAXCMD 255 /* ident = 0 not allowed */ 82#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 83#define AMR_MAXLD 40 84 85#define AMR_MAX_CHANNELS 8 86#define AMR_MAX_TARGETS 15 87#define AMR_MAX_LUNS 7 88#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 89 90#define AMR_MAX_CDB_LEN 0x0a 91#define AMR_MAX_EXTCDB_LEN 0x10 92#define AMR_MAX_REQ_SENSE_LEN 0x20 93 94#define AMR_BLKSIZE 512 /* constant for all controllers */ 95 96/* 97 * Perform at-startup board initialisation. 98 * At this point in time, this code doesn't work correctly, so leave it disabled. 99 */ 100/*#define AMR_BOARD_INIT*/ 101 102/******************************************************************************** 103 ******************************************************************************** 104 Interface Magic Numbers 105 ******************************************************************************** 106 ********************************************************************************/ 107 108/* 109 * Mailbox commands 110 */ 111#define AMR_CMD_LREAD 0x01 112#define AMR_CMD_LWRITE 0x02 113#define AMR_CMD_PASS 0x03 114#define AMR_CMD_EXT_ENQUIRY 0x04 115#define AMR_CMD_ENQUIRY 0x05 116#define AMR_CMD_FLUSH 0x0a 117#define AMR_CMD_EXT_ENQUIRY2 0x0c 118#define AMR_CONFIG_PRODINFO 0x0e 119#define AMR_CMD_GET_MACHINEID 0x36 120#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 121#define AMR_CMD_CONFIG 0xa1 122#define AMR_CMD_LREAD64 0xa7 123#define AMR_CMD_LWRITE64 0xa8 124#define AMR_CMD_PASS_64 0xc3 125#define AMR_CMD_EXTPASS 0xe3 126 127#define AMR_CONFIG_READ_NVRAM_CONFIG 0x04 128#define AMR_CONFIG_WRITE_NVRAM_CONFIG 0x0d 129#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 130#define AMR_CONFIG_PRODUCT_INFO 0x0e 131#define AMR_CONFIG_ENQ3 0x0f 132#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 133#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 134#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 135 136/* 137 * Command for random deletion of logical drives 138 */ 139#define FC_DEL_LOGDRV 0xA4 140#define OP_SUP_DEL_LOGDRV 0x2A 141#define OP_GET_LDID_MAP 0x18 142#define OP_DEL_LOGDRV 0x1C 143 144/* 145 * Command results 146 */ 147#define AMR_STATUS_SUCCESS 0x00 148#define AMR_STATUS_ABORTED 0x02 149#define AMR_STATUS_FAILED 0x80 150 151/* 152 * Physical/logical drive states 153 */ 154#define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 155#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 156#define AMR_DRV_OFFLINE 0x00 157#define AMR_DRV_DEGRADED 0x01 158#define AMR_DRV_OPTIMAL 0x02 159#define AMR_DRV_ONLINE 0x03 160#define AMR_DRV_FAILED 0x04 161#define AMR_DRV_REBUILD 0x05 162#define AMR_DRV_HOTSPARE 0x06 163 164/* 165 * Logical drive properties 166 */ 167#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 168#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 169#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 170#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 171 172/* 173 * Battery status 174 */ 175#define AMR_BATT_MODULE_MISSING 0x01 176#define AMR_BATT_LOW_VOLTAGE 0x02 177#define AMR_BATT_TEMP_HIGH 0x04 178#define AMR_BATT_PACK_MISSING 0x08 179#define AMR_BATT_CHARGE_MASK 0x30 180#define AMR_BATT_CHARGE_DONE 0x00 181#define AMR_BATT_CHARGE_INPROG 0x10 182#define AMR_BATT_CHARGE_FAIL 0x20 183#define AMR_BATT_CYCLES_EXCEEDED 0x40 184 185 186/******************************************************************************** 187 ******************************************************************************** 188 8LD Firmware Interface 189 ******************************************************************************** 190 ********************************************************************************/ 191 192/* 193 * Array constraints 194 */ 195#define AMR_8LD_MAXDRIVES 8 196#define AMR_8LD_MAXCHAN 5 197#define AMR_8LD_MAXTARG 15 198#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 199 200/* 201 * Adapter Info structure 202 */ 203struct amr_adapter_info 204{ 205 u_int8_t aa_maxio; 206 u_int8_t aa_rebuild_rate; 207 u_int8_t aa_maxtargchan; 208 u_int8_t aa_channels; 209 u_int8_t aa_firmware[4]; 210 u_int16_t aa_flashage; 211 u_int8_t aa_chipsetvalue; 212 u_int8_t aa_memorysize; 213 u_int8_t aa_cacheflush; 214 u_int8_t aa_bios[4]; 215 u_int8_t aa_boardtype; 216 u_int8_t aa_scsisensealert; 217 u_int8_t aa_writeconfigcount; 218 u_int8_t aa_driveinsertioncount; 219 u_int8_t aa_inserteddrive; 220 u_int8_t aa_batterystatus; 221 u_int8_t res1; 222} __packed; 223 224/* 225 * Logical Drive info structure 226 */ 227struct amr_logdrive_info 228{ 229 u_int8_t al_numdrives; 230 u_int8_t res1[3]; 231 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 232 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 233 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 234} __packed; 235 236/* 237 * Physical Drive info structure 238 */ 239struct amr_physdrive_info 240{ 241 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 242 u_int8_t ap_predictivefailure; 243} __packed; 244 245/* 246 * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 247 * AMR_CMD_EXT_ENQUIRY2. 248 * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 249 */ 250struct amr_enquiry 251{ 252 struct amr_adapter_info ae_adapter; /* X X X */ 253 struct amr_logdrive_info ae_ldrv; /* X X X */ 254 struct amr_physdrive_info ae_pdrv; /* X X X */ 255 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 256 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 257 u_int32_t ae_extlen; /* X */ 258 u_int16_t ae_subsystem; /* X */ 259 u_int16_t ae_subvendor; /* X */ 260 u_int32_t ae_signature; /* X */ 261#define AMR_SIG_431 0xfffe0001 262#define AMR_SIG_438 0xfffd0002 263#define AMR_SIG_762 0xfffc0003 264#define AMR_SIG_T5 0xfffb0004 265#define AMR_SIG_466 0xfffa0005 266#define AMR_SIG_467 0xfff90006 267#define AMR_SIG_T7 0xfff80007 268#define AMR_SIG_490 0xfff70008 269 u_int8_t res2[844]; /* X */ 270} __packed; 271 272 273/******************************************************************************** 274 ******************************************************************************** 275 40LD Firmware Interface 276 ******************************************************************************** 277 ********************************************************************************/ 278 279/* 280 * Array constraints 281 */ 282#define AMR_40LD_MAXDRIVES 40 283#define AMR_40LD_MAXCHAN 16 284#define AMR_40LD_MAXTARG 16 285#define AMR_40LD_MAXPHYSDRIVES 256 286 287/* 288 * Product Info structure 289 */ 290struct amr_prodinfo 291{ 292 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 293 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 294 * logical drives, 0x20 maximum stripes and 0x08 295 * maximum spans */ 296 u_int8_t ap_firmware[16]; /* printable identifiers */ 297 u_int8_t ap_bios[16]; 298 u_int8_t ap_product[80]; 299 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 300 u_int8_t ap_nschan; /* number of SCSI channels present */ 301 u_int8_t ap_fcloops; /* number of fibre loops present */ 302 u_int8_t ap_memtype; /* memory type */ 303 u_int32_t ap_signature; 304 u_int16_t ap_memsize; /* onboard memory in MB */ 305 u_int16_t ap_subsystem; /* subsystem identifier */ 306 u_int16_t ap_subvendor; /* subsystem vendor ID */ 307 u_int8_t ap_numnotifyctr; /* number of notify counters */ 308} __packed; 309 310/* 311 * Notify structure 312 */ 313struct amr_notify 314{ 315 u_int32_t an_globalcounter; /* change counter */ 316 317 u_int8_t an_paramcounter; /* parameter change counter */ 318 u_int8_t an_paramid; 319#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 320#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 321#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 322#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 323#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 324 u_int16_t an_paramval; 325 326 u_int8_t an_writeconfigcounter; /* write config occurred */ 327 u_int8_t res1[3]; 328 329 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 330 u_int8_t an_ldrvopid; 331 u_int8_t an_ldrvopcmd; 332#define AMR_LDRVOP_CHECK 0x01 333#define AMR_LDRVOP_INIT 0x02 334#define AMR_LDRVOP_REBUILD 0x03 335 u_int8_t an_ldrvopstatus; 336#define AMR_LDRVOP_SUCCESS 0x00 337#define AMR_LDRVOP_FAILED 0x01 338#define AMR_LDRVOP_ABORTED 0x02 339#define AMR_LDRVOP_CORRECTED 0x03 340#define AMR_LDRVOP_STARTED 0x04 341 342 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 343 u_int8_t an_ldrvstateid; 344 u_int8_t an_ldrvstatenew; 345 u_int8_t an_ldrvstateold; 346 347 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 348 u_int8_t an_pdrvstateid; 349 u_int8_t an_pdrvstatenew; 350 u_int8_t an_pdrvstateold; 351 352 u_int8_t an_pdrvfmtcounter; 353 u_int8_t an_pdrvfmtid; 354 u_int8_t an_pdrvfmtval; 355#define AMR_FORMAT_START 0x01 356#define AMR_FORMAT_COMPLETE 0x02 357 u_int8_t res2; 358 359 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 360 u_int8_t an_targxferid; 361 u_int8_t an_targxferval; 362 u_int8_t res3; 363 364 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 365 u_int8_t an_fcloopidpdrvid; 366 u_int8_t an_fcloopid0; 367 u_int8_t an_fcloopid1; 368 369 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 370 u_int8_t an_fcloopstate0; 371 u_int8_t an_fcloopstate1; 372 u_int8_t res4; 373} __packed; 374 375/* 376 * Enquiry3 structure 377 */ 378struct amr_enquiry3 379{ 380 u_int32_t ae_datasize; /* valid data size in this structure */ 381 union { /* event notify structure */ 382 struct amr_notify n; 383 u_int8_t pad[0x80]; 384 } ae_notify; 385 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 386 u_int8_t ae_cacheflush; /* flush interval in seconds */ 387 u_int8_t ae_sensealert; 388 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 389 u_int8_t ae_batterystatus; 390 u_int8_t ae_numldrives; 391 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 392 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 393 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 394 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 395 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 396 u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES]; 397 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 398 399 u_int8_t res1[263]; /* pad to 1024 bytes */ 400} __packed; 401 402 403/******************************************************************************** 404 ******************************************************************************** 405 Mailbox and Command Structures 406 ******************************************************************************** 407 ********************************************************************************/ 408 409#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 410 411struct amr_mailbox 412{ 413 u_int8_t mb_command; 414 u_int8_t mb_ident; 415 u_int16_t mb_blkcount; /* u_int8_t opcode */ 416 /* u_int8_t subopcode */ 417 u_int32_t mb_lba; 418 u_int32_t mb_physaddr; 419 u_int8_t mb_drive; 420 u_int8_t mb_nsgelem; /* u_int8_t rserv[0] */ 421 u_int8_t res1; /* u_int8_t rserv[1] */ 422 u_int8_t mb_busy; /* u_int8_t rserv[2] */ 423 u_int8_t mb_nstatus; 424 u_int8_t mb_status; 425 u_int8_t mb_completed[46]; 426 u_int8_t mb_poll; 427 u_int8_t mb_ack; 428 u_int8_t res2[16]; 429} __packed; 430 431struct amr_mailbox64 432{ 433 u_int8_t pad[8]; /* Needed for alignment */ 434 u_int32_t sg64_lo; /* S/G pointer for 64-bit commands */ 435 u_int32_t sg64_hi; /* S/G pointer for 64-bit commands */ 436 struct amr_mailbox mb; 437} __packed; 438 439struct amr_mailbox_ioctl 440{ 441 u_int8_t mb_command; 442 u_int8_t mb_ident; 443 u_int8_t mb_channel; 444 u_int8_t mb_param; 445 u_int8_t mb_pad[4]; 446 u_int32_t mb_physaddr; 447 u_int8_t mb_drive; 448 u_int8_t mb_nsgelem; 449 u_int8_t res1; 450 u_int8_t mb_busy; 451 u_int8_t mb_nstatus; 452 u_int8_t mb_completed[46]; 453 u_int8_t mb_poll; 454 u_int8_t mb_ack; 455 u_int8_t res4[16]; 456} __packed; 457 458struct amr_sgentry 459{ 460 u_int32_t sg_addr; 461 u_int32_t sg_count; 462} __packed; 463 464struct amr_sg64entry 465{ 466 u_int64_t sg_addr; 467 u_int32_t sg_count; 468} __packed; 469 470struct amr_passthrough 471{ 472 u_int8_t ap_timeout:3; 473 u_int8_t ap_ars:1; 474 u_int8_t ap_dummy:3; 475 u_int8_t ap_islogical:1; 476 u_int8_t ap_logical_drive_no; 477 u_int8_t ap_channel; 478 u_int8_t ap_scsi_id; 479 u_int8_t ap_queue_tag; 480 u_int8_t ap_queue_action; 481 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 482 u_int8_t ap_cdb_length; 483 u_int8_t ap_request_sense_length; 484 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 485 u_int8_t ap_no_sg_elements; 486 u_int8_t ap_scsi_status; 487 u_int32_t ap_data_transfer_address; 488 u_int32_t ap_data_transfer_length; 489} __packed; 490 491struct amr_ext_passthrough 492{ 493 u_int8_t ap_timeout:3; 494 u_int8_t ap_ars:1; 495 u_int8_t ap_rsvd1:1; 496 u_int8_t ap_cd_rom:1; 497 u_int8_t ap_rsvd2:1; 498 u_int8_t ap_islogical:1; 499 u_int8_t ap_logical_drive_no; 500 u_int8_t ap_channel; 501 u_int8_t ap_scsi_id; 502 u_int8_t ap_queue_tag; 503 u_int8_t ap_queue_action; 504 u_int8_t ap_cdb_length; 505 u_int8_t ap_rsvd3; 506 u_int8_t ap_cdb[AMR_MAX_EXTCDB_LEN]; 507 u_int8_t ap_no_sg_elements; 508 u_int8_t ap_scsi_status; 509 u_int8_t ap_request_sense_length; 510 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 511 u_int8_t ap_rsvd4; 512 u_int32_t ap_data_transfer_address; 513 u_int32_t ap_data_transfer_length; 514} __packed; 515 516struct amr_linux_ioctl { 517 u_int32_t inlen; 518 u_int32_t outlen; 519 union { 520 u_int8_t fca[16]; 521 struct { 522 u_int8_t opcode; 523 u_int8_t subopcode; 524 u_int16_t adapno; 525 u_int32_t buffer; 526 u_int8_t pad[4]; 527 u_int32_t length; 528 } __packed fcs; 529 } __packed ui; 530 u_int8_t mbox[18]; 531 struct amr_passthrough pthru; 532 u_int32_t data; 533 u_int8_t pad[4]; 534} __packed; 535 536#ifdef _KERNEL 537/******************************************************************************** 538 ******************************************************************************** 539 "Quartz" i960 PCI bridge interface 540 ******************************************************************************** 541 ********************************************************************************/ 542 543#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 544#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 545#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 546 547/* 548 * Doorbell registers 549 */ 550#define AMR_QIDB 0x20 551#define AMR_QODB 0x2c 552#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 553#define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 554#define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 555 556/* 557 * Initialisation status 558 */ 559#define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 560#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 561#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 562#define AMR_QINIT_INPROG 0xdc /* init in progress */ 563#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 564#define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 565#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 566#define AMR_QINIT_DONE 0x9c /* init successfully done */ 567 568/* 569 * I/O primitives 570 */ 571#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 572#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 573#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 574#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 575 576#ifdef AMR_BOARD_INIT 577#define AMR_QRESET(sc) \ 578 do { \ 579 pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 580 pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 581 } while (0) 582#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 583#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 584#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 585#endif 586 587/******************************************************************************** 588 ******************************************************************************** 589 "Standard" old-style ASIC bridge interface 590 ******************************************************************************** 591 ********************************************************************************/ 592 593/* 594 * I/O registers 595 */ 596#define AMR_SCMD 0x10 /* command/ack register (write) */ 597#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 598#define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 599#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 600#define AMR_SMBOX_1 0x15 601#define AMR_SMBOX_2 0x16 602#define AMR_SMBOX_3 0x17 /* high byte */ 603#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 604#define AMR_SINTR 0x1a /* interrupt status */ 605 606/* 607 * I/O magic numbers 608 */ 609#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 610#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 611#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 612#define AMR_SINTR_VALID 0x40 /* in SINTR */ 613#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 614#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 615 616/* 617 * Initialisation status 618 */ 619#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 620#define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 621#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 622#define AMR_SINIT_INPROG 0x11 /* init in progress */ 623#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 624#define AMR_SINIT_DONE 0x99 /* init successfully done */ 625 626/* 627 * I/O primitives 628 */ 629#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 630#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 631#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 632#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 633#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 634#define AMR_SENABLE_INTR(sc) \ 635 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 636 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 637#define AMR_SDISABLE_INTR(sc) \ 638 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 639 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 640#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 641 642#ifdef AMR_BOARD_INIT 643#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 644#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 645#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 646#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 647#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 648#endif 649 650#endif /* _KERNEL */ 651