amrreg.h revision 105419
1/*- 2 * Copyright (c) 1999,2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * 3. The party using or redistributing the source code and binary forms 28 * agrees to the above disclaimer and the terms and conditions set forth 29 * herein. 30 * 31 * Additional Copyright (c) 2002 by Eric Moore under same license. 32 * Additional Copyright (c) 2002 LSI Logic Corporation 33 * 34 * $FreeBSD: head/sys/dev/amr/amrreg.h 105419 2002-10-18 21:29:14Z emoore $ 35 */ 36 37/******************************************************************************** 38 ******************************************************************************** 39 Driver parameters 40 ******************************************************************************** 41 ********************************************************************************/ 42 43/* 44 * We could actually use all 17 segments, but using only 16 means that 45 * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 46 * maps crossing page boundaries. 47 * 48 * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 49 * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 50 * since we allocate the s/g maps contiguously anyway? 51 */ 52#define AMR_NSEG 16 53 54#define AMR_MAXCMD 255 /* ident = 0 not allowed */ 55#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 56#define AMR_MAXLD 40 57 58#define AMR_MAX_CHANNELS 4 59#define AMR_MAX_TARGETS 15 60#define AMR_MAX_LUNS 7 61#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 62 63#define AMR_MAX_CDB_LEN 0x0a 64#define AMR_MAX_REQ_SENSE_LEN 0x20 65 66#define AMR_BLKSIZE 512 /* constant for all controllers */ 67 68/* 69 * Perform at-startup board initialisation. 70 * At this point in time, this code doesn't work correctly, so leave it disabled. 71 */ 72/*#define AMR_BOARD_INIT*/ 73 74/******************************************************************************** 75 ******************************************************************************** 76 Interface Magic Numbers 77 ******************************************************************************** 78 ********************************************************************************/ 79 80/* 81 * Mailbox commands 82 */ 83#define AMR_CMD_LREAD 0x01 84#define AMR_CMD_LWRITE 0x02 85#define AMR_CMD_PASS 0x03 86#define AMR_CMD_EXT_ENQUIRY 0x04 87#define AMR_CMD_ENQUIRY 0x05 88#define AMR_CMD_FLUSH 0x0a 89#define AMR_CMD_EXT_ENQUIRY2 0x0c 90#define AMR_CONFIG_PRODINFO 0x0e 91#define AMR_CMD_GET_MACHINEID 0x36 92#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 93#define AMR_CMD_CONFIG 0xa1 94#define AMR_CONFIG_PRODUCT_INFO 0x0e 95#define AMR_CONFIG_ENQ3 0x0f 96#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 97#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 98#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 99 100/* 101 * Command results 102 */ 103#define AMR_STATUS_SUCCESS 0x00 104#define AMR_STATUS_ABORTED 0x02 105#define AMR_STATUS_FAILED 0x80 106 107/* 108 * Physical/logical drive states 109 */ 110#define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 111#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 112#define AMR_DRV_OFFLINE 0x00 113#define AMR_DRV_DEGRADED 0x01 114#define AMR_DRV_OPTIMAL 0x02 115#define AMR_DRV_ONLINE 0x03 116#define AMR_DRV_FAILED 0x04 117#define AMR_DRV_REBUILD 0x05 118#define AMR_DRV_HOTSPARE 0x06 119 120/* 121 * Logical drive properties 122 */ 123#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 124#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 125#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 126#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 127 128/* 129 * Battery status 130 */ 131#define AMR_BATT_MODULE_MISSING 0x01 132#define AMR_BATT_LOW_VOLTAGE 0x02 133#define AMR_BATT_TEMP_HIGH 0x04 134#define AMR_BATT_PACK_MISSING 0x08 135#define AMR_BATT_CHARGE_MASK 0x30 136#define AMR_BATT_CHARGE_DONE 0x00 137#define AMR_BATT_CHARGE_INPROG 0x10 138#define AMR_BATT_CHARGE_FAIL 0x20 139#define AMR_BATT_CYCLES_EXCEEDED 0x40 140 141 142/******************************************************************************** 143 ******************************************************************************** 144 8LD Firmware Interface 145 ******************************************************************************** 146 ********************************************************************************/ 147 148/* 149 * Array constraints 150 */ 151#define AMR_8LD_MAXDRIVES 8 152#define AMR_8LD_MAXCHAN 5 153#define AMR_8LD_MAXTARG 15 154#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 155 156/* 157 * Adapter Info structure 158 */ 159struct amr_adapter_info 160{ 161 u_int8_t aa_maxio; 162 u_int8_t aa_rebuild_rate; 163 u_int8_t aa_maxtargchan; 164 u_int8_t aa_channels; 165 u_int8_t aa_firmware[4]; 166 u_int16_t aa_flashage; 167 u_int8_t aa_chipsetvalue; 168 u_int8_t aa_memorysize; 169 u_int8_t aa_cacheflush; 170 u_int8_t aa_bios[4]; 171 u_int8_t aa_boardtype; 172 u_int8_t aa_scsisensealert; 173 u_int8_t aa_writeconfigcount; 174 u_int8_t aa_driveinsertioncount; 175 u_int8_t aa_inserteddrive; 176 u_int8_t aa_batterystatus; 177 u_int8_t res1; 178} __packed; 179 180/* 181 * Logical Drive info structure 182 */ 183struct amr_logdrive_info 184{ 185 u_int8_t al_numdrives; 186 u_int8_t res1[3]; 187 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 188 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 189 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 190} __packed; 191 192/* 193 * Physical Drive info structure 194 */ 195struct amr_physdrive_info 196{ 197 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 198 u_int8_t ap_predictivefailure; 199} __packed; 200 201/* 202 * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 203 * AMR_CMD_EXT_ENQUIRY2. 204 * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 205 */ 206struct amr_enquiry 207{ 208 struct amr_adapter_info ae_adapter; /* X X X */ 209 struct amr_logdrive_info ae_ldrv; /* X X X */ 210 struct amr_physdrive_info ae_pdrv; /* X X X */ 211 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 212 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 213 u_int32_t ae_extlen; /* X */ 214 u_int16_t ae_subsystem; /* X */ 215 u_int16_t ae_subvendor; /* X */ 216 u_int32_t ae_signature; /* X */ 217#define AMR_SIG_431 0xfffe0001 218#define AMR_SIG_438 0xfffd0002 219#define AMR_SIG_762 0xfffc0003 220#define AMR_SIG_T5 0xfffb0004 221#define AMR_SIG_466 0xfffa0005 222#define AMR_SIG_467 0xfff90006 223#define AMR_SIG_T7 0xfff80007 224#define AMR_SIG_490 0xfff70008 225 u_int8_t res2[844]; /* X */ 226} __packed; 227 228 229/******************************************************************************** 230 ******************************************************************************** 231 40LD Firmware Interface 232 ******************************************************************************** 233 ********************************************************************************/ 234 235/* 236 * Array constraints 237 */ 238#define AMR_40LD_MAXDRIVES 40 239#define AMR_40LD_MAXCHAN 16 240#define AMR_40LD_MAXTARG 16 241#define AMR_40LD_MAXPHYSDRIVES 256 242 243/* 244 * Product Info structure 245 */ 246struct amr_prodinfo 247{ 248 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 249 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 250 * logical drives, 0x20 maximum stripes and 0x08 251 * maximum spans */ 252 u_int8_t ap_firmware[16]; /* printable identifiers */ 253 u_int8_t ap_bios[16]; 254 u_int8_t ap_product[80]; 255 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 256 u_int8_t ap_nschan; /* number of SCSI channels present */ 257 u_int8_t ap_fcloops; /* number of fibre loops present */ 258 u_int8_t ap_memtype; /* memory type */ 259 u_int32_t ap_signature; 260 u_int16_t ap_memsize; /* onboard memory in MB */ 261 u_int16_t ap_subsystem; /* subsystem identifier */ 262 u_int16_t ap_subvendor; /* subsystem vendor ID */ 263 u_int8_t ap_numnotifyctr; /* number of notify counters */ 264} __packed; 265 266/* 267 * Notify structure 268 */ 269struct amr_notify 270{ 271 u_int32_t an_globalcounter; /* change counter */ 272 273 u_int8_t an_paramcounter; /* parameter change counter */ 274 u_int8_t an_paramid; 275#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 276#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 277#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 278#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 279#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 280 u_int16_t an_paramval; 281 282 u_int8_t an_writeconfigcounter; /* write config occurred */ 283 u_int8_t res1[3]; 284 285 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 286 u_int8_t an_ldrvopid; 287 u_int8_t an_ldrvopcmd; 288#define AMR_LDRVOP_CHECK 0x01 289#define AMR_LDRVOP_INIT 0x02 290#define AMR_LDRVOP_REBUILD 0x03 291 u_int8_t an_ldrvopstatus; 292#define AMR_LDRVOP_SUCCESS 0x00 293#define AMR_LDRVOP_FAILED 0x01 294#define AMR_LDRVOP_ABORTED 0x02 295#define AMR_LDRVOP_CORRECTED 0x03 296#define AMR_LDRVOP_STARTED 0x04 297 298 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 299 u_int8_t an_ldrvstateid; 300 u_int8_t an_ldrvstatenew; 301 u_int8_t an_ldrvstateold; 302 303 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 304 u_int8_t an_pdrvstateid; 305 u_int8_t an_pdrvstatenew; 306 u_int8_t an_pdrvstateold; 307 308 u_int8_t an_pdrvfmtcounter; 309 u_int8_t an_pdrvfmtid; 310 u_int8_t an_pdrvfmtval; 311#define AMR_FORMAT_START 0x01 312#define AMR_FORMAT_COMPLETE 0x02 313 u_int8_t res2; 314 315 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 316 u_int8_t an_targxferid; 317 u_int8_t an_targxferval; 318 u_int8_t res3; 319 320 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 321 u_int8_t an_fcloopidpdrvid; 322 u_int8_t an_fcloopid0; 323 u_int8_t an_fcloopid1; 324 325 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 326 u_int8_t an_fcloopstate0; 327 u_int8_t an_fcloopstate1; 328 u_int8_t res4; 329} __packed; 330 331/* 332 * Enquiry3 structure 333 */ 334struct amr_enquiry3 335{ 336 u_int32_t ae_datasize; /* valid data size in this structure */ 337 union { /* event notify structure */ 338 struct amr_notify n; 339 u_int8_t pad[0x80]; 340 } ae_notify; 341 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 342 u_int8_t ae_cacheflush; /* flush interval in seconds */ 343 u_int8_t ae_sensealert; 344 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 345 u_int8_t ae_batterystatus; 346 u_int8_t ae_numldrives; 347 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 348 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 349 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 350 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 351 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 352 u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES]; 353 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 354 355 u_int8_t res1[263]; /* pad to 1024 bytes */ 356} __packed; 357 358 359/******************************************************************************** 360 ******************************************************************************** 361 Mailbox and Command Structures 362 ******************************************************************************** 363 ********************************************************************************/ 364 365#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 366 367struct amr_mailbox 368{ 369 u_int8_t mb_command; 370 u_int8_t mb_ident; 371 u_int16_t mb_blkcount; 372 u_int32_t mb_lba; 373 u_int32_t mb_physaddr; 374 u_int8_t mb_drive; 375 u_int8_t mb_nsgelem; 376 u_int8_t res1; 377 u_int8_t mb_busy; 378 u_int8_t mb_nstatus; 379 u_int8_t mb_status; 380 u_int8_t mb_completed[46]; 381 u_int8_t mb_poll; 382 u_int8_t mb_ack; 383 u_int8_t res2[16]; 384} __packed; 385 386struct amr_mailbox64 387{ 388 u_int32_t mb64_segment; /* for 64-bit controllers */ 389 struct amr_mailbox mb; 390} __packed; 391 392struct amr_mailbox_ioctl 393{ 394 u_int8_t mb_command; 395 u_int8_t mb_ident; 396 u_int8_t mb_channel; 397 u_int8_t mb_param; 398 u_int8_t mb_pad[4]; 399 u_int32_t mb_physaddr; 400 u_int8_t mb_drive; 401 u_int8_t mb_nsgelem; 402 u_int8_t res1; 403 u_int8_t mb_busy; 404 u_int8_t mb_nstatus; 405 u_int8_t mb_completed[46]; 406 u_int8_t mb_poll; 407 u_int8_t mb_ack; 408 u_int8_t res4[16]; 409} __packed; 410 411struct amr_sgentry 412{ 413 u_int32_t sg_addr; 414 u_int32_t sg_count; 415} __packed; 416 417struct amr_passthrough 418{ 419 u_int8_t ap_timeout:3; 420 u_int8_t ap_ars:1; 421 u_int8_t ap_dummy:3; 422 u_int8_t ap_islogical:1; 423 u_int8_t ap_logical_drive_no; 424 u_int8_t ap_channel; 425 u_int8_t ap_scsi_id; 426 u_int8_t ap_queue_tag; 427 u_int8_t ap_queue_action; 428 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 429 u_int8_t ap_cdb_length; 430 u_int8_t ap_request_sense_length; 431 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 432 u_int8_t ap_no_sg_elements; 433 u_int8_t ap_scsi_status; 434 u_int32_t ap_data_transfer_address; 435 u_int32_t ap_data_transfer_length; 436} __packed; 437 438#ifdef _KERNEL 439/******************************************************************************** 440 ******************************************************************************** 441 "Quartz" i960 PCI bridge interface 442 ******************************************************************************** 443 ********************************************************************************/ 444 445#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 446#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 447#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 448 449/* 450 * Doorbell registers 451 */ 452#define AMR_QIDB 0x20 453#define AMR_QODB 0x2c 454#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 455#define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 456#define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 457 458/* 459 * Initialisation status 460 */ 461#define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 462#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 463#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 464#define AMR_QINIT_INPROG 0xdc /* init in progress */ 465#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 466#define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 467#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 468#define AMR_QINIT_DONE 0x9c /* init successfully done */ 469 470/* 471 * I/O primitives 472 */ 473#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 474#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 475#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 476#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 477 478#ifdef AMR_BOARD_INIT 479#define AMR_QRESET(sc) \ 480 do { \ 481 pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 482 pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 483 } while (0) 484#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 485#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 486#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 487#endif 488 489/******************************************************************************** 490 ******************************************************************************** 491 "Standard" old-style ASIC bridge interface 492 ******************************************************************************** 493 ********************************************************************************/ 494 495/* 496 * I/O registers 497 */ 498#define AMR_SCMD 0x10 /* command/ack register (write) */ 499#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 500#define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 501#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 502#define AMR_SMBOX_1 0x15 503#define AMR_SMBOX_2 0x16 504#define AMR_SMBOX_3 0x17 /* high byte */ 505#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 506#define AMR_SINTR 0x1a /* interrupt status */ 507 508/* 509 * I/O magic numbers 510 */ 511#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 512#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 513#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 514#define AMR_SINTR_VALID 0x40 /* in SINTR */ 515#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 516#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 517 518/* 519 * Initialisation status 520 */ 521#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 522#define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 523#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 524#define AMR_SINIT_INPROG 0x11 /* init in progress */ 525#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 526#define AMR_SINIT_DONE 0x99 /* init successfully done */ 527 528/* 529 * I/O primitives 530 */ 531#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 532#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 533#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 534#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 535#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 536#define AMR_SENABLE_INTR(sc) \ 537 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 538 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 539#define AMR_SDISABLE_INTR(sc) \ 540 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 541 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 542#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 543 544#ifdef AMR_BOARD_INIT 545#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 546#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 547#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 548#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 549#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 550#endif 551 552#endif /* _KERNEL */ 553