amrreg.h revision 87796
151974Smsmith/*- 265245Smsmith * Copyright (c) 1999,2000 Michael Smith 365245Smsmith * Copyright (c) 2000 BSDi 451974Smsmith * All rights reserved. 551974Smsmith * 651974Smsmith * Redistribution and use in source and binary forms, with or without 751974Smsmith * modification, are permitted provided that the following conditions 851974Smsmith * are met: 951974Smsmith * 1. Redistributions of source code must retain the above copyright 1051974Smsmith * notice, this list of conditions and the following disclaimer. 1151974Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1251974Smsmith * notice, this list of conditions and the following disclaimer in the 1351974Smsmith * documentation and/or other materials provided with the distribution. 1451974Smsmith * 1551974Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1651974Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1751974Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1851974Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1951974Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2051974Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2151974Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2251974Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2351974Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2451974Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2551974Smsmith * SUCH DAMAGE. 2651974Smsmith * 2751974Smsmith * $FreeBSD: head/sys/dev/amr/amrreg.h 87796 2001-12-13 11:12:30Z jhb $ 2851974Smsmith */ 2951974Smsmith 3065245Smsmith/******************************************************************************** 3165245Smsmith ******************************************************************************** 3265245Smsmith Driver parameters 3365245Smsmith ******************************************************************************** 3465245Smsmith ********************************************************************************/ 3565245Smsmith 3651974Smsmith/* 3765245Smsmith * We could actually use all 17 segments, but using only 16 means that 3865245Smsmith * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 3965245Smsmith * maps crossing page boundaries. 4065245Smsmith * 4165245Smsmith * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 4265245Smsmith * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 4365245Smsmith * since we allocate the s/g maps contiguously anyway? 4465245Smsmith */ 4565245Smsmith#define AMR_NSEG 16 4665245Smsmith 4765245Smsmith#define AMR_MAXCMD 255 /* ident = 0 not allowed */ 4865245Smsmith#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 4965245Smsmith#define AMR_MAXLD 40 5065245Smsmith 5165245Smsmith#define AMR_MAX_CHANNELS 4 5265245Smsmith#define AMR_MAX_TARGETS 15 5365245Smsmith#define AMR_MAX_LUNS 7 5465245Smsmith#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 5565245Smsmith 5665245Smsmith#define AMR_MAX_CDB_LEN 0x0a 5765245Smsmith#define AMR_MAX_REQ_SENSE_LEN 0x20 5865245Smsmith 5965245Smsmith#define AMR_BLKSIZE 512 /* constant for all controllers */ 6065245Smsmith 6165245Smsmith/* 6265245Smsmith * Perform at-startup board initialisation. 6365245Smsmith * At this point in time, this code doesn't work correctly, so leave it disabled. 6465245Smsmith */ 6565245Smsmith/*#define AMR_BOARD_INIT*/ 6665245Smsmith 6765245Smsmith/******************************************************************************** 6865245Smsmith ******************************************************************************** 6965245Smsmith Interface Magic Numbers 7065245Smsmith ******************************************************************************** 7165245Smsmith ********************************************************************************/ 7265245Smsmith 7365245Smsmith/* 7451974Smsmith * Mailbox commands 7551974Smsmith */ 7665245Smsmith#define AMR_CMD_LREAD 0x01 7765245Smsmith#define AMR_CMD_LWRITE 0x02 7865245Smsmith#define AMR_CMD_PASS 0x03 7965245Smsmith#define AMR_CMD_EXT_ENQUIRY 0x04 8065245Smsmith#define AMR_CMD_ENQUIRY 0x05 8165245Smsmith#define AMR_CMD_FLUSH 0x0a 8265245Smsmith#define AMR_CMD_EXT_ENQUIRY2 0x0c 8351974Smsmith#define AMR_CONFIG_PRODINFO 0x0e 8465245Smsmith#define AMR_CMD_GET_MACHINEID 0x36 8565245Smsmith#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 8665245Smsmith#define AMR_CMD_CONFIG 0xa1 8765245Smsmith#define AMR_CONFIG_PRODUCT_INFO 0x0e 8865245Smsmith#define AMR_CONFIG_ENQ3 0x0f 8951974Smsmith#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 9051974Smsmith#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 9151974Smsmith#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 9251974Smsmith 9351974Smsmith/* 9451974Smsmith * Command results 9551974Smsmith */ 9651974Smsmith#define AMR_STATUS_SUCCESS 0x00 9751974Smsmith#define AMR_STATUS_ABORTED 0x02 9851974Smsmith#define AMR_STATUS_FAILED 0x80 9951974Smsmith 10051974Smsmith/* 10165245Smsmith * Physical/logical drive states 10251974Smsmith */ 10365245Smsmith#define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 10465245Smsmith#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 10565245Smsmith#define AMR_DRV_OFFLINE 0x00 10665245Smsmith#define AMR_DRV_DEGRADED 0x01 10765245Smsmith#define AMR_DRV_OPTIMAL 0x02 10865245Smsmith#define AMR_DRV_ONLINE 0x03 10965245Smsmith#define AMR_DRV_FAILED 0x04 11065245Smsmith#define AMR_DRV_REBUILD 0x05 11165245Smsmith#define AMR_DRV_HOTSPARE 0x06 11251974Smsmith 11351974Smsmith/* 11465245Smsmith * Logical drive properties 11551974Smsmith */ 11665245Smsmith#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 11765245Smsmith#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 11865245Smsmith#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 11965245Smsmith#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 12051974Smsmith 12151974Smsmith/* 12265245Smsmith * Battery status 12351974Smsmith */ 12465245Smsmith#define AMR_BATT_MODULE_MISSING 0x01 12565245Smsmith#define AMR_BATT_LOW_VOLTAGE 0x02 12665245Smsmith#define AMR_BATT_TEMP_HIGH 0x04 12765245Smsmith#define AMR_BATT_PACK_MISSING 0x08 12865245Smsmith#define AMR_BATT_CHARGE_MASK 0x30 12965245Smsmith#define AMR_BATT_CHARGE_DONE 0x00 13065245Smsmith#define AMR_BATT_CHARGE_INPROG 0x10 13165245Smsmith#define AMR_BATT_CHARGE_FAIL 0x20 13265245Smsmith#define AMR_BATT_CYCLES_EXCEEDED 0x40 13351974Smsmith 13465245Smsmith 13565245Smsmith/******************************************************************************** 13665245Smsmith ******************************************************************************** 13765245Smsmith 8LD Firmware Interface 13865245Smsmith ******************************************************************************** 13965245Smsmith ********************************************************************************/ 14065245Smsmith 14151974Smsmith/* 14265245Smsmith * Array constraints 14351974Smsmith */ 14451974Smsmith#define AMR_8LD_MAXDRIVES 8 14551974Smsmith#define AMR_8LD_MAXCHAN 5 14651974Smsmith#define AMR_8LD_MAXTARG 15 14751974Smsmith#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 14851974Smsmith 14965245Smsmith/* 15065245Smsmith * Adapter Info structure 15165245Smsmith */ 15251974Smsmithstruct amr_adapter_info 15351974Smsmith{ 15451974Smsmith u_int8_t aa_maxio; 15551974Smsmith u_int8_t aa_rebuild_rate; 15651974Smsmith u_int8_t aa_maxtargchan; 15751974Smsmith u_int8_t aa_channels; 15851974Smsmith u_int8_t aa_firmware[4]; 15951974Smsmith u_int16_t aa_flashage; 16051974Smsmith u_int8_t aa_chipsetvalue; 16151974Smsmith u_int8_t aa_memorysize; 16251974Smsmith u_int8_t aa_cacheflush; 16351974Smsmith u_int8_t aa_bios[4]; 16465245Smsmith u_int8_t aa_boardtype; 16565245Smsmith u_int8_t aa_scsisensealert; 16665245Smsmith u_int8_t aa_writeconfigcount; 16765245Smsmith u_int8_t aa_driveinsertioncount; 16865245Smsmith u_int8_t aa_inserteddrive; 16965245Smsmith u_int8_t aa_batterystatus; 17065245Smsmith u_int8_t res1; 17151974Smsmith} __attribute__ ((packed)); 17251974Smsmith 17365245Smsmith/* 17465245Smsmith * Logical Drive info structure 17565245Smsmith */ 17651974Smsmithstruct amr_logdrive_info 17751974Smsmith{ 17851974Smsmith u_int8_t al_numdrives; 17951974Smsmith u_int8_t res1[3]; 18051974Smsmith u_int32_t al_size[AMR_8LD_MAXDRIVES]; 18151974Smsmith u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 18251974Smsmith u_int8_t al_state[AMR_8LD_MAXDRIVES]; 18351974Smsmith} __attribute__ ((packed)); 18451974Smsmith 18565245Smsmith/* 18665245Smsmith * Physical Drive info structure 18765245Smsmith */ 18851974Smsmithstruct amr_physdrive_info 18951974Smsmith{ 19065245Smsmith u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 19165245Smsmith u_int8_t ap_predictivefailure; 19251974Smsmith} __attribute__ ((packed)); 19351974Smsmith 19465245Smsmith/* 19565245Smsmith * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 19665245Smsmith * AMR_CMD_EXT_ENQUIRY2. 19765245Smsmith * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 19865245Smsmith */ 19951974Smsmithstruct amr_enquiry 20051974Smsmith{ 20165245Smsmith struct amr_adapter_info ae_adapter; /* X X X */ 20265245Smsmith struct amr_logdrive_info ae_ldrv; /* X X X */ 20365245Smsmith struct amr_physdrive_info ae_pdrv; /* X X X */ 20465245Smsmith u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 20565245Smsmith u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 20665245Smsmith u_int32_t ae_extlen; /* X */ 20765245Smsmith u_int16_t ae_subsystem; /* X */ 20865245Smsmith u_int16_t ae_subvendor; /* X */ 20965245Smsmith u_int32_t ae_signature; /* X */ 21065245Smsmith#define AMR_SIG_431 0xfffe0001 21165245Smsmith#define AMR_SIG_438 0xfffd0002 21265245Smsmith#define AMR_SIG_762 0xfffc0003 21365245Smsmith#define AMR_SIG_T5 0xfffb0004 21465245Smsmith#define AMR_SIG_466 0xfffa0005 21565245Smsmith#define AMR_SIG_467 0xfff90006 21665245Smsmith#define AMR_SIG_T7 0xfff80007 21765245Smsmith#define AMR_SIG_490 0xfff70008 21865245Smsmith u_int8_t res2[844]; /* X */ 21951974Smsmith} __attribute__ ((packed)); 22051974Smsmith 22165245Smsmith 22265245Smsmith/******************************************************************************** 22365245Smsmith ******************************************************************************** 22465245Smsmith 40LD Firmware Interface 22565245Smsmith ******************************************************************************** 22665245Smsmith ********************************************************************************/ 22765245Smsmith 22865245Smsmith/* 22965245Smsmith * Array constraints 23065245Smsmith */ 23165245Smsmith#define AMR_40LD_MAXDRIVES 40 23265245Smsmith#define AMR_40LD_MAXCHAN 16 23365245Smsmith#define AMR_40LD_MAXTARG 16 23465245Smsmith#define AMR_40LD_MAXPHYSDRIVES 256 23565245Smsmith 23665245Smsmith/* 23765245Smsmith * Product Info structure 23865245Smsmith */ 23951974Smsmithstruct amr_prodinfo 24051974Smsmith{ 24151974Smsmith u_int32_t ap_size; /* current size in bytes (not including resvd) */ 24251974Smsmith u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 24351974Smsmith * logical drives, 0x20 maximum stripes and 0x08 24451974Smsmith * maximum spans */ 24551974Smsmith u_int8_t ap_firmware[16]; /* printable identifiers */ 24651974Smsmith u_int8_t ap_bios[16]; 24751974Smsmith u_int8_t ap_product[80]; 24851974Smsmith u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 24951974Smsmith u_int8_t ap_nschan; /* number of SCSI channels present */ 25051974Smsmith u_int8_t ap_fcloops; /* number of fibre loops present */ 25151974Smsmith u_int8_t ap_memtype; /* memory type */ 25251974Smsmith u_int32_t ap_signature; 25351974Smsmith u_int16_t ap_memsize; /* onboard memory in MB */ 25451974Smsmith u_int16_t ap_subsystem; /* subsystem identifier */ 25551974Smsmith u_int16_t ap_subvendor; /* subsystem vendor ID */ 25651974Smsmith u_int8_t ap_numnotifyctr; /* number of notify counters */ 25751974Smsmith} __attribute__((packed)); 25851974Smsmith 25965245Smsmith/* 26065245Smsmith * Notify structure 26165245Smsmith */ 26265245Smsmithstruct amr_notify 26365245Smsmith{ 26465245Smsmith u_int32_t an_globalcounter; /* change counter */ 26565245Smsmith 26665245Smsmith u_int8_t an_paramcounter; /* parameter change counter */ 26765245Smsmith u_int8_t an_paramid; 26865245Smsmith#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 26965245Smsmith#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 27065245Smsmith#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 27165245Smsmith#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 27265245Smsmith#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 27365245Smsmith u_int16_t an_paramval; 27465245Smsmith 27565245Smsmith u_int8_t an_writeconfigcounter; /* write config occurred */ 27665245Smsmith u_int8_t res1[3]; 27765245Smsmith 27865245Smsmith u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 27965245Smsmith u_int8_t an_ldrvopid; 28065245Smsmith u_int8_t an_ldrvopcmd; 28165245Smsmith#define AMR_LDRVOP_CHECK 0x01 28265245Smsmith#define AMR_LDRVOP_INIT 0x02 28365245Smsmith#define AMR_LDRVOP_REBUILD 0x03 28465245Smsmith u_int8_t an_ldrvopstatus; 28565245Smsmith#define AMR_LDRVOP_SUCCESS 0x00 28665245Smsmith#define AMR_LDRVOP_FAILED 0x01 28765245Smsmith#define AMR_LDRVOP_ABORTED 0x02 28865245Smsmith#define AMR_LDRVOP_CORRECTED 0x03 28965245Smsmith#define AMR_LDRVOP_STARTED 0x04 29065245Smsmith 29165245Smsmith u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 29265245Smsmith u_int8_t an_ldrvstateid; 29365245Smsmith u_int8_t an_ldrvstatenew; 29465245Smsmith u_int8_t an_ldrvstateold; 29565245Smsmith 29665245Smsmith u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 29765245Smsmith u_int8_t an_pdrvstateid; 29865245Smsmith u_int8_t an_pdrvstatenew; 29965245Smsmith u_int8_t an_pdrvstateold; 30065245Smsmith 30165245Smsmith u_int8_t an_pdrvfmtcounter; 30265245Smsmith u_int8_t an_pdrvfmtid; 30365245Smsmith u_int8_t an_pdrvfmtval; 30465245Smsmith#define AMR_FORMAT_START 0x01 30565245Smsmith#define AMR_FORMAT_COMPLETE 0x02 30665245Smsmith u_int8_t res2; 30765245Smsmith 30865245Smsmith u_int8_t an_targxfercounter; /* scsi xfer rate change */ 30965245Smsmith u_int8_t an_targxferid; 31065245Smsmith u_int8_t an_targxferval; 31165245Smsmith u_int8_t res3; 31265245Smsmith 31365245Smsmith u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 31465245Smsmith u_int8_t an_fcloopidpdrvid; 31565245Smsmith u_int8_t an_fcloopid0; 31665245Smsmith u_int8_t an_fcloopid1; 31765245Smsmith 31865245Smsmith u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 31965245Smsmith u_int8_t an_fcloopstate0; 32065245Smsmith u_int8_t an_fcloopstate1; 32165245Smsmith u_int8_t res4; 32265245Smsmith} __attribute__((packed)); 32365245Smsmith 32465245Smsmith/* 32565245Smsmith * Enquiry3 structure 32665245Smsmith */ 32765245Smsmithstruct amr_enquiry3 32865245Smsmith{ 32965245Smsmith u_int32_t ae_datasize; /* valid data size in this structure */ 33065245Smsmith union { /* event notify structure */ 33165245Smsmith struct amr_notify n; 33265245Smsmith u_int8_t pad[0x80]; 33365245Smsmith } ae_notify; 33465245Smsmith u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 33565245Smsmith u_int8_t ae_cacheflush; /* flush interval in seconds */ 33665245Smsmith u_int8_t ae_sensealert; 33765245Smsmith u_int8_t ae_driveinsertcount; /* count of inserted drives */ 33865245Smsmith u_int8_t ae_batterystatus; 33965245Smsmith u_int8_t ae_numldrives; 34065245Smsmith u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 34165245Smsmith u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 34265245Smsmith u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 34365245Smsmith u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 34465245Smsmith u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 34565245Smsmith u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES]; 34665245Smsmith u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 34765245Smsmith 34865245Smsmith u_int8_t res1[263]; /* pad to 1024 bytes */ 34965245Smsmith} __attribute__ ((packed)); 35065245Smsmith 35165245Smsmith 35265245Smsmith/******************************************************************************** 35365245Smsmith ******************************************************************************** 35465245Smsmith Mailbox and Command Structures 35565245Smsmith ******************************************************************************** 35665245Smsmith ********************************************************************************/ 35765245Smsmith 35851974Smsmith#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 35951974Smsmith 36051974Smsmithstruct amr_mailbox 36151974Smsmith{ 36251974Smsmith u_int8_t mb_command; 36351974Smsmith u_int8_t mb_ident; 36451974Smsmith u_int16_t mb_blkcount; 36551974Smsmith u_int32_t mb_lba; 36651974Smsmith u_int32_t mb_physaddr; 36751974Smsmith u_int8_t mb_drive; 36851974Smsmith u_int8_t mb_nsgelem; 36951974Smsmith u_int8_t res1; 37051974Smsmith u_int8_t mb_busy; 37151974Smsmith u_int8_t mb_nstatus; 37251974Smsmith u_int8_t mb_status; 37351974Smsmith u_int8_t mb_completed[46]; 37451974Smsmith u_int8_t mb_poll; 37551974Smsmith u_int8_t mb_ack; 37651974Smsmith u_int8_t res2[16]; 37751974Smsmith} __attribute__ ((packed)); 37851974Smsmith 37951974Smsmithstruct amr_mailbox64 38051974Smsmith{ 38151974Smsmith u_int32_t mb64_segment; /* for 64-bit controllers */ 38251974Smsmith struct amr_mailbox mb; 38351974Smsmith} __attribute__ ((packed)); 38451974Smsmith 38551974Smsmithstruct amr_mailbox_ioctl 38651974Smsmith{ 38751974Smsmith u_int8_t mb_command; 38851974Smsmith u_int8_t mb_ident; 38951974Smsmith u_int8_t mb_channel; 39051974Smsmith u_int8_t mb_param; 39165245Smsmith u_int8_t mb_pad[4]; 39251974Smsmith u_int32_t mb_physaddr; 39351974Smsmith u_int8_t mb_drive; 39451974Smsmith u_int8_t mb_nsgelem; 39565245Smsmith u_int8_t res1; 39651974Smsmith u_int8_t mb_busy; 39751974Smsmith u_int8_t mb_nstatus; 39851974Smsmith u_int8_t mb_completed[46]; 39951974Smsmith u_int8_t mb_poll; 40051974Smsmith u_int8_t mb_ack; 40165245Smsmith u_int8_t res4[16]; 40251974Smsmith} __attribute__ ((packed)); 40351974Smsmith 40451974Smsmithstruct amr_sgentry 40551974Smsmith{ 40651974Smsmith u_int32_t sg_addr; 40751974Smsmith u_int32_t sg_count; 40851974Smsmith} __attribute__ ((packed)); 40951974Smsmith 41065245Smsmithstruct amr_passthrough 41165245Smsmith{ 41265245Smsmith u_int8_t ap_timeout:3; 41365245Smsmith u_int8_t ap_ars:1; 41465245Smsmith u_int8_t ap_dummy:3; 41565245Smsmith u_int8_t ap_islogical:1; 41665245Smsmith u_int8_t ap_logical_drive_no; 41765245Smsmith u_int8_t ap_channel; 41865245Smsmith u_int8_t ap_scsi_id; 41965245Smsmith u_int8_t ap_queue_tag; 42065245Smsmith u_int8_t ap_queue_action; 42165245Smsmith u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 42265245Smsmith u_int8_t ap_cdb_length; 42365245Smsmith u_int8_t ap_request_sense_length; 42465245Smsmith u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 42565245Smsmith u_int8_t ap_no_sg_elements; 42665245Smsmith u_int8_t ap_scsi_status; 42765245Smsmith u_int32_t ap_data_transfer_address; 42865245Smsmith u_int32_t ap_data_transfer_length; 42965245Smsmith} __attribute__ ((packed)); 43051974Smsmith 43165245Smsmith#ifdef _KERNEL 43265245Smsmith/******************************************************************************** 43365245Smsmith ******************************************************************************** 43465245Smsmith "Quartz" i960 PCI bridge interface 43565245Smsmith ******************************************************************************** 43665245Smsmith ********************************************************************************/ 43765245Smsmith 43865245Smsmith#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 43970285Smsmith#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 44070285Smsmith#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 44165245Smsmith 44265245Smsmith/* 44365245Smsmith * Doorbell registers 44465245Smsmith */ 44565245Smsmith#define AMR_QIDB 0x20 44665245Smsmith#define AMR_QODB 0x2c 44765245Smsmith#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 44865245Smsmith#define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 44965245Smsmith#define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 45065245Smsmith 45165245Smsmith/* 45265245Smsmith * Initialisation status 45365245Smsmith */ 45465245Smsmith#define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 45565245Smsmith#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 45665245Smsmith#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 45765245Smsmith#define AMR_QINIT_INPROG 0xdc /* init in progress */ 45865245Smsmith#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 45965245Smsmith#define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 46065245Smsmith#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 46165245Smsmith#define AMR_QINIT_DONE 0x9c /* init successfully done */ 46265245Smsmith 46365245Smsmith/* 46465245Smsmith * I/O primitives 46565245Smsmith */ 46665245Smsmith#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 46765245Smsmith#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 46865245Smsmith#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 46965245Smsmith#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 47065245Smsmith 47165245Smsmith#ifdef AMR_BOARD_INIT 47265245Smsmith#define AMR_QRESET(sc) \ 47365245Smsmith do { \ 47465245Smsmith pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 47565245Smsmith pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 47665245Smsmith } while (0) 47765245Smsmith#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 47865245Smsmith#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 47965245Smsmith#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 48065245Smsmith#endif 48165245Smsmith 48265245Smsmith/******************************************************************************** 48365245Smsmith ******************************************************************************** 48465245Smsmith "Standard" old-style ASIC bridge interface 48565245Smsmith ******************************************************************************** 48665245Smsmith ********************************************************************************/ 48765245Smsmith 48865245Smsmith/* 48965245Smsmith * I/O registers 49065245Smsmith */ 49165245Smsmith#define AMR_SCMD 0x10 /* command/ack register (write) */ 49265245Smsmith#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 49365245Smsmith#define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 49465245Smsmith#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 49565245Smsmith#define AMR_SMBOX_1 0x15 49665245Smsmith#define AMR_SMBOX_2 0x16 49765245Smsmith#define AMR_SMBOX_3 0x17 /* high byte */ 49865245Smsmith#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 49965245Smsmith#define AMR_SINTR 0x1a /* interrupt status */ 50065245Smsmith 50165245Smsmith/* 50265245Smsmith * I/O magic numbers 50365245Smsmith */ 50465245Smsmith#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 50565245Smsmith#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 50665245Smsmith#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 50765245Smsmith#define AMR_SINTR_VALID 0x40 /* in SINTR */ 50865245Smsmith#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 50965245Smsmith#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 51065245Smsmith 51165245Smsmith/* 51265245Smsmith * Initialisation status 51365245Smsmith */ 51465245Smsmith#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 51565245Smsmith#define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 51665245Smsmith#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 51765245Smsmith#define AMR_SINIT_INPROG 0x11 /* init in progress */ 51865245Smsmith#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 51965245Smsmith#define AMR_SINIT_DONE 0x99 /* init successfully done */ 52065245Smsmith 52165245Smsmith/* 52265245Smsmith * I/O primitives 52365245Smsmith */ 52465245Smsmith#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 52565245Smsmith#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 52665245Smsmith#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 52765245Smsmith#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 52865245Smsmith#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 52965245Smsmith#define AMR_SENABLE_INTR(sc) \ 53065245Smsmith bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 53165245Smsmith bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 53265245Smsmith#define AMR_SDISABLE_INTR(sc) \ 53365245Smsmith bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 53465245Smsmith bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 53565245Smsmith#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 53665245Smsmith 53765245Smsmith#ifdef AMR_BOARD_INIT 53865245Smsmith#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 53965245Smsmith#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 54065245Smsmith#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 54165245Smsmith#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 54265245Smsmith#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 54365245Smsmith#endif 54465245Smsmith 54587796Sjhb#endif /* _KERNEL */ 546