151974Smsmith/*- 265245Smsmith * Copyright (c) 1999,2000 Michael Smith 365245Smsmith * Copyright (c) 2000 BSDi 451974Smsmith * All rights reserved. 551974Smsmith * 651974Smsmith * Redistribution and use in source and binary forms, with or without 751974Smsmith * modification, are permitted provided that the following conditions 851974Smsmith * are met: 951974Smsmith * 1. Redistributions of source code must retain the above copyright 1051974Smsmith * notice, this list of conditions and the following disclaimer. 1151974Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1251974Smsmith * notice, this list of conditions and the following disclaimer in the 1351974Smsmith * documentation and/or other materials provided with the distribution. 1451974Smsmith * 1551974Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1651974Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1751974Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1851974Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1951974Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2051974Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2151974Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2251974Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2351974Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2451974Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2551974Smsmith * SUCH DAMAGE. 2651974Smsmith * 27106225Semoore * Copyright (c) 2002 Eric Moore 28106225Semoore * Copyright (c) 2002 LSI Logic Corporation 29106225Semoore * All rights reserved. 30106225Semoore * 31106225Semoore * Redistribution and use in source and binary forms, with or without 32106225Semoore * modification, are permitted provided that the following conditions 33106225Semoore * are met: 34106225Semoore * 1. Redistributions of source code must retain the above copyright 35106225Semoore * notice, this list of conditions and the following disclaimer. 36106225Semoore * 2. Redistributions in binary form must reproduce the above copyright 37106225Semoore * notice, this list of conditions and the following disclaimer in the 38106225Semoore * documentation and/or other materials provided with the distribution. 39105419Semoore * 3. The party using or redistributing the source code and binary forms 40106225Semoore * agrees to the disclaimer below and the terms and conditions set forth 41105419Semoore * herein. 42105419Semoore * 43106225Semoore * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 44106225Semoore * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 45106225Semoore * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 46106225Semoore * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 47106225Semoore * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 48106225Semoore * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 49106225Semoore * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50106225Semoore * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51106225Semoore * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52106225Semoore * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53106225Semoore * SUCH DAMAGE. 54105419Semoore * 55106225Semoore * 5651974Smsmith * $FreeBSD$ 5751974Smsmith */ 5851974Smsmith 5965245Smsmith/******************************************************************************** 6065245Smsmith ******************************************************************************** 6165245Smsmith Driver parameters 6265245Smsmith ******************************************************************************** 6365245Smsmith ********************************************************************************/ 6465245Smsmith 6551974Smsmith/* 6665245Smsmith * We could actually use all 17 segments, but using only 16 means that 6765245Smsmith * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 6865245Smsmith * maps crossing page boundaries. 6965245Smsmith * 7065245Smsmith * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 7165245Smsmith * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 7265245Smsmith * since we allocate the s/g maps contiguously anyway? 7365245Smsmith */ 74106225Semoore/* 75106225Semoore * emoore - Oct 21, 2002 76106225Semoore * firmware doesn't have sglist boundary restrictions. 77106225Semoore * The sgelem can be set to 26 78106225Semoore */ 79106225Semoore#define AMR_NSEG 26 8065245Smsmith 8165245Smsmith#define AMR_MAXCMD 255 /* ident = 0 not allowed */ 8265245Smsmith#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 8365245Smsmith#define AMR_MAXLD 40 8465245Smsmith 85140688Sscottl#define AMR_MAX_CHANNELS 8 8665245Smsmith#define AMR_MAX_TARGETS 15 8765245Smsmith#define AMR_MAX_LUNS 7 8865245Smsmith#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 8965245Smsmith 9065245Smsmith#define AMR_MAX_CDB_LEN 0x0a 91106225Semoore#define AMR_MAX_EXTCDB_LEN 0x10 9265245Smsmith#define AMR_MAX_REQ_SENSE_LEN 0x20 9365245Smsmith 9465245Smsmith#define AMR_BLKSIZE 512 /* constant for all controllers */ 9565245Smsmith 9665245Smsmith/* 9765245Smsmith * Perform at-startup board initialisation. 9865245Smsmith * At this point in time, this code doesn't work correctly, so leave it disabled. 9965245Smsmith */ 10065245Smsmith/*#define AMR_BOARD_INIT*/ 10165245Smsmith 10265245Smsmith/******************************************************************************** 10365245Smsmith ******************************************************************************** 10465245Smsmith Interface Magic Numbers 10565245Smsmith ******************************************************************************** 10665245Smsmith ********************************************************************************/ 10765245Smsmith 10865245Smsmith/* 10951974Smsmith * Mailbox commands 11051974Smsmith */ 11165245Smsmith#define AMR_CMD_LREAD 0x01 11265245Smsmith#define AMR_CMD_LWRITE 0x02 11365245Smsmith#define AMR_CMD_PASS 0x03 11465245Smsmith#define AMR_CMD_EXT_ENQUIRY 0x04 11565245Smsmith#define AMR_CMD_ENQUIRY 0x05 11665245Smsmith#define AMR_CMD_FLUSH 0x0a 11765245Smsmith#define AMR_CMD_EXT_ENQUIRY2 0x0c 11851974Smsmith#define AMR_CONFIG_PRODINFO 0x0e 11965245Smsmith#define AMR_CMD_GET_MACHINEID 0x36 12065245Smsmith#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 12165245Smsmith#define AMR_CMD_CONFIG 0xa1 122153409Sscottl#define AMR_CMD_LREAD64 0xa7 123153409Sscottl#define AMR_CMD_LWRITE64 0xa8 124153409Sscottl#define AMR_CMD_PASS_64 0xc3 125153409Sscottl#define AMR_CMD_EXTPASS 0xe3 126153409Sscottl 127154321Sjkim#define AMR_CONFIG_READ_NVRAM_CONFIG 0x04 128154321Sjkim#define AMR_CONFIG_WRITE_NVRAM_CONFIG 0x0d 12965245Smsmith#define AMR_CONFIG_PRODUCT_INFO 0x0e 13065245Smsmith#define AMR_CONFIG_ENQ3 0x0f 13151974Smsmith#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 13251974Smsmith#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 13351974Smsmith#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 13451974Smsmith 13551974Smsmith/* 136153409Sscottl * Command for random deletion of logical drives 137153409Sscottl */ 138153409Sscottl#define FC_DEL_LOGDRV 0xA4 139153409Sscottl#define OP_SUP_DEL_LOGDRV 0x2A 140153409Sscottl#define OP_GET_LDID_MAP 0x18 141153409Sscottl#define OP_DEL_LOGDRV 0x1C 142153409Sscottl 143153409Sscottl/* 144175622Sscottl * Command for random deletion of logical drives 145175622Sscottl */ 146175622Sscottl#define FC_DEL_LOGDRV 0xA4 147175622Sscottl#define OP_SUP_DEL_LOGDRV 0x2A 148175622Sscottl#define OP_GET_LDID_MAP 0x18 149175622Sscottl#define OP_DEL_LOGDRV 0x1C 150175622Sscottl 151175622Sscottl/* 15251974Smsmith * Command results 15351974Smsmith */ 15451974Smsmith#define AMR_STATUS_SUCCESS 0x00 15551974Smsmith#define AMR_STATUS_ABORTED 0x02 15651974Smsmith#define AMR_STATUS_FAILED 0x80 15751974Smsmith 15851974Smsmith/* 15965245Smsmith * Physical/logical drive states 16051974Smsmith */ 16165245Smsmith#define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 16265245Smsmith#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 16365245Smsmith#define AMR_DRV_OFFLINE 0x00 16465245Smsmith#define AMR_DRV_DEGRADED 0x01 16565245Smsmith#define AMR_DRV_OPTIMAL 0x02 16665245Smsmith#define AMR_DRV_ONLINE 0x03 16765245Smsmith#define AMR_DRV_FAILED 0x04 16865245Smsmith#define AMR_DRV_REBUILD 0x05 16965245Smsmith#define AMR_DRV_HOTSPARE 0x06 17051974Smsmith 17151974Smsmith/* 17265245Smsmith * Logical drive properties 17351974Smsmith */ 17465245Smsmith#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 17565245Smsmith#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 17665245Smsmith#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 17765245Smsmith#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 17851974Smsmith 17951974Smsmith/* 18065245Smsmith * Battery status 18151974Smsmith */ 18265245Smsmith#define AMR_BATT_MODULE_MISSING 0x01 18365245Smsmith#define AMR_BATT_LOW_VOLTAGE 0x02 18465245Smsmith#define AMR_BATT_TEMP_HIGH 0x04 18565245Smsmith#define AMR_BATT_PACK_MISSING 0x08 18665245Smsmith#define AMR_BATT_CHARGE_MASK 0x30 18765245Smsmith#define AMR_BATT_CHARGE_DONE 0x00 18865245Smsmith#define AMR_BATT_CHARGE_INPROG 0x10 18965245Smsmith#define AMR_BATT_CHARGE_FAIL 0x20 19065245Smsmith#define AMR_BATT_CYCLES_EXCEEDED 0x40 19151974Smsmith 19265245Smsmith 19365245Smsmith/******************************************************************************** 19465245Smsmith ******************************************************************************** 19565245Smsmith 8LD Firmware Interface 19665245Smsmith ******************************************************************************** 19765245Smsmith ********************************************************************************/ 19865245Smsmith 19951974Smsmith/* 20065245Smsmith * Array constraints 20151974Smsmith */ 20251974Smsmith#define AMR_8LD_MAXDRIVES 8 20351974Smsmith#define AMR_8LD_MAXCHAN 5 20451974Smsmith#define AMR_8LD_MAXTARG 15 20551974Smsmith#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 20651974Smsmith 20765245Smsmith/* 20865245Smsmith * Adapter Info structure 20965245Smsmith */ 21051974Smsmithstruct amr_adapter_info 21151974Smsmith{ 21251974Smsmith u_int8_t aa_maxio; 21351974Smsmith u_int8_t aa_rebuild_rate; 21451974Smsmith u_int8_t aa_maxtargchan; 21551974Smsmith u_int8_t aa_channels; 21651974Smsmith u_int8_t aa_firmware[4]; 21751974Smsmith u_int16_t aa_flashage; 21851974Smsmith u_int8_t aa_chipsetvalue; 21951974Smsmith u_int8_t aa_memorysize; 22051974Smsmith u_int8_t aa_cacheflush; 22151974Smsmith u_int8_t aa_bios[4]; 22265245Smsmith u_int8_t aa_boardtype; 22365245Smsmith u_int8_t aa_scsisensealert; 22465245Smsmith u_int8_t aa_writeconfigcount; 22565245Smsmith u_int8_t aa_driveinsertioncount; 22665245Smsmith u_int8_t aa_inserteddrive; 22765245Smsmith u_int8_t aa_batterystatus; 22865245Smsmith u_int8_t res1; 229103870Salfred} __packed; 23051974Smsmith 23165245Smsmith/* 23265245Smsmith * Logical Drive info structure 23365245Smsmith */ 23451974Smsmithstruct amr_logdrive_info 23551974Smsmith{ 23651974Smsmith u_int8_t al_numdrives; 23751974Smsmith u_int8_t res1[3]; 23851974Smsmith u_int32_t al_size[AMR_8LD_MAXDRIVES]; 23951974Smsmith u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 24051974Smsmith u_int8_t al_state[AMR_8LD_MAXDRIVES]; 241103870Salfred} __packed; 24251974Smsmith 24365245Smsmith/* 24465245Smsmith * Physical Drive info structure 24565245Smsmith */ 24651974Smsmithstruct amr_physdrive_info 24751974Smsmith{ 24865245Smsmith u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 24965245Smsmith u_int8_t ap_predictivefailure; 250103870Salfred} __packed; 25151974Smsmith 25265245Smsmith/* 25365245Smsmith * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 25465245Smsmith * AMR_CMD_EXT_ENQUIRY2. 25565245Smsmith * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 25665245Smsmith */ 25751974Smsmithstruct amr_enquiry 25851974Smsmith{ 25965245Smsmith struct amr_adapter_info ae_adapter; /* X X X */ 26065245Smsmith struct amr_logdrive_info ae_ldrv; /* X X X */ 26165245Smsmith struct amr_physdrive_info ae_pdrv; /* X X X */ 26265245Smsmith u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 26365245Smsmith u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 26465245Smsmith u_int32_t ae_extlen; /* X */ 26565245Smsmith u_int16_t ae_subsystem; /* X */ 26665245Smsmith u_int16_t ae_subvendor; /* X */ 26765245Smsmith u_int32_t ae_signature; /* X */ 26865245Smsmith#define AMR_SIG_431 0xfffe0001 26965245Smsmith#define AMR_SIG_438 0xfffd0002 27065245Smsmith#define AMR_SIG_762 0xfffc0003 27165245Smsmith#define AMR_SIG_T5 0xfffb0004 27265245Smsmith#define AMR_SIG_466 0xfffa0005 27365245Smsmith#define AMR_SIG_467 0xfff90006 27465245Smsmith#define AMR_SIG_T7 0xfff80007 27565245Smsmith#define AMR_SIG_490 0xfff70008 27665245Smsmith u_int8_t res2[844]; /* X */ 277103870Salfred} __packed; 27851974Smsmith 27965245Smsmith 28065245Smsmith/******************************************************************************** 28165245Smsmith ******************************************************************************** 28265245Smsmith 40LD Firmware Interface 28365245Smsmith ******************************************************************************** 28465245Smsmith ********************************************************************************/ 28565245Smsmith 28665245Smsmith/* 28765245Smsmith * Array constraints 28865245Smsmith */ 28965245Smsmith#define AMR_40LD_MAXDRIVES 40 29065245Smsmith#define AMR_40LD_MAXCHAN 16 29165245Smsmith#define AMR_40LD_MAXTARG 16 29265245Smsmith#define AMR_40LD_MAXPHYSDRIVES 256 29365245Smsmith 29465245Smsmith/* 29565245Smsmith * Product Info structure 29665245Smsmith */ 29751974Smsmithstruct amr_prodinfo 29851974Smsmith{ 29951974Smsmith u_int32_t ap_size; /* current size in bytes (not including resvd) */ 30051974Smsmith u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 30151974Smsmith * logical drives, 0x20 maximum stripes and 0x08 30251974Smsmith * maximum spans */ 30351974Smsmith u_int8_t ap_firmware[16]; /* printable identifiers */ 30451974Smsmith u_int8_t ap_bios[16]; 30551974Smsmith u_int8_t ap_product[80]; 30651974Smsmith u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 30751974Smsmith u_int8_t ap_nschan; /* number of SCSI channels present */ 30851974Smsmith u_int8_t ap_fcloops; /* number of fibre loops present */ 30951974Smsmith u_int8_t ap_memtype; /* memory type */ 31051974Smsmith u_int32_t ap_signature; 31151974Smsmith u_int16_t ap_memsize; /* onboard memory in MB */ 31251974Smsmith u_int16_t ap_subsystem; /* subsystem identifier */ 31351974Smsmith u_int16_t ap_subvendor; /* subsystem vendor ID */ 31451974Smsmith u_int8_t ap_numnotifyctr; /* number of notify counters */ 315103870Salfred} __packed; 31651974Smsmith 31765245Smsmith/* 31865245Smsmith * Notify structure 31965245Smsmith */ 32065245Smsmithstruct amr_notify 32165245Smsmith{ 32265245Smsmith u_int32_t an_globalcounter; /* change counter */ 32365245Smsmith 32465245Smsmith u_int8_t an_paramcounter; /* parameter change counter */ 32565245Smsmith u_int8_t an_paramid; 32665245Smsmith#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 32765245Smsmith#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 32865245Smsmith#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 32965245Smsmith#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 33065245Smsmith#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 33165245Smsmith u_int16_t an_paramval; 33265245Smsmith 33365245Smsmith u_int8_t an_writeconfigcounter; /* write config occurred */ 33465245Smsmith u_int8_t res1[3]; 33565245Smsmith 33665245Smsmith u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 33765245Smsmith u_int8_t an_ldrvopid; 33865245Smsmith u_int8_t an_ldrvopcmd; 33965245Smsmith#define AMR_LDRVOP_CHECK 0x01 34065245Smsmith#define AMR_LDRVOP_INIT 0x02 34165245Smsmith#define AMR_LDRVOP_REBUILD 0x03 34265245Smsmith u_int8_t an_ldrvopstatus; 34365245Smsmith#define AMR_LDRVOP_SUCCESS 0x00 34465245Smsmith#define AMR_LDRVOP_FAILED 0x01 34565245Smsmith#define AMR_LDRVOP_ABORTED 0x02 34665245Smsmith#define AMR_LDRVOP_CORRECTED 0x03 34765245Smsmith#define AMR_LDRVOP_STARTED 0x04 34865245Smsmith 34965245Smsmith u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 35065245Smsmith u_int8_t an_ldrvstateid; 35165245Smsmith u_int8_t an_ldrvstatenew; 35265245Smsmith u_int8_t an_ldrvstateold; 35365245Smsmith 35465245Smsmith u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 35565245Smsmith u_int8_t an_pdrvstateid; 35665245Smsmith u_int8_t an_pdrvstatenew; 35765245Smsmith u_int8_t an_pdrvstateold; 35865245Smsmith 35965245Smsmith u_int8_t an_pdrvfmtcounter; 36065245Smsmith u_int8_t an_pdrvfmtid; 36165245Smsmith u_int8_t an_pdrvfmtval; 36265245Smsmith#define AMR_FORMAT_START 0x01 36365245Smsmith#define AMR_FORMAT_COMPLETE 0x02 36465245Smsmith u_int8_t res2; 36565245Smsmith 36665245Smsmith u_int8_t an_targxfercounter; /* scsi xfer rate change */ 36765245Smsmith u_int8_t an_targxferid; 36865245Smsmith u_int8_t an_targxferval; 36965245Smsmith u_int8_t res3; 37065245Smsmith 37165245Smsmith u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 37265245Smsmith u_int8_t an_fcloopidpdrvid; 37365245Smsmith u_int8_t an_fcloopid0; 37465245Smsmith u_int8_t an_fcloopid1; 37565245Smsmith 37665245Smsmith u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 37765245Smsmith u_int8_t an_fcloopstate0; 37865245Smsmith u_int8_t an_fcloopstate1; 37965245Smsmith u_int8_t res4; 380103870Salfred} __packed; 38165245Smsmith 38265245Smsmith/* 38365245Smsmith * Enquiry3 structure 38465245Smsmith */ 38565245Smsmithstruct amr_enquiry3 38665245Smsmith{ 38765245Smsmith u_int32_t ae_datasize; /* valid data size in this structure */ 38865245Smsmith union { /* event notify structure */ 38965245Smsmith struct amr_notify n; 39065245Smsmith u_int8_t pad[0x80]; 39165245Smsmith } ae_notify; 39265245Smsmith u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 39365245Smsmith u_int8_t ae_cacheflush; /* flush interval in seconds */ 39465245Smsmith u_int8_t ae_sensealert; 39565245Smsmith u_int8_t ae_driveinsertcount; /* count of inserted drives */ 39665245Smsmith u_int8_t ae_batterystatus; 39765245Smsmith u_int8_t ae_numldrives; 39865245Smsmith u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 39965245Smsmith u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 40065245Smsmith u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 40165245Smsmith u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 402154321Sjkim u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* logical drive state */ 403154321Sjkim u_int8_t ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; /* physical drive state */ 404154321Sjkim u_int16_t ae_pdriveformat[AMR_40LD_MAXPHYSDRIVES / 16]; 40565245Smsmith u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 40665245Smsmith 40765245Smsmith u_int8_t res1[263]; /* pad to 1024 bytes */ 408103870Salfred} __packed; 40965245Smsmith 41065245Smsmith 41165245Smsmith/******************************************************************************** 41265245Smsmith ******************************************************************************** 41365245Smsmith Mailbox and Command Structures 41465245Smsmith ******************************************************************************** 41565245Smsmith ********************************************************************************/ 41665245Smsmith 41751974Smsmith#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 41851974Smsmith 41951974Smsmithstruct amr_mailbox 42051974Smsmith{ 42151974Smsmith u_int8_t mb_command; 42251974Smsmith u_int8_t mb_ident; 423153409Sscottl u_int16_t mb_blkcount; /* u_int8_t opcode */ 424153409Sscottl /* u_int8_t subopcode */ 42551974Smsmith u_int32_t mb_lba; 42651974Smsmith u_int32_t mb_physaddr; 42751974Smsmith u_int8_t mb_drive; 428153409Sscottl u_int8_t mb_nsgelem; /* u_int8_t rserv[0] */ 429153409Sscottl u_int8_t res1; /* u_int8_t rserv[1] */ 430153409Sscottl u_int8_t mb_busy; /* u_int8_t rserv[2] */ 43151974Smsmith u_int8_t mb_nstatus; 43251974Smsmith u_int8_t mb_status; 43351974Smsmith u_int8_t mb_completed[46]; 43451974Smsmith u_int8_t mb_poll; 43551974Smsmith u_int8_t mb_ack; 43651974Smsmith u_int8_t res2[16]; 437103870Salfred} __packed; 43851974Smsmith 43951974Smsmithstruct amr_mailbox64 44051974Smsmith{ 441153409Sscottl u_int8_t pad[8]; /* Needed for alignment */ 442153409Sscottl u_int32_t sg64_lo; /* S/G pointer for 64-bit commands */ 443153409Sscottl u_int32_t sg64_hi; /* S/G pointer for 64-bit commands */ 44451974Smsmith struct amr_mailbox mb; 445103870Salfred} __packed; 44651974Smsmith 44751974Smsmithstruct amr_mailbox_ioctl 44851974Smsmith{ 44951974Smsmith u_int8_t mb_command; 45051974Smsmith u_int8_t mb_ident; 45151974Smsmith u_int8_t mb_channel; 45251974Smsmith u_int8_t mb_param; 45365245Smsmith u_int8_t mb_pad[4]; 45451974Smsmith u_int32_t mb_physaddr; 45551974Smsmith u_int8_t mb_drive; 45651974Smsmith u_int8_t mb_nsgelem; 45765245Smsmith u_int8_t res1; 45851974Smsmith u_int8_t mb_busy; 45951974Smsmith u_int8_t mb_nstatus; 46051974Smsmith u_int8_t mb_completed[46]; 46151974Smsmith u_int8_t mb_poll; 46251974Smsmith u_int8_t mb_ack; 46365245Smsmith u_int8_t res4[16]; 464103870Salfred} __packed; 46551974Smsmith 46651974Smsmithstruct amr_sgentry 46751974Smsmith{ 46851974Smsmith u_int32_t sg_addr; 46951974Smsmith u_int32_t sg_count; 470103870Salfred} __packed; 47151974Smsmith 472153409Sscottlstruct amr_sg64entry 473153409Sscottl{ 474153409Sscottl u_int64_t sg_addr; 475153409Sscottl u_int32_t sg_count; 476153409Sscottl} __packed; 477153409Sscottl 47865245Smsmithstruct amr_passthrough 47965245Smsmith{ 48065245Smsmith u_int8_t ap_timeout:3; 48165245Smsmith u_int8_t ap_ars:1; 48265245Smsmith u_int8_t ap_dummy:3; 48365245Smsmith u_int8_t ap_islogical:1; 48465245Smsmith u_int8_t ap_logical_drive_no; 48565245Smsmith u_int8_t ap_channel; 48665245Smsmith u_int8_t ap_scsi_id; 48765245Smsmith u_int8_t ap_queue_tag; 48865245Smsmith u_int8_t ap_queue_action; 48965245Smsmith u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 49065245Smsmith u_int8_t ap_cdb_length; 49165245Smsmith u_int8_t ap_request_sense_length; 49265245Smsmith u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 49365245Smsmith u_int8_t ap_no_sg_elements; 49465245Smsmith u_int8_t ap_scsi_status; 49565245Smsmith u_int32_t ap_data_transfer_address; 49665245Smsmith u_int32_t ap_data_transfer_length; 497103870Salfred} __packed; 49851974Smsmith 499106225Semoorestruct amr_ext_passthrough 500106225Semoore{ 501106225Semoore u_int8_t ap_timeout:3; 502106225Semoore u_int8_t ap_ars:1; 503106225Semoore u_int8_t ap_rsvd1:1; 504106225Semoore u_int8_t ap_cd_rom:1; 505106225Semoore u_int8_t ap_rsvd2:1; 506106225Semoore u_int8_t ap_islogical:1; 507106225Semoore u_int8_t ap_logical_drive_no; 508106225Semoore u_int8_t ap_channel; 509106225Semoore u_int8_t ap_scsi_id; 510106225Semoore u_int8_t ap_queue_tag; 511106225Semoore u_int8_t ap_queue_action; 512106225Semoore u_int8_t ap_cdb_length; 513106225Semoore u_int8_t ap_rsvd3; 514106225Semoore u_int8_t ap_cdb[AMR_MAX_EXTCDB_LEN]; 515106225Semoore u_int8_t ap_no_sg_elements; 516106225Semoore u_int8_t ap_scsi_status; 517106225Semoore u_int8_t ap_request_sense_length; 518106225Semoore u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 519106225Semoore u_int8_t ap_rsvd4; 520106225Semoore u_int32_t ap_data_transfer_address; 521106225Semoore u_int32_t ap_data_transfer_length; 522106225Semoore} __packed; 523106225Semoore 524153409Sscottlstruct amr_linux_ioctl { 525153409Sscottl u_int32_t inlen; 526153409Sscottl u_int32_t outlen; 527153409Sscottl union { 528153409Sscottl u_int8_t fca[16]; 529153409Sscottl struct { 530153409Sscottl u_int8_t opcode; 531153409Sscottl u_int8_t subopcode; 532153409Sscottl u_int16_t adapno; 533153409Sscottl u_int32_t buffer; 534153409Sscottl u_int8_t pad[4]; 535153409Sscottl u_int32_t length; 536153409Sscottl } __packed fcs; 537153409Sscottl } __packed ui; 538153409Sscottl u_int8_t mbox[18]; 539153409Sscottl struct amr_passthrough pthru; 540153409Sscottl u_int32_t data; 541153409Sscottl u_int8_t pad[4]; 542153409Sscottl} __packed; 543153409Sscottl 54465245Smsmith#ifdef _KERNEL 54565245Smsmith/******************************************************************************** 54665245Smsmith ******************************************************************************** 54765245Smsmith "Quartz" i960 PCI bridge interface 54865245Smsmith ******************************************************************************** 54965245Smsmith ********************************************************************************/ 55065245Smsmith 55165245Smsmith#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 55270285Smsmith#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 55370285Smsmith#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 55465245Smsmith 55565245Smsmith/* 55665245Smsmith * Doorbell registers 55765245Smsmith */ 55865245Smsmith#define AMR_QIDB 0x20 55965245Smsmith#define AMR_QODB 0x2c 56065245Smsmith#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 56165245Smsmith#define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 56265245Smsmith#define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 56365245Smsmith 56465245Smsmith/* 56565245Smsmith * Initialisation status 56665245Smsmith */ 56765245Smsmith#define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 56865245Smsmith#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 56965245Smsmith#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 57065245Smsmith#define AMR_QINIT_INPROG 0xdc /* init in progress */ 57165245Smsmith#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 57265245Smsmith#define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 57365245Smsmith#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 57465245Smsmith#define AMR_QINIT_DONE 0x9c /* init successfully done */ 57565245Smsmith 57665245Smsmith/* 57765245Smsmith * I/O primitives 57865245Smsmith */ 57965245Smsmith#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 58065245Smsmith#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 58165245Smsmith#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 58265245Smsmith#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 58365245Smsmith 58465245Smsmith#ifdef AMR_BOARD_INIT 58565245Smsmith#define AMR_QRESET(sc) \ 58665245Smsmith do { \ 58765245Smsmith pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 58865245Smsmith pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 58965245Smsmith } while (0) 59065245Smsmith#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 59165245Smsmith#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 59265245Smsmith#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 59365245Smsmith#endif 59465245Smsmith 59565245Smsmith/******************************************************************************** 59665245Smsmith ******************************************************************************** 59765245Smsmith "Standard" old-style ASIC bridge interface 59865245Smsmith ******************************************************************************** 59965245Smsmith ********************************************************************************/ 60065245Smsmith 60165245Smsmith/* 60265245Smsmith * I/O registers 60365245Smsmith */ 60465245Smsmith#define AMR_SCMD 0x10 /* command/ack register (write) */ 60565245Smsmith#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 60665245Smsmith#define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 60765245Smsmith#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 60865245Smsmith#define AMR_SMBOX_1 0x15 60965245Smsmith#define AMR_SMBOX_2 0x16 61065245Smsmith#define AMR_SMBOX_3 0x17 /* high byte */ 61165245Smsmith#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 61265245Smsmith#define AMR_SINTR 0x1a /* interrupt status */ 61365245Smsmith 61465245Smsmith/* 61565245Smsmith * I/O magic numbers 61665245Smsmith */ 61765245Smsmith#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 61865245Smsmith#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 61965245Smsmith#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 62065245Smsmith#define AMR_SINTR_VALID 0x40 /* in SINTR */ 62165245Smsmith#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 62265245Smsmith#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 62365245Smsmith 62465245Smsmith/* 62565245Smsmith * Initialisation status 62665245Smsmith */ 62765245Smsmith#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 62865245Smsmith#define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 62965245Smsmith#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 63065245Smsmith#define AMR_SINIT_INPROG 0x11 /* init in progress */ 63165245Smsmith#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 63265245Smsmith#define AMR_SINIT_DONE 0x99 /* init successfully done */ 63365245Smsmith 63465245Smsmith/* 63565245Smsmith * I/O primitives 63665245Smsmith */ 63765245Smsmith#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 63865245Smsmith#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 63965245Smsmith#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 64065245Smsmith#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 64165245Smsmith#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 64265245Smsmith#define AMR_SENABLE_INTR(sc) \ 64365245Smsmith bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 64465245Smsmith bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 64565245Smsmith#define AMR_SDISABLE_INTR(sc) \ 64665245Smsmith bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 64765245Smsmith bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 64865245Smsmith#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 64965245Smsmith 65065245Smsmith#ifdef AMR_BOARD_INIT 65165245Smsmith#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 65265245Smsmith#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 65365245Smsmith#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 65465245Smsmith#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 65565245Smsmith#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 65665245Smsmith#endif 65765245Smsmith 65887796Sjhb#endif /* _KERNEL */ 659