amdsbwd.c revision 335537
1/*- 2 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 29 * southbridges. 30 * Please see the following specifications for the descriptions of the 31 * registers and flags: 32 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 33 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 34 * - AMD SB700/710/750 Register Reference Guide (RRG) 35 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 36 * - AMD SB700/710/750 Register Programming Requirements (RPR) 37 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 38 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 39 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 40 * Please see the following for Watchdog Resource Table specification: 41 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 42 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 43 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 44 * specifications, but the table hasn't been spotted in the wild yet. 45 */ 46 47#include <sys/cdefs.h> 48__FBSDID("$FreeBSD: stable/11/sys/dev/amdsbwd/amdsbwd.c 335537 2018-06-22 09:20:00Z avg $"); 49 50#include <sys/param.h> 51#include <sys/kernel.h> 52#include <sys/module.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/bus.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#include <machine/resource.h> 59#include <sys/watchdog.h> 60 61#include <dev/pci/pcivar.h> 62#include <dev/amdsbwd/amd_chipset.h> 63#include <isa/isavar.h> 64 65/* 66 * Registers in the Watchdog IO space. 67 * See SB7xx RRG 2.3.4, WDRT. 68 */ 69#define AMDSB_WD_CTRL 0x00 70#define AMDSB_WD_RUN 0x01 71#define AMDSB_WD_FIRED 0x02 72#define AMDSB_WD_SHUTDOWN 0x04 73#define AMDSB_WD_DISABLE 0x08 74#define AMDSB_WD_RESERVED 0x70 75#define AMDSB_WD_RELOAD 0x80 76#define AMDSB_WD_COUNT 0x04 77#define AMDSB_WD_COUNT_MASK 0xffff 78#define AMDSB_WDIO_REG_WIDTH 4 79 80#define amdsbwd_verbose_printf(dev, ...) \ 81 do { \ 82 if (bootverbose) \ 83 device_printf(dev, __VA_ARGS__);\ 84 } while (0) 85 86struct amdsbwd_softc { 87 device_t dev; 88 eventhandler_tag ev_tag; 89 struct resource *res_ctrl; 90 struct resource *res_count; 91 int rid_ctrl; 92 int rid_count; 93 int ms_per_tick; 94 int max_ticks; 95 int active; 96 unsigned int timeout; 97}; 98 99static void amdsbwd_identify(driver_t *driver, device_t parent); 100static int amdsbwd_probe(device_t dev); 101static int amdsbwd_attach(device_t dev); 102static int amdsbwd_detach(device_t dev); 103static int amdsbwd_suspend(device_t dev); 104static int amdsbwd_resume(device_t dev); 105 106static device_method_t amdsbwd_methods[] = { 107 DEVMETHOD(device_identify, amdsbwd_identify), 108 DEVMETHOD(device_probe, amdsbwd_probe), 109 DEVMETHOD(device_attach, amdsbwd_attach), 110 DEVMETHOD(device_detach, amdsbwd_detach), 111 DEVMETHOD(device_suspend, amdsbwd_suspend), 112 DEVMETHOD(device_resume, amdsbwd_resume), 113#if 0 114 DEVMETHOD(device_shutdown, amdsbwd_detach), 115#endif 116 DEVMETHOD_END 117}; 118 119static devclass_t amdsbwd_devclass; 120static driver_t amdsbwd_driver = { 121 "amdsbwd", 122 amdsbwd_methods, 123 sizeof(struct amdsbwd_softc) 124}; 125 126DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); 127 128 129static uint8_t 130pmio_read(struct resource *res, uint8_t reg) 131{ 132 bus_write_1(res, 0, reg); /* Index */ 133 return (bus_read_1(res, 1)); /* Data */ 134} 135 136static void 137pmio_write(struct resource *res, uint8_t reg, uint8_t val) 138{ 139 bus_write_1(res, 0, reg); /* Index */ 140 bus_write_1(res, 1, val); /* Data */ 141} 142 143static uint32_t 144wdctrl_read(struct amdsbwd_softc *sc) 145{ 146 return (bus_read_4(sc->res_ctrl, 0)); 147} 148 149static void 150wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 151{ 152 bus_write_4(sc->res_ctrl, 0, val); 153} 154 155static __unused uint32_t 156wdcount_read(struct amdsbwd_softc *sc) 157{ 158 return (bus_read_4(sc->res_count, 0)); 159} 160 161static void 162wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 163{ 164 bus_write_4(sc->res_count, 0, val); 165} 166 167static void 168amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 169{ 170 uint32_t val; 171 172 val = wdctrl_read(sc); 173 val |= AMDSB_WD_RUN; 174 wdctrl_write(sc, val); 175 sc->active = 1; 176 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 177} 178 179static void 180amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 181{ 182 uint32_t val; 183 184 val = wdctrl_read(sc); 185 val &= ~AMDSB_WD_RUN; 186 wdctrl_write(sc, val); 187 sc->active = 0; 188 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 189} 190 191static void 192amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 193{ 194 uint32_t val; 195 196 val = wdctrl_read(sc); 197 val |= AMDSB_WD_RELOAD; 198 wdctrl_write(sc, val); 199} 200 201static void 202amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 203{ 204 205 timeout &= AMDSB_WD_COUNT_MASK; 206 wdcount_write(sc, timeout); 207 sc->timeout = timeout; 208 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 209} 210 211static void 212amdsbwd_event(void *arg, unsigned int cmd, int *error) 213{ 214 struct amdsbwd_softc *sc = arg; 215 uint64_t timeout; 216 217 if (cmd != 0) { 218 timeout = 0; 219 cmd &= WD_INTERVAL; 220 if (cmd >= WD_TO_1MS) { 221 timeout = (uint64_t)1 << (cmd - WD_TO_1MS); 222 timeout = timeout / sc->ms_per_tick; 223 } 224 /* For a too short timeout use 1 tick. */ 225 if (timeout == 0) 226 timeout = 1; 227 /* For a too long timeout stop the timer. */ 228 if (timeout > sc->max_ticks) 229 timeout = 0; 230 } else { 231 timeout = 0; 232 } 233 234 if (timeout != 0) { 235 if (timeout != sc->timeout) 236 amdsbwd_tmr_set(sc, timeout); 237 if (!sc->active) 238 amdsbwd_tmr_enable(sc); 239 amdsbwd_tmr_reload(sc); 240 *error = 0; 241 } else { 242 if (sc->active) 243 amdsbwd_tmr_disable(sc); 244 } 245} 246 247static void 248amdsbwd_identify(driver_t *driver, device_t parent) 249{ 250 device_t child; 251 device_t smb_dev; 252 253 if (resource_disabled("amdsbwd", 0)) 254 return; 255 if (device_find_child(parent, "amdsbwd", -1) != NULL) 256 return; 257 258 /* 259 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 260 * that should be present at bus 0, device 20, function 0. 261 */ 262 smb_dev = pci_find_bsf(0, 20, 0); 263 if (smb_dev == NULL) 264 return; 265 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID && 266 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID && 267 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID) 268 return; 269 270 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1); 271 if (child == NULL) 272 device_printf(parent, "add amdsbwd child failed\n"); 273} 274 275 276static void 277amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 278{ 279 uint8_t val; 280 int i; 281 282 /* Report cause of previous reset for user's convenience. */ 283 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 284 if (val != 0) 285 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 286 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 287 if (val != 0) 288 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 289 if ((val & AMDSB_WD_RST_STS) != 0) 290 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 291 292 /* Find base address of memory mapped WDT registers. */ 293 for (*addr = 0, i = 0; i < 4; i++) { 294 *addr <<= 8; 295 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 296 } 297 *addr &= ~0x07u; 298 299 /* Set watchdog timer tick to 1s. */ 300 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 301 val &= ~AMDSB_WDT_RES_MASK; 302 val |= AMDSB_WDT_RES_1S; 303 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 304 305 /* Enable watchdog device (in stopped state). */ 306 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 307 val &= ~AMDSB_WDT_DISABLE; 308 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 309 310 /* 311 * XXX TODO: Ensure that watchdog decode is enabled 312 * (register 0x41, bit 3). 313 */ 314 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 315} 316 317static void 318amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 319{ 320 uint8_t val; 321 int i; 322 323 /* Report cause of previous reset for user's convenience. */ 324 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); 325 if (val != 0) 326 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 327 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); 328 if (val != 0) 329 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 330 if ((val & AMDSB8_WD_RST_STS) != 0) 331 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 332 333 /* Find base address of memory mapped WDT registers. */ 334 for (*addr = 0, i = 0; i < 4; i++) { 335 *addr <<= 8; 336 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 337 } 338 *addr &= ~0x07u; 339 340 /* Set watchdog timer tick to 1s. */ 341 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 342 val &= ~AMDSB8_WDT_RES_MASK; 343 val |= AMDSB8_WDT_1HZ; 344 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 345#ifdef AMDSBWD_DEBUG 346 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 347 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val); 348#endif 349 350 /* 351 * Enable watchdog device (in stopped state) 352 * and decoding of its address. 353 */ 354 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 355 val &= ~AMDSB8_WDT_DISABLE; 356 val |= AMDSB8_WDT_DEC_EN; 357 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 358#ifdef AMDSBWD_DEBUG 359 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 360 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val); 361#endif 362 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer"); 363} 364 365static void 366amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr) 367{ 368 uint8_t val; 369 370 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL); 371 if ((val & AMDFCH41_MMIO_EN) != 0) { 372 /* Fixed offset for the watchdog within ACPI MMIO range. */ 373 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n"); 374 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF; 375 } else { 376 /* 377 * Enable decoding of watchdog MMIO address. 378 */ 379 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 380 val |= AMDFCH41_WDT_EN; 381 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); 382#ifdef AMDSBWD_DEBUG 383 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 384 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", 385 val); 386#endif 387 388 /* Special fixed MMIO range for the watchdog. */ 389 *addr = AMDFCH41_WDT_FIXED_ADDR; 390 } 391 392 /* 393 * Set watchdog timer tick to 1s and 394 * enable the watchdog device (in stopped state). 395 */ 396 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 397 val &= ~AMDFCH41_WDT_RES_MASK; 398 val |= AMDFCH41_WDT_RES_1S; 399 val &= ~AMDFCH41_WDT_EN_MASK; 400 val |= AMDFCH41_WDT_ENABLE; 401 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val); 402#ifdef AMDSBWD_DEBUG 403 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 404 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n", 405 val); 406#endif 407 device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer"); 408} 409 410static int 411amdsbwd_probe(device_t dev) 412{ 413 struct resource *res; 414 device_t smb_dev; 415 uint32_t addr; 416 int rid; 417 int rc; 418 uint32_t devid; 419 uint8_t revid; 420 421 /* Do not claim some ISA PnP device by accident. */ 422 if (isa_get_logicalid(dev) != 0) 423 return (ENXIO); 424 425 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 426 AMDSB_PMIO_WIDTH); 427 if (rc != 0) { 428 device_printf(dev, "bus_set_resource for IO failed\n"); 429 return (ENXIO); 430 } 431 rid = 0; 432 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 433 RF_ACTIVE | RF_SHAREABLE); 434 if (res == NULL) { 435 device_printf(dev, "bus_alloc_resource for IO failed\n"); 436 return (ENXIO); 437 } 438 439 smb_dev = pci_find_bsf(0, 20, 0); 440 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 441 devid = pci_get_devid(smb_dev); 442 revid = pci_get_revid(smb_dev); 443 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID) 444 amdsbwd_probe_sb7xx(dev, res, &addr); 445 else if (devid == AMDSB_SMBUS_DEVID || 446 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || 447 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) 448 amdsbwd_probe_sb8xx(dev, res, &addr); 449 else 450 amdsbwd_probe_fch41(dev, res, &addr); 451 452 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 453 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 454 455 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 456 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 457 AMDSB_WDIO_REG_WIDTH); 458 if (rc != 0) { 459 device_printf(dev, "bus_set_resource for control failed\n"); 460 return (ENXIO); 461 } 462 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 463 AMDSB_WDIO_REG_WIDTH); 464 if (rc != 0) { 465 device_printf(dev, "bus_set_resource for count failed\n"); 466 return (ENXIO); 467 } 468 469 return (0); 470} 471 472static int 473amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 474{ 475 476 sc->max_ticks = UINT16_MAX; 477 sc->rid_ctrl = 0; 478 sc->rid_count = 1; 479 480 sc->ms_per_tick = 1000; 481 482 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 483 &sc->rid_ctrl, RF_ACTIVE); 484 if (sc->res_ctrl == NULL) { 485 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 486 return (ENXIO); 487 } 488 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 489 &sc->rid_count, RF_ACTIVE); 490 if (sc->res_count == NULL) { 491 device_printf(dev, "bus_alloc_resource for count failed\n"); 492 return (ENXIO); 493 } 494 return (0); 495} 496 497static int 498amdsbwd_attach(device_t dev) 499{ 500 struct amdsbwd_softc *sc; 501 int rc; 502 503 sc = device_get_softc(dev); 504 sc->dev = dev; 505 506 rc = amdsbwd_attach_sb(dev, sc); 507 if (rc != 0) 508 goto fail; 509 510#ifdef AMDSBWD_DEBUG 511 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 512 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 513#endif 514 515 /* Setup initial state of Watchdog Control. */ 516 wdctrl_write(sc, AMDSB_WD_FIRED); 517 518 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 519 device_printf(dev, "watchdog hardware is disabled\n"); 520 goto fail; 521 } 522 523 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc, 524 EVENTHANDLER_PRI_ANY); 525 526 return (0); 527 528fail: 529 amdsbwd_detach(dev); 530 return (ENXIO); 531} 532 533static int 534amdsbwd_detach(device_t dev) 535{ 536 struct amdsbwd_softc *sc; 537 538 sc = device_get_softc(dev); 539 if (sc->ev_tag != NULL) 540 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 541 542 if (sc->active) 543 amdsbwd_tmr_disable(sc); 544 545 if (sc->res_ctrl != NULL) 546 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 547 sc->res_ctrl); 548 549 if (sc->res_count != NULL) 550 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 551 sc->res_count); 552 553 return (0); 554} 555 556static int 557amdsbwd_suspend(device_t dev) 558{ 559 struct amdsbwd_softc *sc; 560 uint32_t val; 561 562 sc = device_get_softc(dev); 563 val = wdctrl_read(sc); 564 val &= ~AMDSB_WD_RUN; 565 wdctrl_write(sc, val); 566 return (0); 567} 568 569static int 570amdsbwd_resume(device_t dev) 571{ 572 struct amdsbwd_softc *sc; 573 574 sc = device_get_softc(dev); 575 wdctrl_write(sc, AMDSB_WD_FIRED); 576 if (sc->active) { 577 amdsbwd_tmr_set(sc, sc->timeout); 578 amdsbwd_tmr_enable(sc); 579 amdsbwd_tmr_reload(sc); 580 } 581 return (0); 582} 583