1239676Srwatson/*- 2239676Srwatson * Copyright (c) 2011-2012 Robert N. M. Watson 3239676Srwatson * All rights reserved. 4239676Srwatson * 5239676Srwatson * This software was developed by SRI International and the University of 6239676Srwatson * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7239676Srwatson * ("CTSRD"), as part of the DARPA CRASH research programme. 8239676Srwatson * 9239676Srwatson * Redistribution and use in source and binary forms, with or without 10239676Srwatson * modification, are permitted provided that the following conditions 11239676Srwatson * are met: 12239676Srwatson * 1. Redistributions of source code must retain the above copyright 13239676Srwatson * notice, this list of conditions and the following disclaimer. 14239676Srwatson * 2. Redistributions in binary form must reproduce the above copyright 15239676Srwatson * notice, this list of conditions and the following disclaimer in the 16239676Srwatson * documentation and/or other materials provided with the distribution. 17239676Srwatson * 18239676Srwatson * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19239676Srwatson * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20239676Srwatson * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21239676Srwatson * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22239676Srwatson * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23239676Srwatson * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24239676Srwatson * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25239676Srwatson * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26239676Srwatson * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27239676Srwatson * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28239676Srwatson * SUCH DAMAGE. 29239676Srwatson */ 30239676Srwatson 31239676Srwatson#include <sys/cdefs.h> 32239676Srwatson__FBSDID("$FreeBSD$"); 33239676Srwatson 34239676Srwatson#include <sys/param.h> 35245380Srwatson#include <sys/bus.h> 36239676Srwatson#include <sys/cons.h> 37239676Srwatson#include <sys/endian.h> 38239676Srwatson#include <sys/kdb.h> 39239676Srwatson#include <sys/kernel.h> 40239676Srwatson#include <sys/lock.h> 41239676Srwatson#include <sys/mutex.h> 42239676Srwatson#include <sys/reboot.h> 43239676Srwatson#include <sys/systm.h> 44239676Srwatson#include <sys/tty.h> 45239676Srwatson 46239676Srwatson#include <ddb/ddb.h> 47239676Srwatson 48239676Srwatson#include <dev/altera/jtag_uart/altera_jtag_uart.h> 49239676Srwatson 50245380Srwatsondevclass_t altera_jtag_uart_devclass; 51245380Srwatson 52239676Srwatson/* 53239676Srwatson * One-byte buffer as we can't check whether the UART is readable without 54239676Srwatson * actually reading from it, synchronised by a spinlock; this lock also 55239676Srwatson * synchronises access to the I/O ports for non-atomic sequences. These 56239676Srwatson * symbols are public so that the TTY layer can use them when working on an 57239676Srwatson * instance of the UART that is also a low-level console. 58239676Srwatson */ 59239676Srwatsonchar aju_cons_buffer_data; 60239676Srwatsonint aju_cons_buffer_valid; 61239676Srwatsonint aju_cons_jtag_present; 62239676Srwatsonu_int aju_cons_jtag_missed; 63239676Srwatsonstruct mtx aju_cons_lock; 64239676Srwatson 65239676Srwatson/* 66239676Srwatson * Low-level console driver functions. 67239676Srwatson */ 68239676Srwatsonstatic cn_probe_t aju_cnprobe; 69239676Srwatsonstatic cn_init_t aju_cninit; 70239676Srwatsonstatic cn_term_t aju_cnterm; 71239676Srwatsonstatic cn_getc_t aju_cngetc; 72239676Srwatsonstatic cn_putc_t aju_cnputc; 73239676Srwatsonstatic cn_grab_t aju_cngrab; 74239676Srwatsonstatic cn_ungrab_t aju_cnungrab; 75239676Srwatson 76239676Srwatson/* 77239676Srwatson * JTAG sets the ALTERA_JTAG_UART_CONTROL_AC bit whenever it accesses the 78239676Srwatson * FIFO. This allows us to (sort of) tell when JTAG is present, so that we 79239676Srwatson * can adopt lossy, rather than blocking, behaviour when JTAG isn't there. 80239676Srwatson * When it is present, we do full flow control. This delay is how long we 81239676Srwatson * wait to see if JTAG has really disappeared when finding a full buffer and 82239676Srwatson * no AC bit set. 83239676Srwatson */ 84239676Srwatson#define ALTERA_JTAG_UART_AC_POLL_DELAY 10000 85239676Srwatson 86239676Srwatson/* 87239676Srwatson * I/O routines lifted from Deimos. This is not only MIPS-specific, but also 88240518Seadler * BERI-specific, as we're hard coding the address at which we expect to 89239676Srwatson * find the Altera JTAG UART and using it unconditionally. We use these 90239676Srwatson * low-level routines so that we can perform console I/O long before newbus 91239676Srwatson * has initialised and devices have attached. The TTY layer of the driver 92239676Srwatson * knows about this, and uses the console-layer spinlock instead of the 93239676Srwatson * TTY-layer lock to avoid confusion between layers for the console UART. 94239676Srwatson * 95239676Srwatson * XXXRW: The only place this inter-layer behaviour breaks down is if the 96239676Srwatson * low-level console is used for polled read while the TTY driver is also 97239676Srwatson * looking for input. Probably we should also share buffers between layers. 98239676Srwatson */ 99239676Srwatson#define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000 100239676Srwatson 101239676Srwatsontypedef uint64_t paddr_t; 102239676Srwatsontypedef uint64_t vaddr_t; 103239676Srwatson 104239676Srwatsonstatic inline vaddr_t 105239676Srwatsonmips_phys_to_uncached(paddr_t phys) 106239676Srwatson{ 107239676Srwatson 108239676Srwatson return (phys | MIPS_XKPHYS_UNCACHED_BASE); 109239676Srwatson} 110239676Srwatson 111239676Srwatsonstatic inline uint32_t 112239676Srwatsonmips_ioread_uint32(vaddr_t vaddr) 113239676Srwatson{ 114239676Srwatson uint32_t v; 115239676Srwatson 116239676Srwatson __asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr)); 117239676Srwatson return (v); 118239676Srwatson} 119239676Srwatson 120239676Srwatsonstatic inline void 121239676Srwatsonmips_iowrite_uint32(vaddr_t vaddr, uint32_t v) 122239676Srwatson{ 123239676Srwatson 124239676Srwatson __asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr)); 125239676Srwatson} 126239676Srwatson 127239676Srwatson/* 128239676Srwatson * Little-endian versions of 32-bit I/O routines. 129239676Srwatson */ 130239676Srwatsonstatic inline uint32_t 131239676Srwatsonmips_ioread_uint32le(vaddr_t vaddr) 132239676Srwatson{ 133239676Srwatson 134239676Srwatson return (le32toh(mips_ioread_uint32(vaddr))); 135239676Srwatson} 136239676Srwatson 137239676Srwatsonstatic inline void 138239676Srwatsonmips_iowrite_uint32le(vaddr_t vaddr, uint32_t v) 139239676Srwatson{ 140239676Srwatson 141239676Srwatson mips_iowrite_uint32(vaddr, htole32(v)); 142239676Srwatson} 143239676Srwatson 144239676Srwatson/* 145239676Srwatson * Low-level read and write register routines; the Altera UART is little 146239676Srwatson * endian, so we byte swap 32-bit reads and writes. 147239676Srwatson */ 148239676Srwatsonstatic inline uint32_t 149239676Srwatsonaju_cons_data_read(void) 150239676Srwatson{ 151239676Srwatson 152239676Srwatson return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 153239676Srwatson ALTERA_JTAG_UART_DATA_OFF))); 154239676Srwatson} 155239676Srwatson 156239676Srwatsonstatic inline void 157239676Srwatsonaju_cons_data_write(uint32_t v) 158239676Srwatson{ 159239676Srwatson 160239676Srwatson mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 161239676Srwatson ALTERA_JTAG_UART_DATA_OFF), v); 162239676Srwatson} 163239676Srwatson 164239676Srwatsonstatic inline uint32_t 165239676Srwatsonaju_cons_control_read(void) 166239676Srwatson{ 167239676Srwatson 168239676Srwatson return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 169239676Srwatson ALTERA_JTAG_UART_CONTROL_OFF))); 170239676Srwatson} 171239676Srwatson 172239676Srwatsonstatic inline void 173239676Srwatsonaju_cons_control_write(uint32_t v) 174239676Srwatson{ 175239676Srwatson 176239676Srwatson mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 177239676Srwatson ALTERA_JTAG_UART_CONTROL_OFF), v); 178239676Srwatson} 179239676Srwatson 180239676Srwatson/* 181239676Srwatson * Slightly higher-level routines aware of buffering and flow control. 182239676Srwatson */ 183239676Srwatsonstatic int 184239676Srwatsonaju_cons_readable(void) 185239676Srwatson{ 186239676Srwatson uint32_t v; 187239676Srwatson 188239676Srwatson AJU_CONSOLE_LOCK_ASSERT(); 189239676Srwatson 190239676Srwatson if (aju_cons_buffer_valid) 191239676Srwatson return (1); 192239676Srwatson v = aju_cons_data_read(); 193239676Srwatson if ((v & ALTERA_JTAG_UART_DATA_RVALID) != 0) { 194239676Srwatson aju_cons_buffer_valid = 1; 195239676Srwatson aju_cons_buffer_data = (v & ALTERA_JTAG_UART_DATA_DATA); 196239676Srwatson return (1); 197239676Srwatson } 198239676Srwatson return (0); 199239676Srwatson} 200239676Srwatson 201239676Srwatsonstatic void 202239676Srwatsonaju_cons_write(char ch) 203239676Srwatson{ 204239676Srwatson uint32_t v; 205239676Srwatson 206239676Srwatson AJU_CONSOLE_LOCK_ASSERT(); 207239676Srwatson 208239676Srwatson /* 209239676Srwatson * The flow control logic here is somewhat subtle: we want to wait for 210239676Srwatson * write buffer space only while JTAG is present. However, we can't 211239676Srwatson * directly ask if JTAG is present -- just whether it's been seen 212239676Srwatson * since we last cleared the ALTERA_JTAG_UART_CONTROL_AC bit. As 213239676Srwatson * such, implement a polling loop in which we both wait for space and 214239676Srwatson * try to decide whether JTAG has disappeared on us. We will have to 215239676Srwatson * wait one complete polling delay to detect that JTAG has gone away, 216239676Srwatson * but otherwise shouldn't wait any further once it has gone. And we 217239676Srwatson * had to wait for buffer space anyway, if it was there. 218239676Srwatson * 219239676Srwatson * If JTAG is spotted, reset the TTY-layer miss counter so console- 220239676Srwatson * layer clearing of the bit doesn't trigger a TTY-layer 221239676Srwatson * disconnection. 222239676Srwatson * 223239676Srwatson * XXXRW: The polling delay may require tuning. 224274821Sbrooks * 225274821Sbrooks * XXXRW: Notice the inherent race with hardware: in clearing the 226274821Sbrooks * bit, we may race with hardware setting the same bit. 227239676Srwatson */ 228239676Srwatson v = aju_cons_control_read(); 229239676Srwatson if (v & ALTERA_JTAG_UART_CONTROL_AC) { 230239676Srwatson aju_cons_jtag_present = 1; 231239676Srwatson aju_cons_jtag_missed = 0; 232239676Srwatson v &= ~ALTERA_JTAG_UART_CONTROL_AC; 233239676Srwatson aju_cons_control_write(v); 234239676Srwatson } 235239676Srwatson while ((v & ALTERA_JTAG_UART_CONTROL_WSPACE) == 0) { 236239676Srwatson if (!aju_cons_jtag_present) 237239676Srwatson return; 238239676Srwatson DELAY(ALTERA_JTAG_UART_AC_POLL_DELAY); 239239676Srwatson v = aju_cons_control_read(); 240239676Srwatson if (v & ALTERA_JTAG_UART_CONTROL_AC) { 241239676Srwatson aju_cons_jtag_present = 1; 242239676Srwatson v &= ~ALTERA_JTAG_UART_CONTROL_AC; 243239676Srwatson aju_cons_control_write(v); 244239676Srwatson } else 245239676Srwatson aju_cons_jtag_present = 0; 246239676Srwatson } 247239676Srwatson aju_cons_data_write(ch); 248239676Srwatson} 249239676Srwatson 250239676Srwatsonstatic char 251239676Srwatsonaju_cons_read(void) 252239676Srwatson{ 253239676Srwatson 254239676Srwatson AJU_CONSOLE_LOCK_ASSERT(); 255239676Srwatson 256239676Srwatson while (!aju_cons_readable()); 257239676Srwatson aju_cons_buffer_valid = 0; 258239676Srwatson return (aju_cons_buffer_data); 259239676Srwatson} 260239676Srwatson 261239676Srwatson/* 262239676Srwatson * Implementation of a FreeBSD low-level, polled console driver. 263239676Srwatson */ 264239676Srwatsonstatic void 265239676Srwatsonaju_cnprobe(struct consdev *cp) 266239676Srwatson{ 267239676Srwatson 268239676Srwatson sprintf(cp->cn_name, "%s%d", AJU_TTYNAME, 0); 269239676Srwatson cp->cn_pri = (boothowto & RB_SERIAL) ? CN_REMOTE : CN_NORMAL; 270239676Srwatson} 271239676Srwatson 272239676Srwatsonstatic void 273239676Srwatsonaju_cninit(struct consdev *cp) 274239676Srwatson{ 275239676Srwatson uint32_t v; 276239676Srwatson 277239676Srwatson AJU_CONSOLE_LOCK_INIT(); 278239676Srwatson 279239676Srwatson AJU_CONSOLE_LOCK(); 280239676Srwatson v = aju_cons_control_read(); 281239676Srwatson v &= ~ALTERA_JTAG_UART_CONTROL_AC; 282239676Srwatson aju_cons_control_write(v); 283239676Srwatson AJU_CONSOLE_UNLOCK(); 284239676Srwatson} 285239676Srwatson 286239676Srwatsonstatic void 287239676Srwatsonaju_cnterm(struct consdev *cp) 288239676Srwatson{ 289239676Srwatson 290239676Srwatson} 291239676Srwatson 292239676Srwatsonstatic int 293239676Srwatsonaju_cngetc(struct consdev *cp) 294239676Srwatson{ 295239676Srwatson int ret; 296239676Srwatson 297239676Srwatson AJU_CONSOLE_LOCK(); 298239676Srwatson ret = aju_cons_read(); 299239676Srwatson AJU_CONSOLE_UNLOCK(); 300239676Srwatson return (ret); 301239676Srwatson} 302239676Srwatson 303239676Srwatsonstatic void 304239676Srwatsonaju_cnputc(struct consdev *cp, int c) 305239676Srwatson{ 306239676Srwatson 307239676Srwatson AJU_CONSOLE_LOCK(); 308239676Srwatson aju_cons_write(c); 309239676Srwatson AJU_CONSOLE_UNLOCK(); 310239676Srwatson} 311239676Srwatson 312239676Srwatsonstatic void 313239676Srwatsonaju_cngrab(struct consdev *cp) 314239676Srwatson{ 315239676Srwatson 316239676Srwatson} 317239676Srwatson 318239676Srwatsonstatic void 319239676Srwatsonaju_cnungrab(struct consdev *cp) 320239676Srwatson{ 321239676Srwatson 322239676Srwatson} 323239676Srwatson 324239676SrwatsonCONSOLE_DRIVER(aju); 325