1184870Syongari/*- 2184870Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3184870Syongari * All rights reserved. 4184870Syongari * 5184870Syongari * Redistribution and use in source and binary forms, with or without 6184870Syongari * modification, are permitted provided that the following conditions 7184870Syongari * are met: 8184870Syongari * 1. Redistributions of source code must retain the above copyright 9184870Syongari * notice unmodified, this list of conditions, and the following 10184870Syongari * disclaimer. 11184870Syongari * 2. Redistributions in binary form must reproduce the above copyright 12184870Syongari * notice, this list of conditions and the following disclaimer in the 13184870Syongari * documentation and/or other materials provided with the distribution. 14184870Syongari * 15184870Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16184870Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17184870Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18184870Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19184870Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20222107Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21184870Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22184870Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23184870Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24184870Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25222107Syongari * SUCH DAMAGE. 26184870Syongari * 27184870Syongari * $FreeBSD$ 28184870Syongari */ 29184870Syongari 30184870Syongari#ifndef _IF_ALEREG_H 31184870Syongari#define _IF_ALEREG_H 32184870Syongari 33184870Syongari/* 34184870Syongari * Atheros Communucations, Inc. PCI vendor ID 35184870Syongari */ 36184870Syongari#define VENDORID_ATHEROS 0x1969 37184870Syongari 38184870Syongari/* 39184870Syongari * Atheros AR8121/AR8113/AR8114 device ID 40184870Syongari */ 41184870Syongari#define DEVICEID_ATHEROS_AR81XX 0x1026 42184870Syongari 43184870Syongari#define ALE_SPI_CTRL 0x200 44184870Syongari#define SPI_VPD_ENB 0x00002000 45184870Syongari 46184870Syongari#define ALE_SPI_ADDR 0x204 /* 16bits */ 47184870Syongari 48184870Syongari#define ALE_SPI_DATA 0x208 49184870Syongari 50184870Syongari#define ALE_SPI_CONFIG 0x20C 51184870Syongari 52184870Syongari#define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */ 53184870Syongari 54184870Syongari#define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 55184870Syongari 56184870Syongari#define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 57184870Syongari 58184870Syongari#define ALE_SPI_OP_RDID 0x213 /* 8bits */ 59184870Syongari 60184870Syongari#define ALE_SPI_OP_WREN 0x214 /* 8bits */ 61184870Syongari 62184870Syongari#define ALE_SPI_OP_RDSR 0x215 /* 8bits */ 63184870Syongari 64184870Syongari#define ALE_SPI_OP_WRSR 0x216 /* 8bits */ 65184870Syongari 66184870Syongari#define ALE_SPI_OP_READ 0x217 /* 8bits */ 67184870Syongari 68184870Syongari#define ALE_TWSI_CTRL 0x218 69184870Syongari#define TWSI_CTRL_SW_LD_START 0x00000800 70184870Syongari#define TWSI_CTRL_HW_LD_START 0x00001000 71184870Syongari#define TWSI_CTRL_LD_EXIST 0x00400000 72184870Syongari 73184870Syongari#define ALE_DEV_MISC_CTRL 0x21C 74184870Syongari 75184870Syongari#define ALE_PCIE_PHYMISC 0x1000 76184870Syongari#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 77184870Syongari 78184870Syongari#define ALE_MASTER_CFG 0x1400 79184870Syongari#define MASTER_RESET 0x00000001 80184870Syongari#define MASTER_MTIMER_ENB 0x00000002 81184870Syongari#define MASTER_IM_TX_TIMER_ENB 0x00000004 82184870Syongari#define MASTER_MANUAL_INT_ENB 0x00000008 83184870Syongari#define MASTER_IM_RX_TIMER_ENB 0x00000020 84184870Syongari#define MASTER_INT_RDCLR 0x00000040 85184870Syongari#define MASTER_LED_MODE 0x00000200 86184870Syongari#define MASTER_CHIP_REV_MASK 0x00FF0000 87184870Syongari#define MASTER_CHIP_ID_MASK 0xFF000000 88184870Syongari#define MASTER_CHIP_REV_SHIFT 16 89184870Syongari#define MASTER_CHIP_ID_SHIFT 24 90184870Syongari 91184870Syongari/* Number of ticks per usec for AR81xx. */ 92184870Syongari#define ALE_TICK_USECS 2 93184870Syongari#define ALE_USECS(x) ((x) / ALE_TICK_USECS) 94184870Syongari 95184870Syongari#define ALE_MANUAL_TIMER 0x1404 96184870Syongari 97184870Syongari#define ALE_IM_TIMER 0x1408 98184870Syongari#define IM_TIMER_TX_MASK 0x0000FFFF 99184870Syongari#define IM_TIMER_RX_MASK 0xFFFF0000 100184870Syongari#define IM_TIMER_TX_SHIFT 0 101184870Syongari#define IM_TIMER_RX_SHIFT 16 102184870Syongari#define ALE_IM_TIMER_MIN 0 103184870Syongari#define ALE_IM_TIMER_MAX 130000 /* 130ms */ 104184870Syongari#define ALE_IM_RX_TIMER_DEFAULT 30 105184870Syongari#define ALE_IM_TX_TIMER_DEFAULT 1000 106184870Syongari 107184870Syongari#define ALE_GPHY_CTRL 0x140C /* 16bits */ 108184870Syongari#define GPHY_CTRL_EXT_RESET 0x0001 109184870Syongari#define GPHY_CTRL_PIPE_MOD 0x0002 110184870Syongari#define GPHY_CTRL_BERT_START 0x0010 111184870Syongari#define GPHY_CTRL_GALE_25M_ENB 0x0020 112184870Syongari#define GPHY_CTRL_LPW_EXIT 0x0040 113184870Syongari#define GPHY_CTRL_PHY_IDDQ 0x0080 114184870Syongari#define GPHY_CTRL_PHY_IDDQ_DIS 0x0100 115184870Syongari#define GPHY_CTRL_PCLK_SEL_DIS 0x0200 116184870Syongari#define GPHY_CTRL_HIB_EN 0x0400 117184870Syongari#define GPHY_CTRL_HIB_PULSE 0x0800 118184870Syongari#define GPHY_CTRL_SEL_ANA_RESET 0x1000 119184870Syongari#define GPHY_CTRL_PHY_PLL_ON 0x2000 120184870Syongari#define GPHY_CTRL_PWDOWN_HW 0x4000 121184870Syongari 122184870Syongari#define ALE_INTR_CLR_TIMER 0x140E /* 16bits */ 123184870Syongari 124184870Syongari#define ALE_IDLE_STATUS 0x1410 125184870Syongari#define IDLE_STATUS_RXMAC 0x00000001 126184870Syongari#define IDLE_STATUS_TXMAC 0x00000002 127184870Syongari#define IDLE_STATUS_RXQ 0x00000004 128184870Syongari#define IDLE_STATUS_TXQ 0x00000008 129184870Syongari#define IDLE_STATUS_DMARD 0x00000010 130184870Syongari#define IDLE_STATUS_DMAWR 0x00000020 131184870Syongari#define IDLE_STATUS_SMB 0x00000040 132184870Syongari#define IDLE_STATUS_CMB 0x00000080 133184870Syongari 134184870Syongari#define ALE_MDIO 0x1414 135184870Syongari#define MDIO_DATA_MASK 0x0000FFFF 136184870Syongari#define MDIO_REG_ADDR_MASK 0x001F0000 137184870Syongari#define MDIO_OP_READ 0x00200000 138184870Syongari#define MDIO_OP_WRITE 0x00000000 139184870Syongari#define MDIO_SUP_PREAMBLE 0x00400000 140184870Syongari#define MDIO_OP_EXECUTE 0x00800000 141184870Syongari#define MDIO_CLK_25_4 0x00000000 142184870Syongari#define MDIO_CLK_25_6 0x02000000 143184870Syongari#define MDIO_CLK_25_8 0x03000000 144184870Syongari#define MDIO_CLK_25_10 0x04000000 145184870Syongari#define MDIO_CLK_25_14 0x05000000 146184870Syongari#define MDIO_CLK_25_20 0x06000000 147184870Syongari#define MDIO_CLK_25_28 0x07000000 148184870Syongari#define MDIO_OP_BUSY 0x08000000 149184870Syongari#define MDIO_DATA_SHIFT 0 150184870Syongari#define MDIO_REG_ADDR_SHIFT 16 151184870Syongari 152184870Syongari#define MDIO_REG_ADDR(x) \ 153184870Syongari (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 154184870Syongari/* Default PHY address. */ 155184870Syongari#define ALE_PHY_ADDR 0 156184870Syongari 157184870Syongari#define ALE_PHY_STATUS 0x1418 158184870Syongari#define PHY_STATUS_100M 0x00020000 159184870Syongari 160184870Syongari/* Packet memory BIST. */ 161184870Syongari#define ALE_BIST0 0x141C 162184870Syongari#define BIST0_ENB 0x00000001 163184870Syongari#define BIST0_SRAM_FAIL 0x00000002 164184870Syongari#define BIST0_FUSE_FLAG 0x00000004 165184870Syongari 166184870Syongari/* PCIe retry buffer BIST. */ 167184870Syongari#define ALE_BIST1 0x1420 168184870Syongari#define BIST1_ENB 0x00000001 169184870Syongari#define BIST1_SRAM_FAIL 0x00000002 170184870Syongari#define BIST1_FUSE_FLAG 0x00000004 171184870Syongari 172184870Syongari#define ALE_SERDES_LOCK 0x1424 173184870Syongari#define SERDES_LOCK_DET 0x00000001 174184870Syongari#define SERDES_LOCK_DET_ENB 0x00000002 175184870Syongari 176184870Syongari#define ALE_MAC_CFG 0x1480 177184870Syongari#define MAC_CFG_TX_ENB 0x00000001 178184870Syongari#define MAC_CFG_RX_ENB 0x00000002 179184870Syongari#define MAC_CFG_TX_FC 0x00000004 180184870Syongari#define MAC_CFG_RX_FC 0x00000008 181184870Syongari#define MAC_CFG_LOOP 0x00000010 182184870Syongari#define MAC_CFG_FULL_DUPLEX 0x00000020 183184870Syongari#define MAC_CFG_TX_CRC_ENB 0x00000040 184184870Syongari#define MAC_CFG_TX_AUTO_PAD 0x00000080 185184870Syongari#define MAC_CFG_TX_LENCHK 0x00000100 186184870Syongari#define MAC_CFG_RX_JUMBO_ENB 0x00000200 187184870Syongari#define MAC_CFG_PREAMBLE_MASK 0x00003C00 188184870Syongari#define MAC_CFG_VLAN_TAG_STRIP 0x00004000 189184870Syongari#define MAC_CFG_PROMISC 0x00008000 190184870Syongari#define MAC_CFG_TX_PAUSE 0x00010000 191184870Syongari#define MAC_CFG_SCNT 0x00020000 192184870Syongari#define MAC_CFG_SYNC_RST_TX 0x00040000 193184870Syongari#define MAC_CFG_SPEED_MASK 0x00300000 194184870Syongari#define MAC_CFG_SPEED_10_100 0x00100000 195184870Syongari#define MAC_CFG_SPEED_1000 0x00200000 196184870Syongari#define MAC_CFG_DBG_TX_BACKOFF 0x00400000 197184870Syongari#define MAC_CFG_TX_JUMBO_ENB 0x00800000 198184870Syongari#define MAC_CFG_RXCSUM_ENB 0x01000000 199184870Syongari#define MAC_CFG_ALLMULTI 0x02000000 200184870Syongari#define MAC_CFG_BCAST 0x04000000 201184870Syongari#define MAC_CFG_DBG 0x08000000 202184870Syongari#define MAC_CFG_PREAMBLE_SHIFT 10 203184870Syongari#define MAC_CFG_PREAMBLE_DEFAULT 7 204184870Syongari 205184870Syongari#define ALE_IPG_IFG_CFG 0x1484 206184870Syongari#define IPG_IFG_IPGT_MASK 0x0000007F 207184870Syongari#define IPG_IFG_MIFG_MASK 0x0000FF00 208184870Syongari#define IPG_IFG_IPG1_MASK 0x007F0000 209184870Syongari#define IPG_IFG_IPG2_MASK 0x7F000000 210184870Syongari#define IPG_IFG_IPGT_SHIFT 0 211184870Syongari#define IPG_IFG_IPGT_DEFAULT 0x60 212184870Syongari#define IPG_IFG_MIFG_SHIFT 8 213184870Syongari#define IPG_IFG_MIFG_DEFAULT 0x50 214184870Syongari#define IPG_IFG_IPG1_SHIFT 16 215184870Syongari#define IPG_IFG_IPG1_DEFAULT 0x40 216184870Syongari#define IPG_IFG_IPG2_SHIFT 24 217184870Syongari#define IPG_IFG_IPG2_DEFAULT 0x60 218184870Syongari 219184870Syongari/* Station address. */ 220184870Syongari#define ALE_PAR0 0x1488 221184870Syongari#define ALE_PAR1 0x148C 222184870Syongari 223184870Syongari/* 64bit multicast hash register. */ 224184870Syongari#define ALE_MAR0 0x1490 225184870Syongari#define ALE_MAR1 0x1494 226184870Syongari 227184870Syongari/* half-duplex parameter configuration. */ 228184870Syongari#define ALE_HDPX_CFG 0x1498 229184870Syongari#define HDPX_CFG_LCOL_MASK 0x000003FF 230184870Syongari#define HDPX_CFG_RETRY_MASK 0x0000F000 231184870Syongari#define HDPX_CFG_EXC_DEF_EN 0x00010000 232184870Syongari#define HDPX_CFG_NO_BACK_C 0x00020000 233184870Syongari#define HDPX_CFG_NO_BACK_P 0x00040000 234184870Syongari#define HDPX_CFG_ABEBE 0x00080000 235184870Syongari#define HDPX_CFG_ABEBT_MASK 0x00F00000 236184870Syongari#define HDPX_CFG_JAMIPG_MASK 0x0F000000 237184870Syongari#define HDPX_CFG_LCOL_SHIFT 0 238184870Syongari#define HDPX_CFG_LCOL_DEFAULT 0x37 239184870Syongari#define HDPX_CFG_RETRY_SHIFT 12 240184870Syongari#define HDPX_CFG_RETRY_DEFAULT 0x0F 241184870Syongari#define HDPX_CFG_ABEBT_SHIFT 20 242184870Syongari#define HDPX_CFG_ABEBT_DEFAULT 0x0A 243184870Syongari#define HDPX_CFG_JAMIPG_SHIFT 24 244184870Syongari#define HDPX_CFG_JAMIPG_DEFAULT 0x07 245184870Syongari 246184870Syongari#define ALE_FRAME_SIZE 0x149C 247184870Syongari 248184870Syongari#define ALE_WOL_CFG 0x14A0 249184870Syongari#define WOL_CFG_PATTERN 0x00000001 250184870Syongari#define WOL_CFG_PATTERN_ENB 0x00000002 251184870Syongari#define WOL_CFG_MAGIC 0x00000004 252184870Syongari#define WOL_CFG_MAGIC_ENB 0x00000008 253184870Syongari#define WOL_CFG_LINK_CHG 0x00000010 254184870Syongari#define WOL_CFG_LINK_CHG_ENB 0x00000020 255184870Syongari#define WOL_CFG_PATTERN_DET 0x00000100 256184870Syongari#define WOL_CFG_MAGIC_DET 0x00000200 257184870Syongari#define WOL_CFG_LINK_CHG_DET 0x00000400 258184870Syongari#define WOL_CFG_CLK_SWITCH_ENB 0x00008000 259184870Syongari#define WOL_CFG_PATTERN0 0x00010000 260184870Syongari#define WOL_CFG_PATTERN1 0x00020000 261184870Syongari#define WOL_CFG_PATTERN2 0x00040000 262184870Syongari#define WOL_CFG_PATTERN3 0x00080000 263184870Syongari#define WOL_CFG_PATTERN4 0x00100000 264184870Syongari#define WOL_CFG_PATTERN5 0x00200000 265184870Syongari#define WOL_CFG_PATTERN6 0x00400000 266184870Syongari 267184870Syongari/* WOL pattern length. */ 268184870Syongari#define ALE_PATTERN_CFG0 0x14A4 269184870Syongari#define PATTERN_CFG_0_LEN_MASK 0x0000007F 270184870Syongari#define PATTERN_CFG_1_LEN_MASK 0x00007F00 271184870Syongari#define PATTERN_CFG_2_LEN_MASK 0x007F0000 272184870Syongari#define PATTERN_CFG_3_LEN_MASK 0x7F000000 273184870Syongari 274184870Syongari#define ALE_PATTERN_CFG1 0x14A8 275184870Syongari#define PATTERN_CFG_4_LEN_MASK 0x0000007F 276184870Syongari#define PATTERN_CFG_5_LEN_MASK 0x00007F00 277184870Syongari#define PATTERN_CFG_6_LEN_MASK 0x007F0000 278184870Syongari 279184870Syongari/* RSS */ 280184870Syongari#define ALE_RSS_KEY0 0x14B0 281184870Syongari 282184870Syongari#define ALE_RSS_KEY1 0x14B4 283184870Syongari 284184870Syongari#define ALE_RSS_KEY2 0x14B8 285184870Syongari 286184870Syongari#define ALE_RSS_KEY3 0x14BC 287184870Syongari 288184870Syongari#define ALE_RSS_KEY4 0x14C0 289184870Syongari 290184870Syongari#define ALE_RSS_KEY5 0x14C4 291184870Syongari 292184870Syongari#define ALE_RSS_KEY6 0x14C8 293184870Syongari 294184870Syongari#define ALE_RSS_KEY7 0x14CC 295184870Syongari 296184870Syongari#define ALE_RSS_KEY8 0x14D0 297184870Syongari 298184870Syongari#define ALE_RSS_KEY9 0x14D4 299184870Syongari 300184870Syongari#define ALE_RSS_IDT_TABLE4 0x14E0 301184870Syongari 302184870Syongari#define ALE_RSS_IDT_TABLE5 0x14E4 303184870Syongari 304184870Syongari#define ALE_RSS_IDT_TABLE6 0x14E8 305184870Syongari 306184870Syongari#define ALE_RSS_IDT_TABLE7 0x14EC 307184870Syongari 308184870Syongari#define ALE_SRAM_RD_ADDR 0x1500 309184870Syongari 310184870Syongari#define ALE_SRAM_RD_LEN 0x1504 311184870Syongari 312184870Syongari#define ALE_SRAM_RRD_ADDR 0x1508 313184870Syongari 314184870Syongari#define ALE_SRAM_RRD_LEN 0x150C 315184870Syongari 316184870Syongari#define ALE_SRAM_TPD_ADDR 0x1510 317184870Syongari 318184870Syongari#define ALE_SRAM_TPD_LEN 0x1514 319184870Syongari 320184870Syongari#define ALE_SRAM_TRD_ADDR 0x1518 321184870Syongari 322184870Syongari#define ALE_SRAM_TRD_LEN 0x151C 323184870Syongari 324184870Syongari#define ALE_SRAM_RX_FIFO_ADDR 0x1520 325184870Syongari 326184870Syongari#define ALE_SRAM_RX_FIFO_LEN 0x1524 327184870Syongari 328184870Syongari#define ALE_SRAM_TX_FIFO_ADDR 0x1528 329184870Syongari 330184870Syongari#define ALE_SRAM_TX_FIFO_LEN 0x152C 331184870Syongari 332184870Syongari#define ALE_SRAM_TCPH_ADDR 0x1530 333184870Syongari#define SRAM_TCPH_ADDR_MASK 0x00000FFF 334184870Syongari#define SRAM_PATH_ADDR_MASK 0x0FFF0000 335184870Syongari#define SRAM_TCPH_ADDR_SHIFT 0 336184870Syongari#define SRAM_PATH_ADDR_SHIFT 16 337184870Syongari 338184870Syongari#define ALE_DMA_BLOCK 0x1534 339184870Syongari#define DMA_BLOCK_LOAD 0x00000001 340184870Syongari 341184870Syongari#define ALE_RXF3_ADDR_HI 0x153C 342184870Syongari 343184870Syongari#define ALE_TPD_ADDR_HI 0x1540 344184870Syongari 345184870Syongari#define ALE_RXF0_PAGE0_ADDR_LO 0x1544 346184870Syongari 347184870Syongari#define ALE_RXF0_PAGE1_ADDR_LO 0x1548 348184870Syongari 349184870Syongari#define ALE_TPD_ADDR_LO 0x154C 350184870Syongari 351184870Syongari#define ALE_RXF1_ADDR_HI 0x1550 352184870Syongari 353184870Syongari#define ALE_RXF2_ADDR_HI 0x1554 354184870Syongari 355184870Syongari#define ALE_RXF_PAGE_SIZE 0x1558 356184870Syongari 357184870Syongari#define ALE_TPD_CNT 0x155C 358184870Syongari#define TPD_CNT_MASK 0x00003FF 359184870Syongari#define TPD_CNT_SHIFT 0 360184870Syongari 361184870Syongari#define ALE_RSS_IDT_TABLE0 0x1560 362184870Syongari 363184870Syongari#define ALE_RSS_IDT_TABLE1 0x1564 364184870Syongari 365184870Syongari#define ALE_RSS_IDT_TABLE2 0x1568 366184870Syongari 367184870Syongari#define ALE_RSS_IDT_TABLE3 0x156C 368184870Syongari 369184870Syongari#define ALE_RSS_HASH_VALUE 0x1570 370184870Syongari 371184870Syongari#define ALE_RSS_HASH_FLAG 0x1574 372184870Syongari 373184870Syongari#define ALE_RSS_CPU 0x157C 374184870Syongari 375184870Syongari#define ALE_TXQ_CFG 0x1580 376184870Syongari#define TXQ_CFG_TPD_BURST_MASK 0x0000000F 377184870Syongari#define TXQ_CFG_ENB 0x00000020 378184870Syongari#define TXQ_CFG_ENHANCED_MODE 0x00000040 379184870Syongari#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 380184870Syongari#define TXQ_CFG_TPD_BURST_SHIFT 0 381184870Syongari#define TXQ_CFG_TPD_BURST_DEFAULT 4 382184870Syongari#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 383184870Syongari#define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 384184870Syongari 385184870Syongari#define ALE_TX_JUMBO_THRESH 0x1584 386184870Syongari#define TX_JUMBO_THRESH_MASK 0x000007FF 387184870Syongari#define TX_JUMBO_THRESH_SHIFT 0 388184870Syongari#define TX_JUMBO_THRESH_UNIT 8 389184870Syongari#define TX_JUMBO_THRESH_UNIT_SHIFT 3 390184870Syongari 391184870Syongari#define ALE_RXQ_CFG 0x15A0 392184870Syongari#define RXQ_CFG_ALIGN_32 0x00000000 393184870Syongari#define RXQ_CFG_ALIGN_64 0x00000001 394184870Syongari#define RXQ_CFG_ALIGN_128 0x00000002 395184870Syongari#define RXQ_CFG_ALIGN_256 0x00000003 396184870Syongari#define RXQ_CFG_QUEUE1_ENB 0x00000010 397184870Syongari#define RXQ_CFG_QUEUE2_ENB 0x00000020 398184870Syongari#define RXQ_CFG_QUEUE3_ENB 0x00000040 399184870Syongari#define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080 400184870Syongari#define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 401184870Syongari#define RXQ_CFG_RSS_HASH_IPV4 0x00010000 402184870Syongari#define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 403184870Syongari#define RXQ_CFG_RSS_HASH_IPV6 0x00040000 404184870Syongari#define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 405184870Syongari#define RXQ_CFG_RSS_MODE_DIS 0x00000000 406184870Syongari#define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 407184870Syongari#define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 408184870Syongari#define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 409184870Syongari#define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 410184870Syongari#define RXQ_CFG_RSS_HASH_ENB 0x20000000 411184870Syongari#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 412184870Syongari#define RXQ_CFG_ENB 0x80000000 413184870Syongari#define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 414184870Syongari 415184870Syongari#define ALE_RX_JUMBO_THRESH 0x15A4 /* 16bits */ 416184870Syongari#define RX_JUMBO_THRESH_MASK 0x07FF 417184870Syongari#define RX_JUMBO_LKAH_MASK 0x7800 418184870Syongari#define RX_JUMBO_THRESH_MASK_SHIFT 0 419184870Syongari#define RX_JUMBO_THRESH_UNIT 8 420184870Syongari#define RX_JUMBO_THRESH_UNIT_SHIFT 3 421184870Syongari#define RX_JUMBO_LKAH_SHIFT 11 422184870Syongari#define RX_JUMBO_LKAH_DEFAULT 1 423184870Syongari 424184870Syongari#define ALE_RX_FIFO_PAUSE_THRESH 0x15A8 425184870Syongari#define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 426184870Syongari#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 427184870Syongari#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 428184870Syongari#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 429184870Syongari 430184870Syongari#define ALE_CMB_RXF1 0x15B4 431184870Syongari 432184870Syongari#define ALE_CMB_RXF2 0x15B8 433184870Syongari 434184870Syongari#define ALE_CMB_RXF3 0x15BC 435184870Syongari 436184870Syongari#define ALE_DMA_CFG 0x15C0 437184870Syongari#define DMA_CFG_IN_ORDER 0x00000001 438184870Syongari#define DMA_CFG_ENH_ORDER 0x00000002 439184870Syongari#define DMA_CFG_OUT_ORDER 0x00000004 440184870Syongari#define DMA_CFG_RCB_64 0x00000000 441184870Syongari#define DMA_CFG_RCB_128 0x00000008 442184870Syongari#define DMA_CFG_RD_BURST_128 0x00000000 443184870Syongari#define DMA_CFG_RD_BURST_256 0x00000010 444184870Syongari#define DMA_CFG_RD_BURST_512 0x00000020 445184870Syongari#define DMA_CFG_RD_BURST_1024 0x00000030 446184870Syongari#define DMA_CFG_RD_BURST_2048 0x00000040 447184870Syongari#define DMA_CFG_RD_BURST_4096 0x00000050 448184870Syongari#define DMA_CFG_WR_BURST_128 0x00000000 449184870Syongari#define DMA_CFG_WR_BURST_256 0x00000080 450184870Syongari#define DMA_CFG_WR_BURST_512 0x00000100 451184870Syongari#define DMA_CFG_WR_BURST_1024 0x00000180 452184870Syongari#define DMA_CFG_WR_BURST_2048 0x00000200 453184870Syongari#define DMA_CFG_WR_BURST_4096 0x00000280 454184870Syongari#define DMA_CFG_RD_REQ_PRI 0x00000400 455184870Syongari#define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 456184870Syongari#define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 457184870Syongari#define DMA_CFG_TXCMB_ENB 0x00100000 458184870Syongari#define DMA_CFG_RXCMB_ENB 0x00200000 459184870Syongari#define DMA_CFG_RD_BURST_MASK 0x07 460184870Syongari#define DMA_CFG_RD_BURST_SHIFT 4 461184870Syongari#define DMA_CFG_WR_BURST_MASK 0x07 462184870Syongari#define DMA_CFG_WR_BURST_SHIFT 7 463184870Syongari#define DMA_CFG_RD_DELAY_CNT_SHIFT 11 464184870Syongari#define DMA_CFG_WR_DELAY_CNT_SHIFT 16 465184870Syongari#define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 466184870Syongari#define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 467184870Syongari 468184870Syongari#define ALE_SMB_STAT_TIMER 0x15C4 469184870Syongari 470184870Syongari#define ALE_INT_TRIG_THRESH 0x15C8 471184870Syongari#define INT_TRIG_TX_THRESH_MASK 0x0000FFFF 472184870Syongari#define INT_TRIG_RX_THRESH_MASK 0xFFFF0000 473184870Syongari#define INT_TRIG_TX_THRESH_SHIFT 0 474184870Syongari#define INT_TRIG_RX_THRESH_SHIFT 16 475184870Syongari 476184870Syongari#define ALE_INT_TRIG_TIMER 0x15CC 477184870Syongari#define INT_TRIG_TX_TIMER_MASK 0x0000FFFF 478184870Syongari#define INT_TRIG_RX_TIMER_MASK 0x0000FFFF 479184870Syongari#define INT_TRIG_TX_TIMER_SHIFT 0 480184870Syongari#define INT_TRIG_RX_TIMER_SHIFT 16 481184870Syongari 482184870Syongari#define ALE_RXF1_PAGE0_ADDR_LO 0x15D0 483184870Syongari 484184870Syongari#define ALE_RXF1_PAGE1_ADDR_LO 0x15D4 485184870Syongari 486184870Syongari#define ALE_RXF2_PAGE0_ADDR_LO 0x15D8 487184870Syongari 488184870Syongari#define ALE_RXF2_PAGE1_ADDR_LO 0x15DC 489184870Syongari 490184870Syongari#define ALE_RXF3_PAGE0_ADDR_LO 0x15E0 491184870Syongari 492184870Syongari#define ALE_RXF3_PAGE1_ADDR_LO 0x15E4 493184870Syongari 494184870Syongari#define ALE_MBOX_TPD_PROD_IDX 0x15F0 495184870Syongari 496184870Syongari#define ALE_RXF0_PAGE0 0x15F4 497184870Syongari 498184870Syongari#define ALE_RXF0_PAGE1 0x15F5 499184870Syongari 500184870Syongari#define ALE_RXF1_PAGE0 0x15F6 501184870Syongari 502184870Syongari#define ALE_RXF1_PAGE1 0x15F7 503184870Syongari 504184870Syongari#define ALE_RXF2_PAGE0 0x15F8 505184870Syongari 506184870Syongari#define ALE_RXF2_PAGE1 0x15F9 507184870Syongari 508184870Syongari#define ALE_RXF3_PAGE0 0x15FA 509184870Syongari 510184870Syongari#define ALE_RXF3_PAGE1 0x15FB 511184870Syongari 512184870Syongari#define RXF_VALID 0x01 513184870Syongari 514184870Syongari#define ALE_INTR_STATUS 0x1600 515184870Syongari#define INTR_SMB 0x00000001 516184870Syongari#define INTR_TIMER 0x00000002 517184870Syongari#define INTR_MANUAL_TIMER 0x00000004 518184870Syongari#define INTR_RX_FIFO_OFLOW 0x00000008 519184870Syongari#define INTR_RXF0_OFLOW 0x00000010 520184870Syongari#define INTR_RXF1_OFLOW 0x00000020 521184870Syongari#define INTR_RXF2_OFLOW 0x00000040 522184870Syongari#define INTR_RXF3_OFLOW 0x00000080 523184870Syongari#define INTR_TX_FIFO_UNDERRUN 0x00000100 524184870Syongari#define INTR_RX0_PAGE_FULL 0x00000200 525184870Syongari#define INTR_DMA_RD_TO_RST 0x00000400 526184870Syongari#define INTR_DMA_WR_TO_RST 0x00000800 527184870Syongari#define INTR_GPHY 0x00001000 528184870Syongari#define INTR_TX_CREDIT 0x00002000 529184870Syongari#define INTR_GPHY_LOW_PW 0x00004000 530184870Syongari#define INTR_RX_PKT 0x00010000 531184870Syongari#define INTR_TX_PKT 0x00020000 532184870Syongari#define INTR_TX_DMA 0x00040000 533184870Syongari#define INTR_RX_PKT1 0x00080000 534184870Syongari#define INTR_RX_PKT2 0x00100000 535184870Syongari#define INTR_RX_PKT3 0x00200000 536184870Syongari#define INTR_MAC_RX 0x00400000 537184870Syongari#define INTR_MAC_TX 0x00800000 538184870Syongari#define INTR_UNDERRUN 0x01000000 539184870Syongari#define INTR_FRAME_ERROR 0x02000000 540184870Syongari#define INTR_FRAME_OK 0x04000000 541184870Syongari#define INTR_CSUM_ERROR 0x08000000 542184870Syongari#define INTR_PHY_LINK_DOWN 0x10000000 543184870Syongari#define INTR_DIS_INT 0x80000000 544184870Syongari 545184870Syongari/* Interrupt Mask Register */ 546184870Syongari#define ALE_INTR_MASK 0x1604 547184870Syongari 548184870Syongari#define ALE_INTRS \ 549184870Syongari (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 550184870Syongari INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \ 551184870Syongari INTR_TX_FIFO_UNDERRUN) 552184870Syongari 553184870Syongari/* 554184870Syongari * AR81xx requires register access to get MAC statistics 555184870Syongari * and the format of statistics seems to be the same of L1 . 556184870Syongari */ 557184870Syongari#define ALE_RX_MIB_BASE 0x1700 558184870Syongari 559184870Syongari#define ALE_TX_MIB_BASE 0x1760 560184870Syongari 561184870Syongari/* Statistics counters collected by the MAC. */ 562184870Syongaristruct smb { 563184870Syongari /* Rx stats. */ 564184870Syongari uint32_t rx_frames; 565184870Syongari uint32_t rx_bcast_frames; 566184870Syongari uint32_t rx_mcast_frames; 567184870Syongari uint32_t rx_pause_frames; 568184870Syongari uint32_t rx_control_frames; 569184870Syongari uint32_t rx_crcerrs; 570184870Syongari uint32_t rx_lenerrs; 571184870Syongari uint32_t rx_bytes; 572184870Syongari uint32_t rx_runts; 573184870Syongari uint32_t rx_fragments; 574184870Syongari uint32_t rx_pkts_64; 575184870Syongari uint32_t rx_pkts_65_127; 576184870Syongari uint32_t rx_pkts_128_255; 577184870Syongari uint32_t rx_pkts_256_511; 578184870Syongari uint32_t rx_pkts_512_1023; 579184870Syongari uint32_t rx_pkts_1024_1518; 580184870Syongari uint32_t rx_pkts_1519_max; 581184870Syongari uint32_t rx_pkts_truncated; 582184870Syongari uint32_t rx_fifo_oflows; 583184870Syongari uint32_t rx_rrs_errs; 584184870Syongari uint32_t rx_alignerrs; 585184870Syongari uint32_t rx_bcast_bytes; 586184870Syongari uint32_t rx_mcast_bytes; 587184870Syongari uint32_t rx_pkts_filtered; 588184870Syongari /* Tx stats. */ 589184870Syongari uint32_t tx_frames; 590184870Syongari uint32_t tx_bcast_frames; 591184870Syongari uint32_t tx_mcast_frames; 592184870Syongari uint32_t tx_pause_frames; 593184870Syongari uint32_t tx_excess_defer; 594184870Syongari uint32_t tx_control_frames; 595184870Syongari uint32_t tx_deferred; 596184870Syongari uint32_t tx_bytes; 597184870Syongari uint32_t tx_pkts_64; 598184870Syongari uint32_t tx_pkts_65_127; 599184870Syongari uint32_t tx_pkts_128_255; 600184870Syongari uint32_t tx_pkts_256_511; 601184870Syongari uint32_t tx_pkts_512_1023; 602184870Syongari uint32_t tx_pkts_1024_1518; 603184870Syongari uint32_t tx_pkts_1519_max; 604184870Syongari uint32_t tx_single_colls; 605184870Syongari uint32_t tx_multi_colls; 606184870Syongari uint32_t tx_late_colls; 607184870Syongari uint32_t tx_excess_colls; 608184870Syongari uint32_t tx_underrun; 609184870Syongari uint32_t tx_desc_underrun; 610184870Syongari uint32_t tx_lenerrs; 611184870Syongari uint32_t tx_pkts_truncated; 612184870Syongari uint32_t tx_bcast_bytes; 613184870Syongari uint32_t tx_mcast_bytes; 614184870Syongari} __packed; 615184870Syongari 616184870Syongari#define ALE_HOST_RXF0_PAGEOFF 0x1800 617184870Syongari 618184870Syongari#define ALE_TPD_CONS_IDX 0x1804 619184870Syongari 620184870Syongari#define ALE_HOST_RXF1_PAGEOFF 0x1808 621184870Syongari 622184870Syongari#define ALE_HOST_RXF2_PAGEOFF 0x180C 623184870Syongari 624184870Syongari#define ALE_HOST_RXF3_PAGEOFF 0x1810 625184870Syongari 626184870Syongari#define ALE_RXF0_CMB0_ADDR_LO 0x1820 627184870Syongari 628184870Syongari#define ALE_RXF0_CMB1_ADDR_LO 0x1824 629184870Syongari 630184870Syongari#define ALE_RXF1_CMB0_ADDR_LO 0x1828 631184870Syongari 632184870Syongari#define ALE_RXF1_CMB1_ADDR_LO 0x182C 633184870Syongari 634184870Syongari#define ALE_RXF2_CMB0_ADDR_LO 0x1830 635184870Syongari 636184870Syongari#define ALE_RXF2_CMB1_ADDR_LO 0x1834 637184870Syongari 638184870Syongari#define ALE_RXF3_CMB0_ADDR_LO 0x1838 639184870Syongari 640184870Syongari#define ALE_RXF3_CMB1_ADDR_LO 0x183C 641184870Syongari 642184870Syongari#define ALE_TX_CMB_ADDR_LO 0x1840 643184870Syongari 644184870Syongari#define ALE_SMB_ADDR_LO 0x1844 645184870Syongari 646184870Syongari/* 647184870Syongari * RRS(receive return status) structure. 648184870Syongari * 649184870Syongari * Note: 650184870Syongari * Atheros AR81xx does not support descriptor based DMA on Rx 651184870Syongari * instead it just prepends a Rx status structure prior to a 652184870Syongari * received frame which also resides on the same Rx buffer. 653184870Syongari * This means driver should copy an entire frame from the 654184870Syongari * buffer to new mbuf chain which in turn greatly increases CPU 655184870Syongari * cycles and effectively nullify the advantage of DMA 656184870Syongari * operation of controller. So you should have fast CPU to cope 657184870Syongari * with the copy operation. Implementing flow-controls may help 658184870Syongari * a lot to minimize Rx FIFO overflows but it's not available 659184870Syongari * yet on FreeBSD and hardware doesn't seem to support 660184870Syongari * fine-grained Tx/Rx flow controls. 661184870Syongari */ 662184870Syongaristruct rx_rs { 663184870Syongari uint32_t seqno; 664184870Syongari#define ALE_RD_SEQNO_MASK 0x0000FFFF 665184870Syongari#define ALE_RD_HASH_MASK 0xFFFF0000 666184870Syongari#define ALE_RD_SEQNO_SHIFT 0 667184870Syongari#define ALE_RD_HASH_SHIFT 16 668184870Syongari#define ALE_RX_SEQNO(x) \ 669184870Syongari (((x) & ALE_RD_SEQNO_MASK) >> ALE_RD_SEQNO_SHIFT) 670184870Syongari uint32_t length; 671184870Syongari#define ALE_RD_CSUM_MASK 0x0000FFFF 672184870Syongari#define ALE_RD_LEN_MASK 0x3FFF0000 673184870Syongari#define ALE_RD_CPU_MASK 0xC0000000 674184870Syongari#define ALE_RD_CSUM_SHIFT 0 675184870Syongari#define ALE_RD_LEN_SHIFT 16 676184870Syongari#define ALE_RD_CPU_SHIFT 30 677184870Syongari#define ALE_RX_CSUM(x) \ 678184870Syongari (((x) & ALE_RD_CSUM_MASK) >> ALE_RD_CSUM_SHIFT) 679184870Syongari#define ALE_RX_BYTES(x) \ 680184870Syongari (((x) & ALE_RD_LEN_MASK) >> ALE_RD_LEN_SHIFT) 681184870Syongari#define ALE_RX_CPU(x) \ 682184870Syongari (((x) & ALE_RD_CPU_MASK) >> ALE_RD_CPU_SHIFT) 683184870Syongari uint32_t flags; 684184870Syongari#define ALE_RD_RSS_IPV4 0x00000001 685184870Syongari#define ALE_RD_RSS_IPV4_TCP 0x00000002 686184870Syongari#define ALE_RD_RSS_IPV6 0x00000004 687184870Syongari#define ALE_RD_RSS_IPV6_TCP 0x00000008 688184870Syongari#define ALE_RD_IPV6 0x00000010 689184870Syongari#define ALE_RD_IPV4_FRAG 0x00000020 690184870Syongari#define ALE_RD_IPV4_DF 0x00000040 691184870Syongari#define ALE_RD_802_3 0x00000080 692184870Syongari#define ALE_RD_VLAN 0x00000100 693184870Syongari#define ALE_RD_ERROR 0x00000200 694184870Syongari#define ALE_RD_IPV4 0x00000400 695184870Syongari#define ALE_RD_UDP 0x00000800 696184870Syongari#define ALE_RD_TCP 0x00001000 697184870Syongari#define ALE_RD_BCAST 0x00002000 698184870Syongari#define ALE_RD_MCAST 0x00004000 699184870Syongari#define ALE_RD_PAUSE 0x00008000 700184870Syongari#define ALE_RD_CRC 0x00010000 701184870Syongari#define ALE_RD_CODE 0x00020000 702184870Syongari#define ALE_RD_DRIBBLE 0x00040000 703184870Syongari#define ALE_RD_RUNT 0x00080000 704184870Syongari#define ALE_RD_OFLOW 0x00100000 705184870Syongari#define ALE_RD_TRUNC 0x00200000 706184870Syongari#define ALE_RD_IPCSUM_NOK 0x00400000 707184870Syongari#define ALE_RD_TCP_UDPCSUM_NOK 0x00800000 708184870Syongari#define ALE_RD_LENGTH_NOK 0x01000000 709184870Syongari#define ALE_RD_DES_ADDR_FILTERED 0x02000000 710184870Syongari uint32_t vtags; 711184870Syongari#define ALE_RD_HASH_HI_MASK 0x0000FFFF 712184870Syongari#define ALE_RD_HASH_HI_SHIFT 0 713184870Syongari#define ALE_RD_VLAN_MASK 0xFFFF0000 714184870Syongari#define ALE_RD_VLAN_SHIFT 16 715184870Syongari#define ALE_RX_VLAN(x) \ 716184870Syongari (((x) & ALE_RD_VLAN_MASK) >> ALE_RD_VLAN_SHIFT) 717184870Syongari#define ALE_RX_VLAN_TAG(x) \ 718184870Syongari (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 719184870Syongari} __packed; 720184870Syongari 721184870Syongari/* Tx descriptor. */ 722184870Syongaristruct tx_desc { 723184870Syongari uint64_t addr; 724184870Syongari uint32_t len; 725184870Syongari#define ALE_TD_VLAN_MASK 0xFFFF0000 726184870Syongari#define ALE_TD_PKT_INT 0x00008000 727184870Syongari#define ALE_TD_DMA_INT 0x00004000 728184870Syongari#define ALE_TD_BUFLEN_MASK 0x00003FFF 729184870Syongari#define ALE_TD_VLAN_SHIFT 16 730184870Syongari#define ALE_TX_VLAN_TAG(x) \ 731184870Syongari (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 732184870Syongari#define ALE_TD_BUFLEN_SHIFT 0 733184870Syongari#define ALE_TX_BYTES(x) \ 734184870Syongari (((x) << ALE_TD_BUFLEN_SHIFT) & ALE_TD_BUFLEN_MASK) 735184870Syongari uint32_t flags; 736184870Syongari#define ALE_TD_MSS 0xFFF80000 737184870Syongari#define ALE_TD_TSO_HDR 0x00040000 738184870Syongari#define ALE_TD_TCPHDR_LEN 0x0003C000 739184870Syongari#define ALE_TD_IPHDR_LEN 0x00003C00 740184870Syongari#define ALE_TD_IPV6HDR_LEN2 0x00003C00 741184870Syongari#define ALE_TD_LLC_SNAP 0x00000200 742184870Syongari#define ALE_TD_VLAN_TAGGED 0x00000100 743184870Syongari#define ALE_TD_UDPCSUM 0x00000080 744184870Syongari#define ALE_TD_TCPCSUM 0x00000040 745184870Syongari#define ALE_TD_IPCSUM 0x00000020 746184870Syongari#define ALE_TD_IPV6HDR_LEN1 0x000000E0 747184870Syongari#define ALE_TD_TSO 0x00000010 748184870Syongari#define ALE_TD_CXSUM 0x00000008 749184870Syongari#define ALE_TD_INSERT_VLAN_TAG 0x00000004 750184870Syongari#define ALE_TD_IPV6 0x00000002 751184870Syongari#define ALE_TD_EOP 0x00000001 752184870Syongari 753184870Syongari#define ALE_TD_CSUM_PLOADOFFSET 0x00FF0000 754184870Syongari#define ALE_TD_CSUM_XSUMOFFSET 0xFF000000 755184870Syongari#define ALE_TD_CSUM_XSUMOFFSET_SHIFT 24 756184870Syongari#define ALE_TD_CSUM_PLOADOFFSET_SHIFT 16 757184870Syongari#define ALE_TD_MSS_SHIFT 19 758184870Syongari#define ALE_TD_TCPHDR_LEN_SHIFT 14 759184870Syongari#define ALE_TD_IPHDR_LEN_SHIFT 10 760184870Syongari} __packed; 761184870Syongari 762184870Syongari#endif /* _IF_ALEREG_H */ 763