if_ale.c revision 295735
1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 295735 2016-02-18 01:24:10Z yongari $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/module.h> 41#include <sys/rman.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_var.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_llc.h> 55#include <net/if_media.h> 56#include <net/if_types.h> 57#include <net/if_vlan_var.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/ip.h> 62#include <netinet/tcp.h> 63 64#include <dev/mii/mii.h> 65#include <dev/mii/miivar.h> 66 67#include <dev/pci/pcireg.h> 68#include <dev/pci/pcivar.h> 69 70#include <machine/bus.h> 71#include <machine/in_cksum.h> 72 73#include <dev/ale/if_alereg.h> 74#include <dev/ale/if_alevar.h> 75 76/* "device miibus" required. See GENERIC if you get errors here. */ 77#include "miibus_if.h" 78 79/* For more information about Tx checksum offload issues see ale_encap(). */ 80#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82MODULE_DEPEND(ale, pci, 1, 1, 1); 83MODULE_DEPEND(ale, ether, 1, 1, 1); 84MODULE_DEPEND(ale, miibus, 1, 1, 1); 85 86/* Tunables. */ 87static int msi_disable = 0; 88static int msix_disable = 0; 89TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 90TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 91 92/* 93 * Devices supported by this driver. 94 */ 95static const struct ale_dev { 96 uint16_t ale_vendorid; 97 uint16_t ale_deviceid; 98 const char *ale_name; 99} ale_devs[] = { 100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 102}; 103 104static int ale_attach(device_t); 105static int ale_check_boundary(struct ale_softc *); 106static int ale_detach(device_t); 107static int ale_dma_alloc(struct ale_softc *); 108static void ale_dma_free(struct ale_softc *); 109static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 110static int ale_encap(struct ale_softc *, struct mbuf **); 111static void ale_get_macaddr(struct ale_softc *); 112static void ale_init(void *); 113static void ale_init_locked(struct ale_softc *); 114static void ale_init_rx_pages(struct ale_softc *); 115static void ale_init_tx_ring(struct ale_softc *); 116static void ale_int_task(void *, int); 117static int ale_intr(void *); 118static int ale_ioctl(struct ifnet *, u_long, caddr_t); 119static void ale_mac_config(struct ale_softc *); 120static int ale_miibus_readreg(device_t, int, int); 121static void ale_miibus_statchg(device_t); 122static int ale_miibus_writereg(device_t, int, int, int); 123static int ale_mediachange(struct ifnet *); 124static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 125static void ale_phy_reset(struct ale_softc *); 126static int ale_probe(device_t); 127static void ale_reset(struct ale_softc *); 128static int ale_resume(device_t); 129static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130 uint32_t, uint32_t *); 131static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132static int ale_rxeof(struct ale_softc *sc, int); 133static void ale_rxfilter(struct ale_softc *); 134static void ale_rxvlan(struct ale_softc *); 135static void ale_setlinkspeed(struct ale_softc *); 136static void ale_setwol(struct ale_softc *); 137static int ale_shutdown(device_t); 138static void ale_start(struct ifnet *); 139static void ale_start_locked(struct ifnet *); 140static void ale_stats_clear(struct ale_softc *); 141static void ale_stats_update(struct ale_softc *); 142static void ale_stop(struct ale_softc *); 143static void ale_stop_mac(struct ale_softc *); 144static int ale_suspend(device_t); 145static void ale_sysctl_node(struct ale_softc *); 146static void ale_tick(void *); 147static void ale_txeof(struct ale_softc *); 148static void ale_watchdog(struct ale_softc *); 149static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152 153static device_method_t ale_methods[] = { 154 /* Device interface. */ 155 DEVMETHOD(device_probe, ale_probe), 156 DEVMETHOD(device_attach, ale_attach), 157 DEVMETHOD(device_detach, ale_detach), 158 DEVMETHOD(device_shutdown, ale_shutdown), 159 DEVMETHOD(device_suspend, ale_suspend), 160 DEVMETHOD(device_resume, ale_resume), 161 162 /* MII interface. */ 163 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166 167 DEVMETHOD_END 168}; 169 170static driver_t ale_driver = { 171 "ale", 172 ale_methods, 173 sizeof(struct ale_softc) 174}; 175 176static devclass_t ale_devclass; 177 178DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); 179DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 180 181static struct resource_spec ale_res_spec_mem[] = { 182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183 { -1, 0, 0 } 184}; 185 186static struct resource_spec ale_irq_spec_legacy[] = { 187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188 { -1, 0, 0 } 189}; 190 191static struct resource_spec ale_irq_spec_msi[] = { 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { -1, 0, 0 } 194}; 195 196static struct resource_spec ale_irq_spec_msix[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199}; 200 201static int 202ale_miibus_readreg(device_t dev, int phy, int reg) 203{ 204 struct ale_softc *sc; 205 uint32_t v; 206 int i; 207 208 sc = device_get_softc(dev); 209 210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213 DELAY(5); 214 v = CSR_READ_4(sc, ALE_MDIO); 215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216 break; 217 } 218 219 if (i == 0) { 220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221 return (0); 222 } 223 224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225} 226 227static int 228ale_miibus_writereg(device_t dev, int phy, int reg, int val) 229{ 230 struct ale_softc *sc; 231 uint32_t v; 232 int i; 233 234 sc = device_get_softc(dev); 235 236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240 DELAY(5); 241 v = CSR_READ_4(sc, ALE_MDIO); 242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243 break; 244 } 245 246 if (i == 0) 247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248 249 return (0); 250} 251 252static void 253ale_miibus_statchg(device_t dev) 254{ 255 struct ale_softc *sc; 256 struct mii_data *mii; 257 struct ifnet *ifp; 258 uint32_t reg; 259 260 sc = device_get_softc(dev); 261 mii = device_get_softc(sc->ale_miibus); 262 ifp = sc->ale_ifp; 263 if (mii == NULL || ifp == NULL || 264 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 265 return; 266 267 sc->ale_flags &= ~ALE_FLAG_LINK; 268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 269 (IFM_ACTIVE | IFM_AVALID)) { 270 switch (IFM_SUBTYPE(mii->mii_media_active)) { 271 case IFM_10_T: 272 case IFM_100_TX: 273 sc->ale_flags |= ALE_FLAG_LINK; 274 break; 275 case IFM_1000_T: 276 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 277 sc->ale_flags |= ALE_FLAG_LINK; 278 break; 279 default: 280 break; 281 } 282 } 283 284 /* Stop Rx/Tx MACs. */ 285 ale_stop_mac(sc); 286 287 /* Program MACs with resolved speed/duplex/flow-control. */ 288 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 289 ale_mac_config(sc); 290 /* Reenable Tx/Rx MACs. */ 291 reg = CSR_READ_4(sc, ALE_MAC_CFG); 292 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 294 } 295} 296 297static void 298ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 299{ 300 struct ale_softc *sc; 301 struct mii_data *mii; 302 303 sc = ifp->if_softc; 304 ALE_LOCK(sc); 305 if ((ifp->if_flags & IFF_UP) == 0) { 306 ALE_UNLOCK(sc); 307 return; 308 } 309 mii = device_get_softc(sc->ale_miibus); 310 311 mii_pollstat(mii); 312 ifmr->ifm_status = mii->mii_media_status; 313 ifmr->ifm_active = mii->mii_media_active; 314 ALE_UNLOCK(sc); 315} 316 317static int 318ale_mediachange(struct ifnet *ifp) 319{ 320 struct ale_softc *sc; 321 struct mii_data *mii; 322 struct mii_softc *miisc; 323 int error; 324 325 sc = ifp->if_softc; 326 ALE_LOCK(sc); 327 mii = device_get_softc(sc->ale_miibus); 328 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 329 PHY_RESET(miisc); 330 error = mii_mediachg(mii); 331 ALE_UNLOCK(sc); 332 333 return (error); 334} 335 336static int 337ale_probe(device_t dev) 338{ 339 const struct ale_dev *sp; 340 int i; 341 uint16_t vendor, devid; 342 343 vendor = pci_get_vendor(dev); 344 devid = pci_get_device(dev); 345 sp = ale_devs; 346 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 347 if (vendor == sp->ale_vendorid && 348 devid == sp->ale_deviceid) { 349 device_set_desc(dev, sp->ale_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 sp++; 353 } 354 355 return (ENXIO); 356} 357 358static void 359ale_get_macaddr(struct ale_softc *sc) 360{ 361 uint32_t ea[2], reg; 362 int i, vpdc; 363 364 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 365 if ((reg & SPI_VPD_ENB) != 0) { 366 reg &= ~SPI_VPD_ENB; 367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 368 } 369 370 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 371 /* 372 * PCI VPD capability found, let TWSI reload EEPROM. 373 * This will set ethernet address of controller. 374 */ 375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 376 TWSI_CTRL_SW_LD_START); 377 for (i = 100; i > 0; i--) { 378 DELAY(1000); 379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 380 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 381 break; 382 } 383 if (i == 0) 384 device_printf(sc->ale_dev, 385 "reloading EEPROM timeout!\n"); 386 } else { 387 if (bootverbose) 388 device_printf(sc->ale_dev, 389 "PCI VPD capability not found!\n"); 390 } 391 392 ea[0] = CSR_READ_4(sc, ALE_PAR0); 393 ea[1] = CSR_READ_4(sc, ALE_PAR1); 394 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 395 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 396 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 397 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 398 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 399 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 400} 401 402static void 403ale_phy_reset(struct ale_softc *sc) 404{ 405 406 /* Reset magic from Linux. */ 407 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 408 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 409 GPHY_CTRL_PHY_PLL_ON); 410 DELAY(1000); 411 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 412 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 413 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 414 DELAY(1000); 415 416#define ATPHY_DBG_ADDR 0x1D 417#define ATPHY_DBG_DATA 0x1E 418 419 /* Enable hibernation mode. */ 420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421 ATPHY_DBG_ADDR, 0x0B); 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_DATA, 0xBC00); 424 /* Set Class A/B for all modes. */ 425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 426 ATPHY_DBG_ADDR, 0x00); 427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428 ATPHY_DBG_DATA, 0x02EF); 429 /* Enable 10BT power saving. */ 430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 431 ATPHY_DBG_ADDR, 0x12); 432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433 ATPHY_DBG_DATA, 0x4C04); 434 /* Adjust 1000T power. */ 435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 436 ATPHY_DBG_ADDR, 0x04); 437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438 ATPHY_DBG_ADDR, 0x8BBB); 439 /* 10BT center tap voltage. */ 440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 441 ATPHY_DBG_ADDR, 0x05); 442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 443 ATPHY_DBG_ADDR, 0x2C46); 444 445#undef ATPHY_DBG_ADDR 446#undef ATPHY_DBG_DATA 447 DELAY(1000); 448} 449 450static int 451ale_attach(device_t dev) 452{ 453 struct ale_softc *sc; 454 struct ifnet *ifp; 455 uint16_t burst; 456 int error, i, msic, msixc, pmc; 457 uint32_t rxf_len, txf_len; 458 459 error = 0; 460 sc = device_get_softc(dev); 461 sc->ale_dev = dev; 462 463 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 464 MTX_DEF); 465 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 466 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 467 468 /* Map the device. */ 469 pci_enable_busmaster(dev); 470 sc->ale_res_spec = ale_res_spec_mem; 471 sc->ale_irq_spec = ale_irq_spec_legacy; 472 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 473 if (error != 0) { 474 device_printf(dev, "cannot allocate memory resources.\n"); 475 goto fail; 476 } 477 478 /* Set PHY address. */ 479 sc->ale_phyaddr = ALE_PHY_ADDR; 480 481 /* Reset PHY. */ 482 ale_phy_reset(sc); 483 484 /* Reset the ethernet controller. */ 485 ale_reset(sc); 486 487 /* Get PCI and chip id/revision. */ 488 sc->ale_rev = pci_get_revid(dev); 489 if (sc->ale_rev >= 0xF0) { 490 /* L2E Rev. B. AR8114 */ 491 sc->ale_flags |= ALE_FLAG_FASTETHER; 492 } else { 493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 494 /* L1E AR8121 */ 495 sc->ale_flags |= ALE_FLAG_JUMBO; 496 } else { 497 /* L2E Rev. A. AR8113 */ 498 sc->ale_flags |= ALE_FLAG_FASTETHER; 499 } 500 } 501 /* 502 * All known controllers seems to require 4 bytes alignment 503 * of Tx buffers to make Tx checksum offload with custom 504 * checksum generation method work. 505 */ 506 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 507 /* 508 * All known controllers seems to have issues on Rx checksum 509 * offload for fragmented IP datagrams. 510 */ 511 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 512 /* 513 * Don't use Tx CMB. It is known to cause RRS update failure 514 * under certain circumstances. Typical phenomenon of the 515 * issue would be unexpected sequence number encountered in 516 * Rx handler. 517 */ 518 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 519 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 520 MASTER_CHIP_REV_SHIFT; 521 if (bootverbose) { 522 device_printf(dev, "PCI device revision : 0x%04x\n", 523 sc->ale_rev); 524 device_printf(dev, "Chip id/revision : 0x%04x\n", 525 sc->ale_chip_rev); 526 } 527 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 528 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 529 /* 530 * Uninitialized hardware returns an invalid chip id/revision 531 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 532 */ 533 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 534 rxf_len == 0xFFFFFFF) { 535 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 536 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 537 txf_len, rxf_len); 538 error = ENXIO; 539 goto fail; 540 } 541 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 542 543 /* Allocate IRQ resources. */ 544 msixc = pci_msix_count(dev); 545 msic = pci_msi_count(dev); 546 if (bootverbose) { 547 device_printf(dev, "MSIX count : %d\n", msixc); 548 device_printf(dev, "MSI count : %d\n", msic); 549 } 550 551 /* Prefer MSIX over MSI. */ 552 if (msix_disable == 0 || msi_disable == 0) { 553 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 554 pci_alloc_msix(dev, &msixc) == 0) { 555 if (msixc == ALE_MSIX_MESSAGES) { 556 device_printf(dev, "Using %d MSIX messages.\n", 557 msixc); 558 sc->ale_flags |= ALE_FLAG_MSIX; 559 sc->ale_irq_spec = ale_irq_spec_msix; 560 } else 561 pci_release_msi(dev); 562 } 563 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 564 msic == ALE_MSI_MESSAGES && 565 pci_alloc_msi(dev, &msic) == 0) { 566 if (msic == ALE_MSI_MESSAGES) { 567 device_printf(dev, "Using %d MSI messages.\n", 568 msic); 569 sc->ale_flags |= ALE_FLAG_MSI; 570 sc->ale_irq_spec = ale_irq_spec_msi; 571 } else 572 pci_release_msi(dev); 573 } 574 } 575 576 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 577 if (error != 0) { 578 device_printf(dev, "cannot allocate IRQ resources.\n"); 579 goto fail; 580 } 581 582 /* Get DMA parameters from PCIe device control register. */ 583 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 584 sc->ale_flags |= ALE_FLAG_PCIE; 585 burst = pci_read_config(dev, i + 0x08, 2); 586 /* Max read request size. */ 587 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 588 DMA_CFG_RD_BURST_SHIFT; 589 /* Max payload size. */ 590 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 591 DMA_CFG_WR_BURST_SHIFT; 592 if (bootverbose) { 593 device_printf(dev, "Read request size : %d bytes.\n", 594 128 << ((burst >> 12) & 0x07)); 595 device_printf(dev, "TLP payload size : %d bytes.\n", 596 128 << ((burst >> 5) & 0x07)); 597 } 598 } else { 599 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 600 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 601 } 602 603 /* Create device sysctl node. */ 604 ale_sysctl_node(sc); 605 606 if ((error = ale_dma_alloc(sc)) != 0) 607 goto fail; 608 609 /* Load station address. */ 610 ale_get_macaddr(sc); 611 612 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 613 if (ifp == NULL) { 614 device_printf(dev, "cannot allocate ifnet structure.\n"); 615 error = ENXIO; 616 goto fail; 617 } 618 619 ifp->if_softc = sc; 620 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 622 ifp->if_ioctl = ale_ioctl; 623 ifp->if_start = ale_start; 624 ifp->if_init = ale_init; 625 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 626 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 627 IFQ_SET_READY(&ifp->if_snd); 628 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 629 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 630 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 631 sc->ale_flags |= ALE_FLAG_PMCAP; 632 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 633 } 634 ifp->if_capenable = ifp->if_capabilities; 635 636 /* Set up MII bus. */ 637 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 638 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 639 MIIF_DOPAUSE); 640 if (error != 0) { 641 device_printf(dev, "attaching PHYs failed\n"); 642 goto fail; 643 } 644 645 ether_ifattach(ifp, sc->ale_eaddr); 646 647 /* VLAN capability setup. */ 648 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 649 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 650 ifp->if_capenable = ifp->if_capabilities; 651 /* 652 * Even though controllers supported by ale(3) have Rx checksum 653 * offload bug the workaround for fragmented frames seemed to 654 * work so far. However it seems Rx checksum offload does not 655 * work under certain conditions. So disable Rx checksum offload 656 * until I find more clue about it but allow users to override it. 657 */ 658 ifp->if_capenable &= ~IFCAP_RXCSUM; 659 660 /* Tell the upper layer(s) we support long frames. */ 661 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 662 663 /* Create local taskq. */ 664 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 665 taskqueue_thread_enqueue, &sc->ale_tq); 666 if (sc->ale_tq == NULL) { 667 device_printf(dev, "could not create taskqueue.\n"); 668 ether_ifdetach(ifp); 669 error = ENXIO; 670 goto fail; 671 } 672 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 673 device_get_nameunit(sc->ale_dev)); 674 675 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 676 msic = ALE_MSIX_MESSAGES; 677 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 678 msic = ALE_MSI_MESSAGES; 679 else 680 msic = 1; 681 for (i = 0; i < msic; i++) { 682 error = bus_setup_intr(dev, sc->ale_irq[i], 683 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 684 &sc->ale_intrhand[i]); 685 if (error != 0) 686 break; 687 } 688 if (error != 0) { 689 device_printf(dev, "could not set up interrupt handler.\n"); 690 taskqueue_free(sc->ale_tq); 691 sc->ale_tq = NULL; 692 ether_ifdetach(ifp); 693 goto fail; 694 } 695 696fail: 697 if (error != 0) 698 ale_detach(dev); 699 700 return (error); 701} 702 703static int 704ale_detach(device_t dev) 705{ 706 struct ale_softc *sc; 707 struct ifnet *ifp; 708 int i, msic; 709 710 sc = device_get_softc(dev); 711 712 ifp = sc->ale_ifp; 713 if (device_is_attached(dev)) { 714 ether_ifdetach(ifp); 715 ALE_LOCK(sc); 716 ale_stop(sc); 717 ALE_UNLOCK(sc); 718 callout_drain(&sc->ale_tick_ch); 719 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 720 } 721 722 if (sc->ale_tq != NULL) { 723 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 724 taskqueue_free(sc->ale_tq); 725 sc->ale_tq = NULL; 726 } 727 728 if (sc->ale_miibus != NULL) { 729 device_delete_child(dev, sc->ale_miibus); 730 sc->ale_miibus = NULL; 731 } 732 bus_generic_detach(dev); 733 ale_dma_free(sc); 734 735 if (ifp != NULL) { 736 if_free(ifp); 737 sc->ale_ifp = NULL; 738 } 739 740 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 741 msic = ALE_MSIX_MESSAGES; 742 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 743 msic = ALE_MSI_MESSAGES; 744 else 745 msic = 1; 746 for (i = 0; i < msic; i++) { 747 if (sc->ale_intrhand[i] != NULL) { 748 bus_teardown_intr(dev, sc->ale_irq[i], 749 sc->ale_intrhand[i]); 750 sc->ale_intrhand[i] = NULL; 751 } 752 } 753 754 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 755 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 756 pci_release_msi(dev); 757 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 758 mtx_destroy(&sc->ale_mtx); 759 760 return (0); 761} 762 763#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 764 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 765 766#if __FreeBSD_version >= 900030 767#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 768 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 769#elif __FreeBSD_version > 800000 770#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 771 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 772#else 773#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 774 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 775#endif 776 777static void 778ale_sysctl_node(struct ale_softc *sc) 779{ 780 struct sysctl_ctx_list *ctx; 781 struct sysctl_oid_list *child, *parent; 782 struct sysctl_oid *tree; 783 struct ale_hw_stats *stats; 784 int error; 785 786 stats = &sc->ale_stats; 787 ctx = device_get_sysctl_ctx(sc->ale_dev); 788 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 789 790 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 791 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 792 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 793 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 794 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 795 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 796 /* Pull in device tunables. */ 797 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 798 error = resource_int_value(device_get_name(sc->ale_dev), 799 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 800 if (error == 0) { 801 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 802 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 803 device_printf(sc->ale_dev, "int_rx_mod value out of " 804 "range; using default: %d\n", 805 ALE_IM_RX_TIMER_DEFAULT); 806 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 807 } 808 } 809 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 810 error = resource_int_value(device_get_name(sc->ale_dev), 811 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 812 if (error == 0) { 813 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 814 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 815 device_printf(sc->ale_dev, "int_tx_mod value out of " 816 "range; using default: %d\n", 817 ALE_IM_TX_TIMER_DEFAULT); 818 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 819 } 820 } 821 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 822 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 823 sysctl_hw_ale_proc_limit, "I", 824 "max number of Rx events to process"); 825 /* Pull in device tunables. */ 826 sc->ale_process_limit = ALE_PROC_DEFAULT; 827 error = resource_int_value(device_get_name(sc->ale_dev), 828 device_get_unit(sc->ale_dev), "process_limit", 829 &sc->ale_process_limit); 830 if (error == 0) { 831 if (sc->ale_process_limit < ALE_PROC_MIN || 832 sc->ale_process_limit > ALE_PROC_MAX) { 833 device_printf(sc->ale_dev, 834 "process_limit value out of range; " 835 "using default: %d\n", ALE_PROC_DEFAULT); 836 sc->ale_process_limit = ALE_PROC_DEFAULT; 837 } 838 } 839 840 /* Misc statistics. */ 841 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 842 &stats->reset_brk_seq, 843 "Controller resets due to broken Rx sequnce number"); 844 845 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 846 NULL, "ATE statistics"); 847 parent = SYSCTL_CHILDREN(tree); 848 849 /* Rx statistics. */ 850 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 851 NULL, "Rx MAC statistics"); 852 child = SYSCTL_CHILDREN(tree); 853 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 854 &stats->rx_frames, "Good frames"); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 856 &stats->rx_bcast_frames, "Good broadcast frames"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 858 &stats->rx_mcast_frames, "Good multicast frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 860 &stats->rx_pause_frames, "Pause control frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 862 &stats->rx_control_frames, "Control frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 864 &stats->rx_crcerrs, "CRC errors"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 866 &stats->rx_lenerrs, "Frames with length mismatched"); 867 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 868 &stats->rx_bytes, "Good octets"); 869 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 870 &stats->rx_bcast_bytes, "Good broadcast octets"); 871 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 872 &stats->rx_mcast_bytes, "Good multicast octets"); 873 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 874 &stats->rx_runts, "Too short frames"); 875 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 876 &stats->rx_fragments, "Fragmented frames"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 878 &stats->rx_pkts_64, "64 bytes frames"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 880 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 882 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 884 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 886 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 888 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 890 &stats->rx_pkts_1519_max, "1519 to max frames"); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 892 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 894 &stats->rx_fifo_oflows, "FIFO overflows"); 895 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 896 &stats->rx_rrs_errs, "Return status write-back errors"); 897 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 898 &stats->rx_alignerrs, "Alignment errors"); 899 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 900 &stats->rx_pkts_filtered, 901 "Frames dropped due to address filtering"); 902 903 /* Tx statistics. */ 904 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 905 NULL, "Tx MAC statistics"); 906 child = SYSCTL_CHILDREN(tree); 907 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 908 &stats->tx_frames, "Good frames"); 909 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 910 &stats->tx_bcast_frames, "Good broadcast frames"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 912 &stats->tx_mcast_frames, "Good multicast frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 914 &stats->tx_pause_frames, "Pause control frames"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 916 &stats->tx_control_frames, "Control frames"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 918 &stats->tx_excess_defer, "Frames with excessive derferrals"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 920 &stats->tx_excess_defer, "Frames with derferrals"); 921 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 922 &stats->tx_bytes, "Good octets"); 923 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 924 &stats->tx_bcast_bytes, "Good broadcast octets"); 925 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 926 &stats->tx_mcast_bytes, "Good multicast octets"); 927 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 928 &stats->tx_pkts_64, "64 bytes frames"); 929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 930 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 932 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 934 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 936 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 937 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 938 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 939 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 940 &stats->tx_pkts_1519_max, "1519 to max frames"); 941 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 942 &stats->tx_single_colls, "Single collisions"); 943 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 944 &stats->tx_multi_colls, "Multiple collisions"); 945 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 946 &stats->tx_late_colls, "Late collisions"); 947 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 948 &stats->tx_excess_colls, "Excessive collisions"); 949 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 950 &stats->tx_underrun, "FIFO underruns"); 951 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 952 &stats->tx_desc_underrun, "Descriptor write-back errors"); 953 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 954 &stats->tx_lenerrs, "Frames with length mismatched"); 955 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 956 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 957} 958 959#undef ALE_SYSCTL_STAT_ADD32 960#undef ALE_SYSCTL_STAT_ADD64 961 962struct ale_dmamap_arg { 963 bus_addr_t ale_busaddr; 964}; 965 966static void 967ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 968{ 969 struct ale_dmamap_arg *ctx; 970 971 if (error != 0) 972 return; 973 974 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 975 976 ctx = (struct ale_dmamap_arg *)arg; 977 ctx->ale_busaddr = segs[0].ds_addr; 978} 979 980/* 981 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 982 * which specifies high address region of DMA blocks. Therefore these 983 * blocks should have the same high address of given 4GB address 984 * space(i.e. crossing 4GB boundary is not allowed). 985 */ 986static int 987ale_check_boundary(struct ale_softc *sc) 988{ 989 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 990 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 991 992 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 993 sc->ale_pagesize; 994 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 995 sc->ale_pagesize; 996 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 997 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 998 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 999 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 1000 1001 if ((ALE_ADDR_HI(tx_ring_end) != 1002 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 1003 (ALE_ADDR_HI(rx_page_end[0]) != 1004 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1005 (ALE_ADDR_HI(rx_page_end[1]) != 1006 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1007 (ALE_ADDR_HI(tx_cmb_end) != 1008 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1009 (ALE_ADDR_HI(rx_cmb_end[0]) != 1010 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1011 (ALE_ADDR_HI(rx_cmb_end[1]) != 1012 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1013 return (EFBIG); 1014 1015 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1016 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1017 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1018 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1019 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1020 return (EFBIG); 1021 1022 return (0); 1023} 1024 1025static int 1026ale_dma_alloc(struct ale_softc *sc) 1027{ 1028 struct ale_txdesc *txd; 1029 bus_addr_t lowaddr; 1030 struct ale_dmamap_arg ctx; 1031 int error, guard_size, i; 1032 1033 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1034 guard_size = ALE_JUMBO_FRAMELEN; 1035 else 1036 guard_size = ALE_MAX_FRAMELEN; 1037 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1038 ALE_RX_PAGE_ALIGN); 1039 lowaddr = BUS_SPACE_MAXADDR; 1040again: 1041 /* Create parent DMA tag. */ 1042 error = bus_dma_tag_create( 1043 bus_get_dma_tag(sc->ale_dev), /* parent */ 1044 1, 0, /* alignment, boundary */ 1045 lowaddr, /* lowaddr */ 1046 BUS_SPACE_MAXADDR, /* highaddr */ 1047 NULL, NULL, /* filter, filterarg */ 1048 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1049 0, /* nsegments */ 1050 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1051 0, /* flags */ 1052 NULL, NULL, /* lockfunc, lockarg */ 1053 &sc->ale_cdata.ale_parent_tag); 1054 if (error != 0) { 1055 device_printf(sc->ale_dev, 1056 "could not create parent DMA tag.\n"); 1057 goto fail; 1058 } 1059 1060 /* Create DMA tag for Tx descriptor ring. */ 1061 error = bus_dma_tag_create( 1062 sc->ale_cdata.ale_parent_tag, /* parent */ 1063 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1064 BUS_SPACE_MAXADDR, /* lowaddr */ 1065 BUS_SPACE_MAXADDR, /* highaddr */ 1066 NULL, NULL, /* filter, filterarg */ 1067 ALE_TX_RING_SZ, /* maxsize */ 1068 1, /* nsegments */ 1069 ALE_TX_RING_SZ, /* maxsegsize */ 1070 0, /* flags */ 1071 NULL, NULL, /* lockfunc, lockarg */ 1072 &sc->ale_cdata.ale_tx_ring_tag); 1073 if (error != 0) { 1074 device_printf(sc->ale_dev, 1075 "could not create Tx ring DMA tag.\n"); 1076 goto fail; 1077 } 1078 1079 /* Create DMA tag for Rx pages. */ 1080 for (i = 0; i < ALE_RX_PAGES; i++) { 1081 error = bus_dma_tag_create( 1082 sc->ale_cdata.ale_parent_tag, /* parent */ 1083 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1084 BUS_SPACE_MAXADDR, /* lowaddr */ 1085 BUS_SPACE_MAXADDR, /* highaddr */ 1086 NULL, NULL, /* filter, filterarg */ 1087 sc->ale_pagesize, /* maxsize */ 1088 1, /* nsegments */ 1089 sc->ale_pagesize, /* maxsegsize */ 1090 0, /* flags */ 1091 NULL, NULL, /* lockfunc, lockarg */ 1092 &sc->ale_cdata.ale_rx_page[i].page_tag); 1093 if (error != 0) { 1094 device_printf(sc->ale_dev, 1095 "could not create Rx page %d DMA tag.\n", i); 1096 goto fail; 1097 } 1098 } 1099 1100 /* Create DMA tag for Tx coalescing message block. */ 1101 error = bus_dma_tag_create( 1102 sc->ale_cdata.ale_parent_tag, /* parent */ 1103 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1104 BUS_SPACE_MAXADDR, /* lowaddr */ 1105 BUS_SPACE_MAXADDR, /* highaddr */ 1106 NULL, NULL, /* filter, filterarg */ 1107 ALE_TX_CMB_SZ, /* maxsize */ 1108 1, /* nsegments */ 1109 ALE_TX_CMB_SZ, /* maxsegsize */ 1110 0, /* flags */ 1111 NULL, NULL, /* lockfunc, lockarg */ 1112 &sc->ale_cdata.ale_tx_cmb_tag); 1113 if (error != 0) { 1114 device_printf(sc->ale_dev, 1115 "could not create Tx CMB DMA tag.\n"); 1116 goto fail; 1117 } 1118 1119 /* Create DMA tag for Rx coalescing message block. */ 1120 for (i = 0; i < ALE_RX_PAGES; i++) { 1121 error = bus_dma_tag_create( 1122 sc->ale_cdata.ale_parent_tag, /* parent */ 1123 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1124 BUS_SPACE_MAXADDR, /* lowaddr */ 1125 BUS_SPACE_MAXADDR, /* highaddr */ 1126 NULL, NULL, /* filter, filterarg */ 1127 ALE_RX_CMB_SZ, /* maxsize */ 1128 1, /* nsegments */ 1129 ALE_RX_CMB_SZ, /* maxsegsize */ 1130 0, /* flags */ 1131 NULL, NULL, /* lockfunc, lockarg */ 1132 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1133 if (error != 0) { 1134 device_printf(sc->ale_dev, 1135 "could not create Rx page %d CMB DMA tag.\n", i); 1136 goto fail; 1137 } 1138 } 1139 1140 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1141 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1142 (void **)&sc->ale_cdata.ale_tx_ring, 1143 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1144 &sc->ale_cdata.ale_tx_ring_map); 1145 if (error != 0) { 1146 device_printf(sc->ale_dev, 1147 "could not allocate DMA'able memory for Tx ring.\n"); 1148 goto fail; 1149 } 1150 ctx.ale_busaddr = 0; 1151 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1152 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1153 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1154 if (error != 0 || ctx.ale_busaddr == 0) { 1155 device_printf(sc->ale_dev, 1156 "could not load DMA'able memory for Tx ring.\n"); 1157 goto fail; 1158 } 1159 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1160 1161 /* Rx pages. */ 1162 for (i = 0; i < ALE_RX_PAGES; i++) { 1163 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1164 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1165 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1166 &sc->ale_cdata.ale_rx_page[i].page_map); 1167 if (error != 0) { 1168 device_printf(sc->ale_dev, 1169 "could not allocate DMA'able memory for " 1170 "Rx page %d.\n", i); 1171 goto fail; 1172 } 1173 ctx.ale_busaddr = 0; 1174 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1175 sc->ale_cdata.ale_rx_page[i].page_map, 1176 sc->ale_cdata.ale_rx_page[i].page_addr, 1177 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1178 if (error != 0 || ctx.ale_busaddr == 0) { 1179 device_printf(sc->ale_dev, 1180 "could not load DMA'able memory for " 1181 "Rx page %d.\n", i); 1182 goto fail; 1183 } 1184 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1185 } 1186 1187 /* Tx CMB. */ 1188 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1189 (void **)&sc->ale_cdata.ale_tx_cmb, 1190 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1191 &sc->ale_cdata.ale_tx_cmb_map); 1192 if (error != 0) { 1193 device_printf(sc->ale_dev, 1194 "could not allocate DMA'able memory for Tx CMB.\n"); 1195 goto fail; 1196 } 1197 ctx.ale_busaddr = 0; 1198 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1199 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1200 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1201 if (error != 0 || ctx.ale_busaddr == 0) { 1202 device_printf(sc->ale_dev, 1203 "could not load DMA'able memory for Tx CMB.\n"); 1204 goto fail; 1205 } 1206 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1207 1208 /* Rx CMB. */ 1209 for (i = 0; i < ALE_RX_PAGES; i++) { 1210 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1211 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1212 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1213 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1214 if (error != 0) { 1215 device_printf(sc->ale_dev, "could not allocate " 1216 "DMA'able memory for Rx page %d CMB.\n", i); 1217 goto fail; 1218 } 1219 ctx.ale_busaddr = 0; 1220 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1221 sc->ale_cdata.ale_rx_page[i].cmb_map, 1222 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1223 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1224 if (error != 0 || ctx.ale_busaddr == 0) { 1225 device_printf(sc->ale_dev, "could not load DMA'able " 1226 "memory for Rx page %d CMB.\n", i); 1227 goto fail; 1228 } 1229 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1230 } 1231 1232 /* 1233 * Tx descriptors/RXF0/CMB DMA blocks share the same 1234 * high address region of 64bit DMA address space. 1235 */ 1236 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1237 (error = ale_check_boundary(sc)) != 0) { 1238 device_printf(sc->ale_dev, "4GB boundary crossed, " 1239 "switching to 32bit DMA addressing mode.\n"); 1240 ale_dma_free(sc); 1241 /* 1242 * Limit max allowable DMA address space to 32bit 1243 * and try again. 1244 */ 1245 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1246 goto again; 1247 } 1248 1249 /* 1250 * Create Tx buffer parent tag. 1251 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1252 * needs separate parent DMA tag as parent DMA address space 1253 * could be restricted to be within 32bit address space by 1254 * 4GB boundary crossing. 1255 */ 1256 error = bus_dma_tag_create( 1257 bus_get_dma_tag(sc->ale_dev), /* parent */ 1258 1, 0, /* alignment, boundary */ 1259 BUS_SPACE_MAXADDR, /* lowaddr */ 1260 BUS_SPACE_MAXADDR, /* highaddr */ 1261 NULL, NULL, /* filter, filterarg */ 1262 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1263 0, /* nsegments */ 1264 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1265 0, /* flags */ 1266 NULL, NULL, /* lockfunc, lockarg */ 1267 &sc->ale_cdata.ale_buffer_tag); 1268 if (error != 0) { 1269 device_printf(sc->ale_dev, 1270 "could not create parent buffer DMA tag.\n"); 1271 goto fail; 1272 } 1273 1274 /* Create DMA tag for Tx buffers. */ 1275 error = bus_dma_tag_create( 1276 sc->ale_cdata.ale_buffer_tag, /* parent */ 1277 1, 0, /* alignment, boundary */ 1278 BUS_SPACE_MAXADDR, /* lowaddr */ 1279 BUS_SPACE_MAXADDR, /* highaddr */ 1280 NULL, NULL, /* filter, filterarg */ 1281 ALE_TSO_MAXSIZE, /* maxsize */ 1282 ALE_MAXTXSEGS, /* nsegments */ 1283 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1284 0, /* flags */ 1285 NULL, NULL, /* lockfunc, lockarg */ 1286 &sc->ale_cdata.ale_tx_tag); 1287 if (error != 0) { 1288 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1289 goto fail; 1290 } 1291 1292 /* Create DMA maps for Tx buffers. */ 1293 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1294 txd = &sc->ale_cdata.ale_txdesc[i]; 1295 txd->tx_m = NULL; 1296 txd->tx_dmamap = NULL; 1297 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1298 &txd->tx_dmamap); 1299 if (error != 0) { 1300 device_printf(sc->ale_dev, 1301 "could not create Tx dmamap.\n"); 1302 goto fail; 1303 } 1304 } 1305 1306fail: 1307 return (error); 1308} 1309 1310static void 1311ale_dma_free(struct ale_softc *sc) 1312{ 1313 struct ale_txdesc *txd; 1314 int i; 1315 1316 /* Tx buffers. */ 1317 if (sc->ale_cdata.ale_tx_tag != NULL) { 1318 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1319 txd = &sc->ale_cdata.ale_txdesc[i]; 1320 if (txd->tx_dmamap != NULL) { 1321 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1322 txd->tx_dmamap); 1323 txd->tx_dmamap = NULL; 1324 } 1325 } 1326 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1327 sc->ale_cdata.ale_tx_tag = NULL; 1328 } 1329 /* Tx descriptor ring. */ 1330 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1331 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1332 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1333 sc->ale_cdata.ale_tx_ring_map); 1334 if (sc->ale_cdata.ale_tx_ring != NULL) 1335 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1336 sc->ale_cdata.ale_tx_ring, 1337 sc->ale_cdata.ale_tx_ring_map); 1338 sc->ale_cdata.ale_tx_ring_paddr = 0; 1339 sc->ale_cdata.ale_tx_ring = NULL; 1340 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1341 sc->ale_cdata.ale_tx_ring_tag = NULL; 1342 } 1343 /* Rx page block. */ 1344 for (i = 0; i < ALE_RX_PAGES; i++) { 1345 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1346 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1347 bus_dmamap_unload( 1348 sc->ale_cdata.ale_rx_page[i].page_tag, 1349 sc->ale_cdata.ale_rx_page[i].page_map); 1350 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1351 bus_dmamem_free( 1352 sc->ale_cdata.ale_rx_page[i].page_tag, 1353 sc->ale_cdata.ale_rx_page[i].page_addr, 1354 sc->ale_cdata.ale_rx_page[i].page_map); 1355 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1356 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1357 bus_dma_tag_destroy( 1358 sc->ale_cdata.ale_rx_page[i].page_tag); 1359 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1360 } 1361 } 1362 /* Rx CMB. */ 1363 for (i = 0; i < ALE_RX_PAGES; i++) { 1364 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1365 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1366 bus_dmamap_unload( 1367 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1368 sc->ale_cdata.ale_rx_page[i].cmb_map); 1369 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1370 bus_dmamem_free( 1371 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1372 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1373 sc->ale_cdata.ale_rx_page[i].cmb_map); 1374 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1375 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1376 bus_dma_tag_destroy( 1377 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1378 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1379 } 1380 } 1381 /* Tx CMB. */ 1382 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1383 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1384 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1385 sc->ale_cdata.ale_tx_cmb_map); 1386 if (sc->ale_cdata.ale_tx_cmb != NULL) 1387 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1388 sc->ale_cdata.ale_tx_cmb, 1389 sc->ale_cdata.ale_tx_cmb_map); 1390 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1391 sc->ale_cdata.ale_tx_cmb = NULL; 1392 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1393 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1394 } 1395 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1396 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1397 sc->ale_cdata.ale_buffer_tag = NULL; 1398 } 1399 if (sc->ale_cdata.ale_parent_tag != NULL) { 1400 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1401 sc->ale_cdata.ale_parent_tag = NULL; 1402 } 1403} 1404 1405static int 1406ale_shutdown(device_t dev) 1407{ 1408 1409 return (ale_suspend(dev)); 1410} 1411 1412/* 1413 * Note, this driver resets the link speed to 10/100Mbps by 1414 * restarting auto-negotiation in suspend/shutdown phase but we 1415 * don't know whether that auto-negotiation would succeed or not 1416 * as driver has no control after powering off/suspend operation. 1417 * If the renegotiation fail WOL may not work. Running at 1Gbps 1418 * will draw more power than 375mA at 3.3V which is specified in 1419 * PCI specification and that would result in complete 1420 * shutdowning power to ethernet controller. 1421 * 1422 * TODO 1423 * Save current negotiated media speed/duplex/flow-control to 1424 * softc and restore the same link again after resuming. PHY 1425 * handling such as power down/resetting to 100Mbps may be better 1426 * handled in suspend method in phy driver. 1427 */ 1428static void 1429ale_setlinkspeed(struct ale_softc *sc) 1430{ 1431 struct mii_data *mii; 1432 int aneg, i; 1433 1434 mii = device_get_softc(sc->ale_miibus); 1435 mii_pollstat(mii); 1436 aneg = 0; 1437 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1438 (IFM_ACTIVE | IFM_AVALID)) { 1439 switch IFM_SUBTYPE(mii->mii_media_active) { 1440 case IFM_10_T: 1441 case IFM_100_TX: 1442 return; 1443 case IFM_1000_T: 1444 aneg++; 1445 break; 1446 default: 1447 break; 1448 } 1449 } 1450 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1451 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1452 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1453 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1454 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1455 DELAY(1000); 1456 if (aneg != 0) { 1457 /* 1458 * Poll link state until ale(4) get a 10/100Mbps link. 1459 */ 1460 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1461 mii_pollstat(mii); 1462 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1463 == (IFM_ACTIVE | IFM_AVALID)) { 1464 switch (IFM_SUBTYPE( 1465 mii->mii_media_active)) { 1466 case IFM_10_T: 1467 case IFM_100_TX: 1468 ale_mac_config(sc); 1469 return; 1470 default: 1471 break; 1472 } 1473 } 1474 ALE_UNLOCK(sc); 1475 pause("alelnk", hz); 1476 ALE_LOCK(sc); 1477 } 1478 if (i == MII_ANEGTICKS_GIGE) 1479 device_printf(sc->ale_dev, 1480 "establishing a link failed, WOL may not work!"); 1481 } 1482 /* 1483 * No link, force MAC to have 100Mbps, full-duplex link. 1484 * This is the last resort and may/may not work. 1485 */ 1486 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1487 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1488 ale_mac_config(sc); 1489} 1490 1491static void 1492ale_setwol(struct ale_softc *sc) 1493{ 1494 struct ifnet *ifp; 1495 uint32_t reg, pmcs; 1496 uint16_t pmstat; 1497 int pmc; 1498 1499 ALE_LOCK_ASSERT(sc); 1500 1501 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1502 /* Disable WOL. */ 1503 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1504 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1505 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1506 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1507 /* Force PHY power down. */ 1508 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1509 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1510 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1511 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1512 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1513 return; 1514 } 1515 1516 ifp = sc->ale_ifp; 1517 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1518 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1519 ale_setlinkspeed(sc); 1520 } 1521 1522 pmcs = 0; 1523 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1524 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1525 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1526 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1527 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1528 MAC_CFG_BCAST); 1529 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1530 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1531 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1532 reg |= MAC_CFG_RX_ENB; 1533 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1534 1535 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1536 /* WOL disabled, PHY power down. */ 1537 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1538 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1539 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1540 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1541 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1542 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1543 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1544 GPHY_CTRL_PWDOWN_HW); 1545 } 1546 /* Request PME. */ 1547 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1548 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1549 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1550 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1551 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1552} 1553 1554static int 1555ale_suspend(device_t dev) 1556{ 1557 struct ale_softc *sc; 1558 1559 sc = device_get_softc(dev); 1560 1561 ALE_LOCK(sc); 1562 ale_stop(sc); 1563 ale_setwol(sc); 1564 ALE_UNLOCK(sc); 1565 1566 return (0); 1567} 1568 1569static int 1570ale_resume(device_t dev) 1571{ 1572 struct ale_softc *sc; 1573 struct ifnet *ifp; 1574 int pmc; 1575 uint16_t pmstat; 1576 1577 sc = device_get_softc(dev); 1578 1579 ALE_LOCK(sc); 1580 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1581 /* Disable PME and clear PME status. */ 1582 pmstat = pci_read_config(sc->ale_dev, 1583 pmc + PCIR_POWER_STATUS, 2); 1584 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1585 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1586 pci_write_config(sc->ale_dev, 1587 pmc + PCIR_POWER_STATUS, pmstat, 2); 1588 } 1589 } 1590 /* Reset PHY. */ 1591 ale_phy_reset(sc); 1592 ifp = sc->ale_ifp; 1593 if ((ifp->if_flags & IFF_UP) != 0) { 1594 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1595 ale_init_locked(sc); 1596 } 1597 ALE_UNLOCK(sc); 1598 1599 return (0); 1600} 1601 1602static int 1603ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1604{ 1605 struct ale_txdesc *txd, *txd_last; 1606 struct tx_desc *desc; 1607 struct mbuf *m; 1608 struct ip *ip; 1609 struct tcphdr *tcp; 1610 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1611 bus_dmamap_t map; 1612 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1613 int error, i, nsegs, prod, si; 1614 1615 ALE_LOCK_ASSERT(sc); 1616 1617 M_ASSERTPKTHDR((*m_head)); 1618 1619 m = *m_head; 1620 ip = NULL; 1621 tcp = NULL; 1622 cflags = vtag = 0; 1623 ip_off = poff = 0; 1624 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1625 /* 1626 * AR81xx requires offset of TCP/UDP payload in its Tx 1627 * descriptor to perform hardware Tx checksum offload. 1628 * Additionally, TSO requires IP/TCP header size and 1629 * modification of IP/TCP header in order to make TSO 1630 * engine work. This kind of operation takes many CPU 1631 * cycles on FreeBSD so fast host CPU is required to 1632 * get smooth TSO performance. 1633 */ 1634 struct ether_header *eh; 1635 1636 if (M_WRITABLE(m) == 0) { 1637 /* Get a writable copy. */ 1638 m = m_dup(*m_head, M_NOWAIT); 1639 /* Release original mbufs. */ 1640 m_freem(*m_head); 1641 if (m == NULL) { 1642 *m_head = NULL; 1643 return (ENOBUFS); 1644 } 1645 *m_head = m; 1646 } 1647 1648 /* 1649 * Buggy-controller requires 4 byte aligned Tx buffer 1650 * to make custom checksum offload work. 1651 */ 1652 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1653 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1654 (mtod(m, intptr_t) & 3) != 0) { 1655 m = m_defrag(*m_head, M_NOWAIT); 1656 if (m == NULL) { 1657 m_freem(*m_head); 1658 *m_head = NULL; 1659 return (ENOBUFS); 1660 } 1661 *m_head = m; 1662 } 1663 1664 ip_off = sizeof(struct ether_header); 1665 m = m_pullup(m, ip_off); 1666 if (m == NULL) { 1667 *m_head = NULL; 1668 return (ENOBUFS); 1669 } 1670 eh = mtod(m, struct ether_header *); 1671 /* 1672 * Check if hardware VLAN insertion is off. 1673 * Additional check for LLC/SNAP frame? 1674 */ 1675 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1676 ip_off = sizeof(struct ether_vlan_header); 1677 m = m_pullup(m, ip_off); 1678 if (m == NULL) { 1679 *m_head = NULL; 1680 return (ENOBUFS); 1681 } 1682 } 1683 m = m_pullup(m, ip_off + sizeof(struct ip)); 1684 if (m == NULL) { 1685 *m_head = NULL; 1686 return (ENOBUFS); 1687 } 1688 ip = (struct ip *)(mtod(m, char *) + ip_off); 1689 poff = ip_off + (ip->ip_hl << 2); 1690 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1691 /* 1692 * XXX 1693 * AR81xx requires the first descriptor should 1694 * not include any TCP playload for TSO case. 1695 * (i.e. ethernet header + IP + TCP header only) 1696 * m_pullup(9) above will ensure this too. 1697 * However it's not correct if the first mbuf 1698 * of the chain does not use cluster. 1699 */ 1700 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1701 if (m == NULL) { 1702 *m_head = NULL; 1703 return (ENOBUFS); 1704 } 1705 ip = (struct ip *)(mtod(m, char *) + ip_off); 1706 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1707 m = m_pullup(m, poff + (tcp->th_off << 2)); 1708 if (m == NULL) { 1709 *m_head = NULL; 1710 return (ENOBUFS); 1711 } 1712 /* 1713 * AR81xx requires IP/TCP header size and offset as 1714 * well as TCP pseudo checksum which complicates 1715 * TSO configuration. I guess this comes from the 1716 * adherence to Microsoft NDIS Large Send 1717 * specification which requires insertion of 1718 * pseudo checksum by upper stack. The pseudo 1719 * checksum that NDIS refers to doesn't include 1720 * TCP payload length so ale(4) should recompute 1721 * the pseudo checksum here. Hopefully this wouldn't 1722 * be much burden on modern CPUs. 1723 * Reset IP checksum and recompute TCP pseudo 1724 * checksum as NDIS specification said. 1725 */ 1726 ip->ip_sum = 0; 1727 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1728 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1729 } 1730 *m_head = m; 1731 } 1732 1733 si = prod = sc->ale_cdata.ale_tx_prod; 1734 txd = &sc->ale_cdata.ale_txdesc[prod]; 1735 txd_last = txd; 1736 map = txd->tx_dmamap; 1737 1738 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1739 *m_head, txsegs, &nsegs, 0); 1740 if (error == EFBIG) { 1741 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1742 if (m == NULL) { 1743 m_freem(*m_head); 1744 *m_head = NULL; 1745 return (ENOMEM); 1746 } 1747 *m_head = m; 1748 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1749 *m_head, txsegs, &nsegs, 0); 1750 if (error != 0) { 1751 m_freem(*m_head); 1752 *m_head = NULL; 1753 return (error); 1754 } 1755 } else if (error != 0) 1756 return (error); 1757 if (nsegs == 0) { 1758 m_freem(*m_head); 1759 *m_head = NULL; 1760 return (EIO); 1761 } 1762 1763 /* Check descriptor overrun. */ 1764 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1765 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1766 return (ENOBUFS); 1767 } 1768 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1769 1770 m = *m_head; 1771 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1772 /* Request TSO and set MSS. */ 1773 cflags |= ALE_TD_TSO; 1774 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1775 /* Set IP/TCP header size. */ 1776 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1777 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1778 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1779 /* 1780 * AR81xx supports Tx custom checksum offload feature 1781 * that offloads single 16bit checksum computation. 1782 * So you can choose one among IP, TCP and UDP. 1783 * Normally driver sets checksum start/insertion 1784 * position from the information of TCP/UDP frame as 1785 * TCP/UDP checksum takes more time than that of IP. 1786 * However it seems that custom checksum offload 1787 * requires 4 bytes aligned Tx buffers due to hardware 1788 * bug. 1789 * AR81xx also supports explicit Tx checksum computation 1790 * if it is told that the size of IP header and TCP 1791 * header(for UDP, the header size does not matter 1792 * because it's fixed length). However with this scheme 1793 * TSO does not work so you have to choose one either 1794 * TSO or explicit Tx checksum offload. I chosen TSO 1795 * plus custom checksum offload with work-around which 1796 * will cover most common usage for this consumer 1797 * ethernet controller. The work-around takes a lot of 1798 * CPU cycles if Tx buffer is not aligned on 4 bytes 1799 * boundary, though. 1800 */ 1801 cflags |= ALE_TD_CXSUM; 1802 /* Set checksum start offset. */ 1803 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1804 /* Set checksum insertion position of TCP/UDP. */ 1805 cflags |= ((poff + m->m_pkthdr.csum_data) << 1806 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1807 } 1808 1809 /* Configure VLAN hardware tag insertion. */ 1810 if ((m->m_flags & M_VLANTAG) != 0) { 1811 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1812 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1813 cflags |= ALE_TD_INSERT_VLAN_TAG; 1814 } 1815 1816 i = 0; 1817 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1818 /* 1819 * Make sure the first fragment contains 1820 * only ethernet and IP/TCP header with options. 1821 */ 1822 hdrlen = poff + (tcp->th_off << 2); 1823 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1824 desc->addr = htole64(txsegs[i].ds_addr); 1825 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1826 desc->flags = htole32(cflags); 1827 sc->ale_cdata.ale_tx_cnt++; 1828 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1829 if (m->m_len - hdrlen > 0) { 1830 /* Handle remaining payload of the first fragment. */ 1831 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1832 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1833 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1834 vtag); 1835 desc->flags = htole32(cflags); 1836 sc->ale_cdata.ale_tx_cnt++; 1837 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1838 } 1839 i = 1; 1840 } 1841 for (; i < nsegs; i++) { 1842 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1843 desc->addr = htole64(txsegs[i].ds_addr); 1844 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1845 desc->flags = htole32(cflags); 1846 sc->ale_cdata.ale_tx_cnt++; 1847 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1848 } 1849 /* Update producer index. */ 1850 sc->ale_cdata.ale_tx_prod = prod; 1851 /* Set TSO header on the first descriptor. */ 1852 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1853 desc = &sc->ale_cdata.ale_tx_ring[si]; 1854 desc->flags |= htole32(ALE_TD_TSO_HDR); 1855 } 1856 1857 /* Finally set EOP on the last descriptor. */ 1858 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1859 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1860 desc->flags |= htole32(ALE_TD_EOP); 1861 1862 /* Swap dmamap of the first and the last. */ 1863 txd = &sc->ale_cdata.ale_txdesc[prod]; 1864 map = txd_last->tx_dmamap; 1865 txd_last->tx_dmamap = txd->tx_dmamap; 1866 txd->tx_dmamap = map; 1867 txd->tx_m = m; 1868 1869 /* Sync descriptors. */ 1870 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1871 sc->ale_cdata.ale_tx_ring_map, 1872 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1873 1874 return (0); 1875} 1876 1877static void 1878ale_start(struct ifnet *ifp) 1879{ 1880 struct ale_softc *sc; 1881 1882 sc = ifp->if_softc; 1883 ALE_LOCK(sc); 1884 ale_start_locked(ifp); 1885 ALE_UNLOCK(sc); 1886} 1887 1888static void 1889ale_start_locked(struct ifnet *ifp) 1890{ 1891 struct ale_softc *sc; 1892 struct mbuf *m_head; 1893 int enq; 1894 1895 sc = ifp->if_softc; 1896 1897 ALE_LOCK_ASSERT(sc); 1898 1899 /* Reclaim transmitted frames. */ 1900 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1901 ale_txeof(sc); 1902 1903 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1904 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1905 return; 1906 1907 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1908 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1909 if (m_head == NULL) 1910 break; 1911 /* 1912 * Pack the data into the transmit ring. If we 1913 * don't have room, set the OACTIVE flag and wait 1914 * for the NIC to drain the ring. 1915 */ 1916 if (ale_encap(sc, &m_head)) { 1917 if (m_head == NULL) 1918 break; 1919 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1920 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1921 break; 1922 } 1923 1924 enq++; 1925 /* 1926 * If there's a BPF listener, bounce a copy of this frame 1927 * to him. 1928 */ 1929 ETHER_BPF_MTAP(ifp, m_head); 1930 } 1931 1932 if (enq > 0) { 1933 /* Kick. */ 1934 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1935 sc->ale_cdata.ale_tx_prod); 1936 /* Set a timeout in case the chip goes out to lunch. */ 1937 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1938 } 1939} 1940 1941static void 1942ale_watchdog(struct ale_softc *sc) 1943{ 1944 struct ifnet *ifp; 1945 1946 ALE_LOCK_ASSERT(sc); 1947 1948 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1949 return; 1950 1951 ifp = sc->ale_ifp; 1952 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1953 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1954 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1955 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1956 ale_init_locked(sc); 1957 return; 1958 } 1959 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1960 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1961 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1962 ale_init_locked(sc); 1963 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1964 ale_start_locked(ifp); 1965} 1966 1967static int 1968ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1969{ 1970 struct ale_softc *sc; 1971 struct ifreq *ifr; 1972 struct mii_data *mii; 1973 int error, mask; 1974 1975 sc = ifp->if_softc; 1976 ifr = (struct ifreq *)data; 1977 error = 0; 1978 switch (cmd) { 1979 case SIOCSIFMTU: 1980 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1981 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1982 ifr->ifr_mtu > ETHERMTU)) 1983 error = EINVAL; 1984 else if (ifp->if_mtu != ifr->ifr_mtu) { 1985 ALE_LOCK(sc); 1986 ifp->if_mtu = ifr->ifr_mtu; 1987 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1988 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1989 ale_init_locked(sc); 1990 } 1991 ALE_UNLOCK(sc); 1992 } 1993 break; 1994 case SIOCSIFFLAGS: 1995 ALE_LOCK(sc); 1996 if ((ifp->if_flags & IFF_UP) != 0) { 1997 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1998 if (((ifp->if_flags ^ sc->ale_if_flags) 1999 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2000 ale_rxfilter(sc); 2001 } else { 2002 ale_init_locked(sc); 2003 } 2004 } else { 2005 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2006 ale_stop(sc); 2007 } 2008 sc->ale_if_flags = ifp->if_flags; 2009 ALE_UNLOCK(sc); 2010 break; 2011 case SIOCADDMULTI: 2012 case SIOCDELMULTI: 2013 ALE_LOCK(sc); 2014 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2015 ale_rxfilter(sc); 2016 ALE_UNLOCK(sc); 2017 break; 2018 case SIOCSIFMEDIA: 2019 case SIOCGIFMEDIA: 2020 mii = device_get_softc(sc->ale_miibus); 2021 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2022 break; 2023 case SIOCSIFCAP: 2024 ALE_LOCK(sc); 2025 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2026 if ((mask & IFCAP_TXCSUM) != 0 && 2027 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2028 ifp->if_capenable ^= IFCAP_TXCSUM; 2029 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2030 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2031 else 2032 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2033 } 2034 if ((mask & IFCAP_RXCSUM) != 0 && 2035 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2036 ifp->if_capenable ^= IFCAP_RXCSUM; 2037 if ((mask & IFCAP_TSO4) != 0 && 2038 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2039 ifp->if_capenable ^= IFCAP_TSO4; 2040 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2041 ifp->if_hwassist |= CSUM_TSO; 2042 else 2043 ifp->if_hwassist &= ~CSUM_TSO; 2044 } 2045 2046 if ((mask & IFCAP_WOL_MCAST) != 0 && 2047 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2048 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2049 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2050 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2051 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2052 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2053 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2054 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2055 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2056 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2057 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2058 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2059 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2060 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2061 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2062 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2063 ale_rxvlan(sc); 2064 } 2065 ALE_UNLOCK(sc); 2066 VLAN_CAPABILITIES(ifp); 2067 break; 2068 default: 2069 error = ether_ioctl(ifp, cmd, data); 2070 break; 2071 } 2072 2073 return (error); 2074} 2075 2076static void 2077ale_mac_config(struct ale_softc *sc) 2078{ 2079 struct mii_data *mii; 2080 uint32_t reg; 2081 2082 ALE_LOCK_ASSERT(sc); 2083 2084 mii = device_get_softc(sc->ale_miibus); 2085 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2086 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2087 MAC_CFG_SPEED_MASK); 2088 /* Reprogram MAC with resolved speed/duplex. */ 2089 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2090 case IFM_10_T: 2091 case IFM_100_TX: 2092 reg |= MAC_CFG_SPEED_10_100; 2093 break; 2094 case IFM_1000_T: 2095 reg |= MAC_CFG_SPEED_1000; 2096 break; 2097 } 2098 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2099 reg |= MAC_CFG_FULL_DUPLEX; 2100 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2101 reg |= MAC_CFG_TX_FC; 2102 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2103 reg |= MAC_CFG_RX_FC; 2104 } 2105 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2106} 2107 2108static void 2109ale_stats_clear(struct ale_softc *sc) 2110{ 2111 struct smb sb; 2112 uint32_t *reg; 2113 int i; 2114 2115 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2116 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2117 i += sizeof(uint32_t); 2118 } 2119 /* Read Tx statistics. */ 2120 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2121 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2122 i += sizeof(uint32_t); 2123 } 2124} 2125 2126static void 2127ale_stats_update(struct ale_softc *sc) 2128{ 2129 struct ale_hw_stats *stat; 2130 struct smb sb, *smb; 2131 struct ifnet *ifp; 2132 uint32_t *reg; 2133 int i; 2134 2135 ALE_LOCK_ASSERT(sc); 2136 2137 ifp = sc->ale_ifp; 2138 stat = &sc->ale_stats; 2139 smb = &sb; 2140 2141 /* Read Rx statistics. */ 2142 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2143 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2144 i += sizeof(uint32_t); 2145 } 2146 /* Read Tx statistics. */ 2147 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2148 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2149 i += sizeof(uint32_t); 2150 } 2151 2152 /* Rx stats. */ 2153 stat->rx_frames += smb->rx_frames; 2154 stat->rx_bcast_frames += smb->rx_bcast_frames; 2155 stat->rx_mcast_frames += smb->rx_mcast_frames; 2156 stat->rx_pause_frames += smb->rx_pause_frames; 2157 stat->rx_control_frames += smb->rx_control_frames; 2158 stat->rx_crcerrs += smb->rx_crcerrs; 2159 stat->rx_lenerrs += smb->rx_lenerrs; 2160 stat->rx_bytes += smb->rx_bytes; 2161 stat->rx_runts += smb->rx_runts; 2162 stat->rx_fragments += smb->rx_fragments; 2163 stat->rx_pkts_64 += smb->rx_pkts_64; 2164 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2165 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2166 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2167 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2168 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2169 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2170 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2171 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2172 stat->rx_rrs_errs += smb->rx_rrs_errs; 2173 stat->rx_alignerrs += smb->rx_alignerrs; 2174 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2175 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2176 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2177 2178 /* Tx stats. */ 2179 stat->tx_frames += smb->tx_frames; 2180 stat->tx_bcast_frames += smb->tx_bcast_frames; 2181 stat->tx_mcast_frames += smb->tx_mcast_frames; 2182 stat->tx_pause_frames += smb->tx_pause_frames; 2183 stat->tx_excess_defer += smb->tx_excess_defer; 2184 stat->tx_control_frames += smb->tx_control_frames; 2185 stat->tx_deferred += smb->tx_deferred; 2186 stat->tx_bytes += smb->tx_bytes; 2187 stat->tx_pkts_64 += smb->tx_pkts_64; 2188 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2189 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2190 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2191 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2192 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2193 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2194 stat->tx_single_colls += smb->tx_single_colls; 2195 stat->tx_multi_colls += smb->tx_multi_colls; 2196 stat->tx_late_colls += smb->tx_late_colls; 2197 stat->tx_excess_colls += smb->tx_excess_colls; 2198 stat->tx_underrun += smb->tx_underrun; 2199 stat->tx_desc_underrun += smb->tx_desc_underrun; 2200 stat->tx_lenerrs += smb->tx_lenerrs; 2201 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2202 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2203 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2204 2205 /* Update counters in ifnet. */ 2206 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2207 2208 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2209 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2210 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2211 2212 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2213 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2214 2215 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2216 2217 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2218 smb->rx_crcerrs + smb->rx_lenerrs + 2219 smb->rx_runts + smb->rx_pkts_truncated + 2220 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2221 smb->rx_alignerrs); 2222} 2223 2224static int 2225ale_intr(void *arg) 2226{ 2227 struct ale_softc *sc; 2228 uint32_t status; 2229 2230 sc = (struct ale_softc *)arg; 2231 2232 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2233 if ((status & ALE_INTRS) == 0) 2234 return (FILTER_STRAY); 2235 /* Disable interrupts. */ 2236 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2237 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2238 2239 return (FILTER_HANDLED); 2240} 2241 2242static void 2243ale_int_task(void *arg, int pending) 2244{ 2245 struct ale_softc *sc; 2246 struct ifnet *ifp; 2247 uint32_t status; 2248 int more; 2249 2250 sc = (struct ale_softc *)arg; 2251 2252 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2253 ALE_LOCK(sc); 2254 if (sc->ale_morework != 0) 2255 status |= INTR_RX_PKT; 2256 if ((status & ALE_INTRS) == 0) 2257 goto done; 2258 2259 /* Acknowledge interrupts but still disable interrupts. */ 2260 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2261 2262 ifp = sc->ale_ifp; 2263 more = 0; 2264 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2265 more = ale_rxeof(sc, sc->ale_process_limit); 2266 if (more == EAGAIN) 2267 sc->ale_morework = 1; 2268 else if (more == EIO) { 2269 sc->ale_stats.reset_brk_seq++; 2270 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2271 ale_init_locked(sc); 2272 ALE_UNLOCK(sc); 2273 return; 2274 } 2275 2276 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2277 if ((status & INTR_DMA_RD_TO_RST) != 0) 2278 device_printf(sc->ale_dev, 2279 "DMA read error! -- resetting\n"); 2280 if ((status & INTR_DMA_WR_TO_RST) != 0) 2281 device_printf(sc->ale_dev, 2282 "DMA write error! -- resetting\n"); 2283 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2284 ale_init_locked(sc); 2285 ALE_UNLOCK(sc); 2286 return; 2287 } 2288 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2289 ale_start_locked(ifp); 2290 } 2291 2292 if (more == EAGAIN || 2293 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2294 ALE_UNLOCK(sc); 2295 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2296 return; 2297 } 2298 2299done: 2300 ALE_UNLOCK(sc); 2301 2302 /* Re-enable interrupts. */ 2303 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2304} 2305 2306static void 2307ale_txeof(struct ale_softc *sc) 2308{ 2309 struct ifnet *ifp; 2310 struct ale_txdesc *txd; 2311 uint32_t cons, prod; 2312 int prog; 2313 2314 ALE_LOCK_ASSERT(sc); 2315 2316 ifp = sc->ale_ifp; 2317 2318 if (sc->ale_cdata.ale_tx_cnt == 0) 2319 return; 2320 2321 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2322 sc->ale_cdata.ale_tx_ring_map, 2323 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2324 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2325 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2326 sc->ale_cdata.ale_tx_cmb_map, 2327 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2328 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2329 } else 2330 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2331 cons = sc->ale_cdata.ale_tx_cons; 2332 /* 2333 * Go through our Tx list and free mbufs for those 2334 * frames which have been transmitted. 2335 */ 2336 for (prog = 0; cons != prod; prog++, 2337 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2338 if (sc->ale_cdata.ale_tx_cnt <= 0) 2339 break; 2340 prog++; 2341 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2342 sc->ale_cdata.ale_tx_cnt--; 2343 txd = &sc->ale_cdata.ale_txdesc[cons]; 2344 if (txd->tx_m != NULL) { 2345 /* Reclaim transmitted mbufs. */ 2346 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2347 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2348 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2349 txd->tx_dmamap); 2350 m_freem(txd->tx_m); 2351 txd->tx_m = NULL; 2352 } 2353 } 2354 2355 if (prog > 0) { 2356 sc->ale_cdata.ale_tx_cons = cons; 2357 /* 2358 * Unarm watchdog timer only when there is no pending 2359 * Tx descriptors in queue. 2360 */ 2361 if (sc->ale_cdata.ale_tx_cnt == 0) 2362 sc->ale_watchdog_timer = 0; 2363 } 2364} 2365 2366static void 2367ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2368 uint32_t length, uint32_t *prod) 2369{ 2370 struct ale_rx_page *rx_page; 2371 2372 rx_page = *page; 2373 /* Update consumer position. */ 2374 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2375 ALE_RX_PAGE_ALIGN); 2376 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2377 /* 2378 * End of Rx page reached, let hardware reuse 2379 * this page. 2380 */ 2381 rx_page->cons = 0; 2382 *rx_page->cmb_addr = 0; 2383 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2385 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2386 RXF_VALID); 2387 /* Switch to alternate Rx page. */ 2388 sc->ale_cdata.ale_rx_curp ^= 1; 2389 rx_page = *page = 2390 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2391 /* Page flipped, sync CMB and Rx page. */ 2392 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2393 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2394 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2395 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2396 /* Sync completed, cache updated producer index. */ 2397 *prod = *rx_page->cmb_addr; 2398 } 2399} 2400 2401 2402/* 2403 * It seems that AR81xx controller can compute partial checksum. 2404 * The partial checksum value can be used to accelerate checksum 2405 * computation for fragmented TCP/UDP packets. Upper network stack 2406 * already takes advantage of the partial checksum value in IP 2407 * reassembly stage. But I'm not sure the correctness of the 2408 * partial hardware checksum assistance due to lack of data sheet. 2409 * In addition, the Rx feature of controller that requires copying 2410 * for every frames effectively nullifies one of most nice offload 2411 * capability of controller. 2412 */ 2413static void 2414ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2415{ 2416 struct ifnet *ifp; 2417 struct ip *ip; 2418 char *p; 2419 2420 ifp = sc->ale_ifp; 2421 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2422 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2423 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2424 2425 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2426 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2427 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2428 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2429 m->m_pkthdr.csum_flags |= 2430 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2431 m->m_pkthdr.csum_data = 0xffff; 2432 } 2433 } else { 2434 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2435 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2436 p = mtod(m, char *); 2437 p += ETHER_HDR_LEN; 2438 if ((status & ALE_RD_802_3) != 0) 2439 p += LLC_SNAPFRAMELEN; 2440 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2441 (status & ALE_RD_VLAN) != 0) 2442 p += ETHER_VLAN_ENCAP_LEN; 2443 ip = (struct ip *)p; 2444 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2445 return; 2446 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2447 CSUM_PSEUDO_HDR; 2448 m->m_pkthdr.csum_data = 0xffff; 2449 } 2450 } 2451 /* 2452 * Don't mark bad checksum for TCP/UDP frames 2453 * as fragmented frames may always have set 2454 * bad checksummed bit of frame status. 2455 */ 2456} 2457 2458/* Process received frames. */ 2459static int 2460ale_rxeof(struct ale_softc *sc, int count) 2461{ 2462 struct ale_rx_page *rx_page; 2463 struct rx_rs *rs; 2464 struct ifnet *ifp; 2465 struct mbuf *m; 2466 uint32_t length, prod, seqno, status, vtags; 2467 int prog; 2468 2469 ifp = sc->ale_ifp; 2470 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2471 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2472 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2473 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2474 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2475 /* 2476 * Don't directly access producer index as hardware may 2477 * update it while Rx handler is in progress. It would 2478 * be even better if there is a way to let hardware 2479 * know how far driver processed its received frames. 2480 * Alternatively, hardware could provide a way to disable 2481 * CMB updates until driver acknowledges the end of CMB 2482 * access. 2483 */ 2484 prod = *rx_page->cmb_addr; 2485 for (prog = 0; prog < count; prog++) { 2486 if (rx_page->cons >= prod) 2487 break; 2488 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2489 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2490 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2491 /* 2492 * Normally I believe this should not happen unless 2493 * severe driver bug or corrupted memory. However 2494 * it seems to happen under certain conditions which 2495 * is triggered by abrupt Rx events such as initiation 2496 * of bulk transfer of remote host. It's not easy to 2497 * reproduce this and I doubt it could be related 2498 * with FIFO overflow of hardware or activity of Tx 2499 * CMB updates. I also remember similar behaviour 2500 * seen on RealTek 8139 which uses resembling Rx 2501 * scheme. 2502 */ 2503 if (bootverbose) 2504 device_printf(sc->ale_dev, 2505 "garbled seq: %u, expected: %u -- " 2506 "resetting!\n", seqno, 2507 sc->ale_cdata.ale_rx_seqno); 2508 return (EIO); 2509 } 2510 /* Frame received. */ 2511 sc->ale_cdata.ale_rx_seqno++; 2512 length = ALE_RX_BYTES(le32toh(rs->length)); 2513 status = le32toh(rs->flags); 2514 if ((status & ALE_RD_ERROR) != 0) { 2515 /* 2516 * We want to pass the following frames to upper 2517 * layer regardless of error status of Rx return 2518 * status. 2519 * 2520 * o IP/TCP/UDP checksum is bad. 2521 * o frame length and protocol specific length 2522 * does not match. 2523 */ 2524 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2525 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2526 ALE_RD_TRUNC)) != 0) { 2527 ale_rx_update_page(sc, &rx_page, length, &prod); 2528 continue; 2529 } 2530 } 2531 /* 2532 * m_devget(9) is major bottle-neck of ale(4)(It comes 2533 * from hardware limitation). For jumbo frames we could 2534 * get a slightly better performance if driver use 2535 * m_getjcl(9) with proper buffer size argument. However 2536 * that would make code more complicated and I don't 2537 * think users would expect good Rx performance numbers 2538 * on these low-end consumer ethernet controller. 2539 */ 2540 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2541 ETHER_ALIGN, ifp, NULL); 2542 if (m == NULL) { 2543 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2544 ale_rx_update_page(sc, &rx_page, length, &prod); 2545 continue; 2546 } 2547 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2548 (status & ALE_RD_IPV4) != 0) 2549 ale_rxcsum(sc, m, status); 2550 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2551 (status & ALE_RD_VLAN) != 0) { 2552 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2553 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2554 m->m_flags |= M_VLANTAG; 2555 } 2556 2557 /* Pass it to upper layer. */ 2558 ALE_UNLOCK(sc); 2559 (*ifp->if_input)(ifp, m); 2560 ALE_LOCK(sc); 2561 2562 ale_rx_update_page(sc, &rx_page, length, &prod); 2563 } 2564 2565 return (count > 0 ? 0 : EAGAIN); 2566} 2567 2568static void 2569ale_tick(void *arg) 2570{ 2571 struct ale_softc *sc; 2572 struct mii_data *mii; 2573 2574 sc = (struct ale_softc *)arg; 2575 2576 ALE_LOCK_ASSERT(sc); 2577 2578 mii = device_get_softc(sc->ale_miibus); 2579 mii_tick(mii); 2580 ale_stats_update(sc); 2581 /* 2582 * Reclaim Tx buffers that have been transferred. It's not 2583 * needed here but it would release allocated mbuf chains 2584 * faster and limit the maximum delay to a hz. 2585 */ 2586 ale_txeof(sc); 2587 ale_watchdog(sc); 2588 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2589} 2590 2591static void 2592ale_reset(struct ale_softc *sc) 2593{ 2594 uint32_t reg; 2595 int i; 2596 2597 /* Initialize PCIe module. From Linux. */ 2598 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2599 2600 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2601 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2602 DELAY(10); 2603 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2604 break; 2605 } 2606 if (i == 0) 2607 device_printf(sc->ale_dev, "master reset timeout!\n"); 2608 2609 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2610 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2611 break; 2612 DELAY(10); 2613 } 2614 2615 if (i == 0) 2616 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2617} 2618 2619static void 2620ale_init(void *xsc) 2621{ 2622 struct ale_softc *sc; 2623 2624 sc = (struct ale_softc *)xsc; 2625 ALE_LOCK(sc); 2626 ale_init_locked(sc); 2627 ALE_UNLOCK(sc); 2628} 2629 2630static void 2631ale_init_locked(struct ale_softc *sc) 2632{ 2633 struct ifnet *ifp; 2634 struct mii_data *mii; 2635 uint8_t eaddr[ETHER_ADDR_LEN]; 2636 bus_addr_t paddr; 2637 uint32_t reg, rxf_hi, rxf_lo; 2638 2639 ALE_LOCK_ASSERT(sc); 2640 2641 ifp = sc->ale_ifp; 2642 mii = device_get_softc(sc->ale_miibus); 2643 2644 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2645 return; 2646 /* 2647 * Cancel any pending I/O. 2648 */ 2649 ale_stop(sc); 2650 /* 2651 * Reset the chip to a known state. 2652 */ 2653 ale_reset(sc); 2654 /* Initialize Tx descriptors, DMA memory blocks. */ 2655 ale_init_rx_pages(sc); 2656 ale_init_tx_ring(sc); 2657 2658 /* Reprogram the station address. */ 2659 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2660 CSR_WRITE_4(sc, ALE_PAR0, 2661 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2662 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2663 /* 2664 * Clear WOL status and disable all WOL feature as WOL 2665 * would interfere Rx operation under normal environments. 2666 */ 2667 CSR_READ_4(sc, ALE_WOL_CFG); 2668 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2669 /* 2670 * Set Tx descriptor/RXF0/CMB base addresses. They share 2671 * the same high address part of DMAable region. 2672 */ 2673 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2674 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2675 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2676 CSR_WRITE_4(sc, ALE_TPD_CNT, 2677 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2678 /* Set Rx page base address, note we use single queue. */ 2679 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2680 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2681 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2682 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2683 /* Set Tx/Rx CMB addresses. */ 2684 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2685 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2686 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2687 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2688 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2689 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2690 /* Mark RXF0 is valid. */ 2691 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2692 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2693 /* 2694 * No need to initialize RFX1/RXF2/RXF3. We don't use 2695 * multi-queue yet. 2696 */ 2697 2698 /* Set Rx page size, excluding guard frame size. */ 2699 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2700 /* Tell hardware that we're ready to load DMA blocks. */ 2701 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2702 2703 /* Set Rx/Tx interrupt trigger threshold. */ 2704 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2705 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2706 /* 2707 * XXX 2708 * Set interrupt trigger timer, its purpose and relation 2709 * with interrupt moderation mechanism is not clear yet. 2710 */ 2711 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2712 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2713 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2714 2715 /* Configure interrupt moderation timer. */ 2716 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2717 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2718 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2719 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2720 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2721 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2722 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2723 reg |= MASTER_IM_RX_TIMER_ENB; 2724 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2725 reg |= MASTER_IM_TX_TIMER_ENB; 2726 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2727 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2728 2729 /* Set Maximum frame size of controller. */ 2730 if (ifp->if_mtu < ETHERMTU) 2731 sc->ale_max_frame_size = ETHERMTU; 2732 else 2733 sc->ale_max_frame_size = ifp->if_mtu; 2734 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2735 ETHER_CRC_LEN; 2736 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2737 /* Configure IPG/IFG parameters. */ 2738 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2739 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2740 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2741 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2742 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2743 /* Set parameters for half-duplex media. */ 2744 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2745 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2746 HDPX_CFG_LCOL_MASK) | 2747 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2748 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2749 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2750 HDPX_CFG_ABEBT_MASK) | 2751 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2752 HDPX_CFG_JAMIPG_MASK)); 2753 2754 /* Configure Tx jumbo frame parameters. */ 2755 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2756 if (ifp->if_mtu < ETHERMTU) 2757 reg = sc->ale_max_frame_size; 2758 else if (ifp->if_mtu < 6 * 1024) 2759 reg = (sc->ale_max_frame_size * 2) / 3; 2760 else 2761 reg = sc->ale_max_frame_size / 2; 2762 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2763 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2764 TX_JUMBO_THRESH_UNIT_SHIFT); 2765 } 2766 /* Configure TxQ. */ 2767 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2768 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2769 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2770 TXQ_CFG_TPD_BURST_MASK; 2771 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2772 2773 /* Configure Rx jumbo frame & flow control parameters. */ 2774 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2775 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2776 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2777 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2778 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2779 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2780 RX_JUMBO_LKAH_MASK)); 2781 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2782 rxf_hi = (reg * 7) / 10; 2783 rxf_lo = (reg * 3)/ 10; 2784 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2785 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2786 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2787 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2788 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2789 } 2790 2791 /* Disable RSS. */ 2792 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2793 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2794 2795 /* Configure RxQ. */ 2796 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2797 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2798 2799 /* Configure DMA parameters. */ 2800 reg = 0; 2801 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2802 reg |= DMA_CFG_TXCMB_ENB; 2803 CSR_WRITE_4(sc, ALE_DMA_CFG, 2804 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2805 sc->ale_dma_rd_burst | reg | 2806 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2807 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2808 DMA_CFG_RD_DELAY_CNT_MASK) | 2809 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2810 DMA_CFG_WR_DELAY_CNT_MASK)); 2811 2812 /* 2813 * Hardware can be configured to issue SMB interrupt based 2814 * on programmed interval. Since there is a callout that is 2815 * invoked for every hz in driver we use that instead of 2816 * relying on periodic SMB interrupt. 2817 */ 2818 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2819 /* Clear MAC statistics. */ 2820 ale_stats_clear(sc); 2821 2822 /* 2823 * Configure Tx/Rx MACs. 2824 * - Auto-padding for short frames. 2825 * - Enable CRC generation. 2826 * Actual reconfiguration of MAC for resolved speed/duplex 2827 * is followed after detection of link establishment. 2828 * AR81xx always does checksum computation regardless of 2829 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2830 * cause Rx handling issue for fragmented IP datagrams due 2831 * to silicon bug. 2832 */ 2833 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2834 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2835 MAC_CFG_PREAMBLE_MASK); 2836 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2837 reg |= MAC_CFG_SPEED_10_100; 2838 else 2839 reg |= MAC_CFG_SPEED_1000; 2840 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2841 2842 /* Set up the receive filter. */ 2843 ale_rxfilter(sc); 2844 ale_rxvlan(sc); 2845 2846 /* Acknowledge all pending interrupts and clear it. */ 2847 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2848 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2849 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2850 2851 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2852 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2853 2854 sc->ale_flags &= ~ALE_FLAG_LINK; 2855 /* Switch to the current media. */ 2856 mii_mediachg(mii); 2857 2858 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2859} 2860 2861static void 2862ale_stop(struct ale_softc *sc) 2863{ 2864 struct ifnet *ifp; 2865 struct ale_txdesc *txd; 2866 uint32_t reg; 2867 int i; 2868 2869 ALE_LOCK_ASSERT(sc); 2870 /* 2871 * Mark the interface down and cancel the watchdog timer. 2872 */ 2873 ifp = sc->ale_ifp; 2874 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2875 sc->ale_flags &= ~ALE_FLAG_LINK; 2876 callout_stop(&sc->ale_tick_ch); 2877 sc->ale_watchdog_timer = 0; 2878 ale_stats_update(sc); 2879 /* Disable interrupts. */ 2880 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2881 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2882 /* Disable queue processing and DMA. */ 2883 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2884 reg &= ~TXQ_CFG_ENB; 2885 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2886 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2887 reg &= ~RXQ_CFG_ENB; 2888 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2889 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2890 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2891 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2892 DELAY(1000); 2893 /* Stop Rx/Tx MACs. */ 2894 ale_stop_mac(sc); 2895 /* Disable interrupts which might be touched in taskq handler. */ 2896 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2897 2898 /* 2899 * Free TX mbufs still in the queues. 2900 */ 2901 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2902 txd = &sc->ale_cdata.ale_txdesc[i]; 2903 if (txd->tx_m != NULL) { 2904 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2905 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2906 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2907 txd->tx_dmamap); 2908 m_freem(txd->tx_m); 2909 txd->tx_m = NULL; 2910 } 2911 } 2912} 2913 2914static void 2915ale_stop_mac(struct ale_softc *sc) 2916{ 2917 uint32_t reg; 2918 int i; 2919 2920 ALE_LOCK_ASSERT(sc); 2921 2922 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2923 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2924 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2925 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2926 } 2927 2928 for (i = ALE_TIMEOUT; i > 0; i--) { 2929 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2930 if (reg == 0) 2931 break; 2932 DELAY(10); 2933 } 2934 if (i == 0) 2935 device_printf(sc->ale_dev, 2936 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2937} 2938 2939static void 2940ale_init_tx_ring(struct ale_softc *sc) 2941{ 2942 struct ale_txdesc *txd; 2943 int i; 2944 2945 ALE_LOCK_ASSERT(sc); 2946 2947 sc->ale_cdata.ale_tx_prod = 0; 2948 sc->ale_cdata.ale_tx_cons = 0; 2949 sc->ale_cdata.ale_tx_cnt = 0; 2950 2951 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2952 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2953 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2954 txd = &sc->ale_cdata.ale_txdesc[i]; 2955 txd->tx_m = NULL; 2956 } 2957 *sc->ale_cdata.ale_tx_cmb = 0; 2958 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2959 sc->ale_cdata.ale_tx_cmb_map, 2960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2961 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2962 sc->ale_cdata.ale_tx_ring_map, 2963 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2964} 2965 2966static void 2967ale_init_rx_pages(struct ale_softc *sc) 2968{ 2969 struct ale_rx_page *rx_page; 2970 int i; 2971 2972 ALE_LOCK_ASSERT(sc); 2973 2974 sc->ale_morework = 0; 2975 sc->ale_cdata.ale_rx_seqno = 0; 2976 sc->ale_cdata.ale_rx_curp = 0; 2977 2978 for (i = 0; i < ALE_RX_PAGES; i++) { 2979 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2980 bzero(rx_page->page_addr, sc->ale_pagesize); 2981 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2982 rx_page->cons = 0; 2983 *rx_page->cmb_addr = 0; 2984 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2986 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2987 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2988 } 2989} 2990 2991static void 2992ale_rxvlan(struct ale_softc *sc) 2993{ 2994 struct ifnet *ifp; 2995 uint32_t reg; 2996 2997 ALE_LOCK_ASSERT(sc); 2998 2999 ifp = sc->ale_ifp; 3000 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3001 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3002 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3003 reg |= MAC_CFG_VLAN_TAG_STRIP; 3004 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3005} 3006 3007static void 3008ale_rxfilter(struct ale_softc *sc) 3009{ 3010 struct ifnet *ifp; 3011 struct ifmultiaddr *ifma; 3012 uint32_t crc; 3013 uint32_t mchash[2]; 3014 uint32_t rxcfg; 3015 3016 ALE_LOCK_ASSERT(sc); 3017 3018 ifp = sc->ale_ifp; 3019 3020 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3021 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3022 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3023 rxcfg |= MAC_CFG_BCAST; 3024 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3025 if ((ifp->if_flags & IFF_PROMISC) != 0) 3026 rxcfg |= MAC_CFG_PROMISC; 3027 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3028 rxcfg |= MAC_CFG_ALLMULTI; 3029 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3030 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3031 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3032 return; 3033 } 3034 3035 /* Program new filter. */ 3036 bzero(mchash, sizeof(mchash)); 3037 3038 if_maddr_rlock(ifp); 3039 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3040 if (ifma->ifma_addr->sa_family != AF_LINK) 3041 continue; 3042 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3043 ifma->ifma_addr), ETHER_ADDR_LEN); 3044 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3045 } 3046 if_maddr_runlock(ifp); 3047 3048 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3049 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3050 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3051} 3052 3053static int 3054sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3055{ 3056 int error, value; 3057 3058 if (arg1 == NULL) 3059 return (EINVAL); 3060 value = *(int *)arg1; 3061 error = sysctl_handle_int(oidp, &value, 0, req); 3062 if (error || req->newptr == NULL) 3063 return (error); 3064 if (value < low || value > high) 3065 return (EINVAL); 3066 *(int *)arg1 = value; 3067 3068 return (0); 3069} 3070 3071static int 3072sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3073{ 3074 return (sysctl_int_range(oidp, arg1, arg2, req, 3075 ALE_PROC_MIN, ALE_PROC_MAX)); 3076} 3077 3078static int 3079sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3080{ 3081 3082 return (sysctl_int_range(oidp, arg1, arg2, req, 3083 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3084} 3085