if_alcreg.h revision 222107
1193880Syongari/*- 2193880Syongari * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3193880Syongari * All rights reserved. 4193880Syongari * 5193880Syongari * Redistribution and use in source and binary forms, with or without 6193880Syongari * modification, are permitted provided that the following conditions 7193880Syongari * are met: 8193880Syongari * 1. Redistributions of source code must retain the above copyright 9193880Syongari * notice unmodified, this list of conditions, and the following 10193880Syongari * disclaimer. 11193880Syongari * 2. Redistributions in binary form must reproduce the above copyright 12193880Syongari * notice, this list of conditions and the following disclaimer in the 13193880Syongari * documentation and/or other materials provided with the distribution. 14193880Syongari * 15193880Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16193880Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17193880Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18193880Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19193880Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20222107Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21193880Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22193880Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23193880Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24193880Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25222107Syongari * SUCH DAMAGE. 26193880Syongari * 27193880Syongari * $FreeBSD: head/sys/dev/alc/if_alcreg.h 222107 2011-05-19 23:13:08Z yongari $ 28193880Syongari */ 29193880Syongari 30193880Syongari#ifndef _IF_ALCREG_H 31193880Syongari#define _IF_ALCREG_H 32193880Syongari 33193880Syongari/* 34193880Syongari * Atheros Communucations, Inc. PCI vendor ID 35193880Syongari */ 36193880Syongari#define VENDORID_ATHEROS 0x1969 37193880Syongari 38193880Syongari/* 39211105Syongari * Atheros AR813x/AR815x device ID 40193880Syongari */ 41193880Syongari#define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 42193880Syongari#define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 43211105Syongari#define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 44211105Syongari#define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 45211105Syongari#define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 46211105Syongari#define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 47193880Syongari 48211105Syongari#define ATHEROS_AR8152_B_V10 0xC0 49211105Syongari#define ATHEROS_AR8152_B_V11 0xC1 50211105Syongari 51193880Syongari/* 0x0000 - 0x02FF : PCIe configuration space */ 52193880Syongari 53193880Syongari#define ALC_PEX_UNC_ERR_SEV 0x10C 54193880Syongari#define PEX_UNC_ERR_SEV_TRN 0x00000001 55193880Syongari#define PEX_UNC_ERR_SEV_DLP 0x00000010 56193880Syongari#define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 57193880Syongari#define PEX_UNC_ERR_SEV_FCP 0x00002000 58193880Syongari#define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 59193880Syongari#define PEX_UNC_ERR_SEV_CA 0x00008000 60193880Syongari#define PEX_UNC_ERR_SEV_UC 0x00010000 61193880Syongari#define PEX_UNC_ERR_SEV_ROV 0x00020000 62193880Syongari#define PEX_UNC_ERR_SEV_MLFP 0x00040000 63193880Syongari#define PEX_UNC_ERR_SEV_ECRC 0x00080000 64193880Syongari#define PEX_UNC_ERR_SEV_UR 0x00100000 65193880Syongari 66193880Syongari#define ALC_TWSI_CFG 0x218 67193880Syongari#define TWSI_CFG_SW_LD_START 0x00000800 68193880Syongari#define TWSI_CFG_HW_LD_START 0x00001000 69193880Syongari#define TWSI_CFG_LD_EXIST 0x00400000 70193880Syongari 71193880Syongari#define ALC_PCIE_PHYMISC 0x1000 72193880Syongari#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 73193880Syongari 74211105Syongari#define ALC_PCIE_PHYMISC2 0x1004 75211105Syongari#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 76211105Syongari#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 77211105Syongari#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 78211105Syongari#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 79211105Syongari 80193880Syongari#define ALC_TWSI_DEBUG 0x1108 81193880Syongari#define TWSI_DEBUG_DEV_EXIST 0x20000000 82193880Syongari 83193880Syongari#define ALC_EEPROM_CFG 0x12C0 84193880Syongari#define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 85193880Syongari#define EEPROM_CFG_ADDR_MASK 0x03FF0000 86193880Syongari#define EEPROM_CFG_ACK 0x40000000 87193880Syongari#define EEPROM_CFG_RW 0x80000000 88193880Syongari#define EEPROM_CFG_DATA_HI_SHIFT 0 89193880Syongari#define EEPROM_CFG_ADDR_SHIFT 16 90193880Syongari 91193880Syongari#define ALC_EEPROM_DATA_LO 0x12C4 92193880Syongari 93193880Syongari#define ALC_OPT_CFG 0x12F0 94193880Syongari#define OPT_CFG_CLK_ENB 0x00000002 95193880Syongari 96193880Syongari#define ALC_PM_CFG 0x12F8 97193880Syongari#define PM_CFG_SERDES_ENB 0x00000001 98193880Syongari#define PM_CFG_RBER_ENB 0x00000002 99193880Syongari#define PM_CFG_CLK_REQ_ENB 0x00000004 100193880Syongari#define PM_CFG_ASPM_L1_ENB 0x00000008 101193880Syongari#define PM_CFG_SERDES_L1_ENB 0x00000010 102193880Syongari#define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 103193880Syongari#define PM_CFG_SERDES_PD_EX_L1 0x00000040 104193880Syongari#define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 105193880Syongari#define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 106193880Syongari#define PM_CFG_ASPM_L0S_ENB 0x00001000 107193880Syongari#define PM_CFG_CLK_SWH_L1 0x00002000 108193880Syongari#define PM_CFG_CLK_PWM_VER1_1 0x00004000 109193880Syongari#define PM_CFG_PCIE_RECV 0x00008000 110193880Syongari#define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 111193880Syongari#define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 112217649Syongari#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 113211105Syongari#define PM_CFG_EN_BUFS_RX_L0S 0x10000000 114211105Syongari#define PM_CFG_SA_DLY_ENB 0x20000000 115193880Syongari#define PM_CFG_MAC_ASPM_CHK 0x40000000 116193880Syongari#define PM_CFG_HOTRST 0x80000000 117193880Syongari#define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 118193880Syongari#define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 119193880Syongari#define PM_CFG_PM_REQ_TIMER_SHIFT 20 120193880Syongari#define PM_CFG_LCKDET_TIMER_SHIFT 24 121193880Syongari 122211105Syongari#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 123217649Syongari#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 124217649Syongari#define PM_CFG_LCKDET_TIMER_DEFAULT 12 125217649Syongari#define PM_CFG_PM_REQ_TIMER_DEFAULT 12 126211105Syongari 127211105Syongari#define ALC_LTSSM_ID_CFG 0x12FC 128211105Syongari#define LTSSM_ID_WRO_ENB 0x00001000 129211105Syongari 130193880Syongari#define ALC_MASTER_CFG 0x1400 131193880Syongari#define MASTER_RESET 0x00000001 132210904Syongari#define MASTER_TEST_MODE_MASK 0x0000000C 133193880Syongari#define MASTER_BERT_START 0x00000010 134211105Syongari#define MASTER_OOB_DIS_OFF 0x00000040 135211105Syongari#define MASTER_SA_TIMER_ENB 0x00000080 136193880Syongari#define MASTER_MTIMER_ENB 0x00000100 137193880Syongari#define MASTER_MANUAL_INTR_ENB 0x00000200 138193880Syongari#define MASTER_IM_TX_TIMER_ENB 0x00000400 139193880Syongari#define MASTER_IM_RX_TIMER_ENB 0x00000800 140193880Syongari#define MASTER_CLK_SEL_DIS 0x00001000 141193880Syongari#define MASTER_CLK_SWH_MODE 0x00002000 142193880Syongari#define MASTER_INTR_RD_CLR 0x00004000 143193880Syongari#define MASTER_CHIP_REV_MASK 0x00FF0000 144193880Syongari#define MASTER_CHIP_ID_MASK 0x7F000000 145193880Syongari#define MASTER_OTP_SEL 0x80000000 146193880Syongari#define MASTER_TEST_MODE_SHIFT 2 147193880Syongari#define MASTER_CHIP_REV_SHIFT 16 148193880Syongari#define MASTER_CHIP_ID_SHIFT 24 149193880Syongari 150211105Syongari/* Number of ticks per usec for AR813x/AR815x. */ 151193880Syongari#define ALC_TICK_USECS 2 152193880Syongari#define ALC_USECS(x) ((x) / ALC_TICK_USECS) 153193880Syongari 154193880Syongari#define ALC_MANUAL_TIMER 0x1404 155193880Syongari 156193880Syongari#define ALC_IM_TIMER 0x1408 157193880Syongari#define IM_TIMER_TX_MASK 0x0000FFFF 158193880Syongari#define IM_TIMER_RX_MASK 0xFFFF0000 159193880Syongari#define IM_TIMER_TX_SHIFT 0 160193880Syongari#define IM_TIMER_RX_SHIFT 16 161193880Syongari#define ALC_IM_TIMER_MIN 0 162193880Syongari#define ALC_IM_TIMER_MAX 130000 /* 130ms */ 163193880Syongari/* 164193880Syongari * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 165193880Syongari * interrupts in a second. 166193880Syongari */ 167193880Syongari#define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 168193880Syongari/* 169193880Syongari * alc(4) does not rely on Tx completion interrupts, so set it 170193880Syongari * somewhat large value to reduce Tx completion interrupts. 171193880Syongari */ 172210904Syongari#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 173193880Syongari 174193880Syongari#define ALC_GPHY_CFG 0x140C /* 16bits */ 175193880Syongari#define GPHY_CFG_EXT_RESET 0x0001 176193880Syongari#define GPHY_CFG_RTL_MODE 0x0002 177193880Syongari#define GPHY_CFG_LED_MODE 0x0004 178193880Syongari#define GPHY_CFG_ANEG_NOW 0x0008 179193880Syongari#define GPHY_CFG_RECV_ANEG 0x0010 180193880Syongari#define GPHY_CFG_GATE_25M_ENB 0x0020 181193880Syongari#define GPHY_CFG_LPW_EXIT 0x0040 182193880Syongari#define GPHY_CFG_PHY_IDDQ 0x0080 183193880Syongari#define GPHY_CFG_PHY_IDDQ_DIS 0x0100 184193880Syongari#define GPHY_CFG_PCLK_SEL_DIS 0x0200 185193880Syongari#define GPHY_CFG_HIB_EN 0x0400 186193880Syongari#define GPHY_CFG_HIB_PULSE 0x0800 187193880Syongari#define GPHY_CFG_SEL_ANA_RESET 0x1000 188193880Syongari#define GPHY_CFG_PHY_PLL_ON 0x2000 189193880Syongari#define GPHY_CFG_PWDOWN_HW 0x4000 190193880Syongari#define GPHY_CFG_PHY_PLL_BYPASS 0x8000 191193880Syongari 192193880Syongari#define ALC_IDLE_STATUS 0x1410 193193880Syongari#define IDLE_STATUS_RXMAC 0x00000001 194193880Syongari#define IDLE_STATUS_TXMAC 0x00000002 195193880Syongari#define IDLE_STATUS_RXQ 0x00000004 196193880Syongari#define IDLE_STATUS_TXQ 0x00000008 197193880Syongari#define IDLE_STATUS_DMARD 0x00000010 198193880Syongari#define IDLE_STATUS_DMAWR 0x00000020 199193880Syongari#define IDLE_STATUS_SMB 0x00000040 200193880Syongari#define IDLE_STATUS_CMB 0x00000080 201193880Syongari 202193880Syongari#define ALC_MDIO 0x1414 203193880Syongari#define MDIO_DATA_MASK 0x0000FFFF 204193880Syongari#define MDIO_REG_ADDR_MASK 0x001F0000 205193880Syongari#define MDIO_OP_READ 0x00200000 206193880Syongari#define MDIO_OP_WRITE 0x00000000 207193880Syongari#define MDIO_SUP_PREAMBLE 0x00400000 208193880Syongari#define MDIO_OP_EXECUTE 0x00800000 209193880Syongari#define MDIO_CLK_25_4 0x00000000 210193880Syongari#define MDIO_CLK_25_6 0x02000000 211193880Syongari#define MDIO_CLK_25_8 0x03000000 212193880Syongari#define MDIO_CLK_25_10 0x04000000 213193880Syongari#define MDIO_CLK_25_14 0x05000000 214193880Syongari#define MDIO_CLK_25_20 0x06000000 215193880Syongari#define MDIO_CLK_25_28 0x07000000 216193880Syongari#define MDIO_OP_BUSY 0x08000000 217193880Syongari#define MDIO_AP_ENB 0x10000000 218193880Syongari#define MDIO_DATA_SHIFT 0 219193880Syongari#define MDIO_REG_ADDR_SHIFT 16 220193880Syongari 221193880Syongari#define MDIO_REG_ADDR(x) \ 222193880Syongari (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 223193880Syongari/* Default PHY address. */ 224193880Syongari#define ALC_PHY_ADDR 0 225193880Syongari 226193880Syongari#define ALC_PHY_STATUS 0x1418 227193880Syongari#define PHY_STATUS_RECV_ENB 0x00000001 228193880Syongari#define PHY_STATUS_GENERAL_MASK 0x0000FFFF 229193880Syongari#define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 230193880Syongari#define PHY_STATUS_LPW_STATE 0x80000000 231193880Syongari#define PHY_STATIS_OE_PWSP_SHIFT 16 232193880Syongari 233193880Syongari/* Packet memory BIST. */ 234193880Syongari#define ALC_BIST0 0x141C 235193880Syongari#define BIST0_ENB 0x00000001 236193880Syongari#define BIST0_SRAM_FAIL 0x00000002 237193880Syongari#define BIST0_FUSE_FLAG 0x00000004 238193880Syongari 239193880Syongari/* PCIe retry buffer BIST. */ 240193880Syongari#define ALC_BIST1 0x1420 241193880Syongari#define BIST1_ENB 0x00000001 242193880Syongari#define BIST1_SRAM_FAIL 0x00000002 243193880Syongari#define BIST1_FUSE_FLAG 0x00000004 244193880Syongari 245193880Syongari#define ALC_SERDES_LOCK 0x1424 246193880Syongari#define SERDES_LOCK_DET 0x00000001 247193880Syongari#define SERDES_LOCK_DET_ENB 0x00000002 248211105Syongari#define SERDES_MAC_CLK_SLOWDOWN 0x00020000 249211105Syongari#define SERDES_PHY_CLK_SLOWDOWN 0x00040000 250193880Syongari 251193880Syongari#define ALC_MAC_CFG 0x1480 252193880Syongari#define MAC_CFG_TX_ENB 0x00000001 253193880Syongari#define MAC_CFG_RX_ENB 0x00000002 254193880Syongari#define MAC_CFG_TX_FC 0x00000004 255193880Syongari#define MAC_CFG_RX_FC 0x00000008 256193880Syongari#define MAC_CFG_LOOP 0x00000010 257193880Syongari#define MAC_CFG_FULL_DUPLEX 0x00000020 258193880Syongari#define MAC_CFG_TX_CRC_ENB 0x00000040 259193880Syongari#define MAC_CFG_TX_AUTO_PAD 0x00000080 260193880Syongari#define MAC_CFG_TX_LENCHK 0x00000100 261193880Syongari#define MAC_CFG_RX_JUMBO_ENB 0x00000200 262193880Syongari#define MAC_CFG_PREAMBLE_MASK 0x00003C00 263193880Syongari#define MAC_CFG_VLAN_TAG_STRIP 0x00004000 264193880Syongari#define MAC_CFG_PROMISC 0x00008000 265193880Syongari#define MAC_CFG_TX_PAUSE 0x00010000 266193880Syongari#define MAC_CFG_SCNT 0x00020000 267193880Syongari#define MAC_CFG_SYNC_RST_TX 0x00040000 268193880Syongari#define MAC_CFG_SIM_RST_TX 0x00080000 269193880Syongari#define MAC_CFG_SPEED_MASK 0x00300000 270193880Syongari#define MAC_CFG_SPEED_10_100 0x00100000 271193880Syongari#define MAC_CFG_SPEED_1000 0x00200000 272193880Syongari#define MAC_CFG_DBG_TX_BACKOFF 0x00400000 273193880Syongari#define MAC_CFG_TX_JUMBO_ENB 0x00800000 274193880Syongari#define MAC_CFG_RXCSUM_ENB 0x01000000 275193880Syongari#define MAC_CFG_ALLMULTI 0x02000000 276193880Syongari#define MAC_CFG_BCAST 0x04000000 277193880Syongari#define MAC_CFG_DBG 0x08000000 278193880Syongari#define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 279211105Syongari#define MAC_CFG_HASH_ALG_CRC32 0x20000000 280211105Syongari#define MAC_CFG_SPEED_MODE_SW 0x40000000 281193880Syongari#define MAC_CFG_PREAMBLE_SHIFT 10 282193880Syongari#define MAC_CFG_PREAMBLE_DEFAULT 7 283193880Syongari 284193880Syongari#define ALC_IPG_IFG_CFG 0x1484 285193880Syongari#define IPG_IFG_IPGT_MASK 0x0000007F 286193880Syongari#define IPG_IFG_MIFG_MASK 0x0000FF00 287193880Syongari#define IPG_IFG_IPG1_MASK 0x007F0000 288193880Syongari#define IPG_IFG_IPG2_MASK 0x7F000000 289193880Syongari#define IPG_IFG_IPGT_SHIFT 0 290193880Syongari#define IPG_IFG_IPGT_DEFAULT 0x60 291193880Syongari#define IPG_IFG_MIFG_SHIFT 8 292193880Syongari#define IPG_IFG_MIFG_DEFAULT 0x50 293193880Syongari#define IPG_IFG_IPG1_SHIFT 16 294193880Syongari#define IPG_IFG_IPG1_DEFAULT 0x40 295193880Syongari#define IPG_IFG_IPG2_SHIFT 24 296193880Syongari#define IPG_IFG_IPG2_DEFAULT 0x60 297193880Syongari 298193880Syongari/* Station address. */ 299193880Syongari#define ALC_PAR0 0x1488 300193880Syongari#define ALC_PAR1 0x148C 301193880Syongari 302193880Syongari/* 64bit multicast hash register. */ 303193880Syongari#define ALC_MAR0 0x1490 304193880Syongari#define ALC_MAR1 0x1494 305193880Syongari 306193880Syongari/* half-duplex parameter configuration. */ 307193880Syongari#define ALC_HDPX_CFG 0x1498 308193880Syongari#define HDPX_CFG_LCOL_MASK 0x000003FF 309193880Syongari#define HDPX_CFG_RETRY_MASK 0x0000F000 310193880Syongari#define HDPX_CFG_EXC_DEF_EN 0x00010000 311193880Syongari#define HDPX_CFG_NO_BACK_C 0x00020000 312193880Syongari#define HDPX_CFG_NO_BACK_P 0x00040000 313193880Syongari#define HDPX_CFG_ABEBE 0x00080000 314193880Syongari#define HDPX_CFG_ABEBT_MASK 0x00F00000 315193880Syongari#define HDPX_CFG_JAMIPG_MASK 0x0F000000 316193880Syongari#define HDPX_CFG_LCOL_SHIFT 0 317193880Syongari#define HDPX_CFG_LCOL_DEFAULT 0x37 318193880Syongari#define HDPX_CFG_RETRY_SHIFT 12 319193880Syongari#define HDPX_CFG_RETRY_DEFAULT 0x0F 320193880Syongari#define HDPX_CFG_ABEBT_SHIFT 20 321193880Syongari#define HDPX_CFG_ABEBT_DEFAULT 0x0A 322193880Syongari#define HDPX_CFG_JAMIPG_SHIFT 24 323193880Syongari#define HDPX_CFG_JAMIPG_DEFAULT 0x07 324193880Syongari 325193880Syongari#define ALC_FRAME_SIZE 0x149C 326193880Syongari 327193880Syongari#define ALC_WOL_CFG 0x14A0 328193880Syongari#define WOL_CFG_PATTERN 0x00000001 329193880Syongari#define WOL_CFG_PATTERN_ENB 0x00000002 330193880Syongari#define WOL_CFG_MAGIC 0x00000004 331193880Syongari#define WOL_CFG_MAGIC_ENB 0x00000008 332193880Syongari#define WOL_CFG_LINK_CHG 0x00000010 333193880Syongari#define WOL_CFG_LINK_CHG_ENB 0x00000020 334193880Syongari#define WOL_CFG_PATTERN_DET 0x00000100 335193880Syongari#define WOL_CFG_MAGIC_DET 0x00000200 336193880Syongari#define WOL_CFG_LINK_CHG_DET 0x00000400 337193880Syongari#define WOL_CFG_CLK_SWITCH_ENB 0x00008000 338193880Syongari#define WOL_CFG_PATTERN0 0x00010000 339193880Syongari#define WOL_CFG_PATTERN1 0x00020000 340193880Syongari#define WOL_CFG_PATTERN2 0x00040000 341193880Syongari#define WOL_CFG_PATTERN3 0x00080000 342193880Syongari#define WOL_CFG_PATTERN4 0x00100000 343193880Syongari#define WOL_CFG_PATTERN5 0x00200000 344193880Syongari#define WOL_CFG_PATTERN6 0x00400000 345193880Syongari 346193880Syongari/* WOL pattern length. */ 347193880Syongari#define ALC_PATTERN_CFG0 0x14A4 348193880Syongari#define PATTERN_CFG_0_LEN_MASK 0x0000007F 349193880Syongari#define PATTERN_CFG_1_LEN_MASK 0x00007F00 350193880Syongari#define PATTERN_CFG_2_LEN_MASK 0x007F0000 351193880Syongari#define PATTERN_CFG_3_LEN_MASK 0x7F000000 352193880Syongari 353193880Syongari#define ALC_PATTERN_CFG1 0x14A8 354193880Syongari#define PATTERN_CFG_4_LEN_MASK 0x0000007F 355193880Syongari#define PATTERN_CFG_5_LEN_MASK 0x00007F00 356193880Syongari#define PATTERN_CFG_6_LEN_MASK 0x007F0000 357193880Syongari 358193880Syongari/* RSS */ 359193880Syongari#define ALC_RSS_KEY0 0x14B0 360193880Syongari 361193880Syongari#define ALC_RSS_KEY1 0x14B4 362193880Syongari 363193880Syongari#define ALC_RSS_KEY2 0x14B8 364193880Syongari 365193880Syongari#define ALC_RSS_KEY3 0x14BC 366193880Syongari 367193880Syongari#define ALC_RSS_KEY4 0x14C0 368193880Syongari 369193880Syongari#define ALC_RSS_KEY5 0x14C4 370193880Syongari 371193880Syongari#define ALC_RSS_KEY6 0x14C8 372193880Syongari 373193880Syongari#define ALC_RSS_KEY7 0x14CC 374193880Syongari 375193880Syongari#define ALC_RSS_KEY8 0x14D0 376193880Syongari 377193880Syongari#define ALC_RSS_KEY9 0x14D4 378193880Syongari 379193880Syongari#define ALC_RSS_IDT_TABLE0 0x14E0 380193880Syongari 381193880Syongari#define ALC_RSS_IDT_TABLE1 0x14E4 382193880Syongari 383193880Syongari#define ALC_RSS_IDT_TABLE2 0x14E8 384193880Syongari 385193880Syongari#define ALC_RSS_IDT_TABLE3 0x14EC 386193880Syongari 387193880Syongari#define ALC_RSS_IDT_TABLE4 0x14F0 388193880Syongari 389193880Syongari#define ALC_RSS_IDT_TABLE5 0x14F4 390193880Syongari 391193880Syongari#define ALC_RSS_IDT_TABLE6 0x14F8 392193880Syongari 393193880Syongari#define ALC_RSS_IDT_TABLE7 0x14FC 394193880Syongari 395193880Syongari#define ALC_SRAM_RD0_ADDR 0x1500 396193880Syongari 397193880Syongari#define ALC_SRAM_RD1_ADDR 0x1504 398193880Syongari 399193880Syongari#define ALC_SRAM_RD2_ADDR 0x1508 400193880Syongari 401193880Syongari#define ALC_SRAM_RD3_ADDR 0x150C 402193880Syongari 403193880Syongari#define RD_HEAD_ADDR_MASK 0x000003FF 404193880Syongari#define RD_TAIL_ADDR_MASK 0x03FF0000 405193880Syongari#define RD_HEAD_ADDR_SHIFT 0 406193880Syongari#define RD_TAIL_ADDR_SHIFT 16 407193880Syongari 408193880Syongari#define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 409193880Syongari#define RD_NIC_LEN_MASK 0x000003FF 410193880Syongari 411193880Syongari#define ALC_RD_NIC_LEN1 0x1514 412193880Syongari 413193880Syongari#define ALC_SRAM_TD_ADDR 0x1518 414193880Syongari#define TD_HEAD_ADDR_MASK 0x000003FF 415193880Syongari#define TD_TAIL_ADDR_MASK 0x03FF0000 416193880Syongari#define TD_HEAD_ADDR_SHIFT 0 417193880Syongari#define TD_TAIL_ADDR_SHIFT 16 418193880Syongari 419193880Syongari#define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 420193880Syongari#define SRAM_TD_LEN_MASK 0x000003FF 421193880Syongari 422193880Syongari#define ALC_SRAM_RX_FIFO_ADDR 0x1520 423193880Syongari 424193880Syongari#define ALC_SRAM_RX_FIFO_LEN 0x1524 425193880Syongari 426193880Syongari#define ALC_SRAM_TX_FIFO_ADDR 0x1528 427193880Syongari 428193880Syongari#define ALC_SRAM_TX_FIFO_LEN 0x152C 429193880Syongari 430193880Syongari#define ALC_SRAM_TCPH_ADDR 0x1530 431193880Syongari#define SRAM_TCPH_ADDR_MASK 0x00000FFF 432193880Syongari#define SRAM_PATH_ADDR_MASK 0x0FFF0000 433193880Syongari#define SRAM_TCPH_ADDR_SHIFT 0 434193880Syongari#define SRAM_PKTH_ADDR_SHIFT 16 435193880Syongari 436193880Syongari#define ALC_DMA_BLOCK 0x1534 437193880Syongari#define DMA_BLOCK_LOAD 0x00000001 438193880Syongari 439193880Syongari#define ALC_RX_BASE_ADDR_HI 0x1540 440193880Syongari 441193880Syongari#define ALC_TX_BASE_ADDR_HI 0x1544 442193880Syongari 443193880Syongari#define ALC_SMB_BASE_ADDR_HI 0x1548 444193880Syongari 445193880Syongari#define ALC_SMB_BASE_ADDR_LO 0x154C 446193880Syongari 447193880Syongari#define ALC_RD0_HEAD_ADDR_LO 0x1550 448193880Syongari 449193880Syongari#define ALC_RD1_HEAD_ADDR_LO 0x1554 450193880Syongari 451193880Syongari#define ALC_RD2_HEAD_ADDR_LO 0x1558 452193880Syongari 453193880Syongari#define ALC_RD3_HEAD_ADDR_LO 0x155C 454193880Syongari 455193880Syongari#define ALC_RD_RING_CNT 0x1560 456193880Syongari#define RD_RING_CNT_MASK 0x00000FFF 457193880Syongari#define RD_RING_CNT_SHIFT 0 458193880Syongari 459193880Syongari#define ALC_RX_BUF_SIZE 0x1564 460193880Syongari#define RX_BUF_SIZE_MASK 0x0000FFFF 461193880Syongari/* 462193880Syongari * If larger buffer size than 1536 is specified the controller 463193880Syongari * will be locked up. This is hardware limitation. 464193880Syongari */ 465193880Syongari#define RX_BUF_SIZE_MAX 1536 466193880Syongari 467193880Syongari#define ALC_RRD0_HEAD_ADDR_LO 0x1568 468193880Syongari 469193880Syongari#define ALC_RRD1_HEAD_ADDR_LO 0x156C 470193880Syongari 471193880Syongari#define ALC_RRD2_HEAD_ADDR_LO 0x1570 472193880Syongari 473193880Syongari#define ALC_RRD3_HEAD_ADDR_LO 0x1574 474193880Syongari 475193880Syongari#define ALC_RRD_RING_CNT 0x1578 476193880Syongari#define RRD_RING_CNT_MASK 0x00000FFF 477193880Syongari#define RRD_RING_CNT_SHIFT 0 478193880Syongari 479193880Syongari#define ALC_TDH_HEAD_ADDR_LO 0x157C 480193880Syongari 481193880Syongari#define ALC_TDL_HEAD_ADDR_LO 0x1580 482193880Syongari 483193880Syongari#define ALC_TD_RING_CNT 0x1584 484193880Syongari#define TD_RING_CNT_MASK 0x0000FFFF 485193880Syongari#define TD_RING_CNT_SHIFT 0 486193880Syongari 487193880Syongari#define ALC_CMB_BASE_ADDR_LO 0x1588 488193880Syongari 489193880Syongari#define ALC_TXQ_CFG 0x1590 490193880Syongari#define TXQ_CFG_TD_BURST_MASK 0x0000000F 491193880Syongari#define TXQ_CFG_IP_OPTION_ENB 0x00000010 492193880Syongari#define TXQ_CFG_ENB 0x00000020 493193880Syongari#define TXQ_CFG_ENHANCED_MODE 0x00000040 494193880Syongari#define TXQ_CFG_8023_ENB 0x00000080 495193880Syongari#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 496193880Syongari#define TXQ_CFG_TD_BURST_SHIFT 0 497193880Syongari#define TXQ_CFG_TD_BURST_DEFAULT 5 498193880Syongari#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 499193880Syongari 500193880Syongari#define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 501193880Syongari#define TSO_OFFLOAD_THRESH_MASK 0x000007FF 502193880Syongari#define TSO_OFFLOAD_THRESH_SHIFT 0 503193880Syongari#define TSO_OFFLOAD_THRESH_UNIT 8 504193880Syongari#define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 505193880Syongari 506193880Syongari#define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 507193880Syongari#define TXF_WATER_MARK_HI_MASK 0x00000FFF 508193880Syongari#define TXF_WATER_MARK_LO_MASK 0x0FFF0000 509193880Syongari#define TXF_WATER_MARK_BURST_ENB 0x80000000 510193880Syongari#define TXF_WATER_MARK_LO_SHIFT 0 511193880Syongari#define TXF_WATER_MARK_HI_SHIFT 16 512193880Syongari 513193880Syongari#define ALC_THROUGHPUT_MON 0x159C 514193880Syongari#define THROUGHPUT_MON_RATE_MASK 0x00000003 515193880Syongari#define THROUGHPUT_MON_ENB 0x00000080 516193880Syongari#define THROUGHPUT_MON_RATE_SHIFT 0 517193880Syongari 518193880Syongari#define ALC_RXQ_CFG 0x15A0 519193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 520193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 521193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 522193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 523193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 524193880Syongari#define RXQ_CFG_QUEUE1_ENB 0x00000010 525193880Syongari#define RXQ_CFG_QUEUE2_ENB 0x00000020 526193880Syongari#define RXQ_CFG_QUEUE3_ENB 0x00000040 527193880Syongari#define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 528193880Syongari#define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 529193880Syongari#define RXQ_CFG_RSS_HASH_IPV4 0x00010000 530193880Syongari#define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 531193880Syongari#define RXQ_CFG_RSS_HASH_IPV6 0x00040000 532193880Syongari#define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 533193880Syongari#define RXQ_CFG_RD_BURST_MASK 0x03F00000 534193880Syongari#define RXQ_CFG_RSS_MODE_DIS 0x00000000 535193880Syongari#define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 536193880Syongari#define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 537193880Syongari#define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 538193880Syongari#define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 539193880Syongari#define RXQ_CFG_RSS_HASH_ENB 0x20000000 540193880Syongari#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 541193880Syongari#define RXQ_CFG_QUEUE0_ENB 0x80000000 542193880Syongari#define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 543193880Syongari#define RXQ_CFG_RD_BURST_DEFAULT 8 544193880Syongari#define RXQ_CFG_RD_BURST_SHIFT 20 545193880Syongari#define RXQ_CFG_ENB \ 546193880Syongari (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 547193880Syongari RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 548193880Syongari 549193880Syongari#define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 550193880Syongari#define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 551193880Syongari#define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 552193880Syongari#define RX_RD_FREE_THRESH_HI_SHIFT 0 553193880Syongari#define RX_RD_FREE_THRESH_LO_SHIFT 6 554193880Syongari#define RX_RD_FREE_THRESH_HI_DEFAULT 16 555193880Syongari#define RX_RD_FREE_THRESH_LO_DEFAULT 8 556193880Syongari 557193880Syongari#define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 558193880Syongari#define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 559193880Syongari#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 560193880Syongari#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 561193880Syongari#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 562193880Syongari 563193880Syongari#define ALC_RD_DMA_CFG 0x15AC 564193880Syongari#define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 565193880Syongari#define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 566193880Syongari#define RD_DMA_CFG_THRESH_SHIFT 0 567193880Syongari#define RD_DMA_CFG_TIMER_SHIFT 16 568193880Syongari#define RD_DMA_CFG_THRESH_DEFAULT 0x100 569193880Syongari#define RD_DMA_CFG_TIMER_DEFAULT 0 570193880Syongari#define RD_DMA_CFG_TICK_USECS 8 571193880Syongari#define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 572193880Syongari 573193880Syongari#define ALC_RSS_HASH_VALUE 0x15B0 574193880Syongari 575193880Syongari#define ALC_RSS_HASH_FLAG 0x15B4 576193880Syongari 577193880Syongari#define ALC_RSS_CPU 0x15B8 578193880Syongari 579193880Syongari#define ALC_DMA_CFG 0x15C0 580193880Syongari#define DMA_CFG_IN_ORDER 0x00000001 581193880Syongari#define DMA_CFG_ENH_ORDER 0x00000002 582193880Syongari#define DMA_CFG_OUT_ORDER 0x00000004 583193880Syongari#define DMA_CFG_RCB_64 0x00000000 584193880Syongari#define DMA_CFG_RCB_128 0x00000008 585193880Syongari#define DMA_CFG_RD_BURST_128 0x00000000 586193880Syongari#define DMA_CFG_RD_BURST_256 0x00000010 587193880Syongari#define DMA_CFG_RD_BURST_512 0x00000020 588193880Syongari#define DMA_CFG_RD_BURST_1024 0x00000030 589193880Syongari#define DMA_CFG_RD_BURST_2048 0x00000040 590193880Syongari#define DMA_CFG_RD_BURST_4096 0x00000050 591193880Syongari#define DMA_CFG_WR_BURST_128 0x00000000 592193880Syongari#define DMA_CFG_WR_BURST_256 0x00000080 593193880Syongari#define DMA_CFG_WR_BURST_512 0x00000100 594193880Syongari#define DMA_CFG_WR_BURST_1024 0x00000180 595193880Syongari#define DMA_CFG_WR_BURST_2048 0x00000200 596193880Syongari#define DMA_CFG_WR_BURST_4096 0x00000280 597193880Syongari#define DMA_CFG_RD_REQ_PRI 0x00000400 598193880Syongari#define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 599193880Syongari#define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 600193880Syongari#define DMA_CFG_CMB_ENB 0x00100000 601193880Syongari#define DMA_CFG_SMB_ENB 0x00200000 602193880Syongari#define DMA_CFG_CMB_NOW 0x00400000 603193880Syongari#define DMA_CFG_SMB_DIS 0x01000000 604193880Syongari#define DMA_CFG_SMB_NOW 0x80000000 605193880Syongari#define DMA_CFG_RD_BURST_MASK 0x07 606193880Syongari#define DMA_CFG_RD_BURST_SHIFT 4 607193880Syongari#define DMA_CFG_WR_BURST_MASK 0x07 608193880Syongari#define DMA_CFG_WR_BURST_SHIFT 7 609193880Syongari#define DMA_CFG_RD_DELAY_CNT_SHIFT 11 610193880Syongari#define DMA_CFG_WR_DELAY_CNT_SHIFT 16 611193880Syongari#define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 612193880Syongari#define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 613193880Syongari 614193880Syongari#define ALC_SMB_STAT_TIMER 0x15C4 615193880Syongari#define SMB_STAT_TIMER_MASK 0x00FFFFFF 616193880Syongari#define SMB_STAT_TIMER_SHIFT 0 617193880Syongari 618193880Syongari#define ALC_CMB_TD_THRESH 0x15C8 619193880Syongari#define CMB_TD_THRESH_MASK 0x0000FFFF 620193880Syongari#define CMB_TD_THRESH_SHIFT 0 621193880Syongari 622193880Syongari#define ALC_CMB_TX_TIMER 0x15CC 623193880Syongari#define CMB_TX_TIMER_MASK 0x0000FFFF 624193880Syongari#define CMB_TX_TIMER_SHIFT 0 625193880Syongari 626193880Syongari#define ALC_MBOX_RD0_PROD_IDX 0x15E0 627193880Syongari 628193880Syongari#define ALC_MBOX_RD1_PROD_IDX 0x15E4 629193880Syongari 630193880Syongari#define ALC_MBOX_RD2_PROD_IDX 0x15E8 631193880Syongari 632193880Syongari#define ALC_MBOX_RD3_PROD_IDX 0x15EC 633193880Syongari 634193880Syongari#define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 635193880Syongari#define MBOX_RD_PROD_SHIFT 0 636193880Syongari 637193880Syongari#define ALC_MBOX_TD_PROD_IDX 0x15F0 638193880Syongari#define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 639193880Syongari#define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 640193880Syongari#define MBOX_TD_PROD_HI_IDX_SHIFT 0 641193880Syongari#define MBOX_TD_PROD_LO_IDX_SHIFT 16 642193880Syongari 643193880Syongari#define ALC_MBOX_TD_CONS_IDX 0x15F4 644193880Syongari#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 645193880Syongari#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 646193880Syongari#define MBOX_TD_CONS_HI_IDX_SHIFT 0 647193880Syongari#define MBOX_TD_CONS_LO_IDX_SHIFT 16 648193880Syongari 649193880Syongari#define ALC_MBOX_RD01_CONS_IDX 0x15F8 650193880Syongari#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 651193880Syongari#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 652193880Syongari#define MBOX_RD0_CONS_IDX_SHIFT 0 653193880Syongari#define MBOX_RD1_CONS_IDX_SHIFT 16 654193880Syongari 655193880Syongari#define ALC_MBOX_RD23_CONS_IDX 0x15FC 656193880Syongari#define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 657193880Syongari#define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 658193880Syongari#define MBOX_RD2_CONS_IDX_SHIFT 0 659193880Syongari#define MBOX_RD3_CONS_IDX_SHIFT 16 660193880Syongari 661193880Syongari#define ALC_INTR_STATUS 0x1600 662193880Syongari#define INTR_SMB 0x00000001 663193880Syongari#define INTR_TIMER 0x00000002 664193880Syongari#define INTR_MANUAL_TIMER 0x00000004 665193880Syongari#define INTR_RX_FIFO_OFLOW 0x00000008 666193880Syongari#define INTR_RD0_UNDERRUN 0x00000010 667193880Syongari#define INTR_RD1_UNDERRUN 0x00000020 668193880Syongari#define INTR_RD2_UNDERRUN 0x00000040 669193880Syongari#define INTR_RD3_UNDERRUN 0x00000080 670193880Syongari#define INTR_TX_FIFO_UNDERRUN 0x00000100 671193880Syongari#define INTR_DMA_RD_TO_RST 0x00000200 672193880Syongari#define INTR_DMA_WR_TO_RST 0x00000400 673193880Syongari#define INTR_TX_CREDIT 0x00000800 674193880Syongari#define INTR_GPHY 0x00001000 675193880Syongari#define INTR_GPHY_LOW_PW 0x00002000 676193880Syongari#define INTR_TXQ_TO_RST 0x00004000 677193880Syongari#define INTR_TX_PKT 0x00008000 678193880Syongari#define INTR_RX_PKT0 0x00010000 679193880Syongari#define INTR_RX_PKT1 0x00020000 680193880Syongari#define INTR_RX_PKT2 0x00040000 681193880Syongari#define INTR_RX_PKT3 0x00080000 682193880Syongari#define INTR_MAC_RX 0x00100000 683193880Syongari#define INTR_MAC_TX 0x00200000 684193880Syongari#define INTR_UNDERRUN 0x00400000 685193880Syongari#define INTR_FRAME_ERROR 0x00800000 686193880Syongari#define INTR_FRAME_OK 0x01000000 687193880Syongari#define INTR_CSUM_ERROR 0x02000000 688193880Syongari#define INTR_PHY_LINK_DOWN 0x04000000 689193880Syongari#define INTR_DIS_INT 0x80000000 690193880Syongari 691193880Syongari/* Interrupt Mask Register */ 692193880Syongari#define ALC_INTR_MASK 0x1604 693193880Syongari 694193880Syongari#ifdef notyet 695193880Syongari#define INTR_RX_PKT \ 696193880Syongari (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 697193880Syongari INTR_RX_PKT3) 698193880Syongari#define INTR_RD_UNDERRUN \ 699193880Syongari (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 700193880Syongari INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 701193880Syongari#else 702193880Syongari#define INTR_RX_PKT INTR_RX_PKT0 703193880Syongari#define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 704193880Syongari#endif 705193880Syongari 706193880Syongari#define ALC_INTRS \ 707193880Syongari (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 708193880Syongari INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 709193880Syongari INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 710193880Syongari INTR_TX_FIFO_UNDERRUN) 711193880Syongari 712193880Syongari#define ALC_INTR_RETRIG_TIMER 0x1608 713193880Syongari#define INTR_RETRIG_TIMER_MASK 0x0000FFFF 714193880Syongari#define INTR_RETRIG_TIMER_SHIFT 0 715193880Syongari 716193880Syongari#define ALC_HDS_CFG 0x160C 717193880Syongari#define HDS_CFG_ENB 0x00000001 718193880Syongari#define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 719193880Syongari#define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 720193880Syongari#define HDS_CFG_BACKFILLSIZE_SHIFT 8 721193880Syongari#define HDS_CFG_MAX_HDRSIZE_SHIFT 20 722193880Syongari 723211105Syongari/* AR813x/AR815x registers for MAC statistics */ 724193880Syongari#define ALC_RX_MIB_BASE 0x1700 725193880Syongari 726193880Syongari#define ALC_TX_MIB_BASE 0x1760 727193880Syongari 728217649Syongari#define ALC_CLK_GATING_CFG 0x1814 729217649Syongari#define CLK_GATING_DMAW_ENB 0x0001 730217649Syongari#define CLK_GATING_DMAR_ENB 0x0002 731217649Syongari#define CLK_GATING_TXQ_ENB 0x0004 732217649Syongari#define CLK_GATING_RXQ_ENB 0x0008 733217649Syongari#define CLK_GATING_TXMAC_ENB 0x0010 734217649Syongari#define CLK_GATING_RXMAC_ENB 0x0020 735217649Syongari 736193880Syongari#define ALC_DEBUG_DATA0 0x1900 737193880Syongari 738193880Syongari#define ALC_DEBUG_DATA1 0x1904 739193880Syongari 740193880Syongari#define ALC_MII_DBG_ADDR 0x1D 741193880Syongari#define ALC_MII_DBG_DATA 0x1E 742193880Syongari 743193880Syongari#define MII_ANA_CFG0 0x00 744193880Syongari#define ANA_RESTART_CAL 0x0001 745193880Syongari#define ANA_MANUL_SWICH_ON_MASK 0x001E 746193880Syongari#define ANA_MAN_ENABLE 0x0020 747193880Syongari#define ANA_SEL_HSP 0x0040 748193880Syongari#define ANA_EN_HB 0x0080 749193880Syongari#define ANA_EN_HBIAS 0x0100 750193880Syongari#define ANA_OEN_125M 0x0200 751193880Syongari#define ANA_EN_LCKDT 0x0400 752193880Syongari#define ANA_LCKDT_PHY 0x0800 753193880Syongari#define ANA_AFE_MODE 0x1000 754193880Syongari#define ANA_VCO_SLOW 0x2000 755193880Syongari#define ANA_VCO_FAST 0x4000 756193880Syongari#define ANA_SEL_CLK125M_DSP 0x8000 757193880Syongari#define ANA_MANUL_SWICH_ON_SHIFT 1 758193880Syongari 759193880Syongari#define MII_ANA_CFG4 0x04 760193880Syongari#define ANA_IECHO_ADJ_MASK 0x0F 761193880Syongari#define ANA_IECHO_ADJ_3_MASK 0x000F 762193880Syongari#define ANA_IECHO_ADJ_2_MASK 0x00F0 763193880Syongari#define ANA_IECHO_ADJ_1_MASK 0x0F00 764193880Syongari#define ANA_IECHO_ADJ_0_MASK 0xF000 765193880Syongari#define ANA_IECHO_ADJ_3_SHIFT 0 766193880Syongari#define ANA_IECHO_ADJ_2_SHIFT 4 767193880Syongari#define ANA_IECHO_ADJ_1_SHIFT 8 768193880Syongari#define ANA_IECHO_ADJ_0_SHIFT 12 769193880Syongari 770193880Syongari#define MII_ANA_CFG5 0x05 771193880Syongari#define ANA_SERDES_CDR_BW_MASK 0x0003 772193880Syongari#define ANA_MS_PAD_DBG 0x0004 773193880Syongari#define ANA_SPEEDUP_DBG 0x0008 774193880Syongari#define ANA_SERDES_TH_LOS_MASK 0x0030 775193880Syongari#define ANA_SERDES_EN_DEEM 0x0040 776193880Syongari#define ANA_SERDES_TXELECIDLE 0x0080 777193880Syongari#define ANA_SERDES_BEACON 0x0100 778193880Syongari#define ANA_SERDES_HALFTXDR 0x0200 779193880Syongari#define ANA_SERDES_SEL_HSP 0x0400 780193880Syongari#define ANA_SERDES_EN_PLL 0x0800 781193880Syongari#define ANA_SERDES_EN 0x1000 782193880Syongari#define ANA_SERDES_EN_LCKDT 0x2000 783193880Syongari#define ANA_SERDES_CDR_BW_SHIFT 0 784193880Syongari#define ANA_SERDES_TH_LOS_SHIFT 4 785193880Syongari 786193880Syongari#define MII_ANA_CFG11 0x0B 787193880Syongari#define ANA_PS_HIB_EN 0x8000 788193880Syongari 789193880Syongari#define MII_ANA_CFG18 0x12 790193880Syongari#define ANA_TEST_MODE_10BT_01MASK 0x0003 791193880Syongari#define ANA_LOOP_SEL_10BT 0x0004 792193880Syongari#define ANA_RGMII_MODE_SW 0x0008 793193880Syongari#define ANA_EN_LONGECABLE 0x0010 794193880Syongari#define ANA_TEST_MODE_10BT_2 0x0020 795193880Syongari#define ANA_EN_10BT_IDLE 0x0400 796193880Syongari#define ANA_EN_MASK_TB 0x0800 797193880Syongari#define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 798193880Syongari#define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 799193880Syongari#define ANA_TEST_MODE_10BT_01SHIFT 0 800193880Syongari#define ANA_TRIGGER_SEL_TIMER_SHIFT 12 801193880Syongari#define ANA_INTERVAL_SEL_TIMER_SHIFT 14 802193880Syongari 803193880Syongari#define MII_ANA_CFG41 0x29 804193880Syongari#define ANA_TOP_PS_EN 0x8000 805193880Syongari 806193880Syongari#define MII_ANA_CFG54 0x36 807193880Syongari#define ANA_LONG_CABLE_TH_100_MASK 0x003F 808193880Syongari#define ANA_DESERVED 0x0040 809193880Syongari#define ANA_EN_LIT_CH 0x0080 810193880Syongari#define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 811193880Syongari#define ANA_BP_BAD_LINK_ACCUM 0x4000 812193880Syongari#define ANA_BP_SMALL_BW 0x8000 813193880Syongari#define ANA_LONG_CABLE_TH_100_SHIFT 0 814193880Syongari#define ANA_SHORT_CABLE_TH_100_SHIFT 8 815193880Syongari 816193880Syongari/* Statistics counters collected by the MAC. */ 817193880Syongaristruct smb { 818193880Syongari /* Rx stats. */ 819193880Syongari uint32_t rx_frames; 820193880Syongari uint32_t rx_bcast_frames; 821193880Syongari uint32_t rx_mcast_frames; 822193880Syongari uint32_t rx_pause_frames; 823193880Syongari uint32_t rx_control_frames; 824193880Syongari uint32_t rx_crcerrs; 825193880Syongari uint32_t rx_lenerrs; 826193880Syongari uint32_t rx_bytes; 827193880Syongari uint32_t rx_runts; 828193880Syongari uint32_t rx_fragments; 829193880Syongari uint32_t rx_pkts_64; 830193880Syongari uint32_t rx_pkts_65_127; 831193880Syongari uint32_t rx_pkts_128_255; 832193880Syongari uint32_t rx_pkts_256_511; 833193880Syongari uint32_t rx_pkts_512_1023; 834193880Syongari uint32_t rx_pkts_1024_1518; 835193880Syongari uint32_t rx_pkts_1519_max; 836193880Syongari uint32_t rx_pkts_truncated; 837193880Syongari uint32_t rx_fifo_oflows; 838193880Syongari uint32_t rx_rrs_errs; 839193880Syongari uint32_t rx_alignerrs; 840193880Syongari uint32_t rx_bcast_bytes; 841193880Syongari uint32_t rx_mcast_bytes; 842193880Syongari uint32_t rx_pkts_filtered; 843193880Syongari /* Tx stats. */ 844193880Syongari uint32_t tx_frames; 845193880Syongari uint32_t tx_bcast_frames; 846193880Syongari uint32_t tx_mcast_frames; 847193880Syongari uint32_t tx_pause_frames; 848193880Syongari uint32_t tx_excess_defer; 849193880Syongari uint32_t tx_control_frames; 850193880Syongari uint32_t tx_deferred; 851193880Syongari uint32_t tx_bytes; 852193880Syongari uint32_t tx_pkts_64; 853193880Syongari uint32_t tx_pkts_65_127; 854193880Syongari uint32_t tx_pkts_128_255; 855193880Syongari uint32_t tx_pkts_256_511; 856193880Syongari uint32_t tx_pkts_512_1023; 857193880Syongari uint32_t tx_pkts_1024_1518; 858193880Syongari uint32_t tx_pkts_1519_max; 859193880Syongari uint32_t tx_single_colls; 860193880Syongari uint32_t tx_multi_colls; 861193880Syongari uint32_t tx_late_colls; 862193880Syongari uint32_t tx_excess_colls; 863193880Syongari uint32_t tx_abort; 864193880Syongari uint32_t tx_underrun; 865193880Syongari uint32_t tx_desc_underrun; 866193880Syongari uint32_t tx_lenerrs; 867193880Syongari uint32_t tx_pkts_truncated; 868193880Syongari uint32_t tx_bcast_bytes; 869193880Syongari uint32_t tx_mcast_bytes; 870193880Syongari uint32_t updated; 871193880Syongari}; 872193880Syongari 873193880Syongari/* CMB(Coalesing message block) */ 874193880Syongaristruct cmb { 875193880Syongari uint32_t cons; 876193880Syongari}; 877193880Syongari 878193880Syongari/* Rx free descriptor */ 879193880Syongaristruct rx_desc { 880193880Syongari uint64_t addr; 881193880Syongari}; 882193880Syongari 883193880Syongari/* Rx return descriptor */ 884193880Syongaristruct rx_rdesc { 885193880Syongari uint32_t rdinfo; 886193880Syongari#define RRD_CSUM_MASK 0x0000FFFF 887193880Syongari#define RRD_RD_CNT_MASK 0x000F0000 888193880Syongari#define RRD_RD_IDX_MASK 0xFFF00000 889193880Syongari#define RRD_CSUM_SHIFT 0 890193880Syongari#define RRD_RD_CNT_SHIFT 16 891193880Syongari#define RRD_RD_IDX_SHIFT 20 892193880Syongari#define RRD_CSUM(x) \ 893193880Syongari (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 894193880Syongari#define RRD_RD_CNT(x) \ 895193880Syongari (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 896193880Syongari#define RRD_RD_IDX(x) \ 897193880Syongari (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 898193880Syongari uint32_t rss; 899193880Syongari uint32_t vtag; 900193880Syongari#define RRD_VLAN_MASK 0x0000FFFF 901193880Syongari#define RRD_HEAD_LEN_MASK 0x00FF0000 902193880Syongari#define RRD_HDS_MASK 0x03000000 903193880Syongari#define RRD_HDS_NONE 0x00000000 904193880Syongari#define RRD_HDS_HEAD 0x01000000 905193880Syongari#define RRD_HDS_DATA 0x02000000 906193880Syongari#define RRD_CPU_MASK 0x0C000000 907193880Syongari#define RRD_HASH_FLAG_MASK 0xF0000000 908193880Syongari#define RRD_VLAN_SHIFT 0 909193880Syongari#define RRD_HEAD_LEN_SHIFT 16 910193880Syongari#define RRD_HDS_SHIFT 24 911193880Syongari#define RRD_CPU_SHIFT 26 912193880Syongari#define RRD_HASH_FLAG_SHIFT 28 913193880Syongari#define RRD_VLAN(x) \ 914193880Syongari (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 915193880Syongari#define RRD_HEAD_LEN(x) \ 916193880Syongari (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 917193880Syongari#define RRD_CPU(x) \ 918193880Syongari (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 919193880Syongari uint32_t status; 920193880Syongari#define RRD_LEN_MASK 0x00003FFF 921193880Syongari#define RRD_LEN_SHIFT 0 922193880Syongari#define RRD_TCP_UDPCSUM_NOK 0x00004000 923193880Syongari#define RRD_IPCSUM_NOK 0x00008000 924193880Syongari#define RRD_VLAN_TAG 0x00010000 925193880Syongari#define RRD_PROTO_MASK 0x000E0000 926193880Syongari#define RRD_PROTO_IPV4 0x00020000 927193880Syongari#define RRD_PROTO_IPV6 0x000C0000 928193880Syongari#define RRD_ERR_SUM 0x00100000 929193880Syongari#define RRD_ERR_CRC 0x00200000 930193880Syongari#define RRD_ERR_ALIGN 0x00400000 931193880Syongari#define RRD_ERR_TRUNC 0x00800000 932193880Syongari#define RRD_ERR_RUNT 0x01000000 933193880Syongari#define RRD_ERR_ICMP 0x02000000 934193880Syongari#define RRD_BCAST 0x04000000 935193880Syongari#define RRD_MCAST 0x08000000 936193880Syongari#define RRD_SNAP_LLC 0x10000000 937193880Syongari#define RRD_ETHER 0x00000000 938193880Syongari#define RRD_FIFO_FULL 0x20000000 939193880Syongari#define RRD_ERR_LENGTH 0x40000000 940193880Syongari#define RRD_VALID 0x80000000 941193880Syongari#define RRD_BYTES(x) \ 942193880Syongari (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 943193880Syongari#define RRD_IPV4(x) \ 944193880Syongari (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 945193880Syongari}; 946193880Syongari 947193880Syongari/* Tx descriptor */ 948193880Syongaristruct tx_desc { 949193880Syongari uint32_t len; 950193880Syongari#define TD_BUFLEN_MASK 0x00003FFF 951193880Syongari#define TD_VLAN_MASK 0xFFFF0000 952193880Syongari#define TD_BUFLEN_SHIFT 0 953193880Syongari#define TX_BYTES(x) \ 954193880Syongari (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 955193880Syongari#define TD_VLAN_SHIFT 16 956193880Syongari uint32_t flags; 957193880Syongari#define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 958193880Syongari#define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 959193880Syongari#define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 960193880Syongari#define TD_CUSTOM_CSUM 0x00000100 961193880Syongari#define TD_IPCSUM 0x00000200 962193880Syongari#define TD_TCPCSUM 0x00000400 963193880Syongari#define TD_UDPCSUM 0x00000800 964193880Syongari#define TD_TSO 0x00001000 965193880Syongari#define TD_TSO_DESCV1 0x00000000 966193880Syongari#define TD_TSO_DESCV2 0x00002000 967193880Syongari#define TD_CON_VLAN_TAG 0x00004000 968193880Syongari#define TD_INS_VLAN_TAG 0x00008000 969193880Syongari#define TD_IPV4_DESCV2 0x00010000 970193880Syongari#define TD_LLC_SNAP 0x00020000 971193880Syongari#define TD_ETHERNET 0x00000000 972193880Syongari#define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 973193880Syongari#define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 974193880Syongari#define TD_MSS_MASK 0x7FFC0000 975193880Syongari#define TD_EOP 0x80000000 976193880Syongari#define TD_L4HDR_OFFSET_SHIFT 0 977193880Syongari#define TD_TCPHDR_OFFSET_SHIFT 0 978193880Syongari#define TD_PLOAD_OFFSET_SHIFT 0 979193880Syongari#define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 980193880Syongari#define TD_MSS_SHIFT 18 981193880Syongari uint64_t addr; 982193880Syongari}; 983193880Syongari 984193880Syongari#endif /* _IF_ALCREG_H */ 985