1193880Syongari/*- 2193880Syongari * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3193880Syongari * All rights reserved. 4193880Syongari * 5193880Syongari * Redistribution and use in source and binary forms, with or without 6193880Syongari * modification, are permitted provided that the following conditions 7193880Syongari * are met: 8193880Syongari * 1. Redistributions of source code must retain the above copyright 9193880Syongari * notice unmodified, this list of conditions, and the following 10193880Syongari * disclaimer. 11193880Syongari * 2. Redistributions in binary form must reproduce the above copyright 12193880Syongari * notice, this list of conditions and the following disclaimer in the 13193880Syongari * documentation and/or other materials provided with the distribution. 14193880Syongari * 15193880Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16193880Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17193880Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18193880Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19193880Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20222107Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21193880Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22193880Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23193880Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24193880Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25222107Syongari * SUCH DAMAGE. 26193880Syongari * 27193880Syongari * $FreeBSD: stable/11/sys/dev/alc/if_alcreg.h 314005 2017-02-21 02:19:19Z sephe $ 28193880Syongari */ 29193880Syongari 30193880Syongari#ifndef _IF_ALCREG_H 31193880Syongari#define _IF_ALCREG_H 32193880Syongari 33193880Syongari/* 34193880Syongari * Atheros Communucations, Inc. PCI vendor ID 35193880Syongari */ 36193880Syongari#define VENDORID_ATHEROS 0x1969 37193880Syongari 38193880Syongari/* 39211105Syongari * Atheros AR813x/AR815x device ID 40193880Syongari */ 41193880Syongari#define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 42193880Syongari#define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 43211105Syongari#define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 44211105Syongari#define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 45211105Syongari#define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 46211105Syongari#define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 47272730Syongari#define DEVICEID_ATHEROS_AR8161 0x1091 48272730Syongari#define DEVICEID_ATHEROS_AR8162 0x1090 49272730Syongari#define DEVICEID_ATHEROS_AR8171 0x10A1 50272730Syongari#define DEVICEID_ATHEROS_AR8172 0x10A0 51312358Syongari#define DEVICEID_ATHEROS_E2200 0xE091 52312358Syongari#define DEVICEID_ATHEROS_E2400 0xE0A1 53314005Ssephe#define DEVICEID_ATHEROS_E2500 0xE0B1 54193880Syongari 55211105Syongari#define ATHEROS_AR8152_B_V10 0xC0 56211105Syongari#define ATHEROS_AR8152_B_V11 0xC1 57211105Syongari 58272730Syongari/* 59272730Syongari * Atheros AR816x/AR817x revisions 60272730Syongari */ 61272730Syongari#define AR816X_REV_A0 0 62272730Syongari#define AR816X_REV_A1 1 63272730Syongari#define AR816X_REV_B0 2 64272730Syongari#define AR816X_REV_C0 3 65272730Syongari 66272730Syongari#define AR816X_REV_SHIFT 3 67272730Syongari#define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT) 68272730Syongari 69193880Syongari/* 0x0000 - 0x02FF : PCIe configuration space */ 70193880Syongari 71193880Syongari#define ALC_PEX_UNC_ERR_SEV 0x10C 72193880Syongari#define PEX_UNC_ERR_SEV_TRN 0x00000001 73193880Syongari#define PEX_UNC_ERR_SEV_DLP 0x00000010 74193880Syongari#define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 75193880Syongari#define PEX_UNC_ERR_SEV_FCP 0x00002000 76193880Syongari#define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 77193880Syongari#define PEX_UNC_ERR_SEV_CA 0x00008000 78193880Syongari#define PEX_UNC_ERR_SEV_UC 0x00010000 79193880Syongari#define PEX_UNC_ERR_SEV_ROV 0x00020000 80193880Syongari#define PEX_UNC_ERR_SEV_MLFP 0x00040000 81193880Syongari#define PEX_UNC_ERR_SEV_ECRC 0x00080000 82193880Syongari#define PEX_UNC_ERR_SEV_UR 0x00100000 83193880Syongari 84272730Syongari#define ALC_EEPROM_LD 0x204 /* AR816x */ 85272730Syongari#define EEPROM_LD_START 0x00000001 86272730Syongari#define EEPROM_LD_IDLE 0x00000010 87272730Syongari#define EEPROM_LD_DONE 0x00000000 88272730Syongari#define EEPROM_LD_PROGRESS 0x00000020 89272730Syongari#define EEPROM_LD_EXIST 0x00000100 90272730Syongari#define EEPROM_LD_EEPROM_EXIST 0x00000200 91272730Syongari#define EEPROM_LD_FLASH_EXIST 0x00000400 92272730Syongari#define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 93272730Syongari#define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 94272730Syongari 95193880Syongari#define ALC_TWSI_CFG 0x218 96193880Syongari#define TWSI_CFG_SW_LD_START 0x00000800 97193880Syongari#define TWSI_CFG_HW_LD_START 0x00001000 98193880Syongari#define TWSI_CFG_LD_EXIST 0x00400000 99193880Syongari 100272730Syongari#define ALC_SLD 0x218 /* AR816x */ 101272730Syongari#define SLD_START 0x00000800 102272730Syongari#define SLD_PROGRESS 0x00001000 103272730Syongari#define SLD_IDLE 0x00002000 104272730Syongari#define SLD_SLVADDR_MASK 0x007F0000 105272730Syongari#define SLD_EXIST 0x00800000 106272730Syongari#define SLD_FREQ_MASK 0x03000000 107272730Syongari#define SLD_FREQ_100K 0x00000000 108272730Syongari#define SLD_FREQ_200K 0x01000000 109272730Syongari#define SLD_FREQ_300K 0x02000000 110272730Syongari#define SLD_FREQ_400K 0x03000000 111272730Syongari 112193880Syongari#define ALC_PCIE_PHYMISC 0x1000 113193880Syongari#define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 114193880Syongari 115211105Syongari#define ALC_PCIE_PHYMISC2 0x1004 116211105Syongari#define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 117211105Syongari#define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 118211105Syongari#define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 119211105Syongari#define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 120211105Syongari 121272730Syongari#define ALC_PDLL_TRNS1 0x1104 122272730Syongari#define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800 123272730Syongari 124193880Syongari#define ALC_TWSI_DEBUG 0x1108 125193880Syongari#define TWSI_DEBUG_DEV_EXIST 0x20000000 126193880Syongari 127193880Syongari#define ALC_EEPROM_CFG 0x12C0 128193880Syongari#define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 129193880Syongari#define EEPROM_CFG_ADDR_MASK 0x03FF0000 130193880Syongari#define EEPROM_CFG_ACK 0x40000000 131193880Syongari#define EEPROM_CFG_RW 0x80000000 132193880Syongari#define EEPROM_CFG_DATA_HI_SHIFT 0 133193880Syongari#define EEPROM_CFG_ADDR_SHIFT 16 134193880Syongari 135193880Syongari#define ALC_EEPROM_DATA_LO 0x12C4 136193880Syongari 137193880Syongari#define ALC_OPT_CFG 0x12F0 138193880Syongari#define OPT_CFG_CLK_ENB 0x00000002 139193880Syongari 140193880Syongari#define ALC_PM_CFG 0x12F8 141193880Syongari#define PM_CFG_SERDES_ENB 0x00000001 142193880Syongari#define PM_CFG_RBER_ENB 0x00000002 143193880Syongari#define PM_CFG_CLK_REQ_ENB 0x00000004 144193880Syongari#define PM_CFG_ASPM_L1_ENB 0x00000008 145193880Syongari#define PM_CFG_SERDES_L1_ENB 0x00000010 146193880Syongari#define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 147193880Syongari#define PM_CFG_SERDES_PD_EX_L1 0x00000040 148193880Syongari#define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 149193880Syongari#define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 150272730Syongari#define PM_CFG_RX_L1_AFTER_L0S 0x00000800 151193880Syongari#define PM_CFG_ASPM_L0S_ENB 0x00001000 152193880Syongari#define PM_CFG_CLK_SWH_L1 0x00002000 153193880Syongari#define PM_CFG_CLK_PWM_VER1_1 0x00004000 154193880Syongari#define PM_CFG_PCIE_RECV 0x00008000 155193880Syongari#define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 156272730Syongari#define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000 157272730Syongari#define PM_CFG_TX_L1_AFTER_L0S 0x00080000 158193880Syongari#define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 159217649Syongari#define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 160211105Syongari#define PM_CFG_EN_BUFS_RX_L0S 0x10000000 161211105Syongari#define PM_CFG_SA_DLY_ENB 0x20000000 162193880Syongari#define PM_CFG_MAC_ASPM_CHK 0x40000000 163193880Syongari#define PM_CFG_HOTRST 0x80000000 164193880Syongari#define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 165193880Syongari#define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 166193880Syongari#define PM_CFG_PM_REQ_TIMER_SHIFT 20 167193880Syongari#define PM_CFG_LCKDET_TIMER_SHIFT 24 168193880Syongari 169211105Syongari#define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 170217649Syongari#define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 171272730Syongari#define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4 172217649Syongari#define PM_CFG_LCKDET_TIMER_DEFAULT 12 173217649Syongari#define PM_CFG_PM_REQ_TIMER_DEFAULT 12 174272730Syongari#define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15 175211105Syongari 176211105Syongari#define ALC_LTSSM_ID_CFG 0x12FC 177211105Syongari#define LTSSM_ID_WRO_ENB 0x00001000 178211105Syongari 179193880Syongari#define ALC_MASTER_CFG 0x1400 180193880Syongari#define MASTER_RESET 0x00000001 181210904Syongari#define MASTER_TEST_MODE_MASK 0x0000000C 182193880Syongari#define MASTER_BERT_START 0x00000010 183272730Syongari#define MASTER_WAKEN_25M 0x00000020 184211105Syongari#define MASTER_OOB_DIS_OFF 0x00000040 185211105Syongari#define MASTER_SA_TIMER_ENB 0x00000080 186193880Syongari#define MASTER_MTIMER_ENB 0x00000100 187193880Syongari#define MASTER_MANUAL_INTR_ENB 0x00000200 188193880Syongari#define MASTER_IM_TX_TIMER_ENB 0x00000400 189193880Syongari#define MASTER_IM_RX_TIMER_ENB 0x00000800 190193880Syongari#define MASTER_CLK_SEL_DIS 0x00001000 191193880Syongari#define MASTER_CLK_SWH_MODE 0x00002000 192193880Syongari#define MASTER_INTR_RD_CLR 0x00004000 193193880Syongari#define MASTER_CHIP_REV_MASK 0x00FF0000 194193880Syongari#define MASTER_CHIP_ID_MASK 0x7F000000 195193880Syongari#define MASTER_OTP_SEL 0x80000000 196193880Syongari#define MASTER_TEST_MODE_SHIFT 2 197193880Syongari#define MASTER_CHIP_REV_SHIFT 16 198193880Syongari#define MASTER_CHIP_ID_SHIFT 24 199193880Syongari 200211105Syongari/* Number of ticks per usec for AR813x/AR815x. */ 201193880Syongari#define ALC_TICK_USECS 2 202193880Syongari#define ALC_USECS(x) ((x) / ALC_TICK_USECS) 203193880Syongari 204193880Syongari#define ALC_MANUAL_TIMER 0x1404 205193880Syongari 206193880Syongari#define ALC_IM_TIMER 0x1408 207193880Syongari#define IM_TIMER_TX_MASK 0x0000FFFF 208193880Syongari#define IM_TIMER_RX_MASK 0xFFFF0000 209193880Syongari#define IM_TIMER_TX_SHIFT 0 210193880Syongari#define IM_TIMER_RX_SHIFT 16 211193880Syongari#define ALC_IM_TIMER_MIN 0 212193880Syongari#define ALC_IM_TIMER_MAX 130000 /* 130ms */ 213193880Syongari/* 214193880Syongari * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 215193880Syongari * interrupts in a second. 216193880Syongari */ 217193880Syongari#define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 218193880Syongari/* 219193880Syongari * alc(4) does not rely on Tx completion interrupts, so set it 220193880Syongari * somewhat large value to reduce Tx completion interrupts. 221193880Syongari */ 222210904Syongari#define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 223193880Syongari 224272730Syongari#define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */ 225193880Syongari#define GPHY_CFG_EXT_RESET 0x0001 226193880Syongari#define GPHY_CFG_RTL_MODE 0x0002 227193880Syongari#define GPHY_CFG_LED_MODE 0x0004 228193880Syongari#define GPHY_CFG_ANEG_NOW 0x0008 229193880Syongari#define GPHY_CFG_RECV_ANEG 0x0010 230193880Syongari#define GPHY_CFG_GATE_25M_ENB 0x0020 231193880Syongari#define GPHY_CFG_LPW_EXIT 0x0040 232193880Syongari#define GPHY_CFG_PHY_IDDQ 0x0080 233193880Syongari#define GPHY_CFG_PHY_IDDQ_DIS 0x0100 234193880Syongari#define GPHY_CFG_PCLK_SEL_DIS 0x0200 235193880Syongari#define GPHY_CFG_HIB_EN 0x0400 236193880Syongari#define GPHY_CFG_HIB_PULSE 0x0800 237193880Syongari#define GPHY_CFG_SEL_ANA_RESET 0x1000 238193880Syongari#define GPHY_CFG_PHY_PLL_ON 0x2000 239193880Syongari#define GPHY_CFG_PWDOWN_HW 0x4000 240193880Syongari#define GPHY_CFG_PHY_PLL_BYPASS 0x8000 241272730Syongari#define GPHY_CFG_100AB_ENB 0x00020000 242193880Syongari 243193880Syongari#define ALC_IDLE_STATUS 0x1410 244193880Syongari#define IDLE_STATUS_RXMAC 0x00000001 245193880Syongari#define IDLE_STATUS_TXMAC 0x00000002 246193880Syongari#define IDLE_STATUS_RXQ 0x00000004 247193880Syongari#define IDLE_STATUS_TXQ 0x00000008 248193880Syongari#define IDLE_STATUS_DMARD 0x00000010 249193880Syongari#define IDLE_STATUS_DMAWR 0x00000020 250193880Syongari#define IDLE_STATUS_SMB 0x00000040 251193880Syongari#define IDLE_STATUS_CMB 0x00000080 252193880Syongari 253193880Syongari#define ALC_MDIO 0x1414 254193880Syongari#define MDIO_DATA_MASK 0x0000FFFF 255193880Syongari#define MDIO_REG_ADDR_MASK 0x001F0000 256193880Syongari#define MDIO_OP_READ 0x00200000 257193880Syongari#define MDIO_OP_WRITE 0x00000000 258193880Syongari#define MDIO_SUP_PREAMBLE 0x00400000 259193880Syongari#define MDIO_OP_EXECUTE 0x00800000 260193880Syongari#define MDIO_CLK_25_4 0x00000000 261193880Syongari#define MDIO_CLK_25_6 0x02000000 262193880Syongari#define MDIO_CLK_25_8 0x03000000 263193880Syongari#define MDIO_CLK_25_10 0x04000000 264193880Syongari#define MDIO_CLK_25_14 0x05000000 265193880Syongari#define MDIO_CLK_25_20 0x06000000 266272730Syongari#define MDIO_CLK_25_128 0x07000000 267193880Syongari#define MDIO_OP_BUSY 0x08000000 268193880Syongari#define MDIO_AP_ENB 0x10000000 269272730Syongari#define MDIO_MODE_EXT 0x40000000 270193880Syongari#define MDIO_DATA_SHIFT 0 271193880Syongari#define MDIO_REG_ADDR_SHIFT 16 272193880Syongari 273193880Syongari#define MDIO_REG_ADDR(x) \ 274193880Syongari (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 275193880Syongari/* Default PHY address. */ 276193880Syongari#define ALC_PHY_ADDR 0 277193880Syongari 278193880Syongari#define ALC_PHY_STATUS 0x1418 279193880Syongari#define PHY_STATUS_RECV_ENB 0x00000001 280193880Syongari#define PHY_STATUS_GENERAL_MASK 0x0000FFFF 281193880Syongari#define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 282193880Syongari#define PHY_STATUS_LPW_STATE 0x80000000 283193880Syongari#define PHY_STATIS_OE_PWSP_SHIFT 16 284193880Syongari 285193880Syongari/* Packet memory BIST. */ 286193880Syongari#define ALC_BIST0 0x141C 287193880Syongari#define BIST0_ENB 0x00000001 288193880Syongari#define BIST0_SRAM_FAIL 0x00000002 289193880Syongari#define BIST0_FUSE_FLAG 0x00000004 290193880Syongari 291193880Syongari/* PCIe retry buffer BIST. */ 292193880Syongari#define ALC_BIST1 0x1420 293193880Syongari#define BIST1_ENB 0x00000001 294193880Syongari#define BIST1_SRAM_FAIL 0x00000002 295193880Syongari#define BIST1_FUSE_FLAG 0x00000004 296193880Syongari 297193880Syongari#define ALC_SERDES_LOCK 0x1424 298193880Syongari#define SERDES_LOCK_DET 0x00000001 299193880Syongari#define SERDES_LOCK_DET_ENB 0x00000002 300211105Syongari#define SERDES_MAC_CLK_SLOWDOWN 0x00020000 301211105Syongari#define SERDES_PHY_CLK_SLOWDOWN 0x00040000 302193880Syongari 303272730Syongari#define ALC_LPI_CTL 0x1440 304272730Syongari#define LPI_CTL_ENB 0x00000001 305272730Syongari 306272730Syongari#define ALC_EXT_MDIO 0x1448 307272730Syongari#define EXT_MDIO_REG_MASK 0x0000FFFF 308272730Syongari#define EXT_MDIO_DEVADDR_MASK 0x001F0000 309272730Syongari#define EXT_MDIO_REG_SHIFT 0 310272730Syongari#define EXT_MDIO_DEVADDR_SHIFT 16 311272730Syongari 312272730Syongari#define EXT_MDIO_REG(x) \ 313272730Syongari (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK) 314272730Syongari#define EXT_MDIO_DEVADDR(x) \ 315272730Syongari (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK) 316272730Syongari 317272730Syongari#define ALC_IDLE_DECISN_TIMER 0x1474 318272730Syongari#define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400 319272730Syongari 320193880Syongari#define ALC_MAC_CFG 0x1480 321193880Syongari#define MAC_CFG_TX_ENB 0x00000001 322193880Syongari#define MAC_CFG_RX_ENB 0x00000002 323193880Syongari#define MAC_CFG_TX_FC 0x00000004 324193880Syongari#define MAC_CFG_RX_FC 0x00000008 325193880Syongari#define MAC_CFG_LOOP 0x00000010 326193880Syongari#define MAC_CFG_FULL_DUPLEX 0x00000020 327193880Syongari#define MAC_CFG_TX_CRC_ENB 0x00000040 328193880Syongari#define MAC_CFG_TX_AUTO_PAD 0x00000080 329193880Syongari#define MAC_CFG_TX_LENCHK 0x00000100 330193880Syongari#define MAC_CFG_RX_JUMBO_ENB 0x00000200 331193880Syongari#define MAC_CFG_PREAMBLE_MASK 0x00003C00 332193880Syongari#define MAC_CFG_VLAN_TAG_STRIP 0x00004000 333193880Syongari#define MAC_CFG_PROMISC 0x00008000 334193880Syongari#define MAC_CFG_TX_PAUSE 0x00010000 335193880Syongari#define MAC_CFG_SCNT 0x00020000 336193880Syongari#define MAC_CFG_SYNC_RST_TX 0x00040000 337193880Syongari#define MAC_CFG_SIM_RST_TX 0x00080000 338193880Syongari#define MAC_CFG_SPEED_MASK 0x00300000 339193880Syongari#define MAC_CFG_SPEED_10_100 0x00100000 340193880Syongari#define MAC_CFG_SPEED_1000 0x00200000 341193880Syongari#define MAC_CFG_DBG_TX_BACKOFF 0x00400000 342193880Syongari#define MAC_CFG_TX_JUMBO_ENB 0x00800000 343193880Syongari#define MAC_CFG_RXCSUM_ENB 0x01000000 344193880Syongari#define MAC_CFG_ALLMULTI 0x02000000 345193880Syongari#define MAC_CFG_BCAST 0x04000000 346193880Syongari#define MAC_CFG_DBG 0x08000000 347193880Syongari#define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 348211105Syongari#define MAC_CFG_HASH_ALG_CRC32 0x20000000 349211105Syongari#define MAC_CFG_SPEED_MODE_SW 0x40000000 350272730Syongari#define MAC_CFG_FAST_PAUSE 0x80000000 351193880Syongari#define MAC_CFG_PREAMBLE_SHIFT 10 352193880Syongari#define MAC_CFG_PREAMBLE_DEFAULT 7 353193880Syongari 354193880Syongari#define ALC_IPG_IFG_CFG 0x1484 355193880Syongari#define IPG_IFG_IPGT_MASK 0x0000007F 356193880Syongari#define IPG_IFG_MIFG_MASK 0x0000FF00 357193880Syongari#define IPG_IFG_IPG1_MASK 0x007F0000 358193880Syongari#define IPG_IFG_IPG2_MASK 0x7F000000 359193880Syongari#define IPG_IFG_IPGT_SHIFT 0 360193880Syongari#define IPG_IFG_IPGT_DEFAULT 0x60 361193880Syongari#define IPG_IFG_MIFG_SHIFT 8 362193880Syongari#define IPG_IFG_MIFG_DEFAULT 0x50 363193880Syongari#define IPG_IFG_IPG1_SHIFT 16 364193880Syongari#define IPG_IFG_IPG1_DEFAULT 0x40 365193880Syongari#define IPG_IFG_IPG2_SHIFT 24 366193880Syongari#define IPG_IFG_IPG2_DEFAULT 0x60 367193880Syongari 368193880Syongari/* Station address. */ 369193880Syongari#define ALC_PAR0 0x1488 370193880Syongari#define ALC_PAR1 0x148C 371193880Syongari 372193880Syongari/* 64bit multicast hash register. */ 373193880Syongari#define ALC_MAR0 0x1490 374193880Syongari#define ALC_MAR1 0x1494 375193880Syongari 376193880Syongari/* half-duplex parameter configuration. */ 377193880Syongari#define ALC_HDPX_CFG 0x1498 378193880Syongari#define HDPX_CFG_LCOL_MASK 0x000003FF 379193880Syongari#define HDPX_CFG_RETRY_MASK 0x0000F000 380193880Syongari#define HDPX_CFG_EXC_DEF_EN 0x00010000 381193880Syongari#define HDPX_CFG_NO_BACK_C 0x00020000 382193880Syongari#define HDPX_CFG_NO_BACK_P 0x00040000 383193880Syongari#define HDPX_CFG_ABEBE 0x00080000 384193880Syongari#define HDPX_CFG_ABEBT_MASK 0x00F00000 385193880Syongari#define HDPX_CFG_JAMIPG_MASK 0x0F000000 386193880Syongari#define HDPX_CFG_LCOL_SHIFT 0 387193880Syongari#define HDPX_CFG_LCOL_DEFAULT 0x37 388193880Syongari#define HDPX_CFG_RETRY_SHIFT 12 389193880Syongari#define HDPX_CFG_RETRY_DEFAULT 0x0F 390193880Syongari#define HDPX_CFG_ABEBT_SHIFT 20 391193880Syongari#define HDPX_CFG_ABEBT_DEFAULT 0x0A 392193880Syongari#define HDPX_CFG_JAMIPG_SHIFT 24 393193880Syongari#define HDPX_CFG_JAMIPG_DEFAULT 0x07 394193880Syongari 395193880Syongari#define ALC_FRAME_SIZE 0x149C 396193880Syongari 397193880Syongari#define ALC_WOL_CFG 0x14A0 398193880Syongari#define WOL_CFG_PATTERN 0x00000001 399193880Syongari#define WOL_CFG_PATTERN_ENB 0x00000002 400193880Syongari#define WOL_CFG_MAGIC 0x00000004 401193880Syongari#define WOL_CFG_MAGIC_ENB 0x00000008 402193880Syongari#define WOL_CFG_LINK_CHG 0x00000010 403193880Syongari#define WOL_CFG_LINK_CHG_ENB 0x00000020 404193880Syongari#define WOL_CFG_PATTERN_DET 0x00000100 405193880Syongari#define WOL_CFG_MAGIC_DET 0x00000200 406193880Syongari#define WOL_CFG_LINK_CHG_DET 0x00000400 407193880Syongari#define WOL_CFG_CLK_SWITCH_ENB 0x00008000 408193880Syongari#define WOL_CFG_PATTERN0 0x00010000 409193880Syongari#define WOL_CFG_PATTERN1 0x00020000 410193880Syongari#define WOL_CFG_PATTERN2 0x00040000 411193880Syongari#define WOL_CFG_PATTERN3 0x00080000 412193880Syongari#define WOL_CFG_PATTERN4 0x00100000 413193880Syongari#define WOL_CFG_PATTERN5 0x00200000 414193880Syongari#define WOL_CFG_PATTERN6 0x00400000 415193880Syongari 416193880Syongari/* WOL pattern length. */ 417193880Syongari#define ALC_PATTERN_CFG0 0x14A4 418193880Syongari#define PATTERN_CFG_0_LEN_MASK 0x0000007F 419193880Syongari#define PATTERN_CFG_1_LEN_MASK 0x00007F00 420193880Syongari#define PATTERN_CFG_2_LEN_MASK 0x007F0000 421193880Syongari#define PATTERN_CFG_3_LEN_MASK 0x7F000000 422193880Syongari 423193880Syongari#define ALC_PATTERN_CFG1 0x14A8 424193880Syongari#define PATTERN_CFG_4_LEN_MASK 0x0000007F 425193880Syongari#define PATTERN_CFG_5_LEN_MASK 0x00007F00 426193880Syongari#define PATTERN_CFG_6_LEN_MASK 0x007F0000 427193880Syongari 428193880Syongari/* RSS */ 429193880Syongari#define ALC_RSS_KEY0 0x14B0 430193880Syongari 431193880Syongari#define ALC_RSS_KEY1 0x14B4 432193880Syongari 433193880Syongari#define ALC_RSS_KEY2 0x14B8 434193880Syongari 435193880Syongari#define ALC_RSS_KEY3 0x14BC 436193880Syongari 437193880Syongari#define ALC_RSS_KEY4 0x14C0 438193880Syongari 439193880Syongari#define ALC_RSS_KEY5 0x14C4 440193880Syongari 441193880Syongari#define ALC_RSS_KEY6 0x14C8 442193880Syongari 443193880Syongari#define ALC_RSS_KEY7 0x14CC 444193880Syongari 445193880Syongari#define ALC_RSS_KEY8 0x14D0 446193880Syongari 447193880Syongari#define ALC_RSS_KEY9 0x14D4 448193880Syongari 449193880Syongari#define ALC_RSS_IDT_TABLE0 0x14E0 450193880Syongari 451272730Syongari#define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */ 452272730Syongari 453193880Syongari#define ALC_RSS_IDT_TABLE1 0x14E4 454193880Syongari 455272730Syongari#define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */ 456272730Syongari 457193880Syongari#define ALC_RSS_IDT_TABLE2 0x14E8 458193880Syongari 459193880Syongari#define ALC_RSS_IDT_TABLE3 0x14EC 460193880Syongari 461193880Syongari#define ALC_RSS_IDT_TABLE4 0x14F0 462193880Syongari 463193880Syongari#define ALC_RSS_IDT_TABLE5 0x14F4 464193880Syongari 465193880Syongari#define ALC_RSS_IDT_TABLE6 0x14F8 466193880Syongari 467193880Syongari#define ALC_RSS_IDT_TABLE7 0x14FC 468193880Syongari 469193880Syongari#define ALC_SRAM_RD0_ADDR 0x1500 470193880Syongari 471193880Syongari#define ALC_SRAM_RD1_ADDR 0x1504 472193880Syongari 473193880Syongari#define ALC_SRAM_RD2_ADDR 0x1508 474193880Syongari 475193880Syongari#define ALC_SRAM_RD3_ADDR 0x150C 476193880Syongari 477193880Syongari#define RD_HEAD_ADDR_MASK 0x000003FF 478193880Syongari#define RD_TAIL_ADDR_MASK 0x03FF0000 479193880Syongari#define RD_HEAD_ADDR_SHIFT 0 480193880Syongari#define RD_TAIL_ADDR_SHIFT 16 481193880Syongari 482193880Syongari#define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 483193880Syongari#define RD_NIC_LEN_MASK 0x000003FF 484193880Syongari 485193880Syongari#define ALC_RD_NIC_LEN1 0x1514 486193880Syongari 487193880Syongari#define ALC_SRAM_TD_ADDR 0x1518 488193880Syongari#define TD_HEAD_ADDR_MASK 0x000003FF 489193880Syongari#define TD_TAIL_ADDR_MASK 0x03FF0000 490193880Syongari#define TD_HEAD_ADDR_SHIFT 0 491193880Syongari#define TD_TAIL_ADDR_SHIFT 16 492193880Syongari 493193880Syongari#define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 494193880Syongari#define SRAM_TD_LEN_MASK 0x000003FF 495193880Syongari 496193880Syongari#define ALC_SRAM_RX_FIFO_ADDR 0x1520 497193880Syongari 498193880Syongari#define ALC_SRAM_RX_FIFO_LEN 0x1524 499272730Syongari#define SRAM_RX_FIFO_LEN_MASK 0x00000FFF 500272730Syongari#define SRAM_RX_FIFO_LEN_SHIFT 0 501193880Syongari 502193880Syongari#define ALC_SRAM_TX_FIFO_ADDR 0x1528 503193880Syongari 504193880Syongari#define ALC_SRAM_TX_FIFO_LEN 0x152C 505193880Syongari 506193880Syongari#define ALC_SRAM_TCPH_ADDR 0x1530 507193880Syongari#define SRAM_TCPH_ADDR_MASK 0x00000FFF 508193880Syongari#define SRAM_PATH_ADDR_MASK 0x0FFF0000 509193880Syongari#define SRAM_TCPH_ADDR_SHIFT 0 510193880Syongari#define SRAM_PKTH_ADDR_SHIFT 16 511193880Syongari 512193880Syongari#define ALC_DMA_BLOCK 0x1534 513193880Syongari#define DMA_BLOCK_LOAD 0x00000001 514193880Syongari 515193880Syongari#define ALC_RX_BASE_ADDR_HI 0x1540 516193880Syongari 517193880Syongari#define ALC_TX_BASE_ADDR_HI 0x1544 518193880Syongari 519193880Syongari#define ALC_SMB_BASE_ADDR_HI 0x1548 520193880Syongari 521193880Syongari#define ALC_SMB_BASE_ADDR_LO 0x154C 522193880Syongari 523193880Syongari#define ALC_RD0_HEAD_ADDR_LO 0x1550 524193880Syongari 525193880Syongari#define ALC_RD1_HEAD_ADDR_LO 0x1554 526193880Syongari 527193880Syongari#define ALC_RD2_HEAD_ADDR_LO 0x1558 528193880Syongari 529193880Syongari#define ALC_RD3_HEAD_ADDR_LO 0x155C 530193880Syongari 531193880Syongari#define ALC_RD_RING_CNT 0x1560 532193880Syongari#define RD_RING_CNT_MASK 0x00000FFF 533193880Syongari#define RD_RING_CNT_SHIFT 0 534193880Syongari 535193880Syongari#define ALC_RX_BUF_SIZE 0x1564 536193880Syongari#define RX_BUF_SIZE_MASK 0x0000FFFF 537193880Syongari/* 538193880Syongari * If larger buffer size than 1536 is specified the controller 539193880Syongari * will be locked up. This is hardware limitation. 540193880Syongari */ 541193880Syongari#define RX_BUF_SIZE_MAX 1536 542193880Syongari 543193880Syongari#define ALC_RRD0_HEAD_ADDR_LO 0x1568 544193880Syongari 545193880Syongari#define ALC_RRD1_HEAD_ADDR_LO 0x156C 546193880Syongari 547193880Syongari#define ALC_RRD2_HEAD_ADDR_LO 0x1570 548193880Syongari 549193880Syongari#define ALC_RRD3_HEAD_ADDR_LO 0x1574 550193880Syongari 551193880Syongari#define ALC_RRD_RING_CNT 0x1578 552193880Syongari#define RRD_RING_CNT_MASK 0x00000FFF 553193880Syongari#define RRD_RING_CNT_SHIFT 0 554193880Syongari 555193880Syongari#define ALC_TDH_HEAD_ADDR_LO 0x157C 556193880Syongari 557272730Syongari#define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */ 558272730Syongari 559193880Syongari#define ALC_TDL_HEAD_ADDR_LO 0x1580 560193880Syongari 561272730Syongari#define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */ 562272730Syongari 563193880Syongari#define ALC_TD_RING_CNT 0x1584 564193880Syongari#define TD_RING_CNT_MASK 0x0000FFFF 565193880Syongari#define TD_RING_CNT_SHIFT 0 566193880Syongari 567193880Syongari#define ALC_CMB_BASE_ADDR_LO 0x1588 568193880Syongari 569193880Syongari#define ALC_TXQ_CFG 0x1590 570193880Syongari#define TXQ_CFG_TD_BURST_MASK 0x0000000F 571193880Syongari#define TXQ_CFG_IP_OPTION_ENB 0x00000010 572193880Syongari#define TXQ_CFG_ENB 0x00000020 573193880Syongari#define TXQ_CFG_ENHANCED_MODE 0x00000040 574193880Syongari#define TXQ_CFG_8023_ENB 0x00000080 575193880Syongari#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 576193880Syongari#define TXQ_CFG_TD_BURST_SHIFT 0 577193880Syongari#define TXQ_CFG_TD_BURST_DEFAULT 5 578193880Syongari#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 579193880Syongari 580193880Syongari#define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 581193880Syongari#define TSO_OFFLOAD_THRESH_MASK 0x000007FF 582272730Syongari#define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800 583193880Syongari#define TSO_OFFLOAD_THRESH_SHIFT 0 584193880Syongari#define TSO_OFFLOAD_THRESH_UNIT 8 585193880Syongari#define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 586193880Syongari 587193880Syongari#define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 588193880Syongari#define TXF_WATER_MARK_HI_MASK 0x00000FFF 589193880Syongari#define TXF_WATER_MARK_LO_MASK 0x0FFF0000 590193880Syongari#define TXF_WATER_MARK_BURST_ENB 0x80000000 591193880Syongari#define TXF_WATER_MARK_LO_SHIFT 0 592193880Syongari#define TXF_WATER_MARK_HI_SHIFT 16 593193880Syongari 594193880Syongari#define ALC_THROUGHPUT_MON 0x159C 595193880Syongari#define THROUGHPUT_MON_RATE_MASK 0x00000003 596193880Syongari#define THROUGHPUT_MON_ENB 0x00000080 597193880Syongari#define THROUGHPUT_MON_RATE_SHIFT 0 598193880Syongari 599193880Syongari#define ALC_RXQ_CFG 0x15A0 600193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 601193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 602193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 603193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 604193880Syongari#define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 605193880Syongari#define RXQ_CFG_QUEUE1_ENB 0x00000010 606193880Syongari#define RXQ_CFG_QUEUE2_ENB 0x00000020 607193880Syongari#define RXQ_CFG_QUEUE3_ENB 0x00000040 608193880Syongari#define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 609193880Syongari#define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 610193880Syongari#define RXQ_CFG_RSS_HASH_IPV4 0x00010000 611193880Syongari#define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 612193880Syongari#define RXQ_CFG_RSS_HASH_IPV6 0x00040000 613193880Syongari#define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 614193880Syongari#define RXQ_CFG_RD_BURST_MASK 0x03F00000 615193880Syongari#define RXQ_CFG_RSS_MODE_DIS 0x00000000 616193880Syongari#define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 617193880Syongari#define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 618193880Syongari#define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 619193880Syongari#define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 620193880Syongari#define RXQ_CFG_RSS_HASH_ENB 0x20000000 621193880Syongari#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 622193880Syongari#define RXQ_CFG_QUEUE0_ENB 0x80000000 623193880Syongari#define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 624193880Syongari#define RXQ_CFG_RD_BURST_DEFAULT 8 625193880Syongari#define RXQ_CFG_RD_BURST_SHIFT 20 626193880Syongari#define RXQ_CFG_ENB \ 627193880Syongari (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 628193880Syongari RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 629193880Syongari 630272730Syongari/* AR816x specific bits */ 631272730Syongari#define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004 632272730Syongari#define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008 633272730Syongari#define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010 634272730Syongari#define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020 635272730Syongari#define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C 636272730Syongari#define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080 637272730Syongari#define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00 638272730Syongari#define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8 639272730Syongari#define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100 640272730Syongari 641193880Syongari#define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 642193880Syongari#define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 643193880Syongari#define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 644193880Syongari#define RX_RD_FREE_THRESH_HI_SHIFT 0 645193880Syongari#define RX_RD_FREE_THRESH_LO_SHIFT 6 646193880Syongari#define RX_RD_FREE_THRESH_HI_DEFAULT 16 647193880Syongari#define RX_RD_FREE_THRESH_LO_DEFAULT 8 648193880Syongari 649193880Syongari#define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 650193880Syongari#define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 651193880Syongari#define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 652193880Syongari#define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 653193880Syongari#define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 654272730Syongari/* 655272730Syongari * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + 656272730Syongari * rx-packet(1522) + delay-of-link(64) 657272730Syongari * = 3212. 658272730Syongari */ 659272730Syongari#define RX_FIFO_PAUSE_816X_RSVD 3212 660193880Syongari 661193880Syongari#define ALC_RD_DMA_CFG 0x15AC 662193880Syongari#define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 663193880Syongari#define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 664193880Syongari#define RD_DMA_CFG_THRESH_SHIFT 0 665193880Syongari#define RD_DMA_CFG_TIMER_SHIFT 16 666193880Syongari#define RD_DMA_CFG_THRESH_DEFAULT 0x100 667193880Syongari#define RD_DMA_CFG_TIMER_DEFAULT 0 668193880Syongari#define RD_DMA_CFG_TICK_USECS 8 669193880Syongari#define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 670193880Syongari 671193880Syongari#define ALC_RSS_HASH_VALUE 0x15B0 672193880Syongari 673193880Syongari#define ALC_RSS_HASH_FLAG 0x15B4 674193880Syongari 675193880Syongari#define ALC_RSS_CPU 0x15B8 676193880Syongari 677193880Syongari#define ALC_DMA_CFG 0x15C0 678193880Syongari#define DMA_CFG_IN_ORDER 0x00000001 679193880Syongari#define DMA_CFG_ENH_ORDER 0x00000002 680193880Syongari#define DMA_CFG_OUT_ORDER 0x00000004 681193880Syongari#define DMA_CFG_RCB_64 0x00000000 682193880Syongari#define DMA_CFG_RCB_128 0x00000008 683272730Syongari#define DMA_CFG_PEND_AUTO_RST 0x00000008 684193880Syongari#define DMA_CFG_RD_BURST_128 0x00000000 685193880Syongari#define DMA_CFG_RD_BURST_256 0x00000010 686193880Syongari#define DMA_CFG_RD_BURST_512 0x00000020 687193880Syongari#define DMA_CFG_RD_BURST_1024 0x00000030 688193880Syongari#define DMA_CFG_RD_BURST_2048 0x00000040 689193880Syongari#define DMA_CFG_RD_BURST_4096 0x00000050 690193880Syongari#define DMA_CFG_WR_BURST_128 0x00000000 691193880Syongari#define DMA_CFG_WR_BURST_256 0x00000080 692193880Syongari#define DMA_CFG_WR_BURST_512 0x00000100 693193880Syongari#define DMA_CFG_WR_BURST_1024 0x00000180 694193880Syongari#define DMA_CFG_WR_BURST_2048 0x00000200 695193880Syongari#define DMA_CFG_WR_BURST_4096 0x00000280 696193880Syongari#define DMA_CFG_RD_REQ_PRI 0x00000400 697193880Syongari#define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 698193880Syongari#define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 699193880Syongari#define DMA_CFG_CMB_ENB 0x00100000 700193880Syongari#define DMA_CFG_SMB_ENB 0x00200000 701193880Syongari#define DMA_CFG_CMB_NOW 0x00400000 702193880Syongari#define DMA_CFG_SMB_DIS 0x01000000 703272730Syongari#define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000 704272730Syongari#define DMA_CFG_RD_CHNL_SEL_1 0x00000000 705272730Syongari#define DMA_CFG_RD_CHNL_SEL_2 0x04000000 706272730Syongari#define DMA_CFG_RD_CHNL_SEL_3 0x08000000 707272730Syongari#define DMA_CFG_RD_CHNL_SEL_4 0x0C000000 708272730Syongari#define DMA_CFG_WSRAM_RDCTL 0x10000000 709272730Syongari#define DMA_CFG_RD_PEND_CLR 0x20000000 710272730Syongari#define DMA_CFG_WR_PEND_CLR 0x40000000 711193880Syongari#define DMA_CFG_SMB_NOW 0x80000000 712193880Syongari#define DMA_CFG_RD_BURST_MASK 0x07 713193880Syongari#define DMA_CFG_RD_BURST_SHIFT 4 714193880Syongari#define DMA_CFG_WR_BURST_MASK 0x07 715193880Syongari#define DMA_CFG_WR_BURST_SHIFT 7 716193880Syongari#define DMA_CFG_RD_DELAY_CNT_SHIFT 11 717193880Syongari#define DMA_CFG_WR_DELAY_CNT_SHIFT 16 718193880Syongari#define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 719193880Syongari#define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 720193880Syongari 721193880Syongari#define ALC_SMB_STAT_TIMER 0x15C4 722193880Syongari#define SMB_STAT_TIMER_MASK 0x00FFFFFF 723193880Syongari#define SMB_STAT_TIMER_SHIFT 0 724193880Syongari 725193880Syongari#define ALC_CMB_TD_THRESH 0x15C8 726193880Syongari#define CMB_TD_THRESH_MASK 0x0000FFFF 727193880Syongari#define CMB_TD_THRESH_SHIFT 0 728193880Syongari 729193880Syongari#define ALC_CMB_TX_TIMER 0x15CC 730193880Syongari#define CMB_TX_TIMER_MASK 0x0000FFFF 731193880Syongari#define CMB_TX_TIMER_SHIFT 0 732193880Syongari 733272730Syongari#define ALC_MSI_MAP_TBL1 0x15D0 734272730Syongari 735272730Syongari#define ALC_MSI_ID_MAP 0x15D4 736272730Syongari 737272730Syongari#define ALC_MSI_MAP_TBL2 0x15D8 738272730Syongari 739193880Syongari#define ALC_MBOX_RD0_PROD_IDX 0x15E0 740193880Syongari 741193880Syongari#define ALC_MBOX_RD1_PROD_IDX 0x15E4 742193880Syongari 743193880Syongari#define ALC_MBOX_RD2_PROD_IDX 0x15E8 744193880Syongari 745193880Syongari#define ALC_MBOX_RD3_PROD_IDX 0x15EC 746193880Syongari 747193880Syongari#define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 748193880Syongari#define MBOX_RD_PROD_SHIFT 0 749193880Syongari 750193880Syongari#define ALC_MBOX_TD_PROD_IDX 0x15F0 751193880Syongari#define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 752193880Syongari#define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 753193880Syongari#define MBOX_TD_PROD_HI_IDX_SHIFT 0 754193880Syongari#define MBOX_TD_PROD_LO_IDX_SHIFT 16 755193880Syongari 756272730Syongari#define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */ 757272730Syongari 758272730Syongari#define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */ 759272730Syongari 760193880Syongari#define ALC_MBOX_TD_CONS_IDX 0x15F4 761193880Syongari#define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 762193880Syongari#define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 763193880Syongari#define MBOX_TD_CONS_HI_IDX_SHIFT 0 764193880Syongari#define MBOX_TD_CONS_LO_IDX_SHIFT 16 765193880Syongari 766272730Syongari#define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */ 767272730Syongari 768272730Syongari#define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */ 769272730Syongari 770193880Syongari#define ALC_MBOX_RD01_CONS_IDX 0x15F8 771193880Syongari#define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 772193880Syongari#define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 773193880Syongari#define MBOX_RD0_CONS_IDX_SHIFT 0 774193880Syongari#define MBOX_RD1_CONS_IDX_SHIFT 16 775193880Syongari 776193880Syongari#define ALC_MBOX_RD23_CONS_IDX 0x15FC 777193880Syongari#define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 778193880Syongari#define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 779193880Syongari#define MBOX_RD2_CONS_IDX_SHIFT 0 780193880Syongari#define MBOX_RD3_CONS_IDX_SHIFT 16 781193880Syongari 782193880Syongari#define ALC_INTR_STATUS 0x1600 783193880Syongari#define INTR_SMB 0x00000001 784193880Syongari#define INTR_TIMER 0x00000002 785193880Syongari#define INTR_MANUAL_TIMER 0x00000004 786193880Syongari#define INTR_RX_FIFO_OFLOW 0x00000008 787193880Syongari#define INTR_RD0_UNDERRUN 0x00000010 788193880Syongari#define INTR_RD1_UNDERRUN 0x00000020 789193880Syongari#define INTR_RD2_UNDERRUN 0x00000040 790193880Syongari#define INTR_RD3_UNDERRUN 0x00000080 791193880Syongari#define INTR_TX_FIFO_UNDERRUN 0x00000100 792193880Syongari#define INTR_DMA_RD_TO_RST 0x00000200 793193880Syongari#define INTR_DMA_WR_TO_RST 0x00000400 794193880Syongari#define INTR_TX_CREDIT 0x00000800 795193880Syongari#define INTR_GPHY 0x00001000 796193880Syongari#define INTR_GPHY_LOW_PW 0x00002000 797193880Syongari#define INTR_TXQ_TO_RST 0x00004000 798272730Syongari#define INTR_TX_PKT0 0x00008000 799193880Syongari#define INTR_RX_PKT0 0x00010000 800193880Syongari#define INTR_RX_PKT1 0x00020000 801193880Syongari#define INTR_RX_PKT2 0x00040000 802193880Syongari#define INTR_RX_PKT3 0x00080000 803193880Syongari#define INTR_MAC_RX 0x00100000 804193880Syongari#define INTR_MAC_TX 0x00200000 805193880Syongari#define INTR_UNDERRUN 0x00400000 806193880Syongari#define INTR_FRAME_ERROR 0x00800000 807193880Syongari#define INTR_FRAME_OK 0x01000000 808193880Syongari#define INTR_CSUM_ERROR 0x02000000 809193880Syongari#define INTR_PHY_LINK_DOWN 0x04000000 810193880Syongari#define INTR_DIS_INT 0x80000000 811193880Syongari 812272730Syongari/* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */ 813272730Syongari#define INTR_TX_PKT1 0x00000020 814272730Syongari#define INTR_TX_PKT2 0x00000040 815272730Syongari#define INTR_TX_PKT3 0x00000080 816272730Syongari#define INTR_RX_PKT4 0x08000000 817272730Syongari#define INTR_RX_PKT5 0x10000000 818272730Syongari#define INTR_RX_PKT6 0x20000000 819272730Syongari#define INTR_RX_PKT7 0x40000000 820272730Syongari 821193880Syongari/* Interrupt Mask Register */ 822193880Syongari#define ALC_INTR_MASK 0x1604 823193880Syongari 824193880Syongari#ifdef notyet 825193880Syongari#define INTR_RX_PKT \ 826193880Syongari (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 827193880Syongari INTR_RX_PKT3) 828193880Syongari#define INTR_RD_UNDERRUN \ 829193880Syongari (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 830193880Syongari INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 831193880Syongari#else 832272730Syongari#define INTR_TX_PKT INTR_TX_PKT0 833193880Syongari#define INTR_RX_PKT INTR_RX_PKT0 834193880Syongari#define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 835193880Syongari#endif 836193880Syongari 837193880Syongari#define ALC_INTRS \ 838193880Syongari (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 839193880Syongari INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 840193880Syongari INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 841193880Syongari INTR_TX_FIFO_UNDERRUN) 842193880Syongari 843193880Syongari#define ALC_INTR_RETRIG_TIMER 0x1608 844193880Syongari#define INTR_RETRIG_TIMER_MASK 0x0000FFFF 845193880Syongari#define INTR_RETRIG_TIMER_SHIFT 0 846193880Syongari 847193880Syongari#define ALC_HDS_CFG 0x160C 848193880Syongari#define HDS_CFG_ENB 0x00000001 849193880Syongari#define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 850193880Syongari#define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 851193880Syongari#define HDS_CFG_BACKFILLSIZE_SHIFT 8 852193880Syongari#define HDS_CFG_MAX_HDRSIZE_SHIFT 20 853193880Syongari 854272730Syongari#define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */ 855272730Syongari 856272730Syongari#define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */ 857272730Syongari 858272730Syongari#define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */ 859272730Syongari 860272730Syongari#define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */ 861272730Syongari 862211105Syongari/* AR813x/AR815x registers for MAC statistics */ 863193880Syongari#define ALC_RX_MIB_BASE 0x1700 864193880Syongari 865193880Syongari#define ALC_TX_MIB_BASE 0x1760 866193880Syongari 867272730Syongari#define ALC_DRV 0x1804 /* AR816x */ 868272730Syongari#define DRV_ASPM_SPD10LMT_1M 0x00000000 869272730Syongari#define DRV_ASPM_SPD10LMT_10M 0x00000001 870272730Syongari#define DRV_ASPM_SPD10LMT_100M 0x00000002 871272730Syongari#define DRV_ASPM_SPD10LMT_NO 0x00000003 872272730Syongari#define DRV_ASPM_SPD10LMT_MASK 0x00000003 873272730Syongari#define DRV_ASPM_SPD100LMT_1M 0x00000000 874272730Syongari#define DRV_ASPM_SPD100LMT_10M 0x00000004 875272730Syongari#define DRV_ASPM_SPD100LMT_100M 0x00000008 876272730Syongari#define DRV_ASPM_SPD100LMT_NO 0x0000000C 877272730Syongari#define DRV_ASPM_SPD100LMT_MASK 0x0000000C 878272730Syongari#define DRV_ASPM_SPD1000LMT_100M 0x00000000 879272730Syongari#define DRV_ASPM_SPD1000LMT_NO 0x00000010 880272730Syongari#define DRV_ASPM_SPD1000LMT_1M 0x00000020 881272730Syongari#define DRV_ASPM_SPD1000LMT_10M 0x00000030 882272730Syongari#define DRV_ASPM_SPD1000LMT_MASK 0x00000000 883272730Syongari#define DRV_WOLCAP_BIOS_EN 0x00000100 884272730Syongari#define DRV_WOLMAGIC_EN 0x00000200 885272730Syongari#define DRV_WOLLINKUP_EN 0x00000400 886272730Syongari#define DRV_WOLPATTERN_EN 0x00000800 887272730Syongari#define DRV_AZ_EN 0x00001000 888272730Syongari#define DRV_WOLS5_BIOS_EN 0x00010000 889272730Syongari#define DRV_WOLS5_EN 0x00020000 890272730Syongari#define DRV_DISABLE 0x00040000 891272730Syongari#define DRV_PHY_MASK 0x1FE00000 892272730Syongari#define DRV_PHY_EEE 0x00200000 893272730Syongari#define DRV_PHY_APAUSE 0x00400000 894272730Syongari#define DRV_PHY_PAUSE 0x00800000 895272730Syongari#define DRV_PHY_DUPLEX 0x01000000 896272730Syongari#define DRV_PHY_10 0x02000000 897272730Syongari#define DRV_PHY_100 0x04000000 898272730Syongari#define DRV_PHY_1000 0x08000000 899272730Syongari#define DRV_PHY_AUTO 0x10000000 900272730Syongari#define DRV_PHY_SHIFT 21 901272730Syongari 902217649Syongari#define ALC_CLK_GATING_CFG 0x1814 903217649Syongari#define CLK_GATING_DMAW_ENB 0x0001 904217649Syongari#define CLK_GATING_DMAR_ENB 0x0002 905217649Syongari#define CLK_GATING_TXQ_ENB 0x0004 906217649Syongari#define CLK_GATING_RXQ_ENB 0x0008 907217649Syongari#define CLK_GATING_TXMAC_ENB 0x0010 908217649Syongari#define CLK_GATING_RXMAC_ENB 0x0020 909217649Syongari 910193880Syongari#define ALC_DEBUG_DATA0 0x1900 911193880Syongari 912193880Syongari#define ALC_DEBUG_DATA1 0x1904 913193880Syongari 914272730Syongari#define ALC_MSI_RETRANS_TIMER 0x1920 915272730Syongari#define MSI_RETRANS_TIMER_MASK 0x0000FFFF 916272730Syongari#define MSI_RETRANS_MASK_SEL_STD 0x00000000 917272730Syongari#define MSI_RETRANS_MASK_SEL_LINE 0x00010000 918272730Syongari#define MSI_RETRANS_TIMER_SHIFT 0 919272730Syongari 920272730Syongari#define ALC_WRR 0x1938 921272730Syongari#define WRR_PRI0_MASK 0x0000001F 922272730Syongari#define WRR_PRI1_MASK 0x00001F00 923272730Syongari#define WRR_PRI2_MASK 0x001F0000 924272730Syongari#define WRR_PRI3_MASK 0x1F000000 925272730Syongari#define WRR_PRI_RESTRICT_MASK 0x60000000 926272730Syongari#define WRR_PRI_RESTRICT_ALL 0x00000000 927272730Syongari#define WRR_PRI_RESTRICT_HI 0x20000000 928272730Syongari#define WRR_PRI_RESTRICT_HI2 0x40000000 929272730Syongari#define WRR_PRI_RESTRICT_NONE 0x60000000 930272730Syongari#define WRR_PRI0_SHIFT 0 931272730Syongari#define WRR_PRI1_SHIFT 8 932272730Syongari#define WRR_PRI2_SHIFT 16 933272730Syongari#define WRR_PRI3_SHIFT 24 934272730Syongari#define WRR_PRI_DEFAULT 4 935272730Syongari#define WRR_PRI_RESTRICT_SHIFT 29 936272730Syongari 937272730Syongari#define ALC_HQTD_CFG 0x193C 938272730Syongari#define HQTD_CFG_Q1_BURST_MASK 0x0000000F 939272730Syongari#define HQTD_CFG_Q2_BURST_MASK 0x000000F0 940272730Syongari#define HQTD_CFG_Q3_BURST_MASK 0x00000F00 941272730Syongari#define HQTD_CFG_BURST_ENB 0x80000000 942272730Syongari#define HQTD_CFG_Q1_BURST_SHIFT 0 943272730Syongari#define HQTD_CFG_Q2_BURST_SHIFT 4 944272730Syongari#define HQTD_CFG_Q3_BURST_SHIFT 8 945272730Syongari 946272730Syongari#define ALC_MISC 0x19C0 947272730Syongari#define MISC_INTNLOSC_OPEN 0x00000008 948272730Syongari#define MISC_ISO_ENB 0x00001000 949272730Syongari#define MISC_PSW_OCP_MASK 0x00E00000 950272730Syongari#define MISC_PSW_OCP_SHIFT 21 951272730Syongari#define MISC_PSW_OCP_DEFAULT 7 952272730Syongari 953272730Syongari#define ALC_MISC2 0x19C8 954272730Syongari#define MISC2_CALB_START 0x00000001 955272730Syongari 956272730Syongari#define ALC_MISC3 0x19CC 957272730Syongari#define MISC3_25M_NOTO_INTNL 0x00000001 958272730Syongari#define MISC3_25M_BY_SW 0x00000002 959272730Syongari 960193880Syongari#define ALC_MII_DBG_ADDR 0x1D 961193880Syongari#define ALC_MII_DBG_DATA 0x1E 962193880Syongari 963193880Syongari#define MII_ANA_CFG0 0x00 964193880Syongari#define ANA_RESTART_CAL 0x0001 965193880Syongari#define ANA_MANUL_SWICH_ON_MASK 0x001E 966193880Syongari#define ANA_MAN_ENABLE 0x0020 967193880Syongari#define ANA_SEL_HSP 0x0040 968193880Syongari#define ANA_EN_HB 0x0080 969193880Syongari#define ANA_EN_HBIAS 0x0100 970193880Syongari#define ANA_OEN_125M 0x0200 971193880Syongari#define ANA_EN_LCKDT 0x0400 972193880Syongari#define ANA_LCKDT_PHY 0x0800 973193880Syongari#define ANA_AFE_MODE 0x1000 974193880Syongari#define ANA_VCO_SLOW 0x2000 975193880Syongari#define ANA_VCO_FAST 0x4000 976193880Syongari#define ANA_SEL_CLK125M_DSP 0x8000 977193880Syongari#define ANA_MANUL_SWICH_ON_SHIFT 1 978193880Syongari 979272730Syongari#define MII_DBG_ANACTL 0x00 980272730Syongari#define DBG_ANACTL_DEFAULT 0x02EF 981272730Syongari 982193880Syongari#define MII_ANA_CFG4 0x04 983193880Syongari#define ANA_IECHO_ADJ_MASK 0x0F 984193880Syongari#define ANA_IECHO_ADJ_3_MASK 0x000F 985193880Syongari#define ANA_IECHO_ADJ_2_MASK 0x00F0 986193880Syongari#define ANA_IECHO_ADJ_1_MASK 0x0F00 987193880Syongari#define ANA_IECHO_ADJ_0_MASK 0xF000 988193880Syongari#define ANA_IECHO_ADJ_3_SHIFT 0 989193880Syongari#define ANA_IECHO_ADJ_2_SHIFT 4 990193880Syongari#define ANA_IECHO_ADJ_1_SHIFT 8 991193880Syongari#define ANA_IECHO_ADJ_0_SHIFT 12 992193880Syongari 993272730Syongari#define MII_DBG_SYSMODCTL 0x04 994272730Syongari#define DBG_SYSMODCTL_DEFAULT 0xBB8B 995272730Syongari 996193880Syongari#define MII_ANA_CFG5 0x05 997193880Syongari#define ANA_SERDES_CDR_BW_MASK 0x0003 998193880Syongari#define ANA_MS_PAD_DBG 0x0004 999193880Syongari#define ANA_SPEEDUP_DBG 0x0008 1000193880Syongari#define ANA_SERDES_TH_LOS_MASK 0x0030 1001193880Syongari#define ANA_SERDES_EN_DEEM 0x0040 1002193880Syongari#define ANA_SERDES_TXELECIDLE 0x0080 1003193880Syongari#define ANA_SERDES_BEACON 0x0100 1004193880Syongari#define ANA_SERDES_HALFTXDR 0x0200 1005193880Syongari#define ANA_SERDES_SEL_HSP 0x0400 1006193880Syongari#define ANA_SERDES_EN_PLL 0x0800 1007193880Syongari#define ANA_SERDES_EN 0x1000 1008193880Syongari#define ANA_SERDES_EN_LCKDT 0x2000 1009193880Syongari#define ANA_SERDES_CDR_BW_SHIFT 0 1010193880Syongari#define ANA_SERDES_TH_LOS_SHIFT 4 1011193880Syongari 1012272730Syongari#define MII_DBG_SRDSYSMOD 0x05 1013272730Syongari#define DBG_SRDSYSMOD_DEFAULT 0x2C46 1014272730Syongari 1015193880Syongari#define MII_ANA_CFG11 0x0B 1016193880Syongari#define ANA_PS_HIB_EN 0x8000 1017193880Syongari 1018272730Syongari#define MII_DBG_HIBNEG 0x0B 1019272730Syongari#define DBG_HIBNEG_HIB_PULSE 0x1000 1020272730Syongari#define DBG_HIBNEG_PSHIB_EN 0x8000 1021272730Syongari#define DBG_HIBNEG_DEFAULT 0xBC40 1022272730Syongari 1023193880Syongari#define MII_ANA_CFG18 0x12 1024193880Syongari#define ANA_TEST_MODE_10BT_01MASK 0x0003 1025193880Syongari#define ANA_LOOP_SEL_10BT 0x0004 1026193880Syongari#define ANA_RGMII_MODE_SW 0x0008 1027193880Syongari#define ANA_EN_LONGECABLE 0x0010 1028193880Syongari#define ANA_TEST_MODE_10BT_2 0x0020 1029193880Syongari#define ANA_EN_10BT_IDLE 0x0400 1030193880Syongari#define ANA_EN_MASK_TB 0x0800 1031193880Syongari#define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 1032193880Syongari#define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 1033193880Syongari#define ANA_TEST_MODE_10BT_01SHIFT 0 1034193880Syongari#define ANA_TRIGGER_SEL_TIMER_SHIFT 12 1035193880Syongari#define ANA_INTERVAL_SEL_TIMER_SHIFT 14 1036193880Syongari 1037272730Syongari#define MII_DBG_TST10BTCFG 0x12 1038272730Syongari#define DBG_TST10BTCFG_DEFAULT 0x4C04 1039272730Syongari 1040272730Syongari#define MII_DBG_AZ_ANADECT 0x15 1041272730Syongari#define DBG_AZ_ANADECT_DEFAULT 0x3220 1042272730Syongari#define DBG_AZ_ANADECT_LONG 0x3210 1043272730Syongari 1044272730Syongari#define MII_DBG_MSE16DB 0x18 1045272730Syongari#define DBG_MSE16DB_UP 0x05EA 1046272730Syongari#define DBG_MSE16DB_DOWN 0x02EA 1047272730Syongari 1048272730Syongari#define MII_DBG_MSE20DB 0x1C 1049272730Syongari#define DBG_MSE20DB_TH_MASK 0x01FC 1050272730Syongari#define DBG_MSE20DB_TH_DEFAULT 0x2E 1051272730Syongari#define DBG_MSE20DB_TH_HI 0x54 1052272730Syongari#define DBG_MSE20DB_TH_SHIFT 2 1053272730Syongari 1054272730Syongari#define MII_DBG_AGC 0x23 1055272730Syongari#define DBG_AGC_2_VGA_MASK 0x3F00 1056272730Syongari#define DBG_AGC_2_VGA_SHIFT 8 1057272730Syongari#define DBG_AGC_LONG1G_LIMT 40 1058272730Syongari#define DBG_AGC_LONG100M_LIMT 44 1059272730Syongari 1060193880Syongari#define MII_ANA_CFG41 0x29 1061193880Syongari#define ANA_TOP_PS_EN 0x8000 1062193880Syongari 1063272730Syongari#define MII_DBG_LEGCYPS 0x29 1064272730Syongari#define DBG_LEGCYPS_ENB 0x8000 1065272730Syongari#define DBG_LEGCYPS_DEFAULT 0x129D 1066272730Syongari 1067193880Syongari#define MII_ANA_CFG54 0x36 1068193880Syongari#define ANA_LONG_CABLE_TH_100_MASK 0x003F 1069193880Syongari#define ANA_DESERVED 0x0040 1070193880Syongari#define ANA_EN_LIT_CH 0x0080 1071193880Syongari#define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 1072193880Syongari#define ANA_BP_BAD_LINK_ACCUM 0x4000 1073193880Syongari#define ANA_BP_SMALL_BW 0x8000 1074193880Syongari#define ANA_LONG_CABLE_TH_100_SHIFT 0 1075193880Syongari#define ANA_SHORT_CABLE_TH_100_SHIFT 8 1076193880Syongari 1077272730Syongari#define MII_DBG_TST100BTCFG 0x36 1078272730Syongari#define DBG_TST100BTCFG_DEFAULT 0xE12C 1079272730Syongari 1080272730Syongari#define MII_DBG_GREENCFG 0x3B 1081272730Syongari#define DBG_GREENCFG_DEFAULT 0x7078 1082272730Syongari 1083272730Syongari#define MII_DBG_GREENCFG2 0x3D 1084272730Syongari#define DBG_GREENCFG2_GATE_DFSE_EN 0x0080 1085272730Syongari#define DBG_GREENCFG2_BP_GREEN 0x8000 1086272730Syongari 1087272730Syongari/* Device addr 3 */ 1088272730Syongari#define MII_EXT_PCS 3 1089272730Syongari 1090272730Syongari#define MII_EXT_CLDCTL3 0x8003 1091272730Syongari#define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000 1092272730Syongari 1093272730Syongari#define MII_EXT_CLDCTL5 0x8005 1094272730Syongari#define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000 1095272730Syongari 1096272730Syongari#define MII_EXT_CLDCTL6 0x8006 1097272730Syongari#define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF 1098272730Syongari#define EXT_CLDCTL6_CAB_LEN_SHIFT 0 1099272730Syongari#define EXT_CLDCTL6_CAB_LEN_SHORT1G 116 1100272730Syongari#define EXT_CLDCTL6_CAB_LEN_SHORT100M 152 1101272730Syongari 1102272730Syongari#define MII_EXT_VDRVBIAS 0x8062 1103272730Syongari#define EXT_VDRVBIAS_DEFAULT 3 1104272730Syongari 1105272730Syongari/* Device addr 7 */ 1106272730Syongari#define MII_EXT_ANEG 7 1107272730Syongari 1108272730Syongari#define MII_EXT_ANEG_LOCAL_EEEADV 0x3C 1109272730Syongari#define ANEG_LOCA_EEEADV_100BT 0x0002 1110272730Syongari#define ANEG_LOCA_EEEADV_1000BT 0x0004 1111272730Syongari 1112272730Syongari#define MII_EXT_ANEG_AFE 0x801A 1113272730Syongari#define ANEG_AFEE_10BT_100M_TH 0x0040 1114272730Syongari 1115272730Syongari#define MII_EXT_ANEG_S3DIG10 0x8023 1116272730Syongari#define ANEG_S3DIG10_SL 0x0001 1117272730Syongari#define ANEG_S3DIG10_DEFAULT 0 1118272730Syongari 1119272730Syongari#define MII_EXT_ANEG_NLP78 0x8027 1120272730Syongari#define ANEG_NLP78_120M_DEFAULT 0x8A05 1121272730Syongari 1122193880Syongari/* Statistics counters collected by the MAC. */ 1123193880Syongaristruct smb { 1124193880Syongari /* Rx stats. */ 1125193880Syongari uint32_t rx_frames; 1126193880Syongari uint32_t rx_bcast_frames; 1127193880Syongari uint32_t rx_mcast_frames; 1128193880Syongari uint32_t rx_pause_frames; 1129193880Syongari uint32_t rx_control_frames; 1130193880Syongari uint32_t rx_crcerrs; 1131193880Syongari uint32_t rx_lenerrs; 1132193880Syongari uint32_t rx_bytes; 1133193880Syongari uint32_t rx_runts; 1134193880Syongari uint32_t rx_fragments; 1135193880Syongari uint32_t rx_pkts_64; 1136193880Syongari uint32_t rx_pkts_65_127; 1137193880Syongari uint32_t rx_pkts_128_255; 1138193880Syongari uint32_t rx_pkts_256_511; 1139193880Syongari uint32_t rx_pkts_512_1023; 1140193880Syongari uint32_t rx_pkts_1024_1518; 1141193880Syongari uint32_t rx_pkts_1519_max; 1142193880Syongari uint32_t rx_pkts_truncated; 1143193880Syongari uint32_t rx_fifo_oflows; 1144193880Syongari uint32_t rx_rrs_errs; 1145193880Syongari uint32_t rx_alignerrs; 1146193880Syongari uint32_t rx_bcast_bytes; 1147193880Syongari uint32_t rx_mcast_bytes; 1148193880Syongari uint32_t rx_pkts_filtered; 1149193880Syongari /* Tx stats. */ 1150193880Syongari uint32_t tx_frames; 1151193880Syongari uint32_t tx_bcast_frames; 1152193880Syongari uint32_t tx_mcast_frames; 1153193880Syongari uint32_t tx_pause_frames; 1154193880Syongari uint32_t tx_excess_defer; 1155193880Syongari uint32_t tx_control_frames; 1156193880Syongari uint32_t tx_deferred; 1157193880Syongari uint32_t tx_bytes; 1158193880Syongari uint32_t tx_pkts_64; 1159193880Syongari uint32_t tx_pkts_65_127; 1160193880Syongari uint32_t tx_pkts_128_255; 1161193880Syongari uint32_t tx_pkts_256_511; 1162193880Syongari uint32_t tx_pkts_512_1023; 1163193880Syongari uint32_t tx_pkts_1024_1518; 1164193880Syongari uint32_t tx_pkts_1519_max; 1165193880Syongari uint32_t tx_single_colls; 1166193880Syongari uint32_t tx_multi_colls; 1167193880Syongari uint32_t tx_late_colls; 1168193880Syongari uint32_t tx_excess_colls; 1169193880Syongari uint32_t tx_underrun; 1170193880Syongari uint32_t tx_desc_underrun; 1171193880Syongari uint32_t tx_lenerrs; 1172193880Syongari uint32_t tx_pkts_truncated; 1173193880Syongari uint32_t tx_bcast_bytes; 1174193880Syongari uint32_t tx_mcast_bytes; 1175193880Syongari uint32_t updated; 1176193880Syongari}; 1177193880Syongari 1178193880Syongari/* CMB(Coalesing message block) */ 1179193880Syongaristruct cmb { 1180193880Syongari uint32_t cons; 1181193880Syongari}; 1182193880Syongari 1183193880Syongari/* Rx free descriptor */ 1184193880Syongaristruct rx_desc { 1185193880Syongari uint64_t addr; 1186193880Syongari}; 1187193880Syongari 1188193880Syongari/* Rx return descriptor */ 1189193880Syongaristruct rx_rdesc { 1190193880Syongari uint32_t rdinfo; 1191193880Syongari#define RRD_CSUM_MASK 0x0000FFFF 1192193880Syongari#define RRD_RD_CNT_MASK 0x000F0000 1193193880Syongari#define RRD_RD_IDX_MASK 0xFFF00000 1194193880Syongari#define RRD_CSUM_SHIFT 0 1195193880Syongari#define RRD_RD_CNT_SHIFT 16 1196193880Syongari#define RRD_RD_IDX_SHIFT 20 1197193880Syongari#define RRD_CSUM(x) \ 1198193880Syongari (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 1199193880Syongari#define RRD_RD_CNT(x) \ 1200193880Syongari (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 1201193880Syongari#define RRD_RD_IDX(x) \ 1202193880Syongari (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 1203193880Syongari uint32_t rss; 1204193880Syongari uint32_t vtag; 1205193880Syongari#define RRD_VLAN_MASK 0x0000FFFF 1206193880Syongari#define RRD_HEAD_LEN_MASK 0x00FF0000 1207193880Syongari#define RRD_HDS_MASK 0x03000000 1208193880Syongari#define RRD_HDS_NONE 0x00000000 1209193880Syongari#define RRD_HDS_HEAD 0x01000000 1210193880Syongari#define RRD_HDS_DATA 0x02000000 1211193880Syongari#define RRD_CPU_MASK 0x0C000000 1212193880Syongari#define RRD_HASH_FLAG_MASK 0xF0000000 1213193880Syongari#define RRD_VLAN_SHIFT 0 1214193880Syongari#define RRD_HEAD_LEN_SHIFT 16 1215193880Syongari#define RRD_HDS_SHIFT 24 1216193880Syongari#define RRD_CPU_SHIFT 26 1217193880Syongari#define RRD_HASH_FLAG_SHIFT 28 1218193880Syongari#define RRD_VLAN(x) \ 1219193880Syongari (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 1220193880Syongari#define RRD_HEAD_LEN(x) \ 1221193880Syongari (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 1222193880Syongari#define RRD_CPU(x) \ 1223193880Syongari (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 1224193880Syongari uint32_t status; 1225193880Syongari#define RRD_LEN_MASK 0x00003FFF 1226193880Syongari#define RRD_LEN_SHIFT 0 1227193880Syongari#define RRD_TCP_UDPCSUM_NOK 0x00004000 1228193880Syongari#define RRD_IPCSUM_NOK 0x00008000 1229193880Syongari#define RRD_VLAN_TAG 0x00010000 1230193880Syongari#define RRD_PROTO_MASK 0x000E0000 1231193880Syongari#define RRD_PROTO_IPV4 0x00020000 1232193880Syongari#define RRD_PROTO_IPV6 0x000C0000 1233193880Syongari#define RRD_ERR_SUM 0x00100000 1234193880Syongari#define RRD_ERR_CRC 0x00200000 1235193880Syongari#define RRD_ERR_ALIGN 0x00400000 1236193880Syongari#define RRD_ERR_TRUNC 0x00800000 1237193880Syongari#define RRD_ERR_RUNT 0x01000000 1238193880Syongari#define RRD_ERR_ICMP 0x02000000 1239193880Syongari#define RRD_BCAST 0x04000000 1240193880Syongari#define RRD_MCAST 0x08000000 1241193880Syongari#define RRD_SNAP_LLC 0x10000000 1242193880Syongari#define RRD_ETHER 0x00000000 1243193880Syongari#define RRD_FIFO_FULL 0x20000000 1244193880Syongari#define RRD_ERR_LENGTH 0x40000000 1245193880Syongari#define RRD_VALID 0x80000000 1246193880Syongari#define RRD_BYTES(x) \ 1247193880Syongari (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 1248193880Syongari#define RRD_IPV4(x) \ 1249193880Syongari (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 1250193880Syongari}; 1251193880Syongari 1252193880Syongari/* Tx descriptor */ 1253193880Syongaristruct tx_desc { 1254193880Syongari uint32_t len; 1255193880Syongari#define TD_BUFLEN_MASK 0x00003FFF 1256193880Syongari#define TD_VLAN_MASK 0xFFFF0000 1257193880Syongari#define TD_BUFLEN_SHIFT 0 1258193880Syongari#define TX_BYTES(x) \ 1259193880Syongari (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 1260193880Syongari#define TD_VLAN_SHIFT 16 1261193880Syongari uint32_t flags; 1262193880Syongari#define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 1263193880Syongari#define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 1264193880Syongari#define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 1265193880Syongari#define TD_CUSTOM_CSUM 0x00000100 1266193880Syongari#define TD_IPCSUM 0x00000200 1267193880Syongari#define TD_TCPCSUM 0x00000400 1268193880Syongari#define TD_UDPCSUM 0x00000800 1269193880Syongari#define TD_TSO 0x00001000 1270193880Syongari#define TD_TSO_DESCV1 0x00000000 1271193880Syongari#define TD_TSO_DESCV2 0x00002000 1272193880Syongari#define TD_CON_VLAN_TAG 0x00004000 1273193880Syongari#define TD_INS_VLAN_TAG 0x00008000 1274193880Syongari#define TD_IPV4_DESCV2 0x00010000 1275193880Syongari#define TD_LLC_SNAP 0x00020000 1276193880Syongari#define TD_ETHERNET 0x00000000 1277193880Syongari#define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 1278193880Syongari#define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 1279193880Syongari#define TD_MSS_MASK 0x7FFC0000 1280193880Syongari#define TD_EOP 0x80000000 1281193880Syongari#define TD_L4HDR_OFFSET_SHIFT 0 1282193880Syongari#define TD_TCPHDR_OFFSET_SHIFT 0 1283193880Syongari#define TD_PLOAD_OFFSET_SHIFT 0 1284193880Syongari#define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 1285193880Syongari#define TD_MSS_SHIFT 18 1286193880Syongari uint64_t addr; 1287193880Syongari}; 1288193880Syongari 1289193880Syongari#endif /* _IF_ALCREG_H */ 1290