if_alc.c revision 213844
1/*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/alc/if_alc.c 213844 2010-10-14 18:31:40Z yongari $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_llc.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58#include <net/if_vlan_var.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/ip.h> 63#include <netinet/tcp.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <machine/atomic.h> 72#include <machine/bus.h> 73#include <machine/in_cksum.h> 74 75#include <dev/alc/if_alcreg.h> 76#include <dev/alc/if_alcvar.h> 77 78/* "device miibus" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80#undef ALC_USE_CUSTOM_CSUM 81 82#ifdef ALC_USE_CUSTOM_CSUM 83#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84#else 85#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86#endif 87 88MODULE_DEPEND(alc, pci, 1, 1, 1); 89MODULE_DEPEND(alc, ether, 1, 1, 1); 90MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92/* Tunables. */ 93static int msi_disable = 0; 94static int msix_disable = 0; 95TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98/* 99 * Devices supported by this driver. 100 */ 101static struct alc_ident alc_ident_table[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 103 "Atheros AR8131 PCIe Gigabit Ethernet" }, 104 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 105 "Atheros AR8132 PCIe Fast Ethernet" }, 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 107 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 109 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 111 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 113 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 114 { 0, 0, 0, NULL} 115}; 116 117static void alc_aspm(struct alc_softc *, int); 118static int alc_attach(device_t); 119static int alc_check_boundary(struct alc_softc *); 120static int alc_detach(device_t); 121static void alc_disable_l0s_l1(struct alc_softc *); 122static int alc_dma_alloc(struct alc_softc *); 123static void alc_dma_free(struct alc_softc *); 124static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 125static int alc_encap(struct alc_softc *, struct mbuf **); 126static struct alc_ident * 127 alc_find_ident(device_t); 128#ifndef __NO_STRICT_ALIGNMENT 129static struct mbuf * 130 alc_fixup_rx(struct ifnet *, struct mbuf *); 131#endif 132static void alc_get_macaddr(struct alc_softc *); 133static void alc_init(void *); 134static void alc_init_cmb(struct alc_softc *); 135static void alc_init_locked(struct alc_softc *); 136static void alc_init_rr_ring(struct alc_softc *); 137static int alc_init_rx_ring(struct alc_softc *); 138static void alc_init_smb(struct alc_softc *); 139static void alc_init_tx_ring(struct alc_softc *); 140static void alc_int_task(void *, int); 141static int alc_intr(void *); 142static int alc_ioctl(struct ifnet *, u_long, caddr_t); 143static void alc_mac_config(struct alc_softc *); 144static int alc_miibus_readreg(device_t, int, int); 145static void alc_miibus_statchg(device_t); 146static int alc_miibus_writereg(device_t, int, int, int); 147static int alc_mediachange(struct ifnet *); 148static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 149static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 150static void alc_phy_down(struct alc_softc *); 151static void alc_phy_reset(struct alc_softc *); 152static int alc_probe(device_t); 153static void alc_reset(struct alc_softc *); 154static int alc_resume(device_t); 155static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 156static int alc_rxintr(struct alc_softc *, int); 157static void alc_rxfilter(struct alc_softc *); 158static void alc_rxvlan(struct alc_softc *); 159static void alc_setlinkspeed(struct alc_softc *); 160static void alc_setwol(struct alc_softc *); 161static int alc_shutdown(device_t); 162static void alc_start(struct ifnet *); 163static void alc_start_queue(struct alc_softc *); 164static void alc_stats_clear(struct alc_softc *); 165static void alc_stats_update(struct alc_softc *); 166static void alc_stop(struct alc_softc *); 167static void alc_stop_mac(struct alc_softc *); 168static void alc_stop_queue(struct alc_softc *); 169static int alc_suspend(device_t); 170static void alc_sysctl_node(struct alc_softc *); 171static void alc_tick(void *); 172static void alc_tx_task(void *, int); 173static void alc_txeof(struct alc_softc *); 174static void alc_watchdog(struct alc_softc *); 175static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 176static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 177static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 178 179static device_method_t alc_methods[] = { 180 /* Device interface. */ 181 DEVMETHOD(device_probe, alc_probe), 182 DEVMETHOD(device_attach, alc_attach), 183 DEVMETHOD(device_detach, alc_detach), 184 DEVMETHOD(device_shutdown, alc_shutdown), 185 DEVMETHOD(device_suspend, alc_suspend), 186 DEVMETHOD(device_resume, alc_resume), 187 188 /* MII interface. */ 189 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 190 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 191 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 192 193 { NULL, NULL } 194}; 195 196static driver_t alc_driver = { 197 "alc", 198 alc_methods, 199 sizeof(struct alc_softc) 200}; 201 202static devclass_t alc_devclass; 203 204DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 205DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 206 207static struct resource_spec alc_res_spec_mem[] = { 208 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 209 { -1, 0, 0 } 210}; 211 212static struct resource_spec alc_irq_spec_legacy[] = { 213 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 214 { -1, 0, 0 } 215}; 216 217static struct resource_spec alc_irq_spec_msi[] = { 218 { SYS_RES_IRQ, 1, RF_ACTIVE }, 219 { -1, 0, 0 } 220}; 221 222static struct resource_spec alc_irq_spec_msix[] = { 223 { SYS_RES_IRQ, 1, RF_ACTIVE }, 224 { -1, 0, 0 } 225}; 226 227static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 228 229static int 230alc_miibus_readreg(device_t dev, int phy, int reg) 231{ 232 struct alc_softc *sc; 233 uint32_t v; 234 int i; 235 236 sc = device_get_softc(dev); 237 238 if (phy != sc->alc_phyaddr) 239 return (0); 240 241 /* 242 * For AR8132 fast ethernet controller, do not report 1000baseT 243 * capability to mii(4). Even though AR8132 uses the same 244 * model/revision number of F1 gigabit PHY, the PHY has no 245 * ability to establish 1000baseT link. 246 */ 247 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 248 reg == MII_EXTSR) 249 return (0); 250 251 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 252 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 253 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 254 DELAY(5); 255 v = CSR_READ_4(sc, ALC_MDIO); 256 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 257 break; 258 } 259 260 if (i == 0) { 261 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 262 return (0); 263 } 264 265 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 266} 267 268static int 269alc_miibus_writereg(device_t dev, int phy, int reg, int val) 270{ 271 struct alc_softc *sc; 272 uint32_t v; 273 int i; 274 275 sc = device_get_softc(dev); 276 277 if (phy != sc->alc_phyaddr) 278 return (0); 279 280 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 281 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 282 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 283 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 284 DELAY(5); 285 v = CSR_READ_4(sc, ALC_MDIO); 286 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 287 break; 288 } 289 290 if (i == 0) 291 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 292 293 return (0); 294} 295 296static void 297alc_miibus_statchg(device_t dev) 298{ 299 struct alc_softc *sc; 300 struct mii_data *mii; 301 struct ifnet *ifp; 302 uint32_t reg; 303 304 sc = device_get_softc(dev); 305 306 mii = device_get_softc(sc->alc_miibus); 307 ifp = sc->alc_ifp; 308 if (mii == NULL || ifp == NULL || 309 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 310 return; 311 312 sc->alc_flags &= ~ALC_FLAG_LINK; 313 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 314 (IFM_ACTIVE | IFM_AVALID)) { 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_10_T: 317 case IFM_100_TX: 318 sc->alc_flags |= ALC_FLAG_LINK; 319 break; 320 case IFM_1000_T: 321 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 322 sc->alc_flags |= ALC_FLAG_LINK; 323 break; 324 default: 325 break; 326 } 327 } 328 alc_stop_queue(sc); 329 /* Stop Rx/Tx MACs. */ 330 alc_stop_mac(sc); 331 332 /* Program MACs with resolved speed/duplex/flow-control. */ 333 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 334 alc_start_queue(sc); 335 alc_mac_config(sc); 336 /* Re-enable Tx/Rx MACs. */ 337 reg = CSR_READ_4(sc, ALC_MAC_CFG); 338 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 339 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 340 } 341 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 342} 343 344static void 345alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 346{ 347 struct alc_softc *sc; 348 struct mii_data *mii; 349 350 sc = ifp->if_softc; 351 ALC_LOCK(sc); 352 if ((ifp->if_flags & IFF_UP) == 0) { 353 ALC_UNLOCK(sc); 354 return; 355 } 356 mii = device_get_softc(sc->alc_miibus); 357 358 mii_pollstat(mii); 359 ALC_UNLOCK(sc); 360 ifmr->ifm_status = mii->mii_media_status; 361 ifmr->ifm_active = mii->mii_media_active; 362} 363 364static int 365alc_mediachange(struct ifnet *ifp) 366{ 367 struct alc_softc *sc; 368 struct mii_data *mii; 369 struct mii_softc *miisc; 370 int error; 371 372 sc = ifp->if_softc; 373 ALC_LOCK(sc); 374 mii = device_get_softc(sc->alc_miibus); 375 if (mii->mii_instance != 0) { 376 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 377 mii_phy_reset(miisc); 378 } 379 error = mii_mediachg(mii); 380 ALC_UNLOCK(sc); 381 382 return (error); 383} 384 385static struct alc_ident * 386alc_find_ident(device_t dev) 387{ 388 struct alc_ident *ident; 389 uint16_t vendor, devid; 390 391 vendor = pci_get_vendor(dev); 392 devid = pci_get_device(dev); 393 for (ident = alc_ident_table; ident->name != NULL; ident++) { 394 if (vendor == ident->vendorid && devid == ident->deviceid) 395 return (ident); 396 } 397 398 return (NULL); 399} 400 401static int 402alc_probe(device_t dev) 403{ 404 struct alc_ident *ident; 405 406 ident = alc_find_ident(dev); 407 if (ident != NULL) { 408 device_set_desc(dev, ident->name); 409 return (BUS_PROBE_DEFAULT); 410 } 411 412 return (ENXIO); 413} 414 415static void 416alc_get_macaddr(struct alc_softc *sc) 417{ 418 uint32_t ea[2], opt; 419 uint16_t val; 420 int eeprom, i; 421 422 eeprom = 0; 423 opt = CSR_READ_4(sc, ALC_OPT_CFG); 424 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 425 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 426 /* 427 * EEPROM found, let TWSI reload EEPROM configuration. 428 * This will set ethernet address of controller. 429 */ 430 eeprom++; 431 switch (sc->alc_ident->deviceid) { 432 case DEVICEID_ATHEROS_AR8131: 433 case DEVICEID_ATHEROS_AR8132: 434 if ((opt & OPT_CFG_CLK_ENB) == 0) { 435 opt |= OPT_CFG_CLK_ENB; 436 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 437 CSR_READ_4(sc, ALC_OPT_CFG); 438 DELAY(1000); 439 } 440 break; 441 case DEVICEID_ATHEROS_AR8151: 442 case DEVICEID_ATHEROS_AR8151_V2: 443 case DEVICEID_ATHEROS_AR8152_B: 444 case DEVICEID_ATHEROS_AR8152_B2: 445 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 446 ALC_MII_DBG_ADDR, 0x00); 447 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 448 ALC_MII_DBG_DATA); 449 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 450 ALC_MII_DBG_DATA, val & 0xFF7F); 451 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 452 ALC_MII_DBG_ADDR, 0x3B); 453 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 454 ALC_MII_DBG_DATA); 455 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 456 ALC_MII_DBG_DATA, val | 0x0008); 457 DELAY(20); 458 break; 459 } 460 461 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 462 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 463 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 464 CSR_READ_4(sc, ALC_WOL_CFG); 465 466 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 467 TWSI_CFG_SW_LD_START); 468 for (i = 100; i > 0; i--) { 469 DELAY(1000); 470 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 471 TWSI_CFG_SW_LD_START) == 0) 472 break; 473 } 474 if (i == 0) 475 device_printf(sc->alc_dev, 476 "reloading EEPROM timeout!\n"); 477 } else { 478 if (bootverbose) 479 device_printf(sc->alc_dev, "EEPROM not found!\n"); 480 } 481 if (eeprom != 0) { 482 switch (sc->alc_ident->deviceid) { 483 case DEVICEID_ATHEROS_AR8131: 484 case DEVICEID_ATHEROS_AR8132: 485 if ((opt & OPT_CFG_CLK_ENB) != 0) { 486 opt &= ~OPT_CFG_CLK_ENB; 487 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 488 CSR_READ_4(sc, ALC_OPT_CFG); 489 DELAY(1000); 490 } 491 break; 492 case DEVICEID_ATHEROS_AR8151: 493 case DEVICEID_ATHEROS_AR8151_V2: 494 case DEVICEID_ATHEROS_AR8152_B: 495 case DEVICEID_ATHEROS_AR8152_B2: 496 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 497 ALC_MII_DBG_ADDR, 0x00); 498 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 499 ALC_MII_DBG_DATA); 500 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 501 ALC_MII_DBG_DATA, val | 0x0080); 502 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 503 ALC_MII_DBG_ADDR, 0x3B); 504 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 505 ALC_MII_DBG_DATA); 506 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 507 ALC_MII_DBG_DATA, val & 0xFFF7); 508 DELAY(20); 509 break; 510 } 511 } 512 513 ea[0] = CSR_READ_4(sc, ALC_PAR0); 514 ea[1] = CSR_READ_4(sc, ALC_PAR1); 515 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 516 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 517 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 518 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 519 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 520 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 521} 522 523static void 524alc_disable_l0s_l1(struct alc_softc *sc) 525{ 526 uint32_t pmcfg; 527 528 /* Another magic from vendor. */ 529 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 530 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 531 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 532 PM_CFG_SERDES_PD_EX_L1); 533 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 534 PM_CFG_SERDES_L1_ENB; 535 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 536} 537 538static void 539alc_phy_reset(struct alc_softc *sc) 540{ 541 uint16_t data; 542 543 /* Reset magic from Linux. */ 544 CSR_WRITE_2(sc, ALC_GPHY_CFG, 545 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 546 CSR_READ_2(sc, ALC_GPHY_CFG); 547 DELAY(10 * 1000); 548 549 CSR_WRITE_2(sc, ALC_GPHY_CFG, 550 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 551 GPHY_CFG_SEL_ANA_RESET); 552 CSR_READ_2(sc, ALC_GPHY_CFG); 553 DELAY(10 * 1000); 554 555 /* DSP fixup, Vendor magic. */ 556 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 557 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 558 ALC_MII_DBG_ADDR, 0x000A); 559 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 560 ALC_MII_DBG_DATA); 561 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 562 ALC_MII_DBG_DATA, data & 0xDFFF); 563 } 564 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 565 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 566 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 567 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 568 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 569 ALC_MII_DBG_ADDR, 0x003B); 570 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 571 ALC_MII_DBG_DATA); 572 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 573 ALC_MII_DBG_DATA, data & 0xFFF7); 574 DELAY(20 * 1000); 575 } 576 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 577 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 578 ALC_MII_DBG_ADDR, 0x0029); 579 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 580 ALC_MII_DBG_DATA, 0x929D); 581 } 582 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 583 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 584 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 585 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 586 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 587 ALC_MII_DBG_ADDR, 0x0029); 588 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 589 ALC_MII_DBG_DATA, 0xB6DD); 590 } 591 592 /* Load DSP codes, vendor magic. */ 593 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 594 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 595 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 596 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 597 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 598 ALC_MII_DBG_DATA, data); 599 600 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 601 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 602 ANA_SERDES_EN_LCKDT; 603 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 604 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 605 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 606 ALC_MII_DBG_DATA, data); 607 608 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 609 ANA_LONG_CABLE_TH_100_MASK) | 610 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 611 ANA_SHORT_CABLE_TH_100_SHIFT) | 612 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 613 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 614 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_DATA, data); 617 618 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 619 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 620 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 621 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 622 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 623 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 624 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 625 ALC_MII_DBG_DATA, data); 626 627 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 628 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 629 ANA_OEN_125M; 630 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 631 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 632 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 633 ALC_MII_DBG_DATA, data); 634 DELAY(1000); 635} 636 637static void 638alc_phy_down(struct alc_softc *sc) 639{ 640 641 switch (sc->alc_ident->deviceid) { 642 case DEVICEID_ATHEROS_AR8151: 643 case DEVICEID_ATHEROS_AR8151_V2: 644 /* 645 * GPHY power down caused more problems on AR8151 v2.0. 646 * When driver is reloaded after GPHY power down, 647 * accesses to PHY/MAC registers hung the system. Only 648 * cold boot recovered from it. I'm not sure whether 649 * AR8151 v1.0 also requires this one though. I don't 650 * have AR8151 v1.0 controller in hand. 651 * The only option left is to isolate the PHY and 652 * initiates power down the PHY which in turn saves 653 * more power when driver is unloaded. 654 */ 655 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 656 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 657 break; 658 default: 659 /* Force PHY down. */ 660 CSR_WRITE_2(sc, ALC_GPHY_CFG, 661 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 662 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 663 GPHY_CFG_PWDOWN_HW); 664 DELAY(1000); 665 break; 666 } 667} 668 669static void 670alc_aspm(struct alc_softc *sc, int media) 671{ 672 uint32_t pmcfg; 673 uint16_t linkcfg; 674 675 ALC_LOCK_ASSERT(sc); 676 677 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 678 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 679 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 680 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 681 PCIR_EXPRESS_LINK_CTL); 682 else 683 linkcfg = 0; 684 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 685 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 686 pmcfg |= PM_CFG_MAC_ASPM_CHK; 687 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 688 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 689 690 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 691 /* Disable extended sync except AR8152 B v1.0 */ 692 linkcfg &= ~0x80; 693 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 694 sc->alc_rev == ATHEROS_AR8152_B_V10) 695 linkcfg |= 0x80; 696 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 697 linkcfg); 698 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 699 PM_CFG_HOTRST); 700 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 701 PM_CFG_L1_ENTRY_TIMER_SHIFT); 702 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 703 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 704 PM_CFG_PM_REQ_TIMER_SHIFT); 705 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 706 } 707 708 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 709 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 710 pmcfg |= PM_CFG_ASPM_L0S_ENB; 711 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 712 pmcfg |= PM_CFG_ASPM_L1_ENB; 713 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 714 if (sc->alc_ident->deviceid == 715 DEVICEID_ATHEROS_AR8152_B) 716 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 717 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 718 PM_CFG_SERDES_PLL_L1_ENB | 719 PM_CFG_SERDES_BUDS_RX_L1_ENB); 720 pmcfg |= PM_CFG_CLK_SWH_L1; 721 if (media == IFM_100_TX || media == IFM_1000_T) { 722 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 723 switch (sc->alc_ident->deviceid) { 724 case DEVICEID_ATHEROS_AR8152_B: 725 pmcfg |= (7 << 726 PM_CFG_L1_ENTRY_TIMER_SHIFT); 727 break; 728 case DEVICEID_ATHEROS_AR8152_B2: 729 case DEVICEID_ATHEROS_AR8151_V2: 730 pmcfg |= (4 << 731 PM_CFG_L1_ENTRY_TIMER_SHIFT); 732 break; 733 default: 734 pmcfg |= (15 << 735 PM_CFG_L1_ENTRY_TIMER_SHIFT); 736 break; 737 } 738 } 739 } else { 740 pmcfg |= PM_CFG_SERDES_L1_ENB | 741 PM_CFG_SERDES_PLL_L1_ENB | 742 PM_CFG_SERDES_BUDS_RX_L1_ENB; 743 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 744 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 745 } 746 } else { 747 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 748 PM_CFG_SERDES_PLL_L1_ENB); 749 pmcfg |= PM_CFG_CLK_SWH_L1; 750 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 751 pmcfg |= PM_CFG_ASPM_L1_ENB; 752 } 753 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 754} 755 756static int 757alc_attach(device_t dev) 758{ 759 struct alc_softc *sc; 760 struct ifnet *ifp; 761 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 762 uint16_t burst; 763 int base, error, i, msic, msixc, state; 764 uint32_t cap, ctl, val; 765 766 error = 0; 767 sc = device_get_softc(dev); 768 sc->alc_dev = dev; 769 770 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 771 MTX_DEF); 772 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 773 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 774 sc->alc_ident = alc_find_ident(dev); 775 776 /* Map the device. */ 777 pci_enable_busmaster(dev); 778 sc->alc_res_spec = alc_res_spec_mem; 779 sc->alc_irq_spec = alc_irq_spec_legacy; 780 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 781 if (error != 0) { 782 device_printf(dev, "cannot allocate memory resources.\n"); 783 goto fail; 784 } 785 786 /* Set PHY address. */ 787 sc->alc_phyaddr = ALC_PHY_ADDR; 788 789 /* Initialize DMA parameters. */ 790 sc->alc_dma_rd_burst = 0; 791 sc->alc_dma_wr_burst = 0; 792 sc->alc_rcb = DMA_CFG_RCB_64; 793 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 794 sc->alc_flags |= ALC_FLAG_PCIE; 795 sc->alc_expcap = base; 796 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 797 sc->alc_dma_rd_burst = 798 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 799 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 800 if (bootverbose) { 801 device_printf(dev, "Read request size : %u bytes.\n", 802 alc_dma_burst[sc->alc_dma_rd_burst]); 803 device_printf(dev, "TLP payload size : %u bytes.\n", 804 alc_dma_burst[sc->alc_dma_wr_burst]); 805 } 806 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 807 sc->alc_dma_rd_burst = 3; 808 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 809 sc->alc_dma_wr_burst = 3; 810 /* Clear data link and flow-control protocol error. */ 811 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 812 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 813 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 814 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 815 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 816 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 817 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 818 PCIE_PHYMISC_FORCE_RCV_DET); 819 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 820 sc->alc_rev == ATHEROS_AR8152_B_V10) { 821 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 822 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 823 PCIE_PHYMISC2_SERDES_TH_MASK); 824 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 825 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 826 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 827 } 828 /* Disable ASPM L0S and L1. */ 829 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 830 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 831 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 832 if ((ctl & 0x08) != 0) 833 sc->alc_rcb = DMA_CFG_RCB_128; 834 if (bootverbose) 835 device_printf(dev, "RCB %u bytes\n", 836 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 837 state = ctl & 0x03; 838 if (state & 0x01) 839 sc->alc_flags |= ALC_FLAG_L0S; 840 if (state & 0x02) 841 sc->alc_flags |= ALC_FLAG_L1S; 842 if (bootverbose) 843 device_printf(sc->alc_dev, "ASPM %s %s\n", 844 aspm_state[state], 845 state == 0 ? "disabled" : "enabled"); 846 alc_disable_l0s_l1(sc); 847 } else { 848 if (bootverbose) 849 device_printf(sc->alc_dev, 850 "no ASPM support\n"); 851 } 852 } 853 854 /* Reset PHY. */ 855 alc_phy_reset(sc); 856 857 /* Reset the ethernet controller. */ 858 alc_reset(sc); 859 860 /* 861 * One odd thing is AR8132 uses the same PHY hardware(F1 862 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 863 * the PHY supports 1000Mbps but that's not true. The PHY 864 * used in AR8132 can't establish gigabit link even if it 865 * shows the same PHY model/revision number of AR8131. 866 */ 867 switch (sc->alc_ident->deviceid) { 868 case DEVICEID_ATHEROS_AR8152_B: 869 case DEVICEID_ATHEROS_AR8152_B2: 870 sc->alc_flags |= ALC_FLAG_APS; 871 /* FALLTHROUGH */ 872 case DEVICEID_ATHEROS_AR8132: 873 sc->alc_flags |= ALC_FLAG_FASTETHER; 874 break; 875 case DEVICEID_ATHEROS_AR8151: 876 case DEVICEID_ATHEROS_AR8151_V2: 877 sc->alc_flags |= ALC_FLAG_APS; 878 /* FALLTHROUGH */ 879 default: 880 break; 881 } 882 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 883 884 /* 885 * It seems that AR813x/AR815x has silicon bug for SMB. In 886 * addition, Atheros said that enabling SMB wouldn't improve 887 * performance. However I think it's bad to access lots of 888 * registers to extract MAC statistics. 889 */ 890 sc->alc_flags |= ALC_FLAG_SMB_BUG; 891 /* 892 * Don't use Tx CMB. It is known to have silicon bug. 893 */ 894 sc->alc_flags |= ALC_FLAG_CMB_BUG; 895 sc->alc_rev = pci_get_revid(dev); 896 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 897 MASTER_CHIP_REV_SHIFT; 898 if (bootverbose) { 899 device_printf(dev, "PCI device revision : 0x%04x\n", 900 sc->alc_rev); 901 device_printf(dev, "Chip id/revision : 0x%04x\n", 902 sc->alc_chip_rev); 903 } 904 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 905 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 906 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 907 908 /* Allocate IRQ resources. */ 909 msixc = pci_msix_count(dev); 910 msic = pci_msi_count(dev); 911 if (bootverbose) { 912 device_printf(dev, "MSIX count : %d\n", msixc); 913 device_printf(dev, "MSI count : %d\n", msic); 914 } 915 /* Prefer MSIX over MSI. */ 916 if (msix_disable == 0 || msi_disable == 0) { 917 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 918 pci_alloc_msix(dev, &msixc) == 0) { 919 if (msic == ALC_MSIX_MESSAGES) { 920 device_printf(dev, 921 "Using %d MSIX message(s).\n", msixc); 922 sc->alc_flags |= ALC_FLAG_MSIX; 923 sc->alc_irq_spec = alc_irq_spec_msix; 924 } else 925 pci_release_msi(dev); 926 } 927 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 928 msic == ALC_MSI_MESSAGES && 929 pci_alloc_msi(dev, &msic) == 0) { 930 if (msic == ALC_MSI_MESSAGES) { 931 device_printf(dev, 932 "Using %d MSI message(s).\n", msic); 933 sc->alc_flags |= ALC_FLAG_MSI; 934 sc->alc_irq_spec = alc_irq_spec_msi; 935 } else 936 pci_release_msi(dev); 937 } 938 } 939 940 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 941 if (error != 0) { 942 device_printf(dev, "cannot allocate IRQ resources.\n"); 943 goto fail; 944 } 945 946 /* Create device sysctl node. */ 947 alc_sysctl_node(sc); 948 949 if ((error = alc_dma_alloc(sc) != 0)) 950 goto fail; 951 952 /* Load station address. */ 953 alc_get_macaddr(sc); 954 955 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 956 if (ifp == NULL) { 957 device_printf(dev, "cannot allocate ifnet structure.\n"); 958 error = ENXIO; 959 goto fail; 960 } 961 962 ifp->if_softc = sc; 963 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 964 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 965 ifp->if_ioctl = alc_ioctl; 966 ifp->if_start = alc_start; 967 ifp->if_init = alc_init; 968 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 969 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 970 IFQ_SET_READY(&ifp->if_snd); 971 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 972 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 973 if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) { 974 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 975 sc->alc_flags |= ALC_FLAG_PM; 976 sc->alc_pmcap = base; 977 } 978 ifp->if_capenable = ifp->if_capabilities; 979 980 /* Set up MII bus. */ 981 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 982 alc_mediastatus)) != 0) { 983 device_printf(dev, "no PHY found!\n"); 984 goto fail; 985 } 986 987 ether_ifattach(ifp, sc->alc_eaddr); 988 989 /* VLAN capability setup. */ 990 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 991 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 992 ifp->if_capenable = ifp->if_capabilities; 993 /* 994 * XXX 995 * It seems enabling Tx checksum offloading makes more trouble. 996 * Sometimes the controller does not receive any frames when 997 * Tx checksum offloading is enabled. I'm not sure whether this 998 * is a bug in Tx checksum offloading logic or I got broken 999 * sample boards. To safety, don't enable Tx checksum offloading 1000 * by default but give chance to users to toggle it if they know 1001 * their controllers work without problems. 1002 */ 1003 ifp->if_capenable &= ~IFCAP_TXCSUM; 1004 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1005 1006 /* Tell the upper layer(s) we support long frames. */ 1007 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1008 1009 /* Create local taskq. */ 1010 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1011 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1012 taskqueue_thread_enqueue, &sc->alc_tq); 1013 if (sc->alc_tq == NULL) { 1014 device_printf(dev, "could not create taskqueue.\n"); 1015 ether_ifdetach(ifp); 1016 error = ENXIO; 1017 goto fail; 1018 } 1019 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1020 device_get_nameunit(sc->alc_dev)); 1021 1022 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1023 msic = ALC_MSIX_MESSAGES; 1024 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1025 msic = ALC_MSI_MESSAGES; 1026 else 1027 msic = 1; 1028 for (i = 0; i < msic; i++) { 1029 error = bus_setup_intr(dev, sc->alc_irq[i], 1030 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1031 &sc->alc_intrhand[i]); 1032 if (error != 0) 1033 break; 1034 } 1035 if (error != 0) { 1036 device_printf(dev, "could not set up interrupt handler.\n"); 1037 taskqueue_free(sc->alc_tq); 1038 sc->alc_tq = NULL; 1039 ether_ifdetach(ifp); 1040 goto fail; 1041 } 1042 1043fail: 1044 if (error != 0) 1045 alc_detach(dev); 1046 1047 return (error); 1048} 1049 1050static int 1051alc_detach(device_t dev) 1052{ 1053 struct alc_softc *sc; 1054 struct ifnet *ifp; 1055 int i, msic; 1056 1057 sc = device_get_softc(dev); 1058 1059 ifp = sc->alc_ifp; 1060 if (device_is_attached(dev)) { 1061 ALC_LOCK(sc); 1062 sc->alc_flags |= ALC_FLAG_DETACH; 1063 alc_stop(sc); 1064 ALC_UNLOCK(sc); 1065 callout_drain(&sc->alc_tick_ch); 1066 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1067 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1068 ether_ifdetach(ifp); 1069 } 1070 1071 if (sc->alc_tq != NULL) { 1072 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1073 taskqueue_free(sc->alc_tq); 1074 sc->alc_tq = NULL; 1075 } 1076 1077 if (sc->alc_miibus != NULL) { 1078 device_delete_child(dev, sc->alc_miibus); 1079 sc->alc_miibus = NULL; 1080 } 1081 bus_generic_detach(dev); 1082 alc_dma_free(sc); 1083 1084 if (ifp != NULL) { 1085 if_free(ifp); 1086 sc->alc_ifp = NULL; 1087 } 1088 1089 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1090 msic = ALC_MSIX_MESSAGES; 1091 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1092 msic = ALC_MSI_MESSAGES; 1093 else 1094 msic = 1; 1095 for (i = 0; i < msic; i++) { 1096 if (sc->alc_intrhand[i] != NULL) { 1097 bus_teardown_intr(dev, sc->alc_irq[i], 1098 sc->alc_intrhand[i]); 1099 sc->alc_intrhand[i] = NULL; 1100 } 1101 } 1102 if (sc->alc_res[0] != NULL) 1103 alc_phy_down(sc); 1104 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1105 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1106 pci_release_msi(dev); 1107 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1108 mtx_destroy(&sc->alc_mtx); 1109 1110 return (0); 1111} 1112 1113#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1114 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1115#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1116 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1117 1118static void 1119alc_sysctl_node(struct alc_softc *sc) 1120{ 1121 struct sysctl_ctx_list *ctx; 1122 struct sysctl_oid_list *child, *parent; 1123 struct sysctl_oid *tree; 1124 struct alc_hw_stats *stats; 1125 int error; 1126 1127 stats = &sc->alc_stats; 1128 ctx = device_get_sysctl_ctx(sc->alc_dev); 1129 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1130 1131 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1132 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1133 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1134 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1135 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1136 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1137 /* Pull in device tunables. */ 1138 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1139 error = resource_int_value(device_get_name(sc->alc_dev), 1140 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1141 if (error == 0) { 1142 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1143 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1144 device_printf(sc->alc_dev, "int_rx_mod value out of " 1145 "range; using default: %d\n", 1146 ALC_IM_RX_TIMER_DEFAULT); 1147 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1148 } 1149 } 1150 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1151 error = resource_int_value(device_get_name(sc->alc_dev), 1152 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1153 if (error == 0) { 1154 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1155 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1156 device_printf(sc->alc_dev, "int_tx_mod value out of " 1157 "range; using default: %d\n", 1158 ALC_IM_TX_TIMER_DEFAULT); 1159 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1160 } 1161 } 1162 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1163 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1164 sysctl_hw_alc_proc_limit, "I", 1165 "max number of Rx events to process"); 1166 /* Pull in device tunables. */ 1167 sc->alc_process_limit = ALC_PROC_DEFAULT; 1168 error = resource_int_value(device_get_name(sc->alc_dev), 1169 device_get_unit(sc->alc_dev), "process_limit", 1170 &sc->alc_process_limit); 1171 if (error == 0) { 1172 if (sc->alc_process_limit < ALC_PROC_MIN || 1173 sc->alc_process_limit > ALC_PROC_MAX) { 1174 device_printf(sc->alc_dev, 1175 "process_limit value out of range; " 1176 "using default: %d\n", ALC_PROC_DEFAULT); 1177 sc->alc_process_limit = ALC_PROC_DEFAULT; 1178 } 1179 } 1180 1181 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1182 NULL, "ALC statistics"); 1183 parent = SYSCTL_CHILDREN(tree); 1184 1185 /* Rx statistics. */ 1186 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1187 NULL, "Rx MAC statistics"); 1188 child = SYSCTL_CHILDREN(tree); 1189 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1190 &stats->rx_frames, "Good frames"); 1191 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1192 &stats->rx_bcast_frames, "Good broadcast frames"); 1193 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1194 &stats->rx_mcast_frames, "Good multicast frames"); 1195 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1196 &stats->rx_pause_frames, "Pause control frames"); 1197 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1198 &stats->rx_control_frames, "Control frames"); 1199 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1200 &stats->rx_crcerrs, "CRC errors"); 1201 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1202 &stats->rx_lenerrs, "Frames with length mismatched"); 1203 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1204 &stats->rx_bytes, "Good octets"); 1205 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1206 &stats->rx_bcast_bytes, "Good broadcast octets"); 1207 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1208 &stats->rx_mcast_bytes, "Good multicast octets"); 1209 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1210 &stats->rx_runts, "Too short frames"); 1211 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1212 &stats->rx_fragments, "Fragmented frames"); 1213 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1214 &stats->rx_pkts_64, "64 bytes frames"); 1215 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1216 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1217 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1218 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1219 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1220 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1221 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1222 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1223 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1224 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1225 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1226 &stats->rx_pkts_1519_max, "1519 to max frames"); 1227 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1228 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1229 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1230 &stats->rx_fifo_oflows, "FIFO overflows"); 1231 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1232 &stats->rx_rrs_errs, "Return status write-back errors"); 1233 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1234 &stats->rx_alignerrs, "Alignment errors"); 1235 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1236 &stats->rx_pkts_filtered, 1237 "Frames dropped due to address filtering"); 1238 1239 /* Tx statistics. */ 1240 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1241 NULL, "Tx MAC statistics"); 1242 child = SYSCTL_CHILDREN(tree); 1243 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1244 &stats->tx_frames, "Good frames"); 1245 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1246 &stats->tx_bcast_frames, "Good broadcast frames"); 1247 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1248 &stats->tx_mcast_frames, "Good multicast frames"); 1249 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1250 &stats->tx_pause_frames, "Pause control frames"); 1251 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1252 &stats->tx_control_frames, "Control frames"); 1253 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1254 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1255 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1256 &stats->tx_excess_defer, "Frames with derferrals"); 1257 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1258 &stats->tx_bytes, "Good octets"); 1259 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1260 &stats->tx_bcast_bytes, "Good broadcast octets"); 1261 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1262 &stats->tx_mcast_bytes, "Good multicast octets"); 1263 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1264 &stats->tx_pkts_64, "64 bytes frames"); 1265 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1266 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1267 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1268 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1269 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1270 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1271 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1272 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1273 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1274 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1275 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1276 &stats->tx_pkts_1519_max, "1519 to max frames"); 1277 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1278 &stats->tx_single_colls, "Single collisions"); 1279 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1280 &stats->tx_multi_colls, "Multiple collisions"); 1281 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1282 &stats->tx_late_colls, "Late collisions"); 1283 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1284 &stats->tx_excess_colls, "Excessive collisions"); 1285 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1286 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1287 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1288 &stats->tx_underrun, "FIFO underruns"); 1289 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1290 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1291 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1292 &stats->tx_lenerrs, "Frames with length mismatched"); 1293 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1294 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1295} 1296 1297#undef ALC_SYSCTL_STAT_ADD32 1298#undef ALC_SYSCTL_STAT_ADD64 1299 1300struct alc_dmamap_arg { 1301 bus_addr_t alc_busaddr; 1302}; 1303 1304static void 1305alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1306{ 1307 struct alc_dmamap_arg *ctx; 1308 1309 if (error != 0) 1310 return; 1311 1312 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1313 1314 ctx = (struct alc_dmamap_arg *)arg; 1315 ctx->alc_busaddr = segs[0].ds_addr; 1316} 1317 1318/* 1319 * Normal and high Tx descriptors shares single Tx high address. 1320 * Four Rx descriptor/return rings and CMB shares the same Rx 1321 * high address. 1322 */ 1323static int 1324alc_check_boundary(struct alc_softc *sc) 1325{ 1326 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1327 1328 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1329 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1330 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1331 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1332 1333 /* 4GB boundary crossing is not allowed. */ 1334 if ((ALC_ADDR_HI(rx_ring_end) != 1335 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1336 (ALC_ADDR_HI(rr_ring_end) != 1337 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1338 (ALC_ADDR_HI(cmb_end) != 1339 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1340 (ALC_ADDR_HI(tx_ring_end) != 1341 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1342 return (EFBIG); 1343 /* 1344 * Make sure Rx return descriptor/Rx descriptor/CMB use 1345 * the same high address. 1346 */ 1347 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1348 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1349 return (EFBIG); 1350 1351 return (0); 1352} 1353 1354static int 1355alc_dma_alloc(struct alc_softc *sc) 1356{ 1357 struct alc_txdesc *txd; 1358 struct alc_rxdesc *rxd; 1359 bus_addr_t lowaddr; 1360 struct alc_dmamap_arg ctx; 1361 int error, i; 1362 1363 lowaddr = BUS_SPACE_MAXADDR; 1364again: 1365 /* Create parent DMA tag. */ 1366 error = bus_dma_tag_create( 1367 bus_get_dma_tag(sc->alc_dev), /* parent */ 1368 1, 0, /* alignment, boundary */ 1369 lowaddr, /* lowaddr */ 1370 BUS_SPACE_MAXADDR, /* highaddr */ 1371 NULL, NULL, /* filter, filterarg */ 1372 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1373 0, /* nsegments */ 1374 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1375 0, /* flags */ 1376 NULL, NULL, /* lockfunc, lockarg */ 1377 &sc->alc_cdata.alc_parent_tag); 1378 if (error != 0) { 1379 device_printf(sc->alc_dev, 1380 "could not create parent DMA tag.\n"); 1381 goto fail; 1382 } 1383 1384 /* Create DMA tag for Tx descriptor ring. */ 1385 error = bus_dma_tag_create( 1386 sc->alc_cdata.alc_parent_tag, /* parent */ 1387 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1388 BUS_SPACE_MAXADDR, /* lowaddr */ 1389 BUS_SPACE_MAXADDR, /* highaddr */ 1390 NULL, NULL, /* filter, filterarg */ 1391 ALC_TX_RING_SZ, /* maxsize */ 1392 1, /* nsegments */ 1393 ALC_TX_RING_SZ, /* maxsegsize */ 1394 0, /* flags */ 1395 NULL, NULL, /* lockfunc, lockarg */ 1396 &sc->alc_cdata.alc_tx_ring_tag); 1397 if (error != 0) { 1398 device_printf(sc->alc_dev, 1399 "could not create Tx ring DMA tag.\n"); 1400 goto fail; 1401 } 1402 1403 /* Create DMA tag for Rx free descriptor ring. */ 1404 error = bus_dma_tag_create( 1405 sc->alc_cdata.alc_parent_tag, /* parent */ 1406 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1407 BUS_SPACE_MAXADDR, /* lowaddr */ 1408 BUS_SPACE_MAXADDR, /* highaddr */ 1409 NULL, NULL, /* filter, filterarg */ 1410 ALC_RX_RING_SZ, /* maxsize */ 1411 1, /* nsegments */ 1412 ALC_RX_RING_SZ, /* maxsegsize */ 1413 0, /* flags */ 1414 NULL, NULL, /* lockfunc, lockarg */ 1415 &sc->alc_cdata.alc_rx_ring_tag); 1416 if (error != 0) { 1417 device_printf(sc->alc_dev, 1418 "could not create Rx ring DMA tag.\n"); 1419 goto fail; 1420 } 1421 /* Create DMA tag for Rx return descriptor ring. */ 1422 error = bus_dma_tag_create( 1423 sc->alc_cdata.alc_parent_tag, /* parent */ 1424 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1425 BUS_SPACE_MAXADDR, /* lowaddr */ 1426 BUS_SPACE_MAXADDR, /* highaddr */ 1427 NULL, NULL, /* filter, filterarg */ 1428 ALC_RR_RING_SZ, /* maxsize */ 1429 1, /* nsegments */ 1430 ALC_RR_RING_SZ, /* maxsegsize */ 1431 0, /* flags */ 1432 NULL, NULL, /* lockfunc, lockarg */ 1433 &sc->alc_cdata.alc_rr_ring_tag); 1434 if (error != 0) { 1435 device_printf(sc->alc_dev, 1436 "could not create Rx return ring DMA tag.\n"); 1437 goto fail; 1438 } 1439 1440 /* Create DMA tag for coalescing message block. */ 1441 error = bus_dma_tag_create( 1442 sc->alc_cdata.alc_parent_tag, /* parent */ 1443 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1444 BUS_SPACE_MAXADDR, /* lowaddr */ 1445 BUS_SPACE_MAXADDR, /* highaddr */ 1446 NULL, NULL, /* filter, filterarg */ 1447 ALC_CMB_SZ, /* maxsize */ 1448 1, /* nsegments */ 1449 ALC_CMB_SZ, /* maxsegsize */ 1450 0, /* flags */ 1451 NULL, NULL, /* lockfunc, lockarg */ 1452 &sc->alc_cdata.alc_cmb_tag); 1453 if (error != 0) { 1454 device_printf(sc->alc_dev, 1455 "could not create CMB DMA tag.\n"); 1456 goto fail; 1457 } 1458 /* Create DMA tag for status message block. */ 1459 error = bus_dma_tag_create( 1460 sc->alc_cdata.alc_parent_tag, /* parent */ 1461 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1462 BUS_SPACE_MAXADDR, /* lowaddr */ 1463 BUS_SPACE_MAXADDR, /* highaddr */ 1464 NULL, NULL, /* filter, filterarg */ 1465 ALC_SMB_SZ, /* maxsize */ 1466 1, /* nsegments */ 1467 ALC_SMB_SZ, /* maxsegsize */ 1468 0, /* flags */ 1469 NULL, NULL, /* lockfunc, lockarg */ 1470 &sc->alc_cdata.alc_smb_tag); 1471 if (error != 0) { 1472 device_printf(sc->alc_dev, 1473 "could not create SMB DMA tag.\n"); 1474 goto fail; 1475 } 1476 1477 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1478 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1479 (void **)&sc->alc_rdata.alc_tx_ring, 1480 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1481 &sc->alc_cdata.alc_tx_ring_map); 1482 if (error != 0) { 1483 device_printf(sc->alc_dev, 1484 "could not allocate DMA'able memory for Tx ring.\n"); 1485 goto fail; 1486 } 1487 ctx.alc_busaddr = 0; 1488 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1489 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1490 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1491 if (error != 0 || ctx.alc_busaddr == 0) { 1492 device_printf(sc->alc_dev, 1493 "could not load DMA'able memory for Tx ring.\n"); 1494 goto fail; 1495 } 1496 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1497 1498 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1499 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1500 (void **)&sc->alc_rdata.alc_rx_ring, 1501 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1502 &sc->alc_cdata.alc_rx_ring_map); 1503 if (error != 0) { 1504 device_printf(sc->alc_dev, 1505 "could not allocate DMA'able memory for Rx ring.\n"); 1506 goto fail; 1507 } 1508 ctx.alc_busaddr = 0; 1509 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1510 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1511 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1512 if (error != 0 || ctx.alc_busaddr == 0) { 1513 device_printf(sc->alc_dev, 1514 "could not load DMA'able memory for Rx ring.\n"); 1515 goto fail; 1516 } 1517 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1518 1519 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1520 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1521 (void **)&sc->alc_rdata.alc_rr_ring, 1522 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1523 &sc->alc_cdata.alc_rr_ring_map); 1524 if (error != 0) { 1525 device_printf(sc->alc_dev, 1526 "could not allocate DMA'able memory for Rx return ring.\n"); 1527 goto fail; 1528 } 1529 ctx.alc_busaddr = 0; 1530 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1531 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1532 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1533 if (error != 0 || ctx.alc_busaddr == 0) { 1534 device_printf(sc->alc_dev, 1535 "could not load DMA'able memory for Tx ring.\n"); 1536 goto fail; 1537 } 1538 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1539 1540 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1541 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1542 (void **)&sc->alc_rdata.alc_cmb, 1543 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1544 &sc->alc_cdata.alc_cmb_map); 1545 if (error != 0) { 1546 device_printf(sc->alc_dev, 1547 "could not allocate DMA'able memory for CMB.\n"); 1548 goto fail; 1549 } 1550 ctx.alc_busaddr = 0; 1551 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1552 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1553 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1554 if (error != 0 || ctx.alc_busaddr == 0) { 1555 device_printf(sc->alc_dev, 1556 "could not load DMA'able memory for CMB.\n"); 1557 goto fail; 1558 } 1559 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1560 1561 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1562 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1563 (void **)&sc->alc_rdata.alc_smb, 1564 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1565 &sc->alc_cdata.alc_smb_map); 1566 if (error != 0) { 1567 device_printf(sc->alc_dev, 1568 "could not allocate DMA'able memory for SMB.\n"); 1569 goto fail; 1570 } 1571 ctx.alc_busaddr = 0; 1572 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1573 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1574 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1575 if (error != 0 || ctx.alc_busaddr == 0) { 1576 device_printf(sc->alc_dev, 1577 "could not load DMA'able memory for CMB.\n"); 1578 goto fail; 1579 } 1580 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1581 1582 /* Make sure we've not crossed 4GB boundary. */ 1583 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1584 (error = alc_check_boundary(sc)) != 0) { 1585 device_printf(sc->alc_dev, "4GB boundary crossed, " 1586 "switching to 32bit DMA addressing mode.\n"); 1587 alc_dma_free(sc); 1588 /* 1589 * Limit max allowable DMA address space to 32bit 1590 * and try again. 1591 */ 1592 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1593 goto again; 1594 } 1595 1596 /* 1597 * Create Tx buffer parent tag. 1598 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1599 * so it needs separate parent DMA tag as parent DMA address 1600 * space could be restricted to be within 32bit address space 1601 * by 4GB boundary crossing. 1602 */ 1603 error = bus_dma_tag_create( 1604 bus_get_dma_tag(sc->alc_dev), /* parent */ 1605 1, 0, /* alignment, boundary */ 1606 BUS_SPACE_MAXADDR, /* lowaddr */ 1607 BUS_SPACE_MAXADDR, /* highaddr */ 1608 NULL, NULL, /* filter, filterarg */ 1609 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1610 0, /* nsegments */ 1611 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1612 0, /* flags */ 1613 NULL, NULL, /* lockfunc, lockarg */ 1614 &sc->alc_cdata.alc_buffer_tag); 1615 if (error != 0) { 1616 device_printf(sc->alc_dev, 1617 "could not create parent buffer DMA tag.\n"); 1618 goto fail; 1619 } 1620 1621 /* Create DMA tag for Tx buffers. */ 1622 error = bus_dma_tag_create( 1623 sc->alc_cdata.alc_buffer_tag, /* parent */ 1624 1, 0, /* alignment, boundary */ 1625 BUS_SPACE_MAXADDR, /* lowaddr */ 1626 BUS_SPACE_MAXADDR, /* highaddr */ 1627 NULL, NULL, /* filter, filterarg */ 1628 ALC_TSO_MAXSIZE, /* maxsize */ 1629 ALC_MAXTXSEGS, /* nsegments */ 1630 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1631 0, /* flags */ 1632 NULL, NULL, /* lockfunc, lockarg */ 1633 &sc->alc_cdata.alc_tx_tag); 1634 if (error != 0) { 1635 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1636 goto fail; 1637 } 1638 1639 /* Create DMA tag for Rx buffers. */ 1640 error = bus_dma_tag_create( 1641 sc->alc_cdata.alc_buffer_tag, /* parent */ 1642 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1643 BUS_SPACE_MAXADDR, /* lowaddr */ 1644 BUS_SPACE_MAXADDR, /* highaddr */ 1645 NULL, NULL, /* filter, filterarg */ 1646 MCLBYTES, /* maxsize */ 1647 1, /* nsegments */ 1648 MCLBYTES, /* maxsegsize */ 1649 0, /* flags */ 1650 NULL, NULL, /* lockfunc, lockarg */ 1651 &sc->alc_cdata.alc_rx_tag); 1652 if (error != 0) { 1653 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1654 goto fail; 1655 } 1656 /* Create DMA maps for Tx buffers. */ 1657 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1658 txd = &sc->alc_cdata.alc_txdesc[i]; 1659 txd->tx_m = NULL; 1660 txd->tx_dmamap = NULL; 1661 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1662 &txd->tx_dmamap); 1663 if (error != 0) { 1664 device_printf(sc->alc_dev, 1665 "could not create Tx dmamap.\n"); 1666 goto fail; 1667 } 1668 } 1669 /* Create DMA maps for Rx buffers. */ 1670 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1671 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1672 device_printf(sc->alc_dev, 1673 "could not create spare Rx dmamap.\n"); 1674 goto fail; 1675 } 1676 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1677 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1678 rxd->rx_m = NULL; 1679 rxd->rx_dmamap = NULL; 1680 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1681 &rxd->rx_dmamap); 1682 if (error != 0) { 1683 device_printf(sc->alc_dev, 1684 "could not create Rx dmamap.\n"); 1685 goto fail; 1686 } 1687 } 1688 1689fail: 1690 return (error); 1691} 1692 1693static void 1694alc_dma_free(struct alc_softc *sc) 1695{ 1696 struct alc_txdesc *txd; 1697 struct alc_rxdesc *rxd; 1698 int i; 1699 1700 /* Tx buffers. */ 1701 if (sc->alc_cdata.alc_tx_tag != NULL) { 1702 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1703 txd = &sc->alc_cdata.alc_txdesc[i]; 1704 if (txd->tx_dmamap != NULL) { 1705 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1706 txd->tx_dmamap); 1707 txd->tx_dmamap = NULL; 1708 } 1709 } 1710 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1711 sc->alc_cdata.alc_tx_tag = NULL; 1712 } 1713 /* Rx buffers */ 1714 if (sc->alc_cdata.alc_rx_tag != NULL) { 1715 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1716 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1717 if (rxd->rx_dmamap != NULL) { 1718 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1719 rxd->rx_dmamap); 1720 rxd->rx_dmamap = NULL; 1721 } 1722 } 1723 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1724 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1725 sc->alc_cdata.alc_rx_sparemap); 1726 sc->alc_cdata.alc_rx_sparemap = NULL; 1727 } 1728 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1729 sc->alc_cdata.alc_rx_tag = NULL; 1730 } 1731 /* Tx descriptor ring. */ 1732 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1733 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1734 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1735 sc->alc_cdata.alc_tx_ring_map); 1736 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1737 sc->alc_rdata.alc_tx_ring != NULL) 1738 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1739 sc->alc_rdata.alc_tx_ring, 1740 sc->alc_cdata.alc_tx_ring_map); 1741 sc->alc_rdata.alc_tx_ring = NULL; 1742 sc->alc_cdata.alc_tx_ring_map = NULL; 1743 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1744 sc->alc_cdata.alc_tx_ring_tag = NULL; 1745 } 1746 /* Rx ring. */ 1747 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1748 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1749 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1750 sc->alc_cdata.alc_rx_ring_map); 1751 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1752 sc->alc_rdata.alc_rx_ring != NULL) 1753 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1754 sc->alc_rdata.alc_rx_ring, 1755 sc->alc_cdata.alc_rx_ring_map); 1756 sc->alc_rdata.alc_rx_ring = NULL; 1757 sc->alc_cdata.alc_rx_ring_map = NULL; 1758 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1759 sc->alc_cdata.alc_rx_ring_tag = NULL; 1760 } 1761 /* Rx return ring. */ 1762 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1763 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1764 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1765 sc->alc_cdata.alc_rr_ring_map); 1766 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1767 sc->alc_rdata.alc_rr_ring != NULL) 1768 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1769 sc->alc_rdata.alc_rr_ring, 1770 sc->alc_cdata.alc_rr_ring_map); 1771 sc->alc_rdata.alc_rr_ring = NULL; 1772 sc->alc_cdata.alc_rr_ring_map = NULL; 1773 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1774 sc->alc_cdata.alc_rr_ring_tag = NULL; 1775 } 1776 /* CMB block */ 1777 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1778 if (sc->alc_cdata.alc_cmb_map != NULL) 1779 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1780 sc->alc_cdata.alc_cmb_map); 1781 if (sc->alc_cdata.alc_cmb_map != NULL && 1782 sc->alc_rdata.alc_cmb != NULL) 1783 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1784 sc->alc_rdata.alc_cmb, 1785 sc->alc_cdata.alc_cmb_map); 1786 sc->alc_rdata.alc_cmb = NULL; 1787 sc->alc_cdata.alc_cmb_map = NULL; 1788 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1789 sc->alc_cdata.alc_cmb_tag = NULL; 1790 } 1791 /* SMB block */ 1792 if (sc->alc_cdata.alc_smb_tag != NULL) { 1793 if (sc->alc_cdata.alc_smb_map != NULL) 1794 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1795 sc->alc_cdata.alc_smb_map); 1796 if (sc->alc_cdata.alc_smb_map != NULL && 1797 sc->alc_rdata.alc_smb != NULL) 1798 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1799 sc->alc_rdata.alc_smb, 1800 sc->alc_cdata.alc_smb_map); 1801 sc->alc_rdata.alc_smb = NULL; 1802 sc->alc_cdata.alc_smb_map = NULL; 1803 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1804 sc->alc_cdata.alc_smb_tag = NULL; 1805 } 1806 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1807 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1808 sc->alc_cdata.alc_buffer_tag = NULL; 1809 } 1810 if (sc->alc_cdata.alc_parent_tag != NULL) { 1811 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1812 sc->alc_cdata.alc_parent_tag = NULL; 1813 } 1814} 1815 1816static int 1817alc_shutdown(device_t dev) 1818{ 1819 1820 return (alc_suspend(dev)); 1821} 1822 1823/* 1824 * Note, this driver resets the link speed to 10/100Mbps by 1825 * restarting auto-negotiation in suspend/shutdown phase but we 1826 * don't know whether that auto-negotiation would succeed or not 1827 * as driver has no control after powering off/suspend operation. 1828 * If the renegotiation fail WOL may not work. Running at 1Gbps 1829 * will draw more power than 375mA at 3.3V which is specified in 1830 * PCI specification and that would result in complete 1831 * shutdowning power to ethernet controller. 1832 * 1833 * TODO 1834 * Save current negotiated media speed/duplex/flow-control to 1835 * softc and restore the same link again after resuming. PHY 1836 * handling such as power down/resetting to 100Mbps may be better 1837 * handled in suspend method in phy driver. 1838 */ 1839static void 1840alc_setlinkspeed(struct alc_softc *sc) 1841{ 1842 struct mii_data *mii; 1843 int aneg, i; 1844 1845 mii = device_get_softc(sc->alc_miibus); 1846 mii_pollstat(mii); 1847 aneg = 0; 1848 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1849 (IFM_ACTIVE | IFM_AVALID)) { 1850 switch IFM_SUBTYPE(mii->mii_media_active) { 1851 case IFM_10_T: 1852 case IFM_100_TX: 1853 return; 1854 case IFM_1000_T: 1855 aneg++; 1856 break; 1857 default: 1858 break; 1859 } 1860 } 1861 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1862 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1863 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1864 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1865 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1866 DELAY(1000); 1867 if (aneg != 0) { 1868 /* 1869 * Poll link state until alc(4) get a 10/100Mbps link. 1870 */ 1871 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1872 mii_pollstat(mii); 1873 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1874 == (IFM_ACTIVE | IFM_AVALID)) { 1875 switch (IFM_SUBTYPE( 1876 mii->mii_media_active)) { 1877 case IFM_10_T: 1878 case IFM_100_TX: 1879 alc_mac_config(sc); 1880 return; 1881 default: 1882 break; 1883 } 1884 } 1885 ALC_UNLOCK(sc); 1886 pause("alclnk", hz); 1887 ALC_LOCK(sc); 1888 } 1889 if (i == MII_ANEGTICKS_GIGE) 1890 device_printf(sc->alc_dev, 1891 "establishing a link failed, WOL may not work!"); 1892 } 1893 /* 1894 * No link, force MAC to have 100Mbps, full-duplex link. 1895 * This is the last resort and may/may not work. 1896 */ 1897 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1898 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1899 alc_mac_config(sc); 1900} 1901 1902static void 1903alc_setwol(struct alc_softc *sc) 1904{ 1905 struct ifnet *ifp; 1906 uint32_t reg, pmcs; 1907 uint16_t pmstat; 1908 1909 ALC_LOCK_ASSERT(sc); 1910 1911 alc_disable_l0s_l1(sc); 1912 ifp = sc->alc_ifp; 1913 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1914 /* Disable WOL. */ 1915 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1916 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1917 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1918 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1919 /* Force PHY power down. */ 1920 alc_phy_down(sc); 1921 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1922 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1923 return; 1924 } 1925 1926 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1927 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1928 alc_setlinkspeed(sc); 1929 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1930 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1931 } 1932 1933 pmcs = 0; 1934 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1935 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1936 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1937 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1938 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1939 MAC_CFG_BCAST); 1940 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1941 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1942 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1943 reg |= MAC_CFG_RX_ENB; 1944 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1945 1946 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1947 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1948 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1949 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1950 /* WOL disabled, PHY power down. */ 1951 alc_phy_down(sc); 1952 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1953 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1954 } 1955 /* Request PME. */ 1956 pmstat = pci_read_config(sc->alc_dev, 1957 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1958 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1959 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1960 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1961 pci_write_config(sc->alc_dev, 1962 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1963} 1964 1965static int 1966alc_suspend(device_t dev) 1967{ 1968 struct alc_softc *sc; 1969 1970 sc = device_get_softc(dev); 1971 1972 ALC_LOCK(sc); 1973 alc_stop(sc); 1974 alc_setwol(sc); 1975 ALC_UNLOCK(sc); 1976 1977 return (0); 1978} 1979 1980static int 1981alc_resume(device_t dev) 1982{ 1983 struct alc_softc *sc; 1984 struct ifnet *ifp; 1985 uint16_t pmstat; 1986 1987 sc = device_get_softc(dev); 1988 1989 ALC_LOCK(sc); 1990 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1991 /* Disable PME and clear PME status. */ 1992 pmstat = pci_read_config(sc->alc_dev, 1993 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1994 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1995 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1996 pci_write_config(sc->alc_dev, 1997 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1998 } 1999 } 2000 /* Reset PHY. */ 2001 alc_phy_reset(sc); 2002 ifp = sc->alc_ifp; 2003 if ((ifp->if_flags & IFF_UP) != 0) { 2004 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2005 alc_init_locked(sc); 2006 } 2007 ALC_UNLOCK(sc); 2008 2009 return (0); 2010} 2011 2012static int 2013alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2014{ 2015 struct alc_txdesc *txd, *txd_last; 2016 struct tx_desc *desc; 2017 struct mbuf *m; 2018 struct ip *ip; 2019 struct tcphdr *tcp; 2020 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2021 bus_dmamap_t map; 2022 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2023 int error, idx, nsegs, prod; 2024 2025 ALC_LOCK_ASSERT(sc); 2026 2027 M_ASSERTPKTHDR((*m_head)); 2028 2029 m = *m_head; 2030 ip = NULL; 2031 tcp = NULL; 2032 ip_off = poff = 0; 2033 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2034 /* 2035 * AR813x/AR815x requires offset of TCP/UDP header in its 2036 * Tx descriptor to perform Tx checksum offloading. TSO 2037 * also requires TCP header offset and modification of 2038 * IP/TCP header. This kind of operation takes many CPU 2039 * cycles on FreeBSD so fast host CPU is required to get 2040 * smooth TSO performance. 2041 */ 2042 struct ether_header *eh; 2043 2044 if (M_WRITABLE(m) == 0) { 2045 /* Get a writable copy. */ 2046 m = m_dup(*m_head, M_DONTWAIT); 2047 /* Release original mbufs. */ 2048 m_freem(*m_head); 2049 if (m == NULL) { 2050 *m_head = NULL; 2051 return (ENOBUFS); 2052 } 2053 *m_head = m; 2054 } 2055 2056 ip_off = sizeof(struct ether_header); 2057 m = m_pullup(m, ip_off); 2058 if (m == NULL) { 2059 *m_head = NULL; 2060 return (ENOBUFS); 2061 } 2062 eh = mtod(m, struct ether_header *); 2063 /* 2064 * Check if hardware VLAN insertion is off. 2065 * Additional check for LLC/SNAP frame? 2066 */ 2067 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2068 ip_off = sizeof(struct ether_vlan_header); 2069 m = m_pullup(m, ip_off); 2070 if (m == NULL) { 2071 *m_head = NULL; 2072 return (ENOBUFS); 2073 } 2074 } 2075 m = m_pullup(m, ip_off + sizeof(struct ip)); 2076 if (m == NULL) { 2077 *m_head = NULL; 2078 return (ENOBUFS); 2079 } 2080 ip = (struct ip *)(mtod(m, char *) + ip_off); 2081 poff = ip_off + (ip->ip_hl << 2); 2082 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2083 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2084 if (m == NULL) { 2085 *m_head = NULL; 2086 return (ENOBUFS); 2087 } 2088 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2089 m = m_pullup(m, poff + (tcp->th_off << 2)); 2090 if (m == NULL) { 2091 *m_head = NULL; 2092 return (ENOBUFS); 2093 } 2094 /* 2095 * Due to strict adherence of Microsoft NDIS 2096 * Large Send specification, hardware expects 2097 * a pseudo TCP checksum inserted by upper 2098 * stack. Unfortunately the pseudo TCP 2099 * checksum that NDIS refers to does not include 2100 * TCP payload length so driver should recompute 2101 * the pseudo checksum here. Hopefully this 2102 * wouldn't be much burden on modern CPUs. 2103 * 2104 * Reset IP checksum and recompute TCP pseudo 2105 * checksum as NDIS specification said. 2106 */ 2107 ip = (struct ip *)(mtod(m, char *) + ip_off); 2108 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2109 ip->ip_sum = 0; 2110 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2111 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2112 } 2113 *m_head = m; 2114 } 2115 2116 prod = sc->alc_cdata.alc_tx_prod; 2117 txd = &sc->alc_cdata.alc_txdesc[prod]; 2118 txd_last = txd; 2119 map = txd->tx_dmamap; 2120 2121 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2122 *m_head, txsegs, &nsegs, 0); 2123 if (error == EFBIG) { 2124 m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 2125 if (m == NULL) { 2126 m_freem(*m_head); 2127 *m_head = NULL; 2128 return (ENOMEM); 2129 } 2130 *m_head = m; 2131 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2132 *m_head, txsegs, &nsegs, 0); 2133 if (error != 0) { 2134 m_freem(*m_head); 2135 *m_head = NULL; 2136 return (error); 2137 } 2138 } else if (error != 0) 2139 return (error); 2140 if (nsegs == 0) { 2141 m_freem(*m_head); 2142 *m_head = NULL; 2143 return (EIO); 2144 } 2145 2146 /* Check descriptor overrun. */ 2147 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2148 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2149 return (ENOBUFS); 2150 } 2151 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2152 2153 m = *m_head; 2154 cflags = TD_ETHERNET; 2155 vtag = 0; 2156 desc = NULL; 2157 idx = 0; 2158 /* Configure VLAN hardware tag insertion. */ 2159 if ((m->m_flags & M_VLANTAG) != 0) { 2160 vtag = htons(m->m_pkthdr.ether_vtag); 2161 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2162 cflags |= TD_INS_VLAN_TAG; 2163 } 2164 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2165 /* Request TSO and set MSS. */ 2166 cflags |= TD_TSO | TD_TSO_DESCV1; 2167 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2168 TD_MSS_MASK; 2169 /* Set TCP header offset. */ 2170 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2171 TD_TCPHDR_OFFSET_MASK; 2172 /* 2173 * AR813x/AR815x requires the first buffer should 2174 * only hold IP/TCP header data. Payload should 2175 * be handled in other descriptors. 2176 */ 2177 hdrlen = poff + (tcp->th_off << 2); 2178 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2179 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2180 desc->flags = htole32(cflags); 2181 desc->addr = htole64(txsegs[0].ds_addr); 2182 sc->alc_cdata.alc_tx_cnt++; 2183 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2184 if (m->m_len - hdrlen > 0) { 2185 /* Handle remaining payload of the first fragment. */ 2186 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2187 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2188 vtag)); 2189 desc->flags = htole32(cflags); 2190 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2191 sc->alc_cdata.alc_tx_cnt++; 2192 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2193 } 2194 /* Handle remaining fragments. */ 2195 idx = 1; 2196 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2197 /* Configure Tx checksum offload. */ 2198#ifdef ALC_USE_CUSTOM_CSUM 2199 cflags |= TD_CUSTOM_CSUM; 2200 /* Set checksum start offset. */ 2201 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2202 TD_PLOAD_OFFSET_MASK; 2203 /* Set checksum insertion position of TCP/UDP. */ 2204 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2205 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2206#else 2207 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2208 cflags |= TD_IPCSUM; 2209 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2210 cflags |= TD_TCPCSUM; 2211 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2212 cflags |= TD_UDPCSUM; 2213 /* Set TCP/UDP header offset. */ 2214 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2215 TD_L4HDR_OFFSET_MASK; 2216#endif 2217 } 2218 for (; idx < nsegs; idx++) { 2219 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2220 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2221 desc->flags = htole32(cflags); 2222 desc->addr = htole64(txsegs[idx].ds_addr); 2223 sc->alc_cdata.alc_tx_cnt++; 2224 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2225 } 2226 /* Update producer index. */ 2227 sc->alc_cdata.alc_tx_prod = prod; 2228 2229 /* Finally set EOP on the last descriptor. */ 2230 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2231 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2232 desc->flags |= htole32(TD_EOP); 2233 2234 /* Swap dmamap of the first and the last. */ 2235 txd = &sc->alc_cdata.alc_txdesc[prod]; 2236 map = txd_last->tx_dmamap; 2237 txd_last->tx_dmamap = txd->tx_dmamap; 2238 txd->tx_dmamap = map; 2239 txd->tx_m = m; 2240 2241 return (0); 2242} 2243 2244static void 2245alc_tx_task(void *arg, int pending) 2246{ 2247 struct ifnet *ifp; 2248 2249 ifp = (struct ifnet *)arg; 2250 alc_start(ifp); 2251} 2252 2253static void 2254alc_start(struct ifnet *ifp) 2255{ 2256 struct alc_softc *sc; 2257 struct mbuf *m_head; 2258 int enq; 2259 2260 sc = ifp->if_softc; 2261 2262 ALC_LOCK(sc); 2263 2264 /* Reclaim transmitted frames. */ 2265 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2266 alc_txeof(sc); 2267 2268 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2269 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) { 2270 ALC_UNLOCK(sc); 2271 return; 2272 } 2273 2274 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2275 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2276 if (m_head == NULL) 2277 break; 2278 /* 2279 * Pack the data into the transmit ring. If we 2280 * don't have room, set the OACTIVE flag and wait 2281 * for the NIC to drain the ring. 2282 */ 2283 if (alc_encap(sc, &m_head)) { 2284 if (m_head == NULL) 2285 break; 2286 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2287 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2288 break; 2289 } 2290 2291 enq++; 2292 /* 2293 * If there's a BPF listener, bounce a copy of this frame 2294 * to him. 2295 */ 2296 ETHER_BPF_MTAP(ifp, m_head); 2297 } 2298 2299 if (enq > 0) { 2300 /* Sync descriptors. */ 2301 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2302 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2303 /* Kick. Assume we're using normal Tx priority queue. */ 2304 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2305 (sc->alc_cdata.alc_tx_prod << 2306 MBOX_TD_PROD_LO_IDX_SHIFT) & 2307 MBOX_TD_PROD_LO_IDX_MASK); 2308 /* Set a timeout in case the chip goes out to lunch. */ 2309 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2310 } 2311 2312 ALC_UNLOCK(sc); 2313} 2314 2315static void 2316alc_watchdog(struct alc_softc *sc) 2317{ 2318 struct ifnet *ifp; 2319 2320 ALC_LOCK_ASSERT(sc); 2321 2322 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2323 return; 2324 2325 ifp = sc->alc_ifp; 2326 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2327 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2328 ifp->if_oerrors++; 2329 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2330 alc_init_locked(sc); 2331 return; 2332 } 2333 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2334 ifp->if_oerrors++; 2335 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2336 alc_init_locked(sc); 2337 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2338 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2339} 2340 2341static int 2342alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2343{ 2344 struct alc_softc *sc; 2345 struct ifreq *ifr; 2346 struct mii_data *mii; 2347 int error, mask; 2348 2349 sc = ifp->if_softc; 2350 ifr = (struct ifreq *)data; 2351 error = 0; 2352 switch (cmd) { 2353 case SIOCSIFMTU: 2354 if (ifr->ifr_mtu < ETHERMIN || 2355 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2356 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2357 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2358 ifr->ifr_mtu > ETHERMTU)) 2359 error = EINVAL; 2360 else if (ifp->if_mtu != ifr->ifr_mtu) { 2361 ALC_LOCK(sc); 2362 ifp->if_mtu = ifr->ifr_mtu; 2363 /* AR813x/AR815x has 13 bits MSS field. */ 2364 if (ifp->if_mtu > ALC_TSO_MTU && 2365 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2366 ifp->if_capenable &= ~IFCAP_TSO4; 2367 ifp->if_hwassist &= ~CSUM_TSO; 2368 VLAN_CAPABILITIES(ifp); 2369 } 2370 ALC_UNLOCK(sc); 2371 } 2372 break; 2373 case SIOCSIFFLAGS: 2374 ALC_LOCK(sc); 2375 if ((ifp->if_flags & IFF_UP) != 0) { 2376 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2377 ((ifp->if_flags ^ sc->alc_if_flags) & 2378 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2379 alc_rxfilter(sc); 2380 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2381 alc_init_locked(sc); 2382 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2383 alc_stop(sc); 2384 sc->alc_if_flags = ifp->if_flags; 2385 ALC_UNLOCK(sc); 2386 break; 2387 case SIOCADDMULTI: 2388 case SIOCDELMULTI: 2389 ALC_LOCK(sc); 2390 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2391 alc_rxfilter(sc); 2392 ALC_UNLOCK(sc); 2393 break; 2394 case SIOCSIFMEDIA: 2395 case SIOCGIFMEDIA: 2396 mii = device_get_softc(sc->alc_miibus); 2397 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2398 break; 2399 case SIOCSIFCAP: 2400 ALC_LOCK(sc); 2401 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2402 if ((mask & IFCAP_TXCSUM) != 0 && 2403 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2404 ifp->if_capenable ^= IFCAP_TXCSUM; 2405 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2406 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2407 else 2408 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2409 } 2410 if ((mask & IFCAP_TSO4) != 0 && 2411 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2412 ifp->if_capenable ^= IFCAP_TSO4; 2413 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2414 /* AR813x/AR815x has 13 bits MSS field. */ 2415 if (ifp->if_mtu > ALC_TSO_MTU) { 2416 ifp->if_capenable &= ~IFCAP_TSO4; 2417 ifp->if_hwassist &= ~CSUM_TSO; 2418 } else 2419 ifp->if_hwassist |= CSUM_TSO; 2420 } else 2421 ifp->if_hwassist &= ~CSUM_TSO; 2422 } 2423 if ((mask & IFCAP_WOL_MCAST) != 0 && 2424 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2425 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2426 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2427 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2428 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2429 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2430 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2431 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2432 alc_rxvlan(sc); 2433 } 2434 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2435 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2436 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2437 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2438 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2439 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2440 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2441 ifp->if_capenable &= 2442 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2443 ALC_UNLOCK(sc); 2444 VLAN_CAPABILITIES(ifp); 2445 break; 2446 default: 2447 error = ether_ioctl(ifp, cmd, data); 2448 break; 2449 } 2450 2451 return (error); 2452} 2453 2454static void 2455alc_mac_config(struct alc_softc *sc) 2456{ 2457 struct mii_data *mii; 2458 uint32_t reg; 2459 2460 ALC_LOCK_ASSERT(sc); 2461 2462 mii = device_get_softc(sc->alc_miibus); 2463 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2464 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2465 MAC_CFG_SPEED_MASK); 2466 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2467 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2468 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 2469 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2470 /* Reprogram MAC with resolved speed/duplex. */ 2471 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2472 case IFM_10_T: 2473 case IFM_100_TX: 2474 reg |= MAC_CFG_SPEED_10_100; 2475 break; 2476 case IFM_1000_T: 2477 reg |= MAC_CFG_SPEED_1000; 2478 break; 2479 } 2480 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2481 reg |= MAC_CFG_FULL_DUPLEX; 2482#ifdef notyet 2483 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2484 reg |= MAC_CFG_TX_FC; 2485 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2486 reg |= MAC_CFG_RX_FC; 2487#endif 2488 } 2489 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2490} 2491 2492static void 2493alc_stats_clear(struct alc_softc *sc) 2494{ 2495 struct smb sb, *smb; 2496 uint32_t *reg; 2497 int i; 2498 2499 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2500 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2501 sc->alc_cdata.alc_smb_map, 2502 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2503 smb = sc->alc_rdata.alc_smb; 2504 /* Update done, clear. */ 2505 smb->updated = 0; 2506 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2507 sc->alc_cdata.alc_smb_map, 2508 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2509 } else { 2510 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2511 reg++) { 2512 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2513 i += sizeof(uint32_t); 2514 } 2515 /* Read Tx statistics. */ 2516 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2517 reg++) { 2518 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2519 i += sizeof(uint32_t); 2520 } 2521 } 2522} 2523 2524static void 2525alc_stats_update(struct alc_softc *sc) 2526{ 2527 struct alc_hw_stats *stat; 2528 struct smb sb, *smb; 2529 struct ifnet *ifp; 2530 uint32_t *reg; 2531 int i; 2532 2533 ALC_LOCK_ASSERT(sc); 2534 2535 ifp = sc->alc_ifp; 2536 stat = &sc->alc_stats; 2537 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2538 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2539 sc->alc_cdata.alc_smb_map, 2540 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2541 smb = sc->alc_rdata.alc_smb; 2542 if (smb->updated == 0) 2543 return; 2544 } else { 2545 smb = &sb; 2546 /* Read Rx statistics. */ 2547 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2548 reg++) { 2549 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2550 i += sizeof(uint32_t); 2551 } 2552 /* Read Tx statistics. */ 2553 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2554 reg++) { 2555 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2556 i += sizeof(uint32_t); 2557 } 2558 } 2559 2560 /* Rx stats. */ 2561 stat->rx_frames += smb->rx_frames; 2562 stat->rx_bcast_frames += smb->rx_bcast_frames; 2563 stat->rx_mcast_frames += smb->rx_mcast_frames; 2564 stat->rx_pause_frames += smb->rx_pause_frames; 2565 stat->rx_control_frames += smb->rx_control_frames; 2566 stat->rx_crcerrs += smb->rx_crcerrs; 2567 stat->rx_lenerrs += smb->rx_lenerrs; 2568 stat->rx_bytes += smb->rx_bytes; 2569 stat->rx_runts += smb->rx_runts; 2570 stat->rx_fragments += smb->rx_fragments; 2571 stat->rx_pkts_64 += smb->rx_pkts_64; 2572 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2573 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2574 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2575 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2576 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2577 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2578 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2579 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2580 stat->rx_rrs_errs += smb->rx_rrs_errs; 2581 stat->rx_alignerrs += smb->rx_alignerrs; 2582 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2583 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2584 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2585 2586 /* Tx stats. */ 2587 stat->tx_frames += smb->tx_frames; 2588 stat->tx_bcast_frames += smb->tx_bcast_frames; 2589 stat->tx_mcast_frames += smb->tx_mcast_frames; 2590 stat->tx_pause_frames += smb->tx_pause_frames; 2591 stat->tx_excess_defer += smb->tx_excess_defer; 2592 stat->tx_control_frames += smb->tx_control_frames; 2593 stat->tx_deferred += smb->tx_deferred; 2594 stat->tx_bytes += smb->tx_bytes; 2595 stat->tx_pkts_64 += smb->tx_pkts_64; 2596 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2597 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2598 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2599 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2600 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2601 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2602 stat->tx_single_colls += smb->tx_single_colls; 2603 stat->tx_multi_colls += smb->tx_multi_colls; 2604 stat->tx_late_colls += smb->tx_late_colls; 2605 stat->tx_excess_colls += smb->tx_excess_colls; 2606 stat->tx_abort += smb->tx_abort; 2607 stat->tx_underrun += smb->tx_underrun; 2608 stat->tx_desc_underrun += smb->tx_desc_underrun; 2609 stat->tx_lenerrs += smb->tx_lenerrs; 2610 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2611 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2612 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2613 2614 /* Update counters in ifnet. */ 2615 ifp->if_opackets += smb->tx_frames; 2616 2617 ifp->if_collisions += smb->tx_single_colls + 2618 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2619 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2620 2621 /* 2622 * XXX 2623 * tx_pkts_truncated counter looks suspicious. It constantly 2624 * increments with no sign of Tx errors. This may indicate 2625 * the counter name is not correct one so I've removed the 2626 * counter in output errors. 2627 */ 2628 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2629 smb->tx_underrun; 2630 2631 ifp->if_ipackets += smb->rx_frames; 2632 2633 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2634 smb->rx_runts + smb->rx_pkts_truncated + 2635 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2636 smb->rx_alignerrs; 2637 2638 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2639 /* Update done, clear. */ 2640 smb->updated = 0; 2641 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2642 sc->alc_cdata.alc_smb_map, 2643 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2644 } 2645} 2646 2647static int 2648alc_intr(void *arg) 2649{ 2650 struct alc_softc *sc; 2651 uint32_t status; 2652 2653 sc = (struct alc_softc *)arg; 2654 2655 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2656 if ((status & ALC_INTRS) == 0) 2657 return (FILTER_STRAY); 2658 /* Disable interrupts. */ 2659 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2660 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2661 2662 return (FILTER_HANDLED); 2663} 2664 2665static void 2666alc_int_task(void *arg, int pending) 2667{ 2668 struct alc_softc *sc; 2669 struct ifnet *ifp; 2670 uint32_t status; 2671 int more; 2672 2673 sc = (struct alc_softc *)arg; 2674 ifp = sc->alc_ifp; 2675 2676 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2677 more = atomic_readandclear_int(&sc->alc_morework); 2678 if (more != 0) 2679 status |= INTR_RX_PKT; 2680 if ((status & ALC_INTRS) == 0) 2681 goto done; 2682 2683 /* Acknowledge interrupts but still disable interrupts. */ 2684 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2685 2686 more = 0; 2687 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2688 if ((status & INTR_RX_PKT) != 0) { 2689 more = alc_rxintr(sc, sc->alc_process_limit); 2690 if (more == EAGAIN) 2691 atomic_set_int(&sc->alc_morework, 1); 2692 else if (more == EIO) { 2693 ALC_LOCK(sc); 2694 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2695 alc_init_locked(sc); 2696 ALC_UNLOCK(sc); 2697 return; 2698 } 2699 } 2700 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2701 INTR_TXQ_TO_RST)) != 0) { 2702 if ((status & INTR_DMA_RD_TO_RST) != 0) 2703 device_printf(sc->alc_dev, 2704 "DMA read error! -- resetting\n"); 2705 if ((status & INTR_DMA_WR_TO_RST) != 0) 2706 device_printf(sc->alc_dev, 2707 "DMA write error! -- resetting\n"); 2708 if ((status & INTR_TXQ_TO_RST) != 0) 2709 device_printf(sc->alc_dev, 2710 "TxQ reset! -- resetting\n"); 2711 ALC_LOCK(sc); 2712 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2713 alc_init_locked(sc); 2714 ALC_UNLOCK(sc); 2715 return; 2716 } 2717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2718 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2719 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2720 } 2721 2722 if (more == EAGAIN || 2723 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2724 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2725 return; 2726 } 2727 2728done: 2729 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2730 /* Re-enable interrupts if we're running. */ 2731 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2732 } 2733} 2734 2735static void 2736alc_txeof(struct alc_softc *sc) 2737{ 2738 struct ifnet *ifp; 2739 struct alc_txdesc *txd; 2740 uint32_t cons, prod; 2741 int prog; 2742 2743 ALC_LOCK_ASSERT(sc); 2744 2745 ifp = sc->alc_ifp; 2746 2747 if (sc->alc_cdata.alc_tx_cnt == 0) 2748 return; 2749 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2750 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2751 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2752 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2753 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2754 prod = sc->alc_rdata.alc_cmb->cons; 2755 } else 2756 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2757 /* Assume we're using normal Tx priority queue. */ 2758 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2759 MBOX_TD_CONS_LO_IDX_SHIFT; 2760 cons = sc->alc_cdata.alc_tx_cons; 2761 /* 2762 * Go through our Tx list and free mbufs for those 2763 * frames which have been transmitted. 2764 */ 2765 for (prog = 0; cons != prod; prog++, 2766 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2767 if (sc->alc_cdata.alc_tx_cnt <= 0) 2768 break; 2769 prog++; 2770 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2771 sc->alc_cdata.alc_tx_cnt--; 2772 txd = &sc->alc_cdata.alc_txdesc[cons]; 2773 if (txd->tx_m != NULL) { 2774 /* Reclaim transmitted mbufs. */ 2775 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2776 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2777 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2778 txd->tx_dmamap); 2779 m_freem(txd->tx_m); 2780 txd->tx_m = NULL; 2781 } 2782 } 2783 2784 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2785 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2786 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2787 sc->alc_cdata.alc_tx_cons = cons; 2788 /* 2789 * Unarm watchdog timer only when there is no pending 2790 * frames in Tx queue. 2791 */ 2792 if (sc->alc_cdata.alc_tx_cnt == 0) 2793 sc->alc_watchdog_timer = 0; 2794} 2795 2796static int 2797alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2798{ 2799 struct mbuf *m; 2800 bus_dma_segment_t segs[1]; 2801 bus_dmamap_t map; 2802 int nsegs; 2803 2804 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2805 if (m == NULL) 2806 return (ENOBUFS); 2807 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2808#ifndef __NO_STRICT_ALIGNMENT 2809 m_adj(m, sizeof(uint64_t)); 2810#endif 2811 2812 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2813 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2814 m_freem(m); 2815 return (ENOBUFS); 2816 } 2817 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2818 2819 if (rxd->rx_m != NULL) { 2820 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2821 BUS_DMASYNC_POSTREAD); 2822 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2823 } 2824 map = rxd->rx_dmamap; 2825 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2826 sc->alc_cdata.alc_rx_sparemap = map; 2827 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2828 BUS_DMASYNC_PREREAD); 2829 rxd->rx_m = m; 2830 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2831 return (0); 2832} 2833 2834static int 2835alc_rxintr(struct alc_softc *sc, int count) 2836{ 2837 struct ifnet *ifp; 2838 struct rx_rdesc *rrd; 2839 uint32_t nsegs, status; 2840 int rr_cons, prog; 2841 2842 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2843 sc->alc_cdata.alc_rr_ring_map, 2844 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2845 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2846 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2847 rr_cons = sc->alc_cdata.alc_rr_cons; 2848 ifp = sc->alc_ifp; 2849 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2850 if (count-- <= 0) 2851 break; 2852 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2853 status = le32toh(rrd->status); 2854 if ((status & RRD_VALID) == 0) 2855 break; 2856 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2857 if (nsegs == 0) { 2858 /* This should not happen! */ 2859 device_printf(sc->alc_dev, 2860 "unexpected segment count -- resetting\n"); 2861 return (EIO); 2862 } 2863 alc_rxeof(sc, rrd); 2864 /* Clear Rx return status. */ 2865 rrd->status = 0; 2866 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2867 sc->alc_cdata.alc_rx_cons += nsegs; 2868 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2869 prog += nsegs; 2870 } 2871 2872 if (prog > 0) { 2873 /* Update the consumer index. */ 2874 sc->alc_cdata.alc_rr_cons = rr_cons; 2875 /* Sync Rx return descriptors. */ 2876 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2877 sc->alc_cdata.alc_rr_ring_map, 2878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2879 /* 2880 * Sync updated Rx descriptors such that controller see 2881 * modified buffer addresses. 2882 */ 2883 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2884 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2885 /* 2886 * Let controller know availability of new Rx buffers. 2887 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2888 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2889 * only when Rx buffer pre-fetching is required. In 2890 * addition we already set ALC_RX_RD_FREE_THRESH to 2891 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2892 * it still seems that pre-fetching needs more 2893 * experimentation. 2894 */ 2895 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2896 sc->alc_cdata.alc_rx_cons); 2897 } 2898 2899 return (count > 0 ? 0 : EAGAIN); 2900} 2901 2902#ifndef __NO_STRICT_ALIGNMENT 2903static struct mbuf * 2904alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2905{ 2906 struct mbuf *n; 2907 int i; 2908 uint16_t *src, *dst; 2909 2910 src = mtod(m, uint16_t *); 2911 dst = src - 3; 2912 2913 if (m->m_next == NULL) { 2914 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2915 *dst++ = *src++; 2916 m->m_data -= 6; 2917 return (m); 2918 } 2919 /* 2920 * Append a new mbuf to received mbuf chain and copy ethernet 2921 * header from the mbuf chain. This can save lots of CPU 2922 * cycles for jumbo frame. 2923 */ 2924 MGETHDR(n, M_DONTWAIT, MT_DATA); 2925 if (n == NULL) { 2926 ifp->if_iqdrops++; 2927 m_freem(m); 2928 return (NULL); 2929 } 2930 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2931 m->m_data += ETHER_HDR_LEN; 2932 m->m_len -= ETHER_HDR_LEN; 2933 n->m_len = ETHER_HDR_LEN; 2934 M_MOVE_PKTHDR(n, m); 2935 n->m_next = m; 2936 return (n); 2937} 2938#endif 2939 2940/* Receive a frame. */ 2941static void 2942alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2943{ 2944 struct alc_rxdesc *rxd; 2945 struct ifnet *ifp; 2946 struct mbuf *mp, *m; 2947 uint32_t rdinfo, status, vtag; 2948 int count, nsegs, rx_cons; 2949 2950 ifp = sc->alc_ifp; 2951 status = le32toh(rrd->status); 2952 rdinfo = le32toh(rrd->rdinfo); 2953 rx_cons = RRD_RD_IDX(rdinfo); 2954 nsegs = RRD_RD_CNT(rdinfo); 2955 2956 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2957 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2958 /* 2959 * We want to pass the following frames to upper 2960 * layer regardless of error status of Rx return 2961 * ring. 2962 * 2963 * o IP/TCP/UDP checksum is bad. 2964 * o frame length and protocol specific length 2965 * does not match. 2966 * 2967 * Force network stack compute checksum for 2968 * errored frames. 2969 */ 2970 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2971 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2972 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2973 return; 2974 } 2975 2976 for (count = 0; count < nsegs; count++, 2977 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2978 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2979 mp = rxd->rx_m; 2980 /* Add a new receive buffer to the ring. */ 2981 if (alc_newbuf(sc, rxd) != 0) { 2982 ifp->if_iqdrops++; 2983 /* Reuse Rx buffers. */ 2984 if (sc->alc_cdata.alc_rxhead != NULL) 2985 m_freem(sc->alc_cdata.alc_rxhead); 2986 break; 2987 } 2988 2989 /* 2990 * Assume we've received a full sized frame. 2991 * Actual size is fixed when we encounter the end of 2992 * multi-segmented frame. 2993 */ 2994 mp->m_len = sc->alc_buf_size; 2995 2996 /* Chain received mbufs. */ 2997 if (sc->alc_cdata.alc_rxhead == NULL) { 2998 sc->alc_cdata.alc_rxhead = mp; 2999 sc->alc_cdata.alc_rxtail = mp; 3000 } else { 3001 mp->m_flags &= ~M_PKTHDR; 3002 sc->alc_cdata.alc_rxprev_tail = 3003 sc->alc_cdata.alc_rxtail; 3004 sc->alc_cdata.alc_rxtail->m_next = mp; 3005 sc->alc_cdata.alc_rxtail = mp; 3006 } 3007 3008 if (count == nsegs - 1) { 3009 /* Last desc. for this frame. */ 3010 m = sc->alc_cdata.alc_rxhead; 3011 m->m_flags |= M_PKTHDR; 3012 /* 3013 * It seems that L1C/L2C controller has no way 3014 * to tell hardware to strip CRC bytes. 3015 */ 3016 m->m_pkthdr.len = 3017 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3018 if (nsegs > 1) { 3019 /* Set last mbuf size. */ 3020 mp->m_len = sc->alc_cdata.alc_rxlen - 3021 (nsegs - 1) * sc->alc_buf_size; 3022 /* Remove the CRC bytes in chained mbufs. */ 3023 if (mp->m_len <= ETHER_CRC_LEN) { 3024 sc->alc_cdata.alc_rxtail = 3025 sc->alc_cdata.alc_rxprev_tail; 3026 sc->alc_cdata.alc_rxtail->m_len -= 3027 (ETHER_CRC_LEN - mp->m_len); 3028 sc->alc_cdata.alc_rxtail->m_next = NULL; 3029 m_freem(mp); 3030 } else { 3031 mp->m_len -= ETHER_CRC_LEN; 3032 } 3033 } else 3034 m->m_len = m->m_pkthdr.len; 3035 m->m_pkthdr.rcvif = ifp; 3036 /* 3037 * Due to hardware bugs, Rx checksum offloading 3038 * was intentionally disabled. 3039 */ 3040 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3041 (status & RRD_VLAN_TAG) != 0) { 3042 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3043 m->m_pkthdr.ether_vtag = ntohs(vtag); 3044 m->m_flags |= M_VLANTAG; 3045 } 3046#ifndef __NO_STRICT_ALIGNMENT 3047 m = alc_fixup_rx(ifp, m); 3048 if (m != NULL) 3049#endif 3050 { 3051 /* Pass it on. */ 3052 (*ifp->if_input)(ifp, m); 3053 } 3054 } 3055 } 3056 /* Reset mbuf chains. */ 3057 ALC_RXCHAIN_RESET(sc); 3058} 3059 3060static void 3061alc_tick(void *arg) 3062{ 3063 struct alc_softc *sc; 3064 struct mii_data *mii; 3065 3066 sc = (struct alc_softc *)arg; 3067 3068 ALC_LOCK_ASSERT(sc); 3069 3070 mii = device_get_softc(sc->alc_miibus); 3071 mii_tick(mii); 3072 alc_stats_update(sc); 3073 /* 3074 * alc(4) does not rely on Tx completion interrupts to reclaim 3075 * transferred buffers. Instead Tx completion interrupts are 3076 * used to hint for scheduling Tx task. So it's necessary to 3077 * release transmitted buffers by kicking Tx completion 3078 * handler. This limits the maximum reclamation delay to a hz. 3079 */ 3080 alc_txeof(sc); 3081 alc_watchdog(sc); 3082 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3083} 3084 3085static void 3086alc_reset(struct alc_softc *sc) 3087{ 3088 uint32_t reg; 3089 int i; 3090 3091 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3092 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3093 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3094 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3095 DELAY(10); 3096 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3097 break; 3098 } 3099 if (i == 0) 3100 device_printf(sc->alc_dev, "master reset timeout!\n"); 3101 3102 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3103 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3104 break; 3105 DELAY(10); 3106 } 3107 3108 if (i == 0) 3109 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3110} 3111 3112static void 3113alc_init(void *xsc) 3114{ 3115 struct alc_softc *sc; 3116 3117 sc = (struct alc_softc *)xsc; 3118 ALC_LOCK(sc); 3119 alc_init_locked(sc); 3120 ALC_UNLOCK(sc); 3121} 3122 3123static void 3124alc_init_locked(struct alc_softc *sc) 3125{ 3126 struct ifnet *ifp; 3127 struct mii_data *mii; 3128 uint8_t eaddr[ETHER_ADDR_LEN]; 3129 bus_addr_t paddr; 3130 uint32_t reg, rxf_hi, rxf_lo; 3131 3132 ALC_LOCK_ASSERT(sc); 3133 3134 ifp = sc->alc_ifp; 3135 mii = device_get_softc(sc->alc_miibus); 3136 3137 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3138 return; 3139 /* 3140 * Cancel any pending I/O. 3141 */ 3142 alc_stop(sc); 3143 /* 3144 * Reset the chip to a known state. 3145 */ 3146 alc_reset(sc); 3147 3148 /* Initialize Rx descriptors. */ 3149 if (alc_init_rx_ring(sc) != 0) { 3150 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3151 alc_stop(sc); 3152 return; 3153 } 3154 alc_init_rr_ring(sc); 3155 alc_init_tx_ring(sc); 3156 alc_init_cmb(sc); 3157 alc_init_smb(sc); 3158 3159 /* Reprogram the station address. */ 3160 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3161 CSR_WRITE_4(sc, ALC_PAR0, 3162 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3163 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3164 /* 3165 * Clear WOL status and disable all WOL feature as WOL 3166 * would interfere Rx operation under normal environments. 3167 */ 3168 CSR_READ_4(sc, ALC_WOL_CFG); 3169 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3170 /* Set Tx descriptor base addresses. */ 3171 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3172 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3173 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3174 /* We don't use high priority ring. */ 3175 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3176 /* Set Tx descriptor counter. */ 3177 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3178 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3179 /* Set Rx descriptor base addresses. */ 3180 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3181 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3182 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3183 /* We use one Rx ring. */ 3184 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3185 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3186 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3187 /* Set Rx descriptor counter. */ 3188 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3189 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3190 3191 /* 3192 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3193 * if it do not fit the buffer size. Rx return descriptor holds 3194 * a counter that indicates how many fragments were made by the 3195 * hardware. The buffer size should be multiple of 8 bytes. 3196 * Since hardware has limit on the size of buffer size, always 3197 * use the maximum value. 3198 * For strict-alignment architectures make sure to reduce buffer 3199 * size by 8 bytes to make room for alignment fixup. 3200 */ 3201#ifndef __NO_STRICT_ALIGNMENT 3202 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3203#else 3204 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3205#endif 3206 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3207 3208 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3209 /* Set Rx return descriptor base addresses. */ 3210 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3211 /* We use one Rx return ring. */ 3212 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3213 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3214 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3215 /* Set Rx return descriptor counter. */ 3216 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3217 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3218 paddr = sc->alc_rdata.alc_cmb_paddr; 3219 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3220 paddr = sc->alc_rdata.alc_smb_paddr; 3221 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3222 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3223 3224 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3225 /* Reconfigure SRAM - Vendor magic. */ 3226 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3227 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3228 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3229 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3230 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3231 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3232 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3233 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3234 } 3235 3236 /* Tell hardware that we're ready to load DMA blocks. */ 3237 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3238 3239 /* Configure interrupt moderation timer. */ 3240 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3241 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3242 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3243 /* 3244 * We don't want to automatic interrupt clear as task queue 3245 * for the interrupt should know interrupt status. 3246 */ 3247 reg = MASTER_SA_TIMER_ENB; 3248 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3249 reg |= MASTER_IM_RX_TIMER_ENB; 3250 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3251 reg |= MASTER_IM_TX_TIMER_ENB; 3252 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3253 /* 3254 * Disable interrupt re-trigger timer. We don't want automatic 3255 * re-triggering of un-ACKed interrupts. 3256 */ 3257 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3258 /* Configure CMB. */ 3259 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3260 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3261 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3262 } else 3263 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3264 /* 3265 * Hardware can be configured to issue SMB interrupt based 3266 * on programmed interval. Since there is a callout that is 3267 * invoked for every hz in driver we use that instead of 3268 * relying on periodic SMB interrupt. 3269 */ 3270 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3271 /* Clear MAC statistics. */ 3272 alc_stats_clear(sc); 3273 3274 /* 3275 * Always use maximum frame size that controller can support. 3276 * Otherwise received frames that has larger frame length 3277 * than alc(4) MTU would be silently dropped in hardware. This 3278 * would make path-MTU discovery hard as sender wouldn't get 3279 * any responses from receiver. alc(4) supports 3280 * multi-fragmented frames on Rx path so it has no issue on 3281 * assembling fragmented frames. Using maximum frame size also 3282 * removes the need to reinitialize hardware when interface 3283 * MTU configuration was changed. 3284 * 3285 * Be conservative in what you do, be liberal in what you 3286 * accept from others - RFC 793. 3287 */ 3288 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3289 3290 /* Disable header split(?) */ 3291 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3292 3293 /* Configure IPG/IFG parameters. */ 3294 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3295 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3296 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3297 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3298 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3299 /* Set parameters for half-duplex media. */ 3300 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3301 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3302 HDPX_CFG_LCOL_MASK) | 3303 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3304 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3305 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3306 HDPX_CFG_ABEBT_MASK) | 3307 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3308 HDPX_CFG_JAMIPG_MASK)); 3309 /* 3310 * Set TSO/checksum offload threshold. For frames that is 3311 * larger than this threshold, hardware wouldn't do 3312 * TSO/checksum offloading. 3313 */ 3314 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3315 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3316 TSO_OFFLOAD_THRESH_MASK); 3317 /* Configure TxQ. */ 3318 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3319 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3320 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3321 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3322 reg >>= 1; 3323 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3324 TXQ_CFG_TD_BURST_MASK; 3325 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3326 3327 /* Configure Rx free descriptor pre-fetching. */ 3328 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3329 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3330 RX_RD_FREE_THRESH_HI_MASK) | 3331 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3332 RX_RD_FREE_THRESH_LO_MASK)); 3333 3334 /* 3335 * Configure flow control parameters. 3336 * XON : 80% of Rx FIFO 3337 * XOFF : 30% of Rx FIFO 3338 */ 3339 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3340 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3341 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3342 rxf_hi = (reg * 8) / 10; 3343 rxf_lo = (reg * 3) / 10; 3344 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3345 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3346 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3347 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3348 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3349 } 3350 3351 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3352 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3353 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3354 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3355 SERDES_PHY_CLK_SLOWDOWN); 3356 3357 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3358 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3359 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3360 3361 /* Configure RxQ. */ 3362 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3363 RXQ_CFG_RD_BURST_MASK; 3364 reg |= RXQ_CFG_RSS_MODE_DIS; 3365 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3366 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3367 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3368 3369 /* Configure DMA parameters. */ 3370 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3371 reg |= sc->alc_rcb; 3372 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3373 reg |= DMA_CFG_CMB_ENB; 3374 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3375 reg |= DMA_CFG_SMB_ENB; 3376 else 3377 reg |= DMA_CFG_SMB_DIS; 3378 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3379 DMA_CFG_RD_BURST_SHIFT; 3380 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3381 DMA_CFG_WR_BURST_SHIFT; 3382 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3383 DMA_CFG_RD_DELAY_CNT_MASK; 3384 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3385 DMA_CFG_WR_DELAY_CNT_MASK; 3386 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3387 3388 /* 3389 * Configure Tx/Rx MACs. 3390 * - Auto-padding for short frames. 3391 * - Enable CRC generation. 3392 * Actual reconfiguration of MAC for resolved speed/duplex 3393 * is followed after detection of link establishment. 3394 * AR813x/AR815x always does checksum computation regardless 3395 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3396 * have bug in protocol field in Rx return structure so 3397 * these controllers can't handle fragmented frames. Disable 3398 * Rx checksum offloading until there is a newer controller 3399 * that has sane implementation. 3400 */ 3401 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3402 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3403 MAC_CFG_PREAMBLE_MASK); 3404 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3405 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3406 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3407 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3408 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3409 reg |= MAC_CFG_SPEED_10_100; 3410 else 3411 reg |= MAC_CFG_SPEED_1000; 3412 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3413 3414 /* Set up the receive filter. */ 3415 alc_rxfilter(sc); 3416 alc_rxvlan(sc); 3417 3418 /* Acknowledge all pending interrupts and clear it. */ 3419 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3420 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3421 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3422 3423 sc->alc_flags &= ~ALC_FLAG_LINK; 3424 /* Switch to the current media. */ 3425 mii_mediachg(mii); 3426 3427 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3428 3429 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3430 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3431} 3432 3433static void 3434alc_stop(struct alc_softc *sc) 3435{ 3436 struct ifnet *ifp; 3437 struct alc_txdesc *txd; 3438 struct alc_rxdesc *rxd; 3439 uint32_t reg; 3440 int i; 3441 3442 ALC_LOCK_ASSERT(sc); 3443 /* 3444 * Mark the interface down and cancel the watchdog timer. 3445 */ 3446 ifp = sc->alc_ifp; 3447 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3448 sc->alc_flags &= ~ALC_FLAG_LINK; 3449 callout_stop(&sc->alc_tick_ch); 3450 sc->alc_watchdog_timer = 0; 3451 alc_stats_update(sc); 3452 /* Disable interrupts. */ 3453 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3454 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3455 alc_stop_queue(sc); 3456 /* Disable DMA. */ 3457 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3458 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3459 reg |= DMA_CFG_SMB_DIS; 3460 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3461 DELAY(1000); 3462 /* Stop Rx/Tx MACs. */ 3463 alc_stop_mac(sc); 3464 /* Disable interrupts which might be touched in taskq handler. */ 3465 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3466 3467 /* Reclaim Rx buffers that have been processed. */ 3468 if (sc->alc_cdata.alc_rxhead != NULL) 3469 m_freem(sc->alc_cdata.alc_rxhead); 3470 ALC_RXCHAIN_RESET(sc); 3471 /* 3472 * Free Tx/Rx mbufs still in the queues. 3473 */ 3474 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3475 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3476 if (rxd->rx_m != NULL) { 3477 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3478 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3479 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3480 rxd->rx_dmamap); 3481 m_freem(rxd->rx_m); 3482 rxd->rx_m = NULL; 3483 } 3484 } 3485 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3486 txd = &sc->alc_cdata.alc_txdesc[i]; 3487 if (txd->tx_m != NULL) { 3488 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3489 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3490 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3491 txd->tx_dmamap); 3492 m_freem(txd->tx_m); 3493 txd->tx_m = NULL; 3494 } 3495 } 3496} 3497 3498static void 3499alc_stop_mac(struct alc_softc *sc) 3500{ 3501 uint32_t reg; 3502 int i; 3503 3504 ALC_LOCK_ASSERT(sc); 3505 3506 /* Disable Rx/Tx MAC. */ 3507 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3508 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3509 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3510 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3511 } 3512 for (i = ALC_TIMEOUT; i > 0; i--) { 3513 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3514 if (reg == 0) 3515 break; 3516 DELAY(10); 3517 } 3518 if (i == 0) 3519 device_printf(sc->alc_dev, 3520 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3521} 3522 3523static void 3524alc_start_queue(struct alc_softc *sc) 3525{ 3526 uint32_t qcfg[] = { 3527 0, 3528 RXQ_CFG_QUEUE0_ENB, 3529 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3530 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3531 RXQ_CFG_ENB 3532 }; 3533 uint32_t cfg; 3534 3535 ALC_LOCK_ASSERT(sc); 3536 3537 /* Enable RxQ. */ 3538 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3539 cfg &= ~RXQ_CFG_ENB; 3540 cfg |= qcfg[1]; 3541 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3542 /* Enable TxQ. */ 3543 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3544 cfg |= TXQ_CFG_ENB; 3545 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3546} 3547 3548static void 3549alc_stop_queue(struct alc_softc *sc) 3550{ 3551 uint32_t reg; 3552 int i; 3553 3554 ALC_LOCK_ASSERT(sc); 3555 3556 /* Disable RxQ. */ 3557 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3558 if ((reg & RXQ_CFG_ENB) != 0) { 3559 reg &= ~RXQ_CFG_ENB; 3560 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3561 } 3562 /* Disable TxQ. */ 3563 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3564 if ((reg & TXQ_CFG_ENB) == 0) { 3565 reg &= ~TXQ_CFG_ENB; 3566 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3567 } 3568 for (i = ALC_TIMEOUT; i > 0; i--) { 3569 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3570 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3571 break; 3572 DELAY(10); 3573 } 3574 if (i == 0) 3575 device_printf(sc->alc_dev, 3576 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3577} 3578 3579static void 3580alc_init_tx_ring(struct alc_softc *sc) 3581{ 3582 struct alc_ring_data *rd; 3583 struct alc_txdesc *txd; 3584 int i; 3585 3586 ALC_LOCK_ASSERT(sc); 3587 3588 sc->alc_cdata.alc_tx_prod = 0; 3589 sc->alc_cdata.alc_tx_cons = 0; 3590 sc->alc_cdata.alc_tx_cnt = 0; 3591 3592 rd = &sc->alc_rdata; 3593 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3594 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3595 txd = &sc->alc_cdata.alc_txdesc[i]; 3596 txd->tx_m = NULL; 3597 } 3598 3599 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3600 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3601} 3602 3603static int 3604alc_init_rx_ring(struct alc_softc *sc) 3605{ 3606 struct alc_ring_data *rd; 3607 struct alc_rxdesc *rxd; 3608 int i; 3609 3610 ALC_LOCK_ASSERT(sc); 3611 3612 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3613 sc->alc_morework = 0; 3614 rd = &sc->alc_rdata; 3615 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3616 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3617 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3618 rxd->rx_m = NULL; 3619 rxd->rx_desc = &rd->alc_rx_ring[i]; 3620 if (alc_newbuf(sc, rxd) != 0) 3621 return (ENOBUFS); 3622 } 3623 3624 /* 3625 * Since controller does not update Rx descriptors, driver 3626 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3627 * is enough to ensure coherence. 3628 */ 3629 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3630 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3631 /* Let controller know availability of new Rx buffers. */ 3632 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3633 3634 return (0); 3635} 3636 3637static void 3638alc_init_rr_ring(struct alc_softc *sc) 3639{ 3640 struct alc_ring_data *rd; 3641 3642 ALC_LOCK_ASSERT(sc); 3643 3644 sc->alc_cdata.alc_rr_cons = 0; 3645 ALC_RXCHAIN_RESET(sc); 3646 3647 rd = &sc->alc_rdata; 3648 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3649 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3650 sc->alc_cdata.alc_rr_ring_map, 3651 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3652} 3653 3654static void 3655alc_init_cmb(struct alc_softc *sc) 3656{ 3657 struct alc_ring_data *rd; 3658 3659 ALC_LOCK_ASSERT(sc); 3660 3661 rd = &sc->alc_rdata; 3662 bzero(rd->alc_cmb, ALC_CMB_SZ); 3663 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3665} 3666 3667static void 3668alc_init_smb(struct alc_softc *sc) 3669{ 3670 struct alc_ring_data *rd; 3671 3672 ALC_LOCK_ASSERT(sc); 3673 3674 rd = &sc->alc_rdata; 3675 bzero(rd->alc_smb, ALC_SMB_SZ); 3676 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3678} 3679 3680static void 3681alc_rxvlan(struct alc_softc *sc) 3682{ 3683 struct ifnet *ifp; 3684 uint32_t reg; 3685 3686 ALC_LOCK_ASSERT(sc); 3687 3688 ifp = sc->alc_ifp; 3689 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3690 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3691 reg |= MAC_CFG_VLAN_TAG_STRIP; 3692 else 3693 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3694 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3695} 3696 3697static void 3698alc_rxfilter(struct alc_softc *sc) 3699{ 3700 struct ifnet *ifp; 3701 struct ifmultiaddr *ifma; 3702 uint32_t crc; 3703 uint32_t mchash[2]; 3704 uint32_t rxcfg; 3705 3706 ALC_LOCK_ASSERT(sc); 3707 3708 ifp = sc->alc_ifp; 3709 3710 bzero(mchash, sizeof(mchash)); 3711 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3712 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3713 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3714 rxcfg |= MAC_CFG_BCAST; 3715 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3716 if ((ifp->if_flags & IFF_PROMISC) != 0) 3717 rxcfg |= MAC_CFG_PROMISC; 3718 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3719 rxcfg |= MAC_CFG_ALLMULTI; 3720 mchash[0] = 0xFFFFFFFF; 3721 mchash[1] = 0xFFFFFFFF; 3722 goto chipit; 3723 } 3724 3725 if_maddr_rlock(ifp); 3726 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3727 if (ifma->ifma_addr->sa_family != AF_LINK) 3728 continue; 3729 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3730 ifma->ifma_addr), ETHER_ADDR_LEN); 3731 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3732 } 3733 if_maddr_runlock(ifp); 3734 3735chipit: 3736 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3737 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3738 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3739} 3740 3741static int 3742sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3743{ 3744 int error, value; 3745 3746 if (arg1 == NULL) 3747 return (EINVAL); 3748 value = *(int *)arg1; 3749 error = sysctl_handle_int(oidp, &value, 0, req); 3750 if (error || req->newptr == NULL) 3751 return (error); 3752 if (value < low || value > high) 3753 return (EINVAL); 3754 *(int *)arg1 = value; 3755 3756 return (0); 3757} 3758 3759static int 3760sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3761{ 3762 return (sysctl_int_range(oidp, arg1, arg2, req, 3763 ALC_PROC_MIN, ALC_PROC_MAX)); 3764} 3765 3766static int 3767sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3768{ 3769 3770 return (sysctl_int_range(oidp, arg1, arg2, req, 3771 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3772} 3773