if_alc.c revision 211053
1/*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/alc/if_alc.c 211053 2010-08-08 00:43:41Z yongari $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_llc.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58#include <net/if_vlan_var.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/ip.h> 63#include <netinet/tcp.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <machine/atomic.h> 72#include <machine/bus.h> 73#include <machine/in_cksum.h> 74 75#include <dev/alc/if_alcreg.h> 76#include <dev/alc/if_alcvar.h> 77 78/* "device miibus" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80#undef ALC_USE_CUSTOM_CSUM 81 82#ifdef ALC_USE_CUSTOM_CSUM 83#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84#else 85#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86#endif 87 88MODULE_DEPEND(alc, pci, 1, 1, 1); 89MODULE_DEPEND(alc, ether, 1, 1, 1); 90MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92/* Tunables. */ 93static int msi_disable = 0; 94static int msix_disable = 0; 95TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98/* 99 * Devices supported by this driver. 100 */ 101static struct alc_dev { 102 uint16_t alc_vendorid; 103 uint16_t alc_deviceid; 104 const char *alc_name; 105} alc_devs[] = { 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 107 "Atheros AR8131 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 109 "Atheros AR8132 PCIe Fast Ethernet" } 110}; 111 112static void alc_aspm(struct alc_softc *); 113static int alc_attach(device_t); 114static int alc_check_boundary(struct alc_softc *); 115static int alc_detach(device_t); 116static void alc_disable_l0s_l1(struct alc_softc *); 117static int alc_dma_alloc(struct alc_softc *); 118static void alc_dma_free(struct alc_softc *); 119static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 120static int alc_encap(struct alc_softc *, struct mbuf **); 121#ifndef __NO_STRICT_ALIGNMENT 122static struct mbuf * 123 alc_fixup_rx(struct ifnet *, struct mbuf *); 124#endif 125static void alc_get_macaddr(struct alc_softc *); 126static void alc_init(void *); 127static void alc_init_cmb(struct alc_softc *); 128static void alc_init_locked(struct alc_softc *); 129static void alc_init_rr_ring(struct alc_softc *); 130static int alc_init_rx_ring(struct alc_softc *); 131static void alc_init_smb(struct alc_softc *); 132static void alc_init_tx_ring(struct alc_softc *); 133static void alc_int_task(void *, int); 134static int alc_intr(void *); 135static int alc_ioctl(struct ifnet *, u_long, caddr_t); 136static void alc_mac_config(struct alc_softc *); 137static int alc_miibus_readreg(device_t, int, int); 138static void alc_miibus_statchg(device_t); 139static int alc_miibus_writereg(device_t, int, int, int); 140static int alc_mediachange(struct ifnet *); 141static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 142static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 143static void alc_phy_down(struct alc_softc *); 144static void alc_phy_reset(struct alc_softc *); 145static int alc_probe(device_t); 146static void alc_reset(struct alc_softc *); 147static int alc_resume(device_t); 148static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 149static int alc_rxintr(struct alc_softc *, int); 150static void alc_rxfilter(struct alc_softc *); 151static void alc_rxvlan(struct alc_softc *); 152static void alc_setlinkspeed(struct alc_softc *); 153static void alc_setwol(struct alc_softc *); 154static int alc_shutdown(device_t); 155static void alc_start(struct ifnet *); 156static void alc_start_queue(struct alc_softc *); 157static void alc_stats_clear(struct alc_softc *); 158static void alc_stats_update(struct alc_softc *); 159static void alc_stop(struct alc_softc *); 160static void alc_stop_mac(struct alc_softc *); 161static void alc_stop_queue(struct alc_softc *); 162static int alc_suspend(device_t); 163static void alc_sysctl_node(struct alc_softc *); 164static void alc_tick(void *); 165static void alc_tx_task(void *, int); 166static void alc_txeof(struct alc_softc *); 167static void alc_watchdog(struct alc_softc *); 168static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 169static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 170static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 171 172static device_method_t alc_methods[] = { 173 /* Device interface. */ 174 DEVMETHOD(device_probe, alc_probe), 175 DEVMETHOD(device_attach, alc_attach), 176 DEVMETHOD(device_detach, alc_detach), 177 DEVMETHOD(device_shutdown, alc_shutdown), 178 DEVMETHOD(device_suspend, alc_suspend), 179 DEVMETHOD(device_resume, alc_resume), 180 181 /* MII interface. */ 182 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 183 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 184 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 185 186 { NULL, NULL } 187}; 188 189static driver_t alc_driver = { 190 "alc", 191 alc_methods, 192 sizeof(struct alc_softc) 193}; 194 195static devclass_t alc_devclass; 196 197DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 198DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 199 200static struct resource_spec alc_res_spec_mem[] = { 201 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 202 { -1, 0, 0 } 203}; 204 205static struct resource_spec alc_irq_spec_legacy[] = { 206 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 207 { -1, 0, 0 } 208}; 209 210static struct resource_spec alc_irq_spec_msi[] = { 211 { SYS_RES_IRQ, 1, RF_ACTIVE }, 212 { -1, 0, 0 } 213}; 214 215static struct resource_spec alc_irq_spec_msix[] = { 216 { SYS_RES_IRQ, 1, RF_ACTIVE }, 217 { -1, 0, 0 } 218}; 219 220static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 221 222static int 223alc_miibus_readreg(device_t dev, int phy, int reg) 224{ 225 struct alc_softc *sc; 226 uint32_t v; 227 int i; 228 229 sc = device_get_softc(dev); 230 231 if (phy != sc->alc_phyaddr) 232 return (0); 233 234 /* 235 * For AR8132 fast ethernet controller, do not report 1000baseT 236 * capability to mii(4). Even though AR8132 uses the same 237 * model/revision number of F1 gigabit PHY, the PHY has no 238 * ability to establish 1000baseT link. 239 */ 240 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 241 reg == MII_EXTSR) 242 return (0); 243 244 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(5); 248 v = CSR_READ_4(sc, ALC_MDIO); 249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250 break; 251 } 252 253 if (i == 0) { 254 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 255 return (0); 256 } 257 258 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 259} 260 261static int 262alc_miibus_writereg(device_t dev, int phy, int reg, int val) 263{ 264 struct alc_softc *sc; 265 uint32_t v; 266 int i; 267 268 sc = device_get_softc(dev); 269 270 if (phy != sc->alc_phyaddr) 271 return (0); 272 273 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 274 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 275 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 276 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 277 DELAY(5); 278 v = CSR_READ_4(sc, ALC_MDIO); 279 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 280 break; 281 } 282 283 if (i == 0) 284 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 285 286 return (0); 287} 288 289static void 290alc_miibus_statchg(device_t dev) 291{ 292 struct alc_softc *sc; 293 struct mii_data *mii; 294 struct ifnet *ifp; 295 uint32_t reg; 296 297 sc = device_get_softc(dev); 298 299 mii = device_get_softc(sc->alc_miibus); 300 ifp = sc->alc_ifp; 301 if (mii == NULL || ifp == NULL || 302 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 303 return; 304 305 sc->alc_flags &= ~ALC_FLAG_LINK; 306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 307 (IFM_ACTIVE | IFM_AVALID)) { 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_10_T: 310 case IFM_100_TX: 311 sc->alc_flags |= ALC_FLAG_LINK; 312 break; 313 case IFM_1000_T: 314 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 315 sc->alc_flags |= ALC_FLAG_LINK; 316 break; 317 default: 318 break; 319 } 320 } 321 alc_stop_queue(sc); 322 /* Stop Rx/Tx MACs. */ 323 alc_stop_mac(sc); 324 325 /* Program MACs with resolved speed/duplex/flow-control. */ 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 327 alc_start_queue(sc); 328 alc_mac_config(sc); 329 /* Re-enable Tx/Rx MACs. */ 330 reg = CSR_READ_4(sc, ALC_MAC_CFG); 331 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 332 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 333 } 334 alc_aspm(sc); 335} 336 337static void 338alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 339{ 340 struct alc_softc *sc; 341 struct mii_data *mii; 342 343 sc = ifp->if_softc; 344 ALC_LOCK(sc); 345 if ((ifp->if_flags & IFF_UP) == 0) { 346 ALC_UNLOCK(sc); 347 return; 348 } 349 mii = device_get_softc(sc->alc_miibus); 350 351 mii_pollstat(mii); 352 ALC_UNLOCK(sc); 353 ifmr->ifm_status = mii->mii_media_status; 354 ifmr->ifm_active = mii->mii_media_active; 355} 356 357static int 358alc_mediachange(struct ifnet *ifp) 359{ 360 struct alc_softc *sc; 361 struct mii_data *mii; 362 struct mii_softc *miisc; 363 int error; 364 365 sc = ifp->if_softc; 366 ALC_LOCK(sc); 367 mii = device_get_softc(sc->alc_miibus); 368 if (mii->mii_instance != 0) { 369 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 370 mii_phy_reset(miisc); 371 } 372 error = mii_mediachg(mii); 373 ALC_UNLOCK(sc); 374 375 return (error); 376} 377 378static int 379alc_probe(device_t dev) 380{ 381 struct alc_dev *sp; 382 int i; 383 uint16_t vendor, devid; 384 385 vendor = pci_get_vendor(dev); 386 devid = pci_get_device(dev); 387 sp = alc_devs; 388 for (i = 0; i < sizeof(alc_devs) / sizeof(alc_devs[0]); i++) { 389 if (vendor == sp->alc_vendorid && 390 devid == sp->alc_deviceid) { 391 device_set_desc(dev, sp->alc_name); 392 return (BUS_PROBE_DEFAULT); 393 } 394 sp++; 395 } 396 397 return (ENXIO); 398} 399 400static void 401alc_get_macaddr(struct alc_softc *sc) 402{ 403 uint32_t ea[2], opt; 404 int i; 405 406 opt = CSR_READ_4(sc, ALC_OPT_CFG); 407 if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 408 /* 409 * EEPROM found, let TWSI reload EEPROM configuration. 410 * This will set ethernet address of controller. 411 */ 412 if ((opt & OPT_CFG_CLK_ENB) == 0) { 413 opt |= OPT_CFG_CLK_ENB; 414 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 415 CSR_READ_4(sc, ALC_OPT_CFG); 416 DELAY(1000); 417 } 418 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 419 TWSI_CFG_SW_LD_START); 420 for (i = 100; i > 0; i--) { 421 DELAY(1000); 422 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 423 TWSI_CFG_SW_LD_START) == 0) 424 break; 425 } 426 if (i == 0) 427 device_printf(sc->alc_dev, 428 "reloading EEPROM timeout!\n"); 429 } else { 430 if (bootverbose) 431 device_printf(sc->alc_dev, "EEPROM not found!\n"); 432 } 433 if ((opt & OPT_CFG_CLK_ENB) != 0) { 434 opt &= ~OPT_CFG_CLK_ENB; 435 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 436 CSR_READ_4(sc, ALC_OPT_CFG); 437 DELAY(1000); 438 } 439 440 ea[0] = CSR_READ_4(sc, ALC_PAR0); 441 ea[1] = CSR_READ_4(sc, ALC_PAR1); 442 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 443 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 444 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 445 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 446 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 447 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 448} 449 450static void 451alc_disable_l0s_l1(struct alc_softc *sc) 452{ 453 uint32_t pmcfg; 454 455 /* Another magic from vendor. */ 456 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 457 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 458 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 459 PM_CFG_SERDES_PD_EX_L1); 460 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 461 PM_CFG_SERDES_L1_ENB; 462 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 463} 464 465static void 466alc_phy_reset(struct alc_softc *sc) 467{ 468 uint16_t data; 469 470 /* Reset magic from Linux. */ 471 CSR_WRITE_2(sc, ALC_GPHY_CFG, 472 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 473 CSR_READ_2(sc, ALC_GPHY_CFG); 474 DELAY(10 * 1000); 475 476 CSR_WRITE_2(sc, ALC_GPHY_CFG, 477 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 478 GPHY_CFG_SEL_ANA_RESET); 479 CSR_READ_2(sc, ALC_GPHY_CFG); 480 DELAY(10 * 1000); 481 482 /* Load DSP codes, vendor magic. */ 483 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 484 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 485 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 486 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 487 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 488 ALC_MII_DBG_DATA, data); 489 490 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 491 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 492 ANA_SERDES_EN_LCKDT; 493 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 494 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 495 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_DATA, data); 497 498 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 499 ANA_LONG_CABLE_TH_100_MASK) | 500 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 501 ANA_SHORT_CABLE_TH_100_SHIFT) | 502 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 503 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 504 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 505 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 506 ALC_MII_DBG_DATA, data); 507 508 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 509 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 510 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 511 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 512 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 513 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 514 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_DATA, data); 516 517 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 518 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 519 ANA_OEN_125M; 520 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 521 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 522 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 523 ALC_MII_DBG_DATA, data); 524 DELAY(1000); 525} 526 527static void 528alc_phy_down(struct alc_softc *sc) 529{ 530 531 /* Force PHY down. */ 532 CSR_WRITE_2(sc, ALC_GPHY_CFG, 533 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 534 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW); 535 DELAY(1000); 536} 537 538static void 539alc_aspm(struct alc_softc *sc) 540{ 541 uint32_t pmcfg; 542 543 ALC_LOCK_ASSERT(sc); 544 545 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 546 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 547 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB; 548 pmcfg |= PM_CFG_SERDES_L1_ENB; 549 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 550 pmcfg |= PM_CFG_MAC_ASPM_CHK; 551 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 552 pmcfg |= PM_CFG_SERDES_PLL_L1_ENB; 553 pmcfg &= ~PM_CFG_CLK_SWH_L1; 554 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 555 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 556 } else { 557 pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB; 558 pmcfg |= PM_CFG_CLK_SWH_L1; 559 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 560 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 561 } 562 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 563} 564 565static int 566alc_attach(device_t dev) 567{ 568 struct alc_softc *sc; 569 struct ifnet *ifp; 570 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" }; 571 uint16_t burst; 572 int base, error, i, msic, msixc, state; 573 uint32_t cap, ctl, val; 574 575 error = 0; 576 sc = device_get_softc(dev); 577 sc->alc_dev = dev; 578 579 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 580 MTX_DEF); 581 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 582 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 583 584 /* Map the device. */ 585 pci_enable_busmaster(dev); 586 sc->alc_res_spec = alc_res_spec_mem; 587 sc->alc_irq_spec = alc_irq_spec_legacy; 588 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 589 if (error != 0) { 590 device_printf(dev, "cannot allocate memory resources.\n"); 591 goto fail; 592 } 593 594 /* Set PHY address. */ 595 sc->alc_phyaddr = ALC_PHY_ADDR; 596 597 /* Initialize DMA parameters. */ 598 sc->alc_dma_rd_burst = 0; 599 sc->alc_dma_wr_burst = 0; 600 sc->alc_rcb = DMA_CFG_RCB_64; 601 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 602 sc->alc_flags |= ALC_FLAG_PCIE; 603 sc->alc_expcap = base; 604 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 605 sc->alc_dma_rd_burst = 606 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 607 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 608 if (bootverbose) { 609 device_printf(dev, "Read request size : %u bytes.\n", 610 alc_dma_burst[sc->alc_dma_rd_burst]); 611 device_printf(dev, "TLP payload size : %u bytes.\n", 612 alc_dma_burst[sc->alc_dma_wr_burst]); 613 } 614 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 615 sc->alc_dma_rd_burst = 3; 616 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 617 sc->alc_dma_wr_burst = 3; 618 /* Clear data link and flow-control protocol error. */ 619 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 620 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 621 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 622 /* Disable ASPM L0S and L1. */ 623 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 624 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 625 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 626 if ((ctl & 0x08) != 0) 627 sc->alc_rcb = DMA_CFG_RCB_128; 628 if (bootverbose) 629 device_printf(dev, "RCB %u bytes\n", 630 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 631 state = ctl & 0x03; 632 if (bootverbose) 633 device_printf(sc->alc_dev, "ASPM %s %s\n", 634 aspm_state[state], 635 state == 0 ? "disabled" : "enabled"); 636 if (state != 0) 637 alc_disable_l0s_l1(sc); 638 } 639 } 640 641 /* Reset PHY. */ 642 alc_phy_reset(sc); 643 644 /* Reset the ethernet controller. */ 645 alc_reset(sc); 646 647 /* 648 * One odd thing is AR8132 uses the same PHY hardware(F1 649 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 650 * the PHY supports 1000Mbps but that's not true. The PHY 651 * used in AR8132 can't establish gigabit link even if it 652 * shows the same PHY model/revision number of AR8131. 653 */ 654 if (pci_get_device(dev) == DEVICEID_ATHEROS_AR8132) 655 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO; 656 else 657 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON; 658 /* 659 * It seems that AR8131/AR8132 has silicon bug for SMB. In 660 * addition, Atheros said that enabling SMB wouldn't improve 661 * performance. However I think it's bad to access lots of 662 * registers to extract MAC statistics. 663 */ 664 sc->alc_flags |= ALC_FLAG_SMB_BUG; 665 /* 666 * Don't use Tx CMB. It is known to have silicon bug. 667 */ 668 sc->alc_flags |= ALC_FLAG_CMB_BUG; 669 sc->alc_rev = pci_get_revid(dev); 670 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 671 MASTER_CHIP_REV_SHIFT; 672 if (bootverbose) { 673 device_printf(dev, "PCI device revision : 0x%04x\n", 674 sc->alc_rev); 675 device_printf(dev, "Chip id/revision : 0x%04x\n", 676 sc->alc_chip_rev); 677 } 678 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 679 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 680 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 681 682 /* Allocate IRQ resources. */ 683 msixc = pci_msix_count(dev); 684 msic = pci_msi_count(dev); 685 if (bootverbose) { 686 device_printf(dev, "MSIX count : %d\n", msixc); 687 device_printf(dev, "MSI count : %d\n", msic); 688 } 689 /* Prefer MSIX over MSI. */ 690 if (msix_disable == 0 || msi_disable == 0) { 691 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 692 pci_alloc_msix(dev, &msixc) == 0) { 693 if (msic == ALC_MSIX_MESSAGES) { 694 device_printf(dev, 695 "Using %d MSIX message(s).\n", msixc); 696 sc->alc_flags |= ALC_FLAG_MSIX; 697 sc->alc_irq_spec = alc_irq_spec_msix; 698 } else 699 pci_release_msi(dev); 700 } 701 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 702 msic == ALC_MSI_MESSAGES && 703 pci_alloc_msi(dev, &msic) == 0) { 704 if (msic == ALC_MSI_MESSAGES) { 705 device_printf(dev, 706 "Using %d MSI message(s).\n", msic); 707 sc->alc_flags |= ALC_FLAG_MSI; 708 sc->alc_irq_spec = alc_irq_spec_msi; 709 } else 710 pci_release_msi(dev); 711 } 712 } 713 714 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 715 if (error != 0) { 716 device_printf(dev, "cannot allocate IRQ resources.\n"); 717 goto fail; 718 } 719 720 /* Create device sysctl node. */ 721 alc_sysctl_node(sc); 722 723 if ((error = alc_dma_alloc(sc) != 0)) 724 goto fail; 725 726 /* Load station address. */ 727 alc_get_macaddr(sc); 728 729 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 730 if (ifp == NULL) { 731 device_printf(dev, "cannot allocate ifnet structure.\n"); 732 error = ENXIO; 733 goto fail; 734 } 735 736 ifp->if_softc = sc; 737 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 738 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 739 ifp->if_ioctl = alc_ioctl; 740 ifp->if_start = alc_start; 741 ifp->if_init = alc_init; 742 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 743 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 744 IFQ_SET_READY(&ifp->if_snd); 745 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 746 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 747 if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) { 748 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 749 sc->alc_flags |= ALC_FLAG_PM; 750 sc->alc_pmcap = base; 751 } 752 ifp->if_capenable = ifp->if_capabilities; 753 754 /* Set up MII bus. */ 755 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 756 alc_mediastatus)) != 0) { 757 device_printf(dev, "no PHY found!\n"); 758 goto fail; 759 } 760 761 ether_ifattach(ifp, sc->alc_eaddr); 762 763 /* VLAN capability setup. */ 764 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 765 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 766 ifp->if_capenable = ifp->if_capabilities; 767 /* 768 * XXX 769 * It seems enabling Tx checksum offloading makes more trouble. 770 * Sometimes the controller does not receive any frames when 771 * Tx checksum offloading is enabled. I'm not sure whether this 772 * is a bug in Tx checksum offloading logic or I got broken 773 * sample boards. To safety, don't enable Tx checksum offloading 774 * by default but give chance to users to toggle it if they know 775 * their controllers work without problems. 776 */ 777 ifp->if_capenable &= ~IFCAP_TXCSUM; 778 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 779 780 /* Tell the upper layer(s) we support long frames. */ 781 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 782 783 /* Create local taskq. */ 784 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 785 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 786 taskqueue_thread_enqueue, &sc->alc_tq); 787 if (sc->alc_tq == NULL) { 788 device_printf(dev, "could not create taskqueue.\n"); 789 ether_ifdetach(ifp); 790 error = ENXIO; 791 goto fail; 792 } 793 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 794 device_get_nameunit(sc->alc_dev)); 795 796 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 797 msic = ALC_MSIX_MESSAGES; 798 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 799 msic = ALC_MSI_MESSAGES; 800 else 801 msic = 1; 802 for (i = 0; i < msic; i++) { 803 error = bus_setup_intr(dev, sc->alc_irq[i], 804 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 805 &sc->alc_intrhand[i]); 806 if (error != 0) 807 break; 808 } 809 if (error != 0) { 810 device_printf(dev, "could not set up interrupt handler.\n"); 811 taskqueue_free(sc->alc_tq); 812 sc->alc_tq = NULL; 813 ether_ifdetach(ifp); 814 goto fail; 815 } 816 817fail: 818 if (error != 0) 819 alc_detach(dev); 820 821 return (error); 822} 823 824static int 825alc_detach(device_t dev) 826{ 827 struct alc_softc *sc; 828 struct ifnet *ifp; 829 int i, msic; 830 831 sc = device_get_softc(dev); 832 833 ifp = sc->alc_ifp; 834 if (device_is_attached(dev)) { 835 ALC_LOCK(sc); 836 sc->alc_flags |= ALC_FLAG_DETACH; 837 alc_stop(sc); 838 ALC_UNLOCK(sc); 839 callout_drain(&sc->alc_tick_ch); 840 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 841 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 842 ether_ifdetach(ifp); 843 } 844 845 if (sc->alc_tq != NULL) { 846 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 847 taskqueue_free(sc->alc_tq); 848 sc->alc_tq = NULL; 849 } 850 851 if (sc->alc_miibus != NULL) { 852 device_delete_child(dev, sc->alc_miibus); 853 sc->alc_miibus = NULL; 854 } 855 bus_generic_detach(dev); 856 alc_dma_free(sc); 857 858 if (ifp != NULL) { 859 if_free(ifp); 860 sc->alc_ifp = NULL; 861 } 862 863 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 864 msic = ALC_MSIX_MESSAGES; 865 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 866 msic = ALC_MSI_MESSAGES; 867 else 868 msic = 1; 869 for (i = 0; i < msic; i++) { 870 if (sc->alc_intrhand[i] != NULL) { 871 bus_teardown_intr(dev, sc->alc_irq[i], 872 sc->alc_intrhand[i]); 873 sc->alc_intrhand[i] = NULL; 874 } 875 } 876 if (sc->alc_res[0] != NULL) 877 alc_phy_down(sc); 878 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 879 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 880 pci_release_msi(dev); 881 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 882 mtx_destroy(&sc->alc_mtx); 883 884 return (0); 885} 886 887#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 888 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 889#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 890 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 891 892static void 893alc_sysctl_node(struct alc_softc *sc) 894{ 895 struct sysctl_ctx_list *ctx; 896 struct sysctl_oid_list *child, *parent; 897 struct sysctl_oid *tree; 898 struct alc_hw_stats *stats; 899 int error; 900 901 stats = &sc->alc_stats; 902 ctx = device_get_sysctl_ctx(sc->alc_dev); 903 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 904 905 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 906 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 907 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 908 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 909 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 910 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 911 /* Pull in device tunables. */ 912 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 913 error = resource_int_value(device_get_name(sc->alc_dev), 914 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 915 if (error == 0) { 916 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 917 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 918 device_printf(sc->alc_dev, "int_rx_mod value out of " 919 "range; using default: %d\n", 920 ALC_IM_RX_TIMER_DEFAULT); 921 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 922 } 923 } 924 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 925 error = resource_int_value(device_get_name(sc->alc_dev), 926 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 927 if (error == 0) { 928 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 929 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 930 device_printf(sc->alc_dev, "int_tx_mod value out of " 931 "range; using default: %d\n", 932 ALC_IM_TX_TIMER_DEFAULT); 933 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 934 } 935 } 936 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 937 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 938 sysctl_hw_alc_proc_limit, "I", 939 "max number of Rx events to process"); 940 /* Pull in device tunables. */ 941 sc->alc_process_limit = ALC_PROC_DEFAULT; 942 error = resource_int_value(device_get_name(sc->alc_dev), 943 device_get_unit(sc->alc_dev), "process_limit", 944 &sc->alc_process_limit); 945 if (error == 0) { 946 if (sc->alc_process_limit < ALC_PROC_MIN || 947 sc->alc_process_limit > ALC_PROC_MAX) { 948 device_printf(sc->alc_dev, 949 "process_limit value out of range; " 950 "using default: %d\n", ALC_PROC_DEFAULT); 951 sc->alc_process_limit = ALC_PROC_DEFAULT; 952 } 953 } 954 955 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 956 NULL, "ALC statistics"); 957 parent = SYSCTL_CHILDREN(tree); 958 959 /* Rx statistics. */ 960 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 961 NULL, "Rx MAC statistics"); 962 child = SYSCTL_CHILDREN(tree); 963 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 964 &stats->rx_frames, "Good frames"); 965 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 966 &stats->rx_bcast_frames, "Good broadcast frames"); 967 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 968 &stats->rx_mcast_frames, "Good multicast frames"); 969 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 970 &stats->rx_pause_frames, "Pause control frames"); 971 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 972 &stats->rx_control_frames, "Control frames"); 973 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 974 &stats->rx_crcerrs, "CRC errors"); 975 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 976 &stats->rx_lenerrs, "Frames with length mismatched"); 977 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 978 &stats->rx_bytes, "Good octets"); 979 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 980 &stats->rx_bcast_bytes, "Good broadcast octets"); 981 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 982 &stats->rx_mcast_bytes, "Good multicast octets"); 983 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 984 &stats->rx_runts, "Too short frames"); 985 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 986 &stats->rx_fragments, "Fragmented frames"); 987 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 988 &stats->rx_pkts_64, "64 bytes frames"); 989 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 990 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 991 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 992 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 993 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 994 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 995 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 996 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 997 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 998 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 999 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1000 &stats->rx_pkts_1519_max, "1519 to max frames"); 1001 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1002 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1003 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1004 &stats->rx_fifo_oflows, "FIFO overflows"); 1005 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1006 &stats->rx_rrs_errs, "Return status write-back errors"); 1007 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1008 &stats->rx_alignerrs, "Alignment errors"); 1009 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1010 &stats->rx_pkts_filtered, 1011 "Frames dropped due to address filtering"); 1012 1013 /* Tx statistics. */ 1014 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1015 NULL, "Tx MAC statistics"); 1016 child = SYSCTL_CHILDREN(tree); 1017 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1018 &stats->tx_frames, "Good frames"); 1019 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1020 &stats->tx_bcast_frames, "Good broadcast frames"); 1021 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1022 &stats->tx_mcast_frames, "Good multicast frames"); 1023 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1024 &stats->tx_pause_frames, "Pause control frames"); 1025 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1026 &stats->tx_control_frames, "Control frames"); 1027 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1028 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1029 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1030 &stats->tx_excess_defer, "Frames with derferrals"); 1031 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1032 &stats->tx_bytes, "Good octets"); 1033 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1034 &stats->tx_bcast_bytes, "Good broadcast octets"); 1035 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1036 &stats->tx_mcast_bytes, "Good multicast octets"); 1037 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1038 &stats->tx_pkts_64, "64 bytes frames"); 1039 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1040 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1041 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1042 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1043 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1044 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1045 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1046 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1047 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1048 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1049 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1050 &stats->tx_pkts_1519_max, "1519 to max frames"); 1051 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1052 &stats->tx_single_colls, "Single collisions"); 1053 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1054 &stats->tx_multi_colls, "Multiple collisions"); 1055 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1056 &stats->tx_late_colls, "Late collisions"); 1057 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1058 &stats->tx_excess_colls, "Excessive collisions"); 1059 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1060 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1061 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1062 &stats->tx_underrun, "FIFO underruns"); 1063 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1064 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1065 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1066 &stats->tx_lenerrs, "Frames with length mismatched"); 1067 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1068 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1069} 1070 1071#undef ALC_SYSCTL_STAT_ADD32 1072#undef ALC_SYSCTL_STAT_ADD64 1073 1074struct alc_dmamap_arg { 1075 bus_addr_t alc_busaddr; 1076}; 1077 1078static void 1079alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1080{ 1081 struct alc_dmamap_arg *ctx; 1082 1083 if (error != 0) 1084 return; 1085 1086 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1087 1088 ctx = (struct alc_dmamap_arg *)arg; 1089 ctx->alc_busaddr = segs[0].ds_addr; 1090} 1091 1092/* 1093 * Normal and high Tx descriptors shares single Tx high address. 1094 * Four Rx descriptor/return rings and CMB shares the same Rx 1095 * high address. 1096 */ 1097static int 1098alc_check_boundary(struct alc_softc *sc) 1099{ 1100 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1101 1102 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1103 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1104 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1105 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1106 1107 /* 4GB boundary crossing is not allowed. */ 1108 if ((ALC_ADDR_HI(rx_ring_end) != 1109 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1110 (ALC_ADDR_HI(rr_ring_end) != 1111 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1112 (ALC_ADDR_HI(cmb_end) != 1113 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1114 (ALC_ADDR_HI(tx_ring_end) != 1115 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1116 return (EFBIG); 1117 /* 1118 * Make sure Rx return descriptor/Rx descriptor/CMB use 1119 * the same high address. 1120 */ 1121 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1122 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1123 return (EFBIG); 1124 1125 return (0); 1126} 1127 1128static int 1129alc_dma_alloc(struct alc_softc *sc) 1130{ 1131 struct alc_txdesc *txd; 1132 struct alc_rxdesc *rxd; 1133 bus_addr_t lowaddr; 1134 struct alc_dmamap_arg ctx; 1135 int error, i; 1136 1137 lowaddr = BUS_SPACE_MAXADDR; 1138again: 1139 /* Create parent DMA tag. */ 1140 error = bus_dma_tag_create( 1141 bus_get_dma_tag(sc->alc_dev), /* parent */ 1142 1, 0, /* alignment, boundary */ 1143 lowaddr, /* lowaddr */ 1144 BUS_SPACE_MAXADDR, /* highaddr */ 1145 NULL, NULL, /* filter, filterarg */ 1146 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1147 0, /* nsegments */ 1148 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1149 0, /* flags */ 1150 NULL, NULL, /* lockfunc, lockarg */ 1151 &sc->alc_cdata.alc_parent_tag); 1152 if (error != 0) { 1153 device_printf(sc->alc_dev, 1154 "could not create parent DMA tag.\n"); 1155 goto fail; 1156 } 1157 1158 /* Create DMA tag for Tx descriptor ring. */ 1159 error = bus_dma_tag_create( 1160 sc->alc_cdata.alc_parent_tag, /* parent */ 1161 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1162 BUS_SPACE_MAXADDR, /* lowaddr */ 1163 BUS_SPACE_MAXADDR, /* highaddr */ 1164 NULL, NULL, /* filter, filterarg */ 1165 ALC_TX_RING_SZ, /* maxsize */ 1166 1, /* nsegments */ 1167 ALC_TX_RING_SZ, /* maxsegsize */ 1168 0, /* flags */ 1169 NULL, NULL, /* lockfunc, lockarg */ 1170 &sc->alc_cdata.alc_tx_ring_tag); 1171 if (error != 0) { 1172 device_printf(sc->alc_dev, 1173 "could not create Tx ring DMA tag.\n"); 1174 goto fail; 1175 } 1176 1177 /* Create DMA tag for Rx free descriptor ring. */ 1178 error = bus_dma_tag_create( 1179 sc->alc_cdata.alc_parent_tag, /* parent */ 1180 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1181 BUS_SPACE_MAXADDR, /* lowaddr */ 1182 BUS_SPACE_MAXADDR, /* highaddr */ 1183 NULL, NULL, /* filter, filterarg */ 1184 ALC_RX_RING_SZ, /* maxsize */ 1185 1, /* nsegments */ 1186 ALC_RX_RING_SZ, /* maxsegsize */ 1187 0, /* flags */ 1188 NULL, NULL, /* lockfunc, lockarg */ 1189 &sc->alc_cdata.alc_rx_ring_tag); 1190 if (error != 0) { 1191 device_printf(sc->alc_dev, 1192 "could not create Rx ring DMA tag.\n"); 1193 goto fail; 1194 } 1195 /* Create DMA tag for Rx return descriptor ring. */ 1196 error = bus_dma_tag_create( 1197 sc->alc_cdata.alc_parent_tag, /* parent */ 1198 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1199 BUS_SPACE_MAXADDR, /* lowaddr */ 1200 BUS_SPACE_MAXADDR, /* highaddr */ 1201 NULL, NULL, /* filter, filterarg */ 1202 ALC_RR_RING_SZ, /* maxsize */ 1203 1, /* nsegments */ 1204 ALC_RR_RING_SZ, /* maxsegsize */ 1205 0, /* flags */ 1206 NULL, NULL, /* lockfunc, lockarg */ 1207 &sc->alc_cdata.alc_rr_ring_tag); 1208 if (error != 0) { 1209 device_printf(sc->alc_dev, 1210 "could not create Rx return ring DMA tag.\n"); 1211 goto fail; 1212 } 1213 1214 /* Create DMA tag for coalescing message block. */ 1215 error = bus_dma_tag_create( 1216 sc->alc_cdata.alc_parent_tag, /* parent */ 1217 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1218 BUS_SPACE_MAXADDR, /* lowaddr */ 1219 BUS_SPACE_MAXADDR, /* highaddr */ 1220 NULL, NULL, /* filter, filterarg */ 1221 ALC_CMB_SZ, /* maxsize */ 1222 1, /* nsegments */ 1223 ALC_CMB_SZ, /* maxsegsize */ 1224 0, /* flags */ 1225 NULL, NULL, /* lockfunc, lockarg */ 1226 &sc->alc_cdata.alc_cmb_tag); 1227 if (error != 0) { 1228 device_printf(sc->alc_dev, 1229 "could not create CMB DMA tag.\n"); 1230 goto fail; 1231 } 1232 /* Create DMA tag for status message block. */ 1233 error = bus_dma_tag_create( 1234 sc->alc_cdata.alc_parent_tag, /* parent */ 1235 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1236 BUS_SPACE_MAXADDR, /* lowaddr */ 1237 BUS_SPACE_MAXADDR, /* highaddr */ 1238 NULL, NULL, /* filter, filterarg */ 1239 ALC_SMB_SZ, /* maxsize */ 1240 1, /* nsegments */ 1241 ALC_SMB_SZ, /* maxsegsize */ 1242 0, /* flags */ 1243 NULL, NULL, /* lockfunc, lockarg */ 1244 &sc->alc_cdata.alc_smb_tag); 1245 if (error != 0) { 1246 device_printf(sc->alc_dev, 1247 "could not create SMB DMA tag.\n"); 1248 goto fail; 1249 } 1250 1251 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1252 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1253 (void **)&sc->alc_rdata.alc_tx_ring, 1254 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1255 &sc->alc_cdata.alc_tx_ring_map); 1256 if (error != 0) { 1257 device_printf(sc->alc_dev, 1258 "could not allocate DMA'able memory for Tx ring.\n"); 1259 goto fail; 1260 } 1261 ctx.alc_busaddr = 0; 1262 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1263 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1264 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1265 if (error != 0 || ctx.alc_busaddr == 0) { 1266 device_printf(sc->alc_dev, 1267 "could not load DMA'able memory for Tx ring.\n"); 1268 goto fail; 1269 } 1270 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1271 1272 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1273 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1274 (void **)&sc->alc_rdata.alc_rx_ring, 1275 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1276 &sc->alc_cdata.alc_rx_ring_map); 1277 if (error != 0) { 1278 device_printf(sc->alc_dev, 1279 "could not allocate DMA'able memory for Rx ring.\n"); 1280 goto fail; 1281 } 1282 ctx.alc_busaddr = 0; 1283 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1284 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1285 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1286 if (error != 0 || ctx.alc_busaddr == 0) { 1287 device_printf(sc->alc_dev, 1288 "could not load DMA'able memory for Rx ring.\n"); 1289 goto fail; 1290 } 1291 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1292 1293 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1294 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1295 (void **)&sc->alc_rdata.alc_rr_ring, 1296 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1297 &sc->alc_cdata.alc_rr_ring_map); 1298 if (error != 0) { 1299 device_printf(sc->alc_dev, 1300 "could not allocate DMA'able memory for Rx return ring.\n"); 1301 goto fail; 1302 } 1303 ctx.alc_busaddr = 0; 1304 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1305 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1306 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1307 if (error != 0 || ctx.alc_busaddr == 0) { 1308 device_printf(sc->alc_dev, 1309 "could not load DMA'able memory for Tx ring.\n"); 1310 goto fail; 1311 } 1312 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1313 1314 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1315 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1316 (void **)&sc->alc_rdata.alc_cmb, 1317 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1318 &sc->alc_cdata.alc_cmb_map); 1319 if (error != 0) { 1320 device_printf(sc->alc_dev, 1321 "could not allocate DMA'able memory for CMB.\n"); 1322 goto fail; 1323 } 1324 ctx.alc_busaddr = 0; 1325 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1326 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1327 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1328 if (error != 0 || ctx.alc_busaddr == 0) { 1329 device_printf(sc->alc_dev, 1330 "could not load DMA'able memory for CMB.\n"); 1331 goto fail; 1332 } 1333 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1334 1335 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1336 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1337 (void **)&sc->alc_rdata.alc_smb, 1338 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1339 &sc->alc_cdata.alc_smb_map); 1340 if (error != 0) { 1341 device_printf(sc->alc_dev, 1342 "could not allocate DMA'able memory for SMB.\n"); 1343 goto fail; 1344 } 1345 ctx.alc_busaddr = 0; 1346 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1347 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1348 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1349 if (error != 0 || ctx.alc_busaddr == 0) { 1350 device_printf(sc->alc_dev, 1351 "could not load DMA'able memory for CMB.\n"); 1352 goto fail; 1353 } 1354 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1355 1356 /* Make sure we've not crossed 4GB boundary. */ 1357 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1358 (error = alc_check_boundary(sc)) != 0) { 1359 device_printf(sc->alc_dev, "4GB boundary crossed, " 1360 "switching to 32bit DMA addressing mode.\n"); 1361 alc_dma_free(sc); 1362 /* 1363 * Limit max allowable DMA address space to 32bit 1364 * and try again. 1365 */ 1366 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1367 goto again; 1368 } 1369 1370 /* 1371 * Create Tx buffer parent tag. 1372 * AR8131/AR8132 allows 64bit DMA addressing of Tx/Rx buffers 1373 * so it needs separate parent DMA tag as parent DMA address 1374 * space could be restricted to be within 32bit address space 1375 * by 4GB boundary crossing. 1376 */ 1377 error = bus_dma_tag_create( 1378 bus_get_dma_tag(sc->alc_dev), /* parent */ 1379 1, 0, /* alignment, boundary */ 1380 BUS_SPACE_MAXADDR, /* lowaddr */ 1381 BUS_SPACE_MAXADDR, /* highaddr */ 1382 NULL, NULL, /* filter, filterarg */ 1383 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1384 0, /* nsegments */ 1385 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1386 0, /* flags */ 1387 NULL, NULL, /* lockfunc, lockarg */ 1388 &sc->alc_cdata.alc_buffer_tag); 1389 if (error != 0) { 1390 device_printf(sc->alc_dev, 1391 "could not create parent buffer DMA tag.\n"); 1392 goto fail; 1393 } 1394 1395 /* Create DMA tag for Tx buffers. */ 1396 error = bus_dma_tag_create( 1397 sc->alc_cdata.alc_buffer_tag, /* parent */ 1398 1, 0, /* alignment, boundary */ 1399 BUS_SPACE_MAXADDR, /* lowaddr */ 1400 BUS_SPACE_MAXADDR, /* highaddr */ 1401 NULL, NULL, /* filter, filterarg */ 1402 ALC_TSO_MAXSIZE, /* maxsize */ 1403 ALC_MAXTXSEGS, /* nsegments */ 1404 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1405 0, /* flags */ 1406 NULL, NULL, /* lockfunc, lockarg */ 1407 &sc->alc_cdata.alc_tx_tag); 1408 if (error != 0) { 1409 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1410 goto fail; 1411 } 1412 1413 /* Create DMA tag for Rx buffers. */ 1414 error = bus_dma_tag_create( 1415 sc->alc_cdata.alc_buffer_tag, /* parent */ 1416 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1417 BUS_SPACE_MAXADDR, /* lowaddr */ 1418 BUS_SPACE_MAXADDR, /* highaddr */ 1419 NULL, NULL, /* filter, filterarg */ 1420 MCLBYTES, /* maxsize */ 1421 1, /* nsegments */ 1422 MCLBYTES, /* maxsegsize */ 1423 0, /* flags */ 1424 NULL, NULL, /* lockfunc, lockarg */ 1425 &sc->alc_cdata.alc_rx_tag); 1426 if (error != 0) { 1427 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1428 goto fail; 1429 } 1430 /* Create DMA maps for Tx buffers. */ 1431 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1432 txd = &sc->alc_cdata.alc_txdesc[i]; 1433 txd->tx_m = NULL; 1434 txd->tx_dmamap = NULL; 1435 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1436 &txd->tx_dmamap); 1437 if (error != 0) { 1438 device_printf(sc->alc_dev, 1439 "could not create Tx dmamap.\n"); 1440 goto fail; 1441 } 1442 } 1443 /* Create DMA maps for Rx buffers. */ 1444 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1445 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1446 device_printf(sc->alc_dev, 1447 "could not create spare Rx dmamap.\n"); 1448 goto fail; 1449 } 1450 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1451 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1452 rxd->rx_m = NULL; 1453 rxd->rx_dmamap = NULL; 1454 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1455 &rxd->rx_dmamap); 1456 if (error != 0) { 1457 device_printf(sc->alc_dev, 1458 "could not create Rx dmamap.\n"); 1459 goto fail; 1460 } 1461 } 1462 1463fail: 1464 return (error); 1465} 1466 1467static void 1468alc_dma_free(struct alc_softc *sc) 1469{ 1470 struct alc_txdesc *txd; 1471 struct alc_rxdesc *rxd; 1472 int i; 1473 1474 /* Tx buffers. */ 1475 if (sc->alc_cdata.alc_tx_tag != NULL) { 1476 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1477 txd = &sc->alc_cdata.alc_txdesc[i]; 1478 if (txd->tx_dmamap != NULL) { 1479 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1480 txd->tx_dmamap); 1481 txd->tx_dmamap = NULL; 1482 } 1483 } 1484 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1485 sc->alc_cdata.alc_tx_tag = NULL; 1486 } 1487 /* Rx buffers */ 1488 if (sc->alc_cdata.alc_rx_tag != NULL) { 1489 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1490 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1491 if (rxd->rx_dmamap != NULL) { 1492 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1493 rxd->rx_dmamap); 1494 rxd->rx_dmamap = NULL; 1495 } 1496 } 1497 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1498 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1499 sc->alc_cdata.alc_rx_sparemap); 1500 sc->alc_cdata.alc_rx_sparemap = NULL; 1501 } 1502 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1503 sc->alc_cdata.alc_rx_tag = NULL; 1504 } 1505 /* Tx descriptor ring. */ 1506 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1507 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1508 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1509 sc->alc_cdata.alc_tx_ring_map); 1510 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1511 sc->alc_rdata.alc_tx_ring != NULL) 1512 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1513 sc->alc_rdata.alc_tx_ring, 1514 sc->alc_cdata.alc_tx_ring_map); 1515 sc->alc_rdata.alc_tx_ring = NULL; 1516 sc->alc_cdata.alc_tx_ring_map = NULL; 1517 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1518 sc->alc_cdata.alc_tx_ring_tag = NULL; 1519 } 1520 /* Rx ring. */ 1521 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1522 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1523 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1524 sc->alc_cdata.alc_rx_ring_map); 1525 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1526 sc->alc_rdata.alc_rx_ring != NULL) 1527 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1528 sc->alc_rdata.alc_rx_ring, 1529 sc->alc_cdata.alc_rx_ring_map); 1530 sc->alc_rdata.alc_rx_ring = NULL; 1531 sc->alc_cdata.alc_rx_ring_map = NULL; 1532 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1533 sc->alc_cdata.alc_rx_ring_tag = NULL; 1534 } 1535 /* Rx return ring. */ 1536 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1537 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1538 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1539 sc->alc_cdata.alc_rr_ring_map); 1540 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1541 sc->alc_rdata.alc_rr_ring != NULL) 1542 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1543 sc->alc_rdata.alc_rr_ring, 1544 sc->alc_cdata.alc_rr_ring_map); 1545 sc->alc_rdata.alc_rr_ring = NULL; 1546 sc->alc_cdata.alc_rr_ring_map = NULL; 1547 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1548 sc->alc_cdata.alc_rr_ring_tag = NULL; 1549 } 1550 /* CMB block */ 1551 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1552 if (sc->alc_cdata.alc_cmb_map != NULL) 1553 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1554 sc->alc_cdata.alc_cmb_map); 1555 if (sc->alc_cdata.alc_cmb_map != NULL && 1556 sc->alc_rdata.alc_cmb != NULL) 1557 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1558 sc->alc_rdata.alc_cmb, 1559 sc->alc_cdata.alc_cmb_map); 1560 sc->alc_rdata.alc_cmb = NULL; 1561 sc->alc_cdata.alc_cmb_map = NULL; 1562 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1563 sc->alc_cdata.alc_cmb_tag = NULL; 1564 } 1565 /* SMB block */ 1566 if (sc->alc_cdata.alc_smb_tag != NULL) { 1567 if (sc->alc_cdata.alc_smb_map != NULL) 1568 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1569 sc->alc_cdata.alc_smb_map); 1570 if (sc->alc_cdata.alc_smb_map != NULL && 1571 sc->alc_rdata.alc_smb != NULL) 1572 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1573 sc->alc_rdata.alc_smb, 1574 sc->alc_cdata.alc_smb_map); 1575 sc->alc_rdata.alc_smb = NULL; 1576 sc->alc_cdata.alc_smb_map = NULL; 1577 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1578 sc->alc_cdata.alc_smb_tag = NULL; 1579 } 1580 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1581 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1582 sc->alc_cdata.alc_buffer_tag = NULL; 1583 } 1584 if (sc->alc_cdata.alc_parent_tag != NULL) { 1585 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1586 sc->alc_cdata.alc_parent_tag = NULL; 1587 } 1588} 1589 1590static int 1591alc_shutdown(device_t dev) 1592{ 1593 1594 return (alc_suspend(dev)); 1595} 1596 1597/* 1598 * Note, this driver resets the link speed to 10/100Mbps by 1599 * restarting auto-negotiation in suspend/shutdown phase but we 1600 * don't know whether that auto-negotiation would succeed or not 1601 * as driver has no control after powering off/suspend operation. 1602 * If the renegotiation fail WOL may not work. Running at 1Gbps 1603 * will draw more power than 375mA at 3.3V which is specified in 1604 * PCI specification and that would result in complete 1605 * shutdowning power to ethernet controller. 1606 * 1607 * TODO 1608 * Save current negotiated media speed/duplex/flow-control to 1609 * softc and restore the same link again after resuming. PHY 1610 * handling such as power down/resetting to 100Mbps may be better 1611 * handled in suspend method in phy driver. 1612 */ 1613static void 1614alc_setlinkspeed(struct alc_softc *sc) 1615{ 1616 struct mii_data *mii; 1617 int aneg, i; 1618 1619 mii = device_get_softc(sc->alc_miibus); 1620 mii_pollstat(mii); 1621 aneg = 0; 1622 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1623 (IFM_ACTIVE | IFM_AVALID)) { 1624 switch IFM_SUBTYPE(mii->mii_media_active) { 1625 case IFM_10_T: 1626 case IFM_100_TX: 1627 return; 1628 case IFM_1000_T: 1629 aneg++; 1630 break; 1631 default: 1632 break; 1633 } 1634 } 1635 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1636 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1637 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1638 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1639 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1640 DELAY(1000); 1641 if (aneg != 0) { 1642 /* 1643 * Poll link state until alc(4) get a 10/100Mbps link. 1644 */ 1645 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1646 mii_pollstat(mii); 1647 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1648 == (IFM_ACTIVE | IFM_AVALID)) { 1649 switch (IFM_SUBTYPE( 1650 mii->mii_media_active)) { 1651 case IFM_10_T: 1652 case IFM_100_TX: 1653 alc_mac_config(sc); 1654 return; 1655 default: 1656 break; 1657 } 1658 } 1659 ALC_UNLOCK(sc); 1660 pause("alclnk", hz); 1661 ALC_LOCK(sc); 1662 } 1663 if (i == MII_ANEGTICKS_GIGE) 1664 device_printf(sc->alc_dev, 1665 "establishing a link failed, WOL may not work!"); 1666 } 1667 /* 1668 * No link, force MAC to have 100Mbps, full-duplex link. 1669 * This is the last resort and may/may not work. 1670 */ 1671 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1672 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1673 alc_mac_config(sc); 1674} 1675 1676static void 1677alc_setwol(struct alc_softc *sc) 1678{ 1679 struct ifnet *ifp; 1680 uint32_t reg, pmcs; 1681 uint16_t pmstat; 1682 1683 ALC_LOCK_ASSERT(sc); 1684 1685 alc_disable_l0s_l1(sc); 1686 ifp = sc->alc_ifp; 1687 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1688 /* Disable WOL. */ 1689 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1690 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1691 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1692 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1693 /* Force PHY power down. */ 1694 alc_phy_down(sc); 1695 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1696 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1697 return; 1698 } 1699 1700 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1701 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1702 alc_setlinkspeed(sc); 1703 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1704 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1705 } 1706 1707 pmcs = 0; 1708 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1709 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1710 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1711 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1712 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1713 MAC_CFG_BCAST); 1714 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1715 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1716 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1717 reg |= MAC_CFG_RX_ENB; 1718 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1719 1720 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1721 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1722 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1723 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1724 /* WOL disabled, PHY power down. */ 1725 alc_phy_down(sc); 1726 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1727 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1728 } 1729 /* Request PME. */ 1730 pmstat = pci_read_config(sc->alc_dev, 1731 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1732 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1733 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1734 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1735 pci_write_config(sc->alc_dev, 1736 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1737} 1738 1739static int 1740alc_suspend(device_t dev) 1741{ 1742 struct alc_softc *sc; 1743 1744 sc = device_get_softc(dev); 1745 1746 ALC_LOCK(sc); 1747 alc_stop(sc); 1748 alc_setwol(sc); 1749 ALC_UNLOCK(sc); 1750 1751 return (0); 1752} 1753 1754static int 1755alc_resume(device_t dev) 1756{ 1757 struct alc_softc *sc; 1758 struct ifnet *ifp; 1759 uint16_t pmstat; 1760 1761 sc = device_get_softc(dev); 1762 1763 ALC_LOCK(sc); 1764 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1765 /* Disable PME and clear PME status. */ 1766 pmstat = pci_read_config(sc->alc_dev, 1767 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1768 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1769 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1770 pci_write_config(sc->alc_dev, 1771 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1772 } 1773 } 1774 /* Reset PHY. */ 1775 alc_phy_reset(sc); 1776 ifp = sc->alc_ifp; 1777 if ((ifp->if_flags & IFF_UP) != 0) { 1778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1779 alc_init_locked(sc); 1780 } 1781 ALC_UNLOCK(sc); 1782 1783 return (0); 1784} 1785 1786static int 1787alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1788{ 1789 struct alc_txdesc *txd, *txd_last; 1790 struct tx_desc *desc; 1791 struct mbuf *m; 1792 struct ip *ip; 1793 struct tcphdr *tcp; 1794 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 1795 bus_dmamap_t map; 1796 uint32_t cflags, hdrlen, poff, vtag; 1797 int error, idx, nsegs, prod; 1798 1799 ALC_LOCK_ASSERT(sc); 1800 1801 M_ASSERTPKTHDR((*m_head)); 1802 1803 m = *m_head; 1804 ip = NULL; 1805 tcp = NULL; 1806 poff = 0; 1807 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 1808 /* 1809 * AR8131/AR8132 requires offset of TCP/UDP header in its 1810 * Tx descriptor to perform Tx checksum offloading. TSO 1811 * also requires TCP header offset and modification of 1812 * IP/TCP header. This kind of operation takes many CPU 1813 * cycles on FreeBSD so fast host CPU is required to get 1814 * smooth TSO performance. 1815 */ 1816 1817 if (M_WRITABLE(m) == 0) { 1818 /* Get a writable copy. */ 1819 m = m_dup(*m_head, M_DONTWAIT); 1820 /* Release original mbufs. */ 1821 m_freem(*m_head); 1822 if (m == NULL) { 1823 *m_head = NULL; 1824 return (ENOBUFS); 1825 } 1826 *m_head = m; 1827 } 1828 1829 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 1830 if (m == NULL) { 1831 *m_head = NULL; 1832 return (ENOBUFS); 1833 } 1834 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 1835 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 1836 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1837 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1838 if (m == NULL) { 1839 *m_head = NULL; 1840 return (ENOBUFS); 1841 } 1842 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1843 m = m_pullup(m, poff + (tcp->th_off << 2)); 1844 if (m == NULL) { 1845 *m_head = NULL; 1846 return (ENOBUFS); 1847 } 1848 /* 1849 * Due to strict adherence of Microsoft NDIS 1850 * Large Send specification, hardware expects 1851 * a pseudo TCP checksum inserted by upper 1852 * stack. Unfortunately the pseudo TCP 1853 * checksum that NDIS refers to does not include 1854 * TCP payload length so driver should recompute 1855 * the pseudo checksum here. Hopefully this 1856 * wouldn't be much burden on modern CPUs. 1857 * 1858 * Reset IP checksum and recompute TCP pseudo 1859 * checksum as NDIS specification said. 1860 */ 1861 ip->ip_sum = 0; 1862 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1863 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1864 } 1865 *m_head = m; 1866 } 1867 1868 prod = sc->alc_cdata.alc_tx_prod; 1869 txd = &sc->alc_cdata.alc_txdesc[prod]; 1870 txd_last = txd; 1871 map = txd->tx_dmamap; 1872 1873 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 1874 *m_head, txsegs, &nsegs, 0); 1875 if (error == EFBIG) { 1876 m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 1877 if (m == NULL) { 1878 m_freem(*m_head); 1879 *m_head = NULL; 1880 return (ENOMEM); 1881 } 1882 *m_head = m; 1883 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 1884 *m_head, txsegs, &nsegs, 0); 1885 if (error != 0) { 1886 m_freem(*m_head); 1887 *m_head = NULL; 1888 return (error); 1889 } 1890 } else if (error != 0) 1891 return (error); 1892 if (nsegs == 0) { 1893 m_freem(*m_head); 1894 *m_head = NULL; 1895 return (EIO); 1896 } 1897 1898 /* Check descriptor overrun. */ 1899 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1900 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 1901 return (ENOBUFS); 1902 } 1903 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 1904 1905 m = *m_head; 1906 cflags = TD_ETHERNET; 1907 vtag = 0; 1908 desc = NULL; 1909 idx = 0; 1910 /* Configure VLAN hardware tag insertion. */ 1911 if ((m->m_flags & M_VLANTAG) != 0) { 1912 vtag = htons(m->m_pkthdr.ether_vtag); 1913 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1914 cflags |= TD_INS_VLAN_TAG; 1915 } 1916 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1917 /* Request TSO and set MSS. */ 1918 cflags |= TD_TSO | TD_TSO_DESCV1; 1919 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 1920 TD_MSS_MASK; 1921 /* Set TCP header offset. */ 1922 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 1923 TD_TCPHDR_OFFSET_MASK; 1924 /* 1925 * AR8131/AR8132 requires the first buffer should 1926 * only hold IP/TCP header data. Payload should 1927 * be handled in other descriptors. 1928 */ 1929 hdrlen = poff + (tcp->th_off << 2); 1930 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1931 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 1932 desc->flags = htole32(cflags); 1933 desc->addr = htole64(txsegs[0].ds_addr); 1934 sc->alc_cdata.alc_tx_cnt++; 1935 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1936 if (m->m_len - hdrlen > 0) { 1937 /* Handle remaining payload of the first fragment. */ 1938 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1939 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 1940 vtag)); 1941 desc->flags = htole32(cflags); 1942 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1943 sc->alc_cdata.alc_tx_cnt++; 1944 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1945 } 1946 /* Handle remaining fragments. */ 1947 idx = 1; 1948 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1949 /* Configure Tx checksum offload. */ 1950#ifdef ALC_USE_CUSTOM_CSUM 1951 cflags |= TD_CUSTOM_CSUM; 1952 /* Set checksum start offset. */ 1953 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1954 TD_PLOAD_OFFSET_MASK; 1955 /* Set checksum insertion position of TCP/UDP. */ 1956 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 1957 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 1958#else 1959 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1960 cflags |= TD_IPCSUM; 1961 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1962 cflags |= TD_TCPCSUM; 1963 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1964 cflags |= TD_UDPCSUM; 1965 /* Set TCP/UDP header offset. */ 1966 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 1967 TD_L4HDR_OFFSET_MASK; 1968#endif 1969 } 1970 for (; idx < nsegs; idx++) { 1971 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1972 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 1973 desc->flags = htole32(cflags); 1974 desc->addr = htole64(txsegs[idx].ds_addr); 1975 sc->alc_cdata.alc_tx_cnt++; 1976 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1977 } 1978 /* Update producer index. */ 1979 sc->alc_cdata.alc_tx_prod = prod; 1980 1981 /* Finally set EOP on the last descriptor. */ 1982 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1983 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1984 desc->flags |= htole32(TD_EOP); 1985 1986 /* Swap dmamap of the first and the last. */ 1987 txd = &sc->alc_cdata.alc_txdesc[prod]; 1988 map = txd_last->tx_dmamap; 1989 txd_last->tx_dmamap = txd->tx_dmamap; 1990 txd->tx_dmamap = map; 1991 txd->tx_m = m; 1992 1993 return (0); 1994} 1995 1996static void 1997alc_tx_task(void *arg, int pending) 1998{ 1999 struct ifnet *ifp; 2000 2001 ifp = (struct ifnet *)arg; 2002 alc_start(ifp); 2003} 2004 2005static void 2006alc_start(struct ifnet *ifp) 2007{ 2008 struct alc_softc *sc; 2009 struct mbuf *m_head; 2010 int enq; 2011 2012 sc = ifp->if_softc; 2013 2014 ALC_LOCK(sc); 2015 2016 /* Reclaim transmitted frames. */ 2017 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2018 alc_txeof(sc); 2019 2020 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2021 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) { 2022 ALC_UNLOCK(sc); 2023 return; 2024 } 2025 2026 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2027 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2028 if (m_head == NULL) 2029 break; 2030 /* 2031 * Pack the data into the transmit ring. If we 2032 * don't have room, set the OACTIVE flag and wait 2033 * for the NIC to drain the ring. 2034 */ 2035 if (alc_encap(sc, &m_head)) { 2036 if (m_head == NULL) 2037 break; 2038 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2039 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2040 break; 2041 } 2042 2043 enq++; 2044 /* 2045 * If there's a BPF listener, bounce a copy of this frame 2046 * to him. 2047 */ 2048 ETHER_BPF_MTAP(ifp, m_head); 2049 } 2050 2051 if (enq > 0) { 2052 /* Sync descriptors. */ 2053 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2054 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2055 /* Kick. Assume we're using normal Tx priority queue. */ 2056 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2057 (sc->alc_cdata.alc_tx_prod << 2058 MBOX_TD_PROD_LO_IDX_SHIFT) & 2059 MBOX_TD_PROD_LO_IDX_MASK); 2060 /* Set a timeout in case the chip goes out to lunch. */ 2061 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2062 } 2063 2064 ALC_UNLOCK(sc); 2065} 2066 2067static void 2068alc_watchdog(struct alc_softc *sc) 2069{ 2070 struct ifnet *ifp; 2071 2072 ALC_LOCK_ASSERT(sc); 2073 2074 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2075 return; 2076 2077 ifp = sc->alc_ifp; 2078 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2079 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2080 ifp->if_oerrors++; 2081 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2082 alc_init_locked(sc); 2083 return; 2084 } 2085 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2086 ifp->if_oerrors++; 2087 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2088 alc_init_locked(sc); 2089 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2090 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2091} 2092 2093static int 2094alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2095{ 2096 struct alc_softc *sc; 2097 struct ifreq *ifr; 2098 struct mii_data *mii; 2099 int error, mask; 2100 2101 sc = ifp->if_softc; 2102 ifr = (struct ifreq *)data; 2103 error = 0; 2104 switch (cmd) { 2105 case SIOCSIFMTU: 2106 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALC_JUMBO_MTU || 2107 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2108 ifr->ifr_mtu > ETHERMTU)) 2109 error = EINVAL; 2110 else if (ifp->if_mtu != ifr->ifr_mtu) { 2111 ALC_LOCK(sc); 2112 ifp->if_mtu = ifr->ifr_mtu; 2113 /* AR8131/AR8132 has 13 bits MSS field. */ 2114 if (ifp->if_mtu > ALC_TSO_MTU && 2115 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2116 ifp->if_capenable &= ~IFCAP_TSO4; 2117 ifp->if_hwassist &= ~CSUM_TSO; 2118 VLAN_CAPABILITIES(ifp); 2119 } 2120 ALC_UNLOCK(sc); 2121 } 2122 break; 2123 case SIOCSIFFLAGS: 2124 ALC_LOCK(sc); 2125 if ((ifp->if_flags & IFF_UP) != 0) { 2126 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2127 ((ifp->if_flags ^ sc->alc_if_flags) & 2128 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2129 alc_rxfilter(sc); 2130 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2131 alc_init_locked(sc); 2132 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2133 alc_stop(sc); 2134 sc->alc_if_flags = ifp->if_flags; 2135 ALC_UNLOCK(sc); 2136 break; 2137 case SIOCADDMULTI: 2138 case SIOCDELMULTI: 2139 ALC_LOCK(sc); 2140 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2141 alc_rxfilter(sc); 2142 ALC_UNLOCK(sc); 2143 break; 2144 case SIOCSIFMEDIA: 2145 case SIOCGIFMEDIA: 2146 mii = device_get_softc(sc->alc_miibus); 2147 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2148 break; 2149 case SIOCSIFCAP: 2150 ALC_LOCK(sc); 2151 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2152 if ((mask & IFCAP_TXCSUM) != 0 && 2153 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2154 ifp->if_capenable ^= IFCAP_TXCSUM; 2155 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2156 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2157 else 2158 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2159 } 2160 if ((mask & IFCAP_TSO4) != 0 && 2161 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2162 ifp->if_capenable ^= IFCAP_TSO4; 2163 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2164 /* AR8131/AR8132 has 13 bits MSS field. */ 2165 if (ifp->if_mtu > ALC_TSO_MTU) { 2166 ifp->if_capenable &= ~IFCAP_TSO4; 2167 ifp->if_hwassist &= ~CSUM_TSO; 2168 } else 2169 ifp->if_hwassist |= CSUM_TSO; 2170 } else 2171 ifp->if_hwassist &= ~CSUM_TSO; 2172 } 2173 if ((mask & IFCAP_WOL_MCAST) != 0 && 2174 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2175 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2176 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2177 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2178 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2179 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2180 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2181 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2182 alc_rxvlan(sc); 2183 } 2184 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2185 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2186 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2187 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2188 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2189 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2190 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2191 ifp->if_capenable &= 2192 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2193 ALC_UNLOCK(sc); 2194 VLAN_CAPABILITIES(ifp); 2195 break; 2196 default: 2197 error = ether_ioctl(ifp, cmd, data); 2198 break; 2199 } 2200 2201 return (error); 2202} 2203 2204static void 2205alc_mac_config(struct alc_softc *sc) 2206{ 2207 struct mii_data *mii; 2208 uint32_t reg; 2209 2210 ALC_LOCK_ASSERT(sc); 2211 2212 mii = device_get_softc(sc->alc_miibus); 2213 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2214 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2215 MAC_CFG_SPEED_MASK); 2216 /* Reprogram MAC with resolved speed/duplex. */ 2217 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2218 case IFM_10_T: 2219 case IFM_100_TX: 2220 reg |= MAC_CFG_SPEED_10_100; 2221 break; 2222 case IFM_1000_T: 2223 reg |= MAC_CFG_SPEED_1000; 2224 break; 2225 } 2226 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2227 reg |= MAC_CFG_FULL_DUPLEX; 2228#ifdef notyet 2229 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2230 reg |= MAC_CFG_TX_FC; 2231 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2232 reg |= MAC_CFG_RX_FC; 2233#endif 2234 } 2235 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2236} 2237 2238static void 2239alc_stats_clear(struct alc_softc *sc) 2240{ 2241 struct smb sb, *smb; 2242 uint32_t *reg; 2243 int i; 2244 2245 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2246 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2247 sc->alc_cdata.alc_smb_map, 2248 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2249 smb = sc->alc_rdata.alc_smb; 2250 /* Update done, clear. */ 2251 smb->updated = 0; 2252 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2253 sc->alc_cdata.alc_smb_map, 2254 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2255 } else { 2256 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2257 reg++) { 2258 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2259 i += sizeof(uint32_t); 2260 } 2261 /* Read Tx statistics. */ 2262 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2263 reg++) { 2264 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2265 i += sizeof(uint32_t); 2266 } 2267 } 2268} 2269 2270static void 2271alc_stats_update(struct alc_softc *sc) 2272{ 2273 struct alc_hw_stats *stat; 2274 struct smb sb, *smb; 2275 struct ifnet *ifp; 2276 uint32_t *reg; 2277 int i; 2278 2279 ALC_LOCK_ASSERT(sc); 2280 2281 ifp = sc->alc_ifp; 2282 stat = &sc->alc_stats; 2283 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2284 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2285 sc->alc_cdata.alc_smb_map, 2286 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2287 smb = sc->alc_rdata.alc_smb; 2288 if (smb->updated == 0) 2289 return; 2290 } else { 2291 smb = &sb; 2292 /* Read Rx statistics. */ 2293 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2294 reg++) { 2295 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2296 i += sizeof(uint32_t); 2297 } 2298 /* Read Tx statistics. */ 2299 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2300 reg++) { 2301 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2302 i += sizeof(uint32_t); 2303 } 2304 } 2305 2306 /* Rx stats. */ 2307 stat->rx_frames += smb->rx_frames; 2308 stat->rx_bcast_frames += smb->rx_bcast_frames; 2309 stat->rx_mcast_frames += smb->rx_mcast_frames; 2310 stat->rx_pause_frames += smb->rx_pause_frames; 2311 stat->rx_control_frames += smb->rx_control_frames; 2312 stat->rx_crcerrs += smb->rx_crcerrs; 2313 stat->rx_lenerrs += smb->rx_lenerrs; 2314 stat->rx_bytes += smb->rx_bytes; 2315 stat->rx_runts += smb->rx_runts; 2316 stat->rx_fragments += smb->rx_fragments; 2317 stat->rx_pkts_64 += smb->rx_pkts_64; 2318 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2319 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2320 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2321 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2322 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2323 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2324 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2325 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2326 stat->rx_rrs_errs += smb->rx_rrs_errs; 2327 stat->rx_alignerrs += smb->rx_alignerrs; 2328 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2329 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2330 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2331 2332 /* Tx stats. */ 2333 stat->tx_frames += smb->tx_frames; 2334 stat->tx_bcast_frames += smb->tx_bcast_frames; 2335 stat->tx_mcast_frames += smb->tx_mcast_frames; 2336 stat->tx_pause_frames += smb->tx_pause_frames; 2337 stat->tx_excess_defer += smb->tx_excess_defer; 2338 stat->tx_control_frames += smb->tx_control_frames; 2339 stat->tx_deferred += smb->tx_deferred; 2340 stat->tx_bytes += smb->tx_bytes; 2341 stat->tx_pkts_64 += smb->tx_pkts_64; 2342 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2343 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2344 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2345 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2346 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2347 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2348 stat->tx_single_colls += smb->tx_single_colls; 2349 stat->tx_multi_colls += smb->tx_multi_colls; 2350 stat->tx_late_colls += smb->tx_late_colls; 2351 stat->tx_excess_colls += smb->tx_excess_colls; 2352 stat->tx_abort += smb->tx_abort; 2353 stat->tx_underrun += smb->tx_underrun; 2354 stat->tx_desc_underrun += smb->tx_desc_underrun; 2355 stat->tx_lenerrs += smb->tx_lenerrs; 2356 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2357 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2358 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2359 2360 /* Update counters in ifnet. */ 2361 ifp->if_opackets += smb->tx_frames; 2362 2363 ifp->if_collisions += smb->tx_single_colls + 2364 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2365 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2366 2367 /* 2368 * XXX 2369 * tx_pkts_truncated counter looks suspicious. It constantly 2370 * increments with no sign of Tx errors. This may indicate 2371 * the counter name is not correct one so I've removed the 2372 * counter in output errors. 2373 */ 2374 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2375 smb->tx_underrun; 2376 2377 ifp->if_ipackets += smb->rx_frames; 2378 2379 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2380 smb->rx_runts + smb->rx_pkts_truncated + 2381 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2382 smb->rx_alignerrs; 2383 2384 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2385 /* Update done, clear. */ 2386 smb->updated = 0; 2387 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2388 sc->alc_cdata.alc_smb_map, 2389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2390 } 2391} 2392 2393static int 2394alc_intr(void *arg) 2395{ 2396 struct alc_softc *sc; 2397 uint32_t status; 2398 2399 sc = (struct alc_softc *)arg; 2400 2401 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2402 if ((status & ALC_INTRS) == 0) 2403 return (FILTER_STRAY); 2404 /* Disable interrupts. */ 2405 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2406 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2407 2408 return (FILTER_HANDLED); 2409} 2410 2411static void 2412alc_int_task(void *arg, int pending) 2413{ 2414 struct alc_softc *sc; 2415 struct ifnet *ifp; 2416 uint32_t status; 2417 int more; 2418 2419 sc = (struct alc_softc *)arg; 2420 ifp = sc->alc_ifp; 2421 2422 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2423 more = atomic_readandclear_int(&sc->alc_morework); 2424 if (more != 0) 2425 status |= INTR_RX_PKT; 2426 if ((status & ALC_INTRS) == 0) 2427 goto done; 2428 2429 /* Acknowledge interrupts but still disable interrupts. */ 2430 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2431 2432 more = 0; 2433 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2434 if ((status & INTR_RX_PKT) != 0) { 2435 more = alc_rxintr(sc, sc->alc_process_limit); 2436 if (more == EAGAIN) 2437 atomic_set_int(&sc->alc_morework, 1); 2438 else if (more == EIO) { 2439 ALC_LOCK(sc); 2440 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2441 alc_init_locked(sc); 2442 ALC_UNLOCK(sc); 2443 return; 2444 } 2445 } 2446 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2447 INTR_TXQ_TO_RST)) != 0) { 2448 if ((status & INTR_DMA_RD_TO_RST) != 0) 2449 device_printf(sc->alc_dev, 2450 "DMA read error! -- resetting\n"); 2451 if ((status & INTR_DMA_WR_TO_RST) != 0) 2452 device_printf(sc->alc_dev, 2453 "DMA write error! -- resetting\n"); 2454 if ((status & INTR_TXQ_TO_RST) != 0) 2455 device_printf(sc->alc_dev, 2456 "TxQ reset! -- resetting\n"); 2457 ALC_LOCK(sc); 2458 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2459 alc_init_locked(sc); 2460 ALC_UNLOCK(sc); 2461 return; 2462 } 2463 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2464 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2465 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2466 } 2467 2468 if (more == EAGAIN || 2469 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2470 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2471 return; 2472 } 2473 2474done: 2475 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2476 /* Re-enable interrupts if we're running. */ 2477 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2478 } 2479} 2480 2481static void 2482alc_txeof(struct alc_softc *sc) 2483{ 2484 struct ifnet *ifp; 2485 struct alc_txdesc *txd; 2486 uint32_t cons, prod; 2487 int prog; 2488 2489 ALC_LOCK_ASSERT(sc); 2490 2491 ifp = sc->alc_ifp; 2492 2493 if (sc->alc_cdata.alc_tx_cnt == 0) 2494 return; 2495 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2496 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2497 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2498 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2499 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2500 prod = sc->alc_rdata.alc_cmb->cons; 2501 } else 2502 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2503 /* Assume we're using normal Tx priority queue. */ 2504 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2505 MBOX_TD_CONS_LO_IDX_SHIFT; 2506 cons = sc->alc_cdata.alc_tx_cons; 2507 /* 2508 * Go through our Tx list and free mbufs for those 2509 * frames which have been transmitted. 2510 */ 2511 for (prog = 0; cons != prod; prog++, 2512 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2513 if (sc->alc_cdata.alc_tx_cnt <= 0) 2514 break; 2515 prog++; 2516 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2517 sc->alc_cdata.alc_tx_cnt--; 2518 txd = &sc->alc_cdata.alc_txdesc[cons]; 2519 if (txd->tx_m != NULL) { 2520 /* Reclaim transmitted mbufs. */ 2521 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2522 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2523 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2524 txd->tx_dmamap); 2525 m_freem(txd->tx_m); 2526 txd->tx_m = NULL; 2527 } 2528 } 2529 2530 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2531 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2532 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2533 sc->alc_cdata.alc_tx_cons = cons; 2534 /* 2535 * Unarm watchdog timer only when there is no pending 2536 * frames in Tx queue. 2537 */ 2538 if (sc->alc_cdata.alc_tx_cnt == 0) 2539 sc->alc_watchdog_timer = 0; 2540} 2541 2542static int 2543alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2544{ 2545 struct mbuf *m; 2546 bus_dma_segment_t segs[1]; 2547 bus_dmamap_t map; 2548 int nsegs; 2549 2550 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2551 if (m == NULL) 2552 return (ENOBUFS); 2553 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2554#ifndef __NO_STRICT_ALIGNMENT 2555 m_adj(m, sizeof(uint64_t)); 2556#endif 2557 2558 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2559 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2560 m_freem(m); 2561 return (ENOBUFS); 2562 } 2563 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2564 2565 if (rxd->rx_m != NULL) { 2566 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2567 BUS_DMASYNC_POSTREAD); 2568 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2569 } 2570 map = rxd->rx_dmamap; 2571 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2572 sc->alc_cdata.alc_rx_sparemap = map; 2573 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2574 BUS_DMASYNC_PREREAD); 2575 rxd->rx_m = m; 2576 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2577 return (0); 2578} 2579 2580static int 2581alc_rxintr(struct alc_softc *sc, int count) 2582{ 2583 struct ifnet *ifp; 2584 struct rx_rdesc *rrd; 2585 uint32_t nsegs, status; 2586 int rr_cons, prog; 2587 2588 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2589 sc->alc_cdata.alc_rr_ring_map, 2590 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2591 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2592 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2593 rr_cons = sc->alc_cdata.alc_rr_cons; 2594 ifp = sc->alc_ifp; 2595 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2596 if (count-- <= 0) 2597 break; 2598 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2599 status = le32toh(rrd->status); 2600 if ((status & RRD_VALID) == 0) 2601 break; 2602 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2603 if (nsegs == 0) { 2604 /* This should not happen! */ 2605 device_printf(sc->alc_dev, 2606 "unexpected segment count -- resetting\n"); 2607 return (EIO); 2608 } 2609 alc_rxeof(sc, rrd); 2610 /* Clear Rx return status. */ 2611 rrd->status = 0; 2612 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2613 sc->alc_cdata.alc_rx_cons += nsegs; 2614 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2615 prog += nsegs; 2616 } 2617 2618 if (prog > 0) { 2619 /* Update the consumer index. */ 2620 sc->alc_cdata.alc_rr_cons = rr_cons; 2621 /* Sync Rx return descriptors. */ 2622 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2623 sc->alc_cdata.alc_rr_ring_map, 2624 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2625 /* 2626 * Sync updated Rx descriptors such that controller see 2627 * modified buffer addresses. 2628 */ 2629 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2630 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2631 /* 2632 * Let controller know availability of new Rx buffers. 2633 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2634 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2635 * only when Rx buffer pre-fetching is required. In 2636 * addition we already set ALC_RX_RD_FREE_THRESH to 2637 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2638 * it still seems that pre-fetching needs more 2639 * experimentation. 2640 */ 2641 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2642 sc->alc_cdata.alc_rx_cons); 2643 } 2644 2645 return (count > 0 ? 0 : EAGAIN); 2646} 2647 2648#ifndef __NO_STRICT_ALIGNMENT 2649static struct mbuf * 2650alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2651{ 2652 struct mbuf *n; 2653 int i; 2654 uint16_t *src, *dst; 2655 2656 src = mtod(m, uint16_t *); 2657 dst = src - 3; 2658 2659 if (m->m_next == NULL) { 2660 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2661 *dst++ = *src++; 2662 m->m_data -= 6; 2663 return (m); 2664 } 2665 /* 2666 * Append a new mbuf to received mbuf chain and copy ethernet 2667 * header from the mbuf chain. This can save lots of CPU 2668 * cycles for jumbo frame. 2669 */ 2670 MGETHDR(n, M_DONTWAIT, MT_DATA); 2671 if (n == NULL) { 2672 ifp->if_iqdrops++; 2673 m_freem(m); 2674 return (NULL); 2675 } 2676 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2677 m->m_data += ETHER_HDR_LEN; 2678 m->m_len -= ETHER_HDR_LEN; 2679 n->m_len = ETHER_HDR_LEN; 2680 M_MOVE_PKTHDR(n, m); 2681 n->m_next = m; 2682 return (n); 2683} 2684#endif 2685 2686/* Receive a frame. */ 2687static void 2688alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2689{ 2690 struct alc_rxdesc *rxd; 2691 struct ifnet *ifp; 2692 struct mbuf *mp, *m; 2693 uint32_t rdinfo, status, vtag; 2694 int count, nsegs, rx_cons; 2695 2696 ifp = sc->alc_ifp; 2697 status = le32toh(rrd->status); 2698 rdinfo = le32toh(rrd->rdinfo); 2699 rx_cons = RRD_RD_IDX(rdinfo); 2700 nsegs = RRD_RD_CNT(rdinfo); 2701 2702 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2703 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2704 /* 2705 * We want to pass the following frames to upper 2706 * layer regardless of error status of Rx return 2707 * ring. 2708 * 2709 * o IP/TCP/UDP checksum is bad. 2710 * o frame length and protocol specific length 2711 * does not match. 2712 * 2713 * Force network stack compute checksum for 2714 * errored frames. 2715 */ 2716 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2717 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 2718 RRD_ERR_RUNT) != 0) 2719 return; 2720 } 2721 2722 for (count = 0; count < nsegs; count++, 2723 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2724 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2725 mp = rxd->rx_m; 2726 /* Add a new receive buffer to the ring. */ 2727 if (alc_newbuf(sc, rxd) != 0) { 2728 ifp->if_iqdrops++; 2729 /* Reuse Rx buffers. */ 2730 if (sc->alc_cdata.alc_rxhead != NULL) 2731 m_freem(sc->alc_cdata.alc_rxhead); 2732 break; 2733 } 2734 2735 /* 2736 * Assume we've received a full sized frame. 2737 * Actual size is fixed when we encounter the end of 2738 * multi-segmented frame. 2739 */ 2740 mp->m_len = sc->alc_buf_size; 2741 2742 /* Chain received mbufs. */ 2743 if (sc->alc_cdata.alc_rxhead == NULL) { 2744 sc->alc_cdata.alc_rxhead = mp; 2745 sc->alc_cdata.alc_rxtail = mp; 2746 } else { 2747 mp->m_flags &= ~M_PKTHDR; 2748 sc->alc_cdata.alc_rxprev_tail = 2749 sc->alc_cdata.alc_rxtail; 2750 sc->alc_cdata.alc_rxtail->m_next = mp; 2751 sc->alc_cdata.alc_rxtail = mp; 2752 } 2753 2754 if (count == nsegs - 1) { 2755 /* Last desc. for this frame. */ 2756 m = sc->alc_cdata.alc_rxhead; 2757 m->m_flags |= M_PKTHDR; 2758 /* 2759 * It seems that L1C/L2C controller has no way 2760 * to tell hardware to strip CRC bytes. 2761 */ 2762 m->m_pkthdr.len = 2763 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2764 if (nsegs > 1) { 2765 /* Set last mbuf size. */ 2766 mp->m_len = sc->alc_cdata.alc_rxlen - 2767 (nsegs - 1) * sc->alc_buf_size; 2768 /* Remove the CRC bytes in chained mbufs. */ 2769 if (mp->m_len <= ETHER_CRC_LEN) { 2770 sc->alc_cdata.alc_rxtail = 2771 sc->alc_cdata.alc_rxprev_tail; 2772 sc->alc_cdata.alc_rxtail->m_len -= 2773 (ETHER_CRC_LEN - mp->m_len); 2774 sc->alc_cdata.alc_rxtail->m_next = NULL; 2775 m_freem(mp); 2776 } else { 2777 mp->m_len -= ETHER_CRC_LEN; 2778 } 2779 } else 2780 m->m_len = m->m_pkthdr.len; 2781 m->m_pkthdr.rcvif = ifp; 2782 /* 2783 * Due to hardware bugs, Rx checksum offloading 2784 * was intentionally disabled. 2785 */ 2786 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2787 (status & RRD_VLAN_TAG) != 0) { 2788 vtag = RRD_VLAN(le32toh(rrd->vtag)); 2789 m->m_pkthdr.ether_vtag = ntohs(vtag); 2790 m->m_flags |= M_VLANTAG; 2791 } 2792#ifndef __NO_STRICT_ALIGNMENT 2793 m = alc_fixup_rx(ifp, m); 2794 if (m != NULL) 2795#endif 2796 { 2797 /* Pass it on. */ 2798 (*ifp->if_input)(ifp, m); 2799 } 2800 } 2801 } 2802 /* Reset mbuf chains. */ 2803 ALC_RXCHAIN_RESET(sc); 2804} 2805 2806static void 2807alc_tick(void *arg) 2808{ 2809 struct alc_softc *sc; 2810 struct mii_data *mii; 2811 2812 sc = (struct alc_softc *)arg; 2813 2814 ALC_LOCK_ASSERT(sc); 2815 2816 mii = device_get_softc(sc->alc_miibus); 2817 mii_tick(mii); 2818 alc_stats_update(sc); 2819 /* 2820 * alc(4) does not rely on Tx completion interrupts to reclaim 2821 * transferred buffers. Instead Tx completion interrupts are 2822 * used to hint for scheduling Tx task. So it's necessary to 2823 * release transmitted buffers by kicking Tx completion 2824 * handler. This limits the maximum reclamation delay to a hz. 2825 */ 2826 alc_txeof(sc); 2827 alc_watchdog(sc); 2828 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 2829} 2830 2831static void 2832alc_reset(struct alc_softc *sc) 2833{ 2834 uint32_t reg; 2835 int i; 2836 2837 CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET); 2838 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2839 DELAY(10); 2840 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2841 break; 2842 } 2843 if (i == 0) 2844 device_printf(sc->alc_dev, "master reset timeout!\n"); 2845 2846 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2847 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2848 break; 2849 DELAY(10); 2850 } 2851 2852 if (i == 0) 2853 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 2854} 2855 2856static void 2857alc_init(void *xsc) 2858{ 2859 struct alc_softc *sc; 2860 2861 sc = (struct alc_softc *)xsc; 2862 ALC_LOCK(sc); 2863 alc_init_locked(sc); 2864 ALC_UNLOCK(sc); 2865} 2866 2867static void 2868alc_init_locked(struct alc_softc *sc) 2869{ 2870 struct ifnet *ifp; 2871 struct mii_data *mii; 2872 uint8_t eaddr[ETHER_ADDR_LEN]; 2873 bus_addr_t paddr; 2874 uint32_t reg, rxf_hi, rxf_lo; 2875 2876 ALC_LOCK_ASSERT(sc); 2877 2878 ifp = sc->alc_ifp; 2879 mii = device_get_softc(sc->alc_miibus); 2880 2881 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2882 return; 2883 /* 2884 * Cancel any pending I/O. 2885 */ 2886 alc_stop(sc); 2887 /* 2888 * Reset the chip to a known state. 2889 */ 2890 alc_reset(sc); 2891 2892 /* Initialize Rx descriptors. */ 2893 if (alc_init_rx_ring(sc) != 0) { 2894 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 2895 alc_stop(sc); 2896 return; 2897 } 2898 alc_init_rr_ring(sc); 2899 alc_init_tx_ring(sc); 2900 alc_init_cmb(sc); 2901 alc_init_smb(sc); 2902 2903 /* Reprogram the station address. */ 2904 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2905 CSR_WRITE_4(sc, ALC_PAR0, 2906 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2907 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2908 /* 2909 * Clear WOL status and disable all WOL feature as WOL 2910 * would interfere Rx operation under normal environments. 2911 */ 2912 CSR_READ_4(sc, ALC_WOL_CFG); 2913 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2914 /* Set Tx descriptor base addresses. */ 2915 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2916 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2917 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2918 /* We don't use high priority ring. */ 2919 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2920 /* Set Tx descriptor counter. */ 2921 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2922 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2923 /* Set Rx descriptor base addresses. */ 2924 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2925 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2926 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2927 /* We use one Rx ring. */ 2928 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2929 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2930 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2931 /* Set Rx descriptor counter. */ 2932 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2933 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2934 2935 /* 2936 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2937 * if it do not fit the buffer size. Rx return descriptor holds 2938 * a counter that indicates how many fragments were made by the 2939 * hardware. The buffer size should be multiple of 8 bytes. 2940 * Since hardware has limit on the size of buffer size, always 2941 * use the maximum value. 2942 * For strict-alignment architectures make sure to reduce buffer 2943 * size by 8 bytes to make room for alignment fixup. 2944 */ 2945#ifndef __NO_STRICT_ALIGNMENT 2946 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 2947#else 2948 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2949#endif 2950 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2951 2952 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2953 /* Set Rx return descriptor base addresses. */ 2954 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2955 /* We use one Rx return ring. */ 2956 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2957 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2958 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2959 /* Set Rx return descriptor counter. */ 2960 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2961 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2962 paddr = sc->alc_rdata.alc_cmb_paddr; 2963 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2964 paddr = sc->alc_rdata.alc_smb_paddr; 2965 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2966 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2967 2968 /* Tell hardware that we're ready to load DMA blocks. */ 2969 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2970 2971 /* Configure interrupt moderation timer. */ 2972 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2973 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2974 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2975 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2976 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2977 /* 2978 * We don't want to automatic interrupt clear as task queue 2979 * for the interrupt should know interrupt status. 2980 */ 2981 reg &= ~MASTER_INTR_RD_CLR; 2982 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2983 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2984 reg |= MASTER_IM_RX_TIMER_ENB; 2985 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 2986 reg |= MASTER_IM_TX_TIMER_ENB; 2987 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 2988 /* 2989 * Disable interrupt re-trigger timer. We don't want automatic 2990 * re-triggering of un-ACKed interrupts. 2991 */ 2992 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 2993 /* Configure CMB. */ 2994 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2995 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 2996 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 2997 } else 2998 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 2999 /* 3000 * Hardware can be configured to issue SMB interrupt based 3001 * on programmed interval. Since there is a callout that is 3002 * invoked for every hz in driver we use that instead of 3003 * relying on periodic SMB interrupt. 3004 */ 3005 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3006 /* Clear MAC statistics. */ 3007 alc_stats_clear(sc); 3008 3009 /* 3010 * Always use maximum frame size that controller can support. 3011 * Otherwise received frames that has larger frame length 3012 * than alc(4) MTU would be silently dropped in hardware. This 3013 * would make path-MTU discovery hard as sender wouldn't get 3014 * any responses from receiver. alc(4) supports 3015 * multi-fragmented frames on Rx path so it has no issue on 3016 * assembling fragmented frames. Using maximum frame size also 3017 * removes the need to reinitialize hardware when interface 3018 * MTU configuration was changed. 3019 * 3020 * Be conservative in what you do, be liberal in what you 3021 * accept from others - RFC 793. 3022 */ 3023 CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN); 3024 3025 /* Disable header split(?) */ 3026 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3027 3028 /* Configure IPG/IFG parameters. */ 3029 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3030 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3031 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3032 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3033 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3034 /* Set parameters for half-duplex media. */ 3035 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3036 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3037 HDPX_CFG_LCOL_MASK) | 3038 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3039 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3040 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3041 HDPX_CFG_ABEBT_MASK) | 3042 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3043 HDPX_CFG_JAMIPG_MASK)); 3044 /* 3045 * Set TSO/checksum offload threshold. For frames that is 3046 * larger than this threshold, hardware wouldn't do 3047 * TSO/checksum offloading. 3048 */ 3049 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3050 (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3051 TSO_OFFLOAD_THRESH_MASK); 3052 /* Configure TxQ. */ 3053 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3054 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3055 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3056 TXQ_CFG_TD_BURST_MASK; 3057 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3058 3059 /* Configure Rx free descriptor pre-fetching. */ 3060 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3061 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3062 RX_RD_FREE_THRESH_HI_MASK) | 3063 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3064 RX_RD_FREE_THRESH_LO_MASK)); 3065 3066 /* 3067 * Configure flow control parameters. 3068 * XON : 80% of Rx FIFO 3069 * XOFF : 30% of Rx FIFO 3070 */ 3071 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3072 rxf_hi = (reg * 8) / 10; 3073 rxf_lo = (reg * 3)/ 10; 3074 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3075 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3076 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3077 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3078 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3079 3080 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3081 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3082 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3083 3084 /* Configure RxQ. */ 3085 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3086 RXQ_CFG_RD_BURST_MASK; 3087 reg |= RXQ_CFG_RSS_MODE_DIS; 3088 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3089 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 3090 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3091 3092 /* Configure Rx DMAW request thresold. */ 3093 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 3094 ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) & 3095 RD_DMA_CFG_THRESH_MASK) | 3096 ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) & 3097 RD_DMA_CFG_TIMER_MASK)); 3098 /* Configure DMA parameters. */ 3099 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3100 reg |= sc->alc_rcb; 3101 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3102 reg |= DMA_CFG_CMB_ENB; 3103 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3104 reg |= DMA_CFG_SMB_ENB; 3105 else 3106 reg |= DMA_CFG_SMB_DIS; 3107 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3108 DMA_CFG_RD_BURST_SHIFT; 3109 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3110 DMA_CFG_WR_BURST_SHIFT; 3111 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3112 DMA_CFG_RD_DELAY_CNT_MASK; 3113 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3114 DMA_CFG_WR_DELAY_CNT_MASK; 3115 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3116 3117 /* 3118 * Configure Tx/Rx MACs. 3119 * - Auto-padding for short frames. 3120 * - Enable CRC generation. 3121 * Actual reconfiguration of MAC for resolved speed/duplex 3122 * is followed after detection of link establishment. 3123 * AR8131/AR8132 always does checksum computation regardless 3124 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3125 * have bug in protocol field in Rx return structure so 3126 * these controllers can't handle fragmented frames. Disable 3127 * Rx checksum offloading until there is a newer controller 3128 * that has sane implementation. 3129 */ 3130 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3131 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3132 MAC_CFG_PREAMBLE_MASK); 3133 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3134 reg |= MAC_CFG_SPEED_10_100; 3135 else 3136 reg |= MAC_CFG_SPEED_1000; 3137 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3138 3139 /* Set up the receive filter. */ 3140 alc_rxfilter(sc); 3141 alc_rxvlan(sc); 3142 3143 /* Acknowledge all pending interrupts and clear it. */ 3144 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3145 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3146 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3147 3148 sc->alc_flags &= ~ALC_FLAG_LINK; 3149 /* Switch to the current media. */ 3150 mii_mediachg(mii); 3151 3152 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3153 3154 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3155 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3156} 3157 3158static void 3159alc_stop(struct alc_softc *sc) 3160{ 3161 struct ifnet *ifp; 3162 struct alc_txdesc *txd; 3163 struct alc_rxdesc *rxd; 3164 uint32_t reg; 3165 int i; 3166 3167 ALC_LOCK_ASSERT(sc); 3168 /* 3169 * Mark the interface down and cancel the watchdog timer. 3170 */ 3171 ifp = sc->alc_ifp; 3172 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3173 sc->alc_flags &= ~ALC_FLAG_LINK; 3174 callout_stop(&sc->alc_tick_ch); 3175 sc->alc_watchdog_timer = 0; 3176 alc_stats_update(sc); 3177 /* Disable interrupts. */ 3178 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3179 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3180 alc_stop_queue(sc); 3181 /* Disable DMA. */ 3182 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3183 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3184 reg |= DMA_CFG_SMB_DIS; 3185 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3186 DELAY(1000); 3187 /* Stop Rx/Tx MACs. */ 3188 alc_stop_mac(sc); 3189 /* Disable interrupts which might be touched in taskq handler. */ 3190 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3191 3192 /* Reclaim Rx buffers that have been processed. */ 3193 if (sc->alc_cdata.alc_rxhead != NULL) 3194 m_freem(sc->alc_cdata.alc_rxhead); 3195 ALC_RXCHAIN_RESET(sc); 3196 /* 3197 * Free Tx/Rx mbufs still in the queues. 3198 */ 3199 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3200 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3201 if (rxd->rx_m != NULL) { 3202 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3203 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3204 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3205 rxd->rx_dmamap); 3206 m_freem(rxd->rx_m); 3207 rxd->rx_m = NULL; 3208 } 3209 } 3210 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3211 txd = &sc->alc_cdata.alc_txdesc[i]; 3212 if (txd->tx_m != NULL) { 3213 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3214 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3215 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3216 txd->tx_dmamap); 3217 m_freem(txd->tx_m); 3218 txd->tx_m = NULL; 3219 } 3220 } 3221} 3222 3223static void 3224alc_stop_mac(struct alc_softc *sc) 3225{ 3226 uint32_t reg; 3227 int i; 3228 3229 ALC_LOCK_ASSERT(sc); 3230 3231 /* Disable Rx/Tx MAC. */ 3232 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3233 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3234 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 3235 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3236 } 3237 for (i = ALC_TIMEOUT; i > 0; i--) { 3238 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3239 if (reg == 0) 3240 break; 3241 DELAY(10); 3242 } 3243 if (i == 0) 3244 device_printf(sc->alc_dev, 3245 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3246} 3247 3248static void 3249alc_start_queue(struct alc_softc *sc) 3250{ 3251 uint32_t qcfg[] = { 3252 0, 3253 RXQ_CFG_QUEUE0_ENB, 3254 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3255 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3256 RXQ_CFG_ENB 3257 }; 3258 uint32_t cfg; 3259 3260 ALC_LOCK_ASSERT(sc); 3261 3262 /* Enable RxQ. */ 3263 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3264 cfg &= ~RXQ_CFG_ENB; 3265 cfg |= qcfg[1]; 3266 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3267 /* Enable TxQ. */ 3268 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3269 cfg |= TXQ_CFG_ENB; 3270 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3271} 3272 3273static void 3274alc_stop_queue(struct alc_softc *sc) 3275{ 3276 uint32_t reg; 3277 int i; 3278 3279 ALC_LOCK_ASSERT(sc); 3280 3281 /* Disable RxQ. */ 3282 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3283 if ((reg & RXQ_CFG_ENB) != 0) { 3284 reg &= ~RXQ_CFG_ENB; 3285 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3286 } 3287 /* Disable TxQ. */ 3288 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3289 if ((reg & TXQ_CFG_ENB) == 0) { 3290 reg &= ~TXQ_CFG_ENB; 3291 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3292 } 3293 for (i = ALC_TIMEOUT; i > 0; i--) { 3294 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3295 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3296 break; 3297 DELAY(10); 3298 } 3299 if (i == 0) 3300 device_printf(sc->alc_dev, 3301 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3302} 3303 3304static void 3305alc_init_tx_ring(struct alc_softc *sc) 3306{ 3307 struct alc_ring_data *rd; 3308 struct alc_txdesc *txd; 3309 int i; 3310 3311 ALC_LOCK_ASSERT(sc); 3312 3313 sc->alc_cdata.alc_tx_prod = 0; 3314 sc->alc_cdata.alc_tx_cons = 0; 3315 sc->alc_cdata.alc_tx_cnt = 0; 3316 3317 rd = &sc->alc_rdata; 3318 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3319 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3320 txd = &sc->alc_cdata.alc_txdesc[i]; 3321 txd->tx_m = NULL; 3322 } 3323 3324 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3325 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3326} 3327 3328static int 3329alc_init_rx_ring(struct alc_softc *sc) 3330{ 3331 struct alc_ring_data *rd; 3332 struct alc_rxdesc *rxd; 3333 int i; 3334 3335 ALC_LOCK_ASSERT(sc); 3336 3337 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3338 sc->alc_morework = 0; 3339 rd = &sc->alc_rdata; 3340 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3341 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3342 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3343 rxd->rx_m = NULL; 3344 rxd->rx_desc = &rd->alc_rx_ring[i]; 3345 if (alc_newbuf(sc, rxd) != 0) 3346 return (ENOBUFS); 3347 } 3348 3349 /* 3350 * Since controller does not update Rx descriptors, driver 3351 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3352 * is enough to ensure coherence. 3353 */ 3354 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3355 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3356 /* Let controller know availability of new Rx buffers. */ 3357 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3358 3359 return (0); 3360} 3361 3362static void 3363alc_init_rr_ring(struct alc_softc *sc) 3364{ 3365 struct alc_ring_data *rd; 3366 3367 ALC_LOCK_ASSERT(sc); 3368 3369 sc->alc_cdata.alc_rr_cons = 0; 3370 ALC_RXCHAIN_RESET(sc); 3371 3372 rd = &sc->alc_rdata; 3373 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3374 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3375 sc->alc_cdata.alc_rr_ring_map, 3376 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3377} 3378 3379static void 3380alc_init_cmb(struct alc_softc *sc) 3381{ 3382 struct alc_ring_data *rd; 3383 3384 ALC_LOCK_ASSERT(sc); 3385 3386 rd = &sc->alc_rdata; 3387 bzero(rd->alc_cmb, ALC_CMB_SZ); 3388 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3390} 3391 3392static void 3393alc_init_smb(struct alc_softc *sc) 3394{ 3395 struct alc_ring_data *rd; 3396 3397 ALC_LOCK_ASSERT(sc); 3398 3399 rd = &sc->alc_rdata; 3400 bzero(rd->alc_smb, ALC_SMB_SZ); 3401 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3402 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3403} 3404 3405static void 3406alc_rxvlan(struct alc_softc *sc) 3407{ 3408 struct ifnet *ifp; 3409 uint32_t reg; 3410 3411 ALC_LOCK_ASSERT(sc); 3412 3413 ifp = sc->alc_ifp; 3414 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3415 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3416 reg |= MAC_CFG_VLAN_TAG_STRIP; 3417 else 3418 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3419 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3420} 3421 3422static void 3423alc_rxfilter(struct alc_softc *sc) 3424{ 3425 struct ifnet *ifp; 3426 struct ifmultiaddr *ifma; 3427 uint32_t crc; 3428 uint32_t mchash[2]; 3429 uint32_t rxcfg; 3430 3431 ALC_LOCK_ASSERT(sc); 3432 3433 ifp = sc->alc_ifp; 3434 3435 bzero(mchash, sizeof(mchash)); 3436 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3437 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3438 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3439 rxcfg |= MAC_CFG_BCAST; 3440 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3441 if ((ifp->if_flags & IFF_PROMISC) != 0) 3442 rxcfg |= MAC_CFG_PROMISC; 3443 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3444 rxcfg |= MAC_CFG_ALLMULTI; 3445 mchash[0] = 0xFFFFFFFF; 3446 mchash[1] = 0xFFFFFFFF; 3447 goto chipit; 3448 } 3449 3450 if_maddr_rlock(ifp); 3451 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3452 if (ifma->ifma_addr->sa_family != AF_LINK) 3453 continue; 3454 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3455 ifma->ifma_addr), ETHER_ADDR_LEN); 3456 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3457 } 3458 if_maddr_runlock(ifp); 3459 3460chipit: 3461 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3462 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3463 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3464} 3465 3466static int 3467sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3468{ 3469 int error, value; 3470 3471 if (arg1 == NULL) 3472 return (EINVAL); 3473 value = *(int *)arg1; 3474 error = sysctl_handle_int(oidp, &value, 0, req); 3475 if (error || req->newptr == NULL) 3476 return (error); 3477 if (value < low || value > high) 3478 return (EINVAL); 3479 *(int *)arg1 = value; 3480 3481 return (0); 3482} 3483 3484static int 3485sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3486{ 3487 return (sysctl_int_range(oidp, arg1, arg2, req, 3488 ALC_PROC_MIN, ALC_PROC_MAX)); 3489} 3490 3491static int 3492sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3493{ 3494 3495 return (sysctl_int_range(oidp, arg1, arg2, req, 3496 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3497} 3498