if_alc.c revision 204228
1/*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/alc/if_alc.c 204228 2010-02-22 22:41:27Z yongari $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_llc.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58#include <net/if_vlan_var.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/ip.h> 63#include <netinet/tcp.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <machine/atomic.h> 72#include <machine/bus.h> 73#include <machine/in_cksum.h> 74 75#include <dev/alc/if_alcreg.h> 76#include <dev/alc/if_alcvar.h> 77 78/* "device miibus" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80#undef ALC_USE_CUSTOM_CSUM 81 82#ifdef ALC_USE_CUSTOM_CSUM 83#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 84#else 85#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86#endif 87 88MODULE_DEPEND(alc, pci, 1, 1, 1); 89MODULE_DEPEND(alc, ether, 1, 1, 1); 90MODULE_DEPEND(alc, miibus, 1, 1, 1); 91 92/* Tunables. */ 93static int msi_disable = 0; 94static int msix_disable = 0; 95TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 96TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 97 98/* 99 * Devices supported by this driver. 100 */ 101static struct alc_dev { 102 uint16_t alc_vendorid; 103 uint16_t alc_deviceid; 104 const char *alc_name; 105} alc_devs[] = { 106 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 107 "Atheros AR8131 PCIe Gigabit Ethernet" }, 108 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 109 "Atheros AR8132 PCIe Fast Ethernet" } 110}; 111 112static void alc_aspm(struct alc_softc *); 113static int alc_attach(device_t); 114static int alc_check_boundary(struct alc_softc *); 115static int alc_detach(device_t); 116static void alc_disable_l0s_l1(struct alc_softc *); 117static int alc_dma_alloc(struct alc_softc *); 118static void alc_dma_free(struct alc_softc *); 119static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 120static int alc_encap(struct alc_softc *, struct mbuf **); 121#ifndef __NO_STRICT_ALIGNMENT 122static struct mbuf * 123 alc_fixup_rx(struct ifnet *, struct mbuf *); 124#endif 125static void alc_get_macaddr(struct alc_softc *); 126static void alc_init(void *); 127static void alc_init_cmb(struct alc_softc *); 128static void alc_init_locked(struct alc_softc *); 129static void alc_init_rr_ring(struct alc_softc *); 130static int alc_init_rx_ring(struct alc_softc *); 131static void alc_init_smb(struct alc_softc *); 132static void alc_init_tx_ring(struct alc_softc *); 133static void alc_int_task(void *, int); 134static int alc_intr(void *); 135static int alc_ioctl(struct ifnet *, u_long, caddr_t); 136static void alc_mac_config(struct alc_softc *); 137static int alc_miibus_readreg(device_t, int, int); 138static void alc_miibus_statchg(device_t); 139static int alc_miibus_writereg(device_t, int, int, int); 140static int alc_mediachange(struct ifnet *); 141static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 142static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 143static void alc_phy_down(struct alc_softc *); 144static void alc_phy_reset(struct alc_softc *); 145static int alc_probe(device_t); 146static void alc_reset(struct alc_softc *); 147static int alc_resume(device_t); 148static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 149static int alc_rxintr(struct alc_softc *, int); 150static void alc_rxfilter(struct alc_softc *); 151static void alc_rxvlan(struct alc_softc *); 152static void alc_setlinkspeed(struct alc_softc *); 153static void alc_setwol(struct alc_softc *); 154static int alc_shutdown(device_t); 155static void alc_start(struct ifnet *); 156static void alc_start_queue(struct alc_softc *); 157static void alc_stats_clear(struct alc_softc *); 158static void alc_stats_update(struct alc_softc *); 159static void alc_stop(struct alc_softc *); 160static void alc_stop_mac(struct alc_softc *); 161static void alc_stop_queue(struct alc_softc *); 162static int alc_suspend(device_t); 163static void alc_sysctl_node(struct alc_softc *); 164static void alc_tick(void *); 165static void alc_tx_task(void *, int); 166static void alc_txeof(struct alc_softc *); 167static void alc_watchdog(struct alc_softc *); 168static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 169static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 170static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 171 172static device_method_t alc_methods[] = { 173 /* Device interface. */ 174 DEVMETHOD(device_probe, alc_probe), 175 DEVMETHOD(device_attach, alc_attach), 176 DEVMETHOD(device_detach, alc_detach), 177 DEVMETHOD(device_shutdown, alc_shutdown), 178 DEVMETHOD(device_suspend, alc_suspend), 179 DEVMETHOD(device_resume, alc_resume), 180 181 /* MII interface. */ 182 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 183 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 184 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 185 186 { NULL, NULL } 187}; 188 189static driver_t alc_driver = { 190 "alc", 191 alc_methods, 192 sizeof(struct alc_softc) 193}; 194 195static devclass_t alc_devclass; 196 197DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 198DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 199 200static struct resource_spec alc_res_spec_mem[] = { 201 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 202 { -1, 0, 0 } 203}; 204 205static struct resource_spec alc_irq_spec_legacy[] = { 206 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 207 { -1, 0, 0 } 208}; 209 210static struct resource_spec alc_irq_spec_msi[] = { 211 { SYS_RES_IRQ, 1, RF_ACTIVE }, 212 { -1, 0, 0 } 213}; 214 215static struct resource_spec alc_irq_spec_msix[] = { 216 { SYS_RES_IRQ, 1, RF_ACTIVE }, 217 { -1, 0, 0 } 218}; 219 220static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 221 222static int 223alc_miibus_readreg(device_t dev, int phy, int reg) 224{ 225 struct alc_softc *sc; 226 uint32_t v; 227 int i; 228 229 sc = device_get_softc(dev); 230 231 if (phy != sc->alc_phyaddr) 232 return (0); 233 234 /* 235 * For AR8132 fast ethernet controller, do not report 1000baseT 236 * capability to mii(4). Even though AR8132 uses the same 237 * model/revision number of F1 gigabit PHY, the PHY has no 238 * ability to establish 1000baseT link. 239 */ 240 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 241 reg == MII_EXTSR) 242 return (0); 243 244 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(5); 248 v = CSR_READ_4(sc, ALC_MDIO); 249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250 break; 251 } 252 253 if (i == 0) { 254 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 255 return (0); 256 } 257 258 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 259} 260 261static int 262alc_miibus_writereg(device_t dev, int phy, int reg, int val) 263{ 264 struct alc_softc *sc; 265 uint32_t v; 266 int i; 267 268 sc = device_get_softc(dev); 269 270 if (phy != sc->alc_phyaddr) 271 return (0); 272 273 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 274 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 275 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 276 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 277 DELAY(5); 278 v = CSR_READ_4(sc, ALC_MDIO); 279 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 280 break; 281 } 282 283 if (i == 0) 284 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 285 286 return (0); 287} 288 289static void 290alc_miibus_statchg(device_t dev) 291{ 292 struct alc_softc *sc; 293 struct mii_data *mii; 294 struct ifnet *ifp; 295 uint32_t reg; 296 297 sc = device_get_softc(dev); 298 299 mii = device_get_softc(sc->alc_miibus); 300 ifp = sc->alc_ifp; 301 if (mii == NULL || ifp == NULL || 302 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 303 return; 304 305 sc->alc_flags &= ~ALC_FLAG_LINK; 306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 307 (IFM_ACTIVE | IFM_AVALID)) { 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_10_T: 310 case IFM_100_TX: 311 sc->alc_flags |= ALC_FLAG_LINK; 312 break; 313 case IFM_1000_T: 314 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 315 sc->alc_flags |= ALC_FLAG_LINK; 316 break; 317 default: 318 break; 319 } 320 } 321 alc_stop_queue(sc); 322 /* Stop Rx/Tx MACs. */ 323 alc_stop_mac(sc); 324 325 /* Program MACs with resolved speed/duplex/flow-control. */ 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 327 alc_start_queue(sc); 328 alc_mac_config(sc); 329 /* Re-enable Tx/Rx MACs. */ 330 reg = CSR_READ_4(sc, ALC_MAC_CFG); 331 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 332 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 333 } 334 alc_aspm(sc); 335} 336 337static void 338alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 339{ 340 struct alc_softc *sc; 341 struct mii_data *mii; 342 343 sc = ifp->if_softc; 344 ALC_LOCK(sc); 345 if ((ifp->if_flags & IFF_UP) == 0) { 346 ALC_UNLOCK(sc); 347 return; 348 } 349 mii = device_get_softc(sc->alc_miibus); 350 351 mii_pollstat(mii); 352 ALC_UNLOCK(sc); 353 ifmr->ifm_status = mii->mii_media_status; 354 ifmr->ifm_active = mii->mii_media_active; 355} 356 357static int 358alc_mediachange(struct ifnet *ifp) 359{ 360 struct alc_softc *sc; 361 struct mii_data *mii; 362 struct mii_softc *miisc; 363 int error; 364 365 sc = ifp->if_softc; 366 ALC_LOCK(sc); 367 mii = device_get_softc(sc->alc_miibus); 368 if (mii->mii_instance != 0) { 369 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 370 mii_phy_reset(miisc); 371 } 372 error = mii_mediachg(mii); 373 ALC_UNLOCK(sc); 374 375 return (error); 376} 377 378static int 379alc_probe(device_t dev) 380{ 381 struct alc_dev *sp; 382 int i; 383 uint16_t vendor, devid; 384 385 vendor = pci_get_vendor(dev); 386 devid = pci_get_device(dev); 387 sp = alc_devs; 388 for (i = 0; i < sizeof(alc_devs) / sizeof(alc_devs[0]); i++) { 389 if (vendor == sp->alc_vendorid && 390 devid == sp->alc_deviceid) { 391 device_set_desc(dev, sp->alc_name); 392 return (BUS_PROBE_DEFAULT); 393 } 394 sp++; 395 } 396 397 return (ENXIO); 398} 399 400static void 401alc_get_macaddr(struct alc_softc *sc) 402{ 403 uint32_t ea[2], opt; 404 int i; 405 406 opt = CSR_READ_4(sc, ALC_OPT_CFG); 407 if ((CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 408 /* 409 * EEPROM found, let TWSI reload EEPROM configuration. 410 * This will set ethernet address of controller. 411 */ 412 if ((opt & OPT_CFG_CLK_ENB) == 0) { 413 opt |= OPT_CFG_CLK_ENB; 414 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 415 CSR_READ_4(sc, ALC_OPT_CFG); 416 DELAY(1000); 417 } 418 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 419 TWSI_CFG_SW_LD_START); 420 for (i = 100; i > 0; i--) { 421 DELAY(1000); 422 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 423 TWSI_CFG_SW_LD_START) == 0) 424 break; 425 } 426 if (i == 0) 427 device_printf(sc->alc_dev, 428 "reloading EEPROM timeout!\n"); 429 } else { 430 if (bootverbose) 431 device_printf(sc->alc_dev, "EEPROM not found!\n"); 432 } 433 if ((opt & OPT_CFG_CLK_ENB) != 0) { 434 opt &= ~OPT_CFG_CLK_ENB; 435 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 436 CSR_READ_4(sc, ALC_OPT_CFG); 437 DELAY(1000); 438 } 439 440 ea[0] = CSR_READ_4(sc, ALC_PAR0); 441 ea[1] = CSR_READ_4(sc, ALC_PAR1); 442 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 443 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 444 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 445 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 446 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 447 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 448} 449 450static void 451alc_disable_l0s_l1(struct alc_softc *sc) 452{ 453 uint32_t pmcfg; 454 455 /* Another magic from vendor. */ 456 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 457 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 458 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 459 PM_CFG_SERDES_PD_EX_L1); 460 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 461 PM_CFG_SERDES_L1_ENB; 462 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 463} 464 465static void 466alc_phy_reset(struct alc_softc *sc) 467{ 468 uint16_t data; 469 470 /* Reset magic from Linux. */ 471 CSR_WRITE_2(sc, ALC_GPHY_CFG, 472 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 473 CSR_READ_2(sc, ALC_GPHY_CFG); 474 DELAY(10 * 1000); 475 476 CSR_WRITE_2(sc, ALC_GPHY_CFG, 477 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 478 GPHY_CFG_SEL_ANA_RESET); 479 CSR_READ_2(sc, ALC_GPHY_CFG); 480 DELAY(10 * 1000); 481 482 /* Load DSP codes, vendor magic. */ 483 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 484 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 485 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 486 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 487 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 488 ALC_MII_DBG_DATA, data); 489 490 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 491 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 492 ANA_SERDES_EN_LCKDT; 493 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 494 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 495 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_DATA, data); 497 498 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 499 ANA_LONG_CABLE_TH_100_MASK) | 500 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 501 ANA_SHORT_CABLE_TH_100_SHIFT) | 502 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 503 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 504 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 505 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 506 ALC_MII_DBG_DATA, data); 507 508 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 509 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 510 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 511 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 512 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 513 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 514 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_DATA, data); 516 517 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 518 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 519 ANA_OEN_125M; 520 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 521 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 522 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 523 ALC_MII_DBG_DATA, data); 524 DELAY(1000); 525} 526 527static void 528alc_phy_down(struct alc_softc *sc) 529{ 530 531 /* Force PHY down. */ 532 CSR_WRITE_2(sc, ALC_GPHY_CFG, 533 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 534 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW); 535 DELAY(1000); 536} 537 538static void 539alc_aspm(struct alc_softc *sc) 540{ 541 uint32_t pmcfg; 542 543 ALC_LOCK_ASSERT(sc); 544 545 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 546 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 547 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB; 548 pmcfg |= PM_CFG_SERDES_L1_ENB; 549 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 550 pmcfg |= PM_CFG_MAC_ASPM_CHK; 551 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 552 pmcfg |= PM_CFG_SERDES_PLL_L1_ENB; 553 pmcfg &= ~PM_CFG_CLK_SWH_L1; 554 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 555 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 556 } else { 557 pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB; 558 pmcfg |= PM_CFG_CLK_SWH_L1; 559 pmcfg &= ~PM_CFG_ASPM_L1_ENB; 560 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 561 } 562 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 563} 564 565static int 566alc_attach(device_t dev) 567{ 568 struct alc_softc *sc; 569 struct ifnet *ifp; 570 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" }; 571 uint16_t burst; 572 int base, error, i, msic, msixc, pmc, state; 573 uint32_t cap, ctl, val; 574 575 error = 0; 576 sc = device_get_softc(dev); 577 sc->alc_dev = dev; 578 579 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 580 MTX_DEF); 581 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 582 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 583 584 /* Map the device. */ 585 pci_enable_busmaster(dev); 586 sc->alc_res_spec = alc_res_spec_mem; 587 sc->alc_irq_spec = alc_irq_spec_legacy; 588 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 589 if (error != 0) { 590 device_printf(dev, "cannot allocate memory resources.\n"); 591 goto fail; 592 } 593 594 /* Set PHY address. */ 595 sc->alc_phyaddr = ALC_PHY_ADDR; 596 597 /* Initialize DMA parameters. */ 598 sc->alc_dma_rd_burst = 0; 599 sc->alc_dma_wr_burst = 0; 600 sc->alc_rcb = DMA_CFG_RCB_64; 601 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 602 sc->alc_flags |= ALC_FLAG_PCIE; 603 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 604 sc->alc_dma_rd_burst = 605 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 606 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 607 if (bootverbose) { 608 device_printf(dev, "Read request size : %u bytes.\n", 609 alc_dma_burst[sc->alc_dma_rd_burst]); 610 device_printf(dev, "TLP payload size : %u bytes.\n", 611 alc_dma_burst[sc->alc_dma_wr_burst]); 612 } 613 /* Clear data link and flow-control protocol error. */ 614 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 615 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 616 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 617 /* Disable ASPM L0S and L1. */ 618 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 619 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 620 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 621 if ((ctl & 0x08) != 0) 622 sc->alc_rcb = DMA_CFG_RCB_128; 623 if (bootverbose) 624 device_printf(dev, "RCB %u bytes\n", 625 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 626 state = ctl & 0x03; 627 if (bootverbose) 628 device_printf(sc->alc_dev, "ASPM %s %s\n", 629 aspm_state[state], 630 state == 0 ? "disabled" : "enabled"); 631 if (state != 0) 632 alc_disable_l0s_l1(sc); 633 } 634 } 635 636 /* Reset PHY. */ 637 alc_phy_reset(sc); 638 639 /* Reset the ethernet controller. */ 640 alc_reset(sc); 641 642 /* 643 * One odd thing is AR8132 uses the same PHY hardware(F1 644 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 645 * the PHY supports 1000Mbps but that's not true. The PHY 646 * used in AR8132 can't establish gigabit link even if it 647 * shows the same PHY model/revision number of AR8131. 648 */ 649 if (pci_get_device(dev) == DEVICEID_ATHEROS_AR8132) 650 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_JUMBO; 651 else 652 sc->alc_flags |= ALC_FLAG_JUMBO | ALC_FLAG_ASPM_MON; 653 /* 654 * It seems that AR8131/AR8132 has silicon bug for SMB. In 655 * addition, Atheros said that enabling SMB wouldn't improve 656 * performance. However I think it's bad to access lots of 657 * registers to extract MAC statistics. 658 */ 659 sc->alc_flags |= ALC_FLAG_SMB_BUG; 660 /* 661 * Don't use Tx CMB. It is known to have silicon bug. 662 */ 663 sc->alc_flags |= ALC_FLAG_CMB_BUG; 664 sc->alc_rev = pci_get_revid(dev); 665 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 666 MASTER_CHIP_REV_SHIFT; 667 if (bootverbose) { 668 device_printf(dev, "PCI device revision : 0x%04x\n", 669 sc->alc_rev); 670 device_printf(dev, "Chip id/revision : 0x%04x\n", 671 sc->alc_chip_rev); 672 } 673 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 674 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 675 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 676 677 /* Allocate IRQ resources. */ 678 msixc = pci_msix_count(dev); 679 msic = pci_msi_count(dev); 680 if (bootverbose) { 681 device_printf(dev, "MSIX count : %d\n", msixc); 682 device_printf(dev, "MSI count : %d\n", msic); 683 } 684 /* Prefer MSIX over MSI. */ 685 if (msix_disable == 0 || msi_disable == 0) { 686 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 687 pci_alloc_msix(dev, &msixc) == 0) { 688 if (msic == ALC_MSIX_MESSAGES) { 689 device_printf(dev, 690 "Using %d MSIX message(s).\n", msixc); 691 sc->alc_flags |= ALC_FLAG_MSIX; 692 sc->alc_irq_spec = alc_irq_spec_msix; 693 } else 694 pci_release_msi(dev); 695 } 696 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 697 msic == ALC_MSI_MESSAGES && 698 pci_alloc_msi(dev, &msic) == 0) { 699 if (msic == ALC_MSI_MESSAGES) { 700 device_printf(dev, 701 "Using %d MSI message(s).\n", msic); 702 sc->alc_flags |= ALC_FLAG_MSI; 703 sc->alc_irq_spec = alc_irq_spec_msi; 704 } else 705 pci_release_msi(dev); 706 } 707 } 708 709 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 710 if (error != 0) { 711 device_printf(dev, "cannot allocate IRQ resources.\n"); 712 goto fail; 713 } 714 715 /* Create device sysctl node. */ 716 alc_sysctl_node(sc); 717 718 if ((error = alc_dma_alloc(sc) != 0)) 719 goto fail; 720 721 /* Load station address. */ 722 alc_get_macaddr(sc); 723 724 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 725 if (ifp == NULL) { 726 device_printf(dev, "cannot allocate ifnet structure.\n"); 727 error = ENXIO; 728 goto fail; 729 } 730 731 ifp->if_softc = sc; 732 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 733 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 734 ifp->if_ioctl = alc_ioctl; 735 ifp->if_start = alc_start; 736 ifp->if_init = alc_init; 737 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 738 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 739 IFQ_SET_READY(&ifp->if_snd); 740 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 741 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 742 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 743 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 744 ifp->if_capenable = ifp->if_capabilities; 745 746 /* Set up MII bus. */ 747 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 748 alc_mediastatus)) != 0) { 749 device_printf(dev, "no PHY found!\n"); 750 goto fail; 751 } 752 753 ether_ifattach(ifp, sc->alc_eaddr); 754 755 /* VLAN capability setup. */ 756 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 757 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 758 ifp->if_capenable = ifp->if_capabilities; 759 /* 760 * XXX 761 * It seems enabling Tx checksum offloading makes more trouble. 762 * Sometimes the controller does not receive any frames when 763 * Tx checksum offloading is enabled. I'm not sure whether this 764 * is a bug in Tx checksum offloading logic or I got broken 765 * sample boards. To safety, don't enable Tx checksum offloading 766 * by default but give chance to users to toggle it if they know 767 * their controllers work without problems. 768 */ 769 ifp->if_capenable &= ~IFCAP_TXCSUM; 770 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 771 772 /* Tell the upper layer(s) we support long frames. */ 773 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 774 775 /* Create local taskq. */ 776 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 777 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 778 taskqueue_thread_enqueue, &sc->alc_tq); 779 if (sc->alc_tq == NULL) { 780 device_printf(dev, "could not create taskqueue.\n"); 781 ether_ifdetach(ifp); 782 error = ENXIO; 783 goto fail; 784 } 785 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 786 device_get_nameunit(sc->alc_dev)); 787 788 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 789 msic = ALC_MSIX_MESSAGES; 790 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 791 msic = ALC_MSI_MESSAGES; 792 else 793 msic = 1; 794 for (i = 0; i < msic; i++) { 795 error = bus_setup_intr(dev, sc->alc_irq[i], 796 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 797 &sc->alc_intrhand[i]); 798 if (error != 0) 799 break; 800 } 801 if (error != 0) { 802 device_printf(dev, "could not set up interrupt handler.\n"); 803 taskqueue_free(sc->alc_tq); 804 sc->alc_tq = NULL; 805 ether_ifdetach(ifp); 806 goto fail; 807 } 808 809fail: 810 if (error != 0) 811 alc_detach(dev); 812 813 return (error); 814} 815 816static int 817alc_detach(device_t dev) 818{ 819 struct alc_softc *sc; 820 struct ifnet *ifp; 821 int i, msic; 822 823 sc = device_get_softc(dev); 824 825 ifp = sc->alc_ifp; 826 if (device_is_attached(dev)) { 827 ALC_LOCK(sc); 828 sc->alc_flags |= ALC_FLAG_DETACH; 829 alc_stop(sc); 830 ALC_UNLOCK(sc); 831 callout_drain(&sc->alc_tick_ch); 832 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 833 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 834 ether_ifdetach(ifp); 835 } 836 837 if (sc->alc_tq != NULL) { 838 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 839 taskqueue_free(sc->alc_tq); 840 sc->alc_tq = NULL; 841 } 842 843 if (sc->alc_miibus != NULL) { 844 device_delete_child(dev, sc->alc_miibus); 845 sc->alc_miibus = NULL; 846 } 847 bus_generic_detach(dev); 848 alc_dma_free(sc); 849 850 if (ifp != NULL) { 851 if_free(ifp); 852 sc->alc_ifp = NULL; 853 } 854 855 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 856 msic = ALC_MSIX_MESSAGES; 857 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 858 msic = ALC_MSI_MESSAGES; 859 else 860 msic = 1; 861 for (i = 0; i < msic; i++) { 862 if (sc->alc_intrhand[i] != NULL) { 863 bus_teardown_intr(dev, sc->alc_irq[i], 864 sc->alc_intrhand[i]); 865 sc->alc_intrhand[i] = NULL; 866 } 867 } 868 if (sc->alc_res[0] != NULL) 869 alc_phy_down(sc); 870 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 871 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 872 pci_release_msi(dev); 873 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 874 mtx_destroy(&sc->alc_mtx); 875 876 return (0); 877} 878 879#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 880 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 881#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 882 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 883 884static void 885alc_sysctl_node(struct alc_softc *sc) 886{ 887 struct sysctl_ctx_list *ctx; 888 struct sysctl_oid_list *child, *parent; 889 struct sysctl_oid *tree; 890 struct alc_hw_stats *stats; 891 int error; 892 893 stats = &sc->alc_stats; 894 ctx = device_get_sysctl_ctx(sc->alc_dev); 895 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 896 897 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 898 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 899 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 900 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 901 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 902 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 903 /* Pull in device tunables. */ 904 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 905 error = resource_int_value(device_get_name(sc->alc_dev), 906 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 907 if (error == 0) { 908 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 909 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 910 device_printf(sc->alc_dev, "int_rx_mod value out of " 911 "range; using default: %d\n", 912 ALC_IM_RX_TIMER_DEFAULT); 913 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 914 } 915 } 916 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 917 error = resource_int_value(device_get_name(sc->alc_dev), 918 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 919 if (error == 0) { 920 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 921 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 922 device_printf(sc->alc_dev, "int_tx_mod value out of " 923 "range; using default: %d\n", 924 ALC_IM_TX_TIMER_DEFAULT); 925 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 926 } 927 } 928 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 929 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 930 sysctl_hw_alc_proc_limit, "I", 931 "max number of Rx events to process"); 932 /* Pull in device tunables. */ 933 sc->alc_process_limit = ALC_PROC_DEFAULT; 934 error = resource_int_value(device_get_name(sc->alc_dev), 935 device_get_unit(sc->alc_dev), "process_limit", 936 &sc->alc_process_limit); 937 if (error == 0) { 938 if (sc->alc_process_limit < ALC_PROC_MIN || 939 sc->alc_process_limit > ALC_PROC_MAX) { 940 device_printf(sc->alc_dev, 941 "process_limit value out of range; " 942 "using default: %d\n", ALC_PROC_DEFAULT); 943 sc->alc_process_limit = ALC_PROC_DEFAULT; 944 } 945 } 946 947 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 948 NULL, "ALC statistics"); 949 parent = SYSCTL_CHILDREN(tree); 950 951 /* Rx statistics. */ 952 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 953 NULL, "Rx MAC statistics"); 954 child = SYSCTL_CHILDREN(tree); 955 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 956 &stats->rx_frames, "Good frames"); 957 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 958 &stats->rx_bcast_frames, "Good broadcast frames"); 959 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 960 &stats->rx_mcast_frames, "Good multicast frames"); 961 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 962 &stats->rx_pause_frames, "Pause control frames"); 963 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 964 &stats->rx_control_frames, "Control frames"); 965 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 966 &stats->rx_crcerrs, "CRC errors"); 967 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 968 &stats->rx_lenerrs, "Frames with length mismatched"); 969 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 970 &stats->rx_bytes, "Good octets"); 971 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 972 &stats->rx_bcast_bytes, "Good broadcast octets"); 973 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 974 &stats->rx_mcast_bytes, "Good multicast octets"); 975 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 976 &stats->rx_runts, "Too short frames"); 977 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 978 &stats->rx_fragments, "Fragmented frames"); 979 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 980 &stats->rx_pkts_64, "64 bytes frames"); 981 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 982 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 983 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 984 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 985 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 986 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 987 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 988 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 989 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 990 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 991 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 992 &stats->rx_pkts_1519_max, "1519 to max frames"); 993 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 994 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 995 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 996 &stats->rx_fifo_oflows, "FIFO overflows"); 997 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 998 &stats->rx_rrs_errs, "Return status write-back errors"); 999 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1000 &stats->rx_alignerrs, "Alignment errors"); 1001 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1002 &stats->rx_pkts_filtered, 1003 "Frames dropped due to address filtering"); 1004 1005 /* Tx statistics. */ 1006 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1007 NULL, "Tx MAC statistics"); 1008 child = SYSCTL_CHILDREN(tree); 1009 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1010 &stats->tx_frames, "Good frames"); 1011 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1012 &stats->tx_bcast_frames, "Good broadcast frames"); 1013 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1014 &stats->tx_mcast_frames, "Good multicast frames"); 1015 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1016 &stats->tx_pause_frames, "Pause control frames"); 1017 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1018 &stats->tx_control_frames, "Control frames"); 1019 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1020 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1021 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1022 &stats->tx_excess_defer, "Frames with derferrals"); 1023 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1024 &stats->tx_bytes, "Good octets"); 1025 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1026 &stats->tx_bcast_bytes, "Good broadcast octets"); 1027 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1028 &stats->tx_mcast_bytes, "Good multicast octets"); 1029 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1030 &stats->tx_pkts_64, "64 bytes frames"); 1031 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1032 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1033 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1034 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1035 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1036 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1037 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1038 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1039 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1040 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1041 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1042 &stats->tx_pkts_1519_max, "1519 to max frames"); 1043 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1044 &stats->tx_single_colls, "Single collisions"); 1045 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1046 &stats->tx_multi_colls, "Multiple collisions"); 1047 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1048 &stats->tx_late_colls, "Late collisions"); 1049 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1050 &stats->tx_excess_colls, "Excessive collisions"); 1051 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1052 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1053 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1054 &stats->tx_underrun, "FIFO underruns"); 1055 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1056 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1057 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1058 &stats->tx_lenerrs, "Frames with length mismatched"); 1059 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1060 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1061} 1062 1063#undef ALC_SYSCTL_STAT_ADD32 1064#undef ALC_SYSCTL_STAT_ADD64 1065 1066struct alc_dmamap_arg { 1067 bus_addr_t alc_busaddr; 1068}; 1069 1070static void 1071alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1072{ 1073 struct alc_dmamap_arg *ctx; 1074 1075 if (error != 0) 1076 return; 1077 1078 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1079 1080 ctx = (struct alc_dmamap_arg *)arg; 1081 ctx->alc_busaddr = segs[0].ds_addr; 1082} 1083 1084/* 1085 * Normal and high Tx descriptors shares single Tx high address. 1086 * Four Rx descriptor/return rings and CMB shares the same Rx 1087 * high address. 1088 */ 1089static int 1090alc_check_boundary(struct alc_softc *sc) 1091{ 1092 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1093 1094 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1095 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1096 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1097 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1098 1099 /* 4GB boundary crossing is not allowed. */ 1100 if ((ALC_ADDR_HI(rx_ring_end) != 1101 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1102 (ALC_ADDR_HI(rr_ring_end) != 1103 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1104 (ALC_ADDR_HI(cmb_end) != 1105 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1106 (ALC_ADDR_HI(tx_ring_end) != 1107 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1108 return (EFBIG); 1109 /* 1110 * Make sure Rx return descriptor/Rx descriptor/CMB use 1111 * the same high address. 1112 */ 1113 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1114 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1115 return (EFBIG); 1116 1117 return (0); 1118} 1119 1120static int 1121alc_dma_alloc(struct alc_softc *sc) 1122{ 1123 struct alc_txdesc *txd; 1124 struct alc_rxdesc *rxd; 1125 bus_addr_t lowaddr; 1126 struct alc_dmamap_arg ctx; 1127 int error, i; 1128 1129 lowaddr = BUS_SPACE_MAXADDR; 1130again: 1131 /* Create parent DMA tag. */ 1132 error = bus_dma_tag_create( 1133 bus_get_dma_tag(sc->alc_dev), /* parent */ 1134 1, 0, /* alignment, boundary */ 1135 lowaddr, /* lowaddr */ 1136 BUS_SPACE_MAXADDR, /* highaddr */ 1137 NULL, NULL, /* filter, filterarg */ 1138 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1139 0, /* nsegments */ 1140 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1141 0, /* flags */ 1142 NULL, NULL, /* lockfunc, lockarg */ 1143 &sc->alc_cdata.alc_parent_tag); 1144 if (error != 0) { 1145 device_printf(sc->alc_dev, 1146 "could not create parent DMA tag.\n"); 1147 goto fail; 1148 } 1149 1150 /* Create DMA tag for Tx descriptor ring. */ 1151 error = bus_dma_tag_create( 1152 sc->alc_cdata.alc_parent_tag, /* parent */ 1153 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1154 BUS_SPACE_MAXADDR, /* lowaddr */ 1155 BUS_SPACE_MAXADDR, /* highaddr */ 1156 NULL, NULL, /* filter, filterarg */ 1157 ALC_TX_RING_SZ, /* maxsize */ 1158 1, /* nsegments */ 1159 ALC_TX_RING_SZ, /* maxsegsize */ 1160 0, /* flags */ 1161 NULL, NULL, /* lockfunc, lockarg */ 1162 &sc->alc_cdata.alc_tx_ring_tag); 1163 if (error != 0) { 1164 device_printf(sc->alc_dev, 1165 "could not create Tx ring DMA tag.\n"); 1166 goto fail; 1167 } 1168 1169 /* Create DMA tag for Rx free descriptor ring. */ 1170 error = bus_dma_tag_create( 1171 sc->alc_cdata.alc_parent_tag, /* parent */ 1172 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1173 BUS_SPACE_MAXADDR, /* lowaddr */ 1174 BUS_SPACE_MAXADDR, /* highaddr */ 1175 NULL, NULL, /* filter, filterarg */ 1176 ALC_RX_RING_SZ, /* maxsize */ 1177 1, /* nsegments */ 1178 ALC_RX_RING_SZ, /* maxsegsize */ 1179 0, /* flags */ 1180 NULL, NULL, /* lockfunc, lockarg */ 1181 &sc->alc_cdata.alc_rx_ring_tag); 1182 if (error != 0) { 1183 device_printf(sc->alc_dev, 1184 "could not create Rx ring DMA tag.\n"); 1185 goto fail; 1186 } 1187 /* Create DMA tag for Rx return descriptor ring. */ 1188 error = bus_dma_tag_create( 1189 sc->alc_cdata.alc_parent_tag, /* parent */ 1190 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1191 BUS_SPACE_MAXADDR, /* lowaddr */ 1192 BUS_SPACE_MAXADDR, /* highaddr */ 1193 NULL, NULL, /* filter, filterarg */ 1194 ALC_RR_RING_SZ, /* maxsize */ 1195 1, /* nsegments */ 1196 ALC_RR_RING_SZ, /* maxsegsize */ 1197 0, /* flags */ 1198 NULL, NULL, /* lockfunc, lockarg */ 1199 &sc->alc_cdata.alc_rr_ring_tag); 1200 if (error != 0) { 1201 device_printf(sc->alc_dev, 1202 "could not create Rx return ring DMA tag.\n"); 1203 goto fail; 1204 } 1205 1206 /* Create DMA tag for coalescing message block. */ 1207 error = bus_dma_tag_create( 1208 sc->alc_cdata.alc_parent_tag, /* parent */ 1209 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1210 BUS_SPACE_MAXADDR, /* lowaddr */ 1211 BUS_SPACE_MAXADDR, /* highaddr */ 1212 NULL, NULL, /* filter, filterarg */ 1213 ALC_CMB_SZ, /* maxsize */ 1214 1, /* nsegments */ 1215 ALC_CMB_SZ, /* maxsegsize */ 1216 0, /* flags */ 1217 NULL, NULL, /* lockfunc, lockarg */ 1218 &sc->alc_cdata.alc_cmb_tag); 1219 if (error != 0) { 1220 device_printf(sc->alc_dev, 1221 "could not create CMB DMA tag.\n"); 1222 goto fail; 1223 } 1224 /* Create DMA tag for status message block. */ 1225 error = bus_dma_tag_create( 1226 sc->alc_cdata.alc_parent_tag, /* parent */ 1227 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1228 BUS_SPACE_MAXADDR, /* lowaddr */ 1229 BUS_SPACE_MAXADDR, /* highaddr */ 1230 NULL, NULL, /* filter, filterarg */ 1231 ALC_SMB_SZ, /* maxsize */ 1232 1, /* nsegments */ 1233 ALC_SMB_SZ, /* maxsegsize */ 1234 0, /* flags */ 1235 NULL, NULL, /* lockfunc, lockarg */ 1236 &sc->alc_cdata.alc_smb_tag); 1237 if (error != 0) { 1238 device_printf(sc->alc_dev, 1239 "could not create SMB DMA tag.\n"); 1240 goto fail; 1241 } 1242 1243 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1244 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1245 (void **)&sc->alc_rdata.alc_tx_ring, 1246 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1247 &sc->alc_cdata.alc_tx_ring_map); 1248 if (error != 0) { 1249 device_printf(sc->alc_dev, 1250 "could not allocate DMA'able memory for Tx ring.\n"); 1251 goto fail; 1252 } 1253 ctx.alc_busaddr = 0; 1254 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1255 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1256 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1257 if (error != 0 || ctx.alc_busaddr == 0) { 1258 device_printf(sc->alc_dev, 1259 "could not load DMA'able memory for Tx ring.\n"); 1260 goto fail; 1261 } 1262 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1263 1264 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1265 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1266 (void **)&sc->alc_rdata.alc_rx_ring, 1267 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1268 &sc->alc_cdata.alc_rx_ring_map); 1269 if (error != 0) { 1270 device_printf(sc->alc_dev, 1271 "could not allocate DMA'able memory for Rx ring.\n"); 1272 goto fail; 1273 } 1274 ctx.alc_busaddr = 0; 1275 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1276 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1277 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1278 if (error != 0 || ctx.alc_busaddr == 0) { 1279 device_printf(sc->alc_dev, 1280 "could not load DMA'able memory for Rx ring.\n"); 1281 goto fail; 1282 } 1283 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1284 1285 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1286 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1287 (void **)&sc->alc_rdata.alc_rr_ring, 1288 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1289 &sc->alc_cdata.alc_rr_ring_map); 1290 if (error != 0) { 1291 device_printf(sc->alc_dev, 1292 "could not allocate DMA'able memory for Rx return ring.\n"); 1293 goto fail; 1294 } 1295 ctx.alc_busaddr = 0; 1296 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1297 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1298 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1299 if (error != 0 || ctx.alc_busaddr == 0) { 1300 device_printf(sc->alc_dev, 1301 "could not load DMA'able memory for Tx ring.\n"); 1302 goto fail; 1303 } 1304 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1305 1306 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1307 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1308 (void **)&sc->alc_rdata.alc_cmb, 1309 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1310 &sc->alc_cdata.alc_cmb_map); 1311 if (error != 0) { 1312 device_printf(sc->alc_dev, 1313 "could not allocate DMA'able memory for CMB.\n"); 1314 goto fail; 1315 } 1316 ctx.alc_busaddr = 0; 1317 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1318 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1319 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1320 if (error != 0 || ctx.alc_busaddr == 0) { 1321 device_printf(sc->alc_dev, 1322 "could not load DMA'able memory for CMB.\n"); 1323 goto fail; 1324 } 1325 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1326 1327 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1328 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1329 (void **)&sc->alc_rdata.alc_smb, 1330 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1331 &sc->alc_cdata.alc_smb_map); 1332 if (error != 0) { 1333 device_printf(sc->alc_dev, 1334 "could not allocate DMA'able memory for SMB.\n"); 1335 goto fail; 1336 } 1337 ctx.alc_busaddr = 0; 1338 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1339 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1340 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1341 if (error != 0 || ctx.alc_busaddr == 0) { 1342 device_printf(sc->alc_dev, 1343 "could not load DMA'able memory for CMB.\n"); 1344 goto fail; 1345 } 1346 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1347 1348 /* Make sure we've not crossed 4GB boundary. */ 1349 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1350 (error = alc_check_boundary(sc)) != 0) { 1351 device_printf(sc->alc_dev, "4GB boundary crossed, " 1352 "switching to 32bit DMA addressing mode.\n"); 1353 alc_dma_free(sc); 1354 /* 1355 * Limit max allowable DMA address space to 32bit 1356 * and try again. 1357 */ 1358 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1359 goto again; 1360 } 1361 1362 /* 1363 * Create Tx buffer parent tag. 1364 * AR8131/AR8132 allows 64bit DMA addressing of Tx/Rx buffers 1365 * so it needs separate parent DMA tag as parent DMA address 1366 * space could be restricted to be within 32bit address space 1367 * by 4GB boundary crossing. 1368 */ 1369 error = bus_dma_tag_create( 1370 bus_get_dma_tag(sc->alc_dev), /* parent */ 1371 1, 0, /* alignment, boundary */ 1372 BUS_SPACE_MAXADDR, /* lowaddr */ 1373 BUS_SPACE_MAXADDR, /* highaddr */ 1374 NULL, NULL, /* filter, filterarg */ 1375 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1376 0, /* nsegments */ 1377 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1378 0, /* flags */ 1379 NULL, NULL, /* lockfunc, lockarg */ 1380 &sc->alc_cdata.alc_buffer_tag); 1381 if (error != 0) { 1382 device_printf(sc->alc_dev, 1383 "could not create parent buffer DMA tag.\n"); 1384 goto fail; 1385 } 1386 1387 /* Create DMA tag for Tx buffers. */ 1388 error = bus_dma_tag_create( 1389 sc->alc_cdata.alc_buffer_tag, /* parent */ 1390 1, 0, /* alignment, boundary */ 1391 BUS_SPACE_MAXADDR, /* lowaddr */ 1392 BUS_SPACE_MAXADDR, /* highaddr */ 1393 NULL, NULL, /* filter, filterarg */ 1394 ALC_TSO_MAXSIZE, /* maxsize */ 1395 ALC_MAXTXSEGS, /* nsegments */ 1396 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1397 0, /* flags */ 1398 NULL, NULL, /* lockfunc, lockarg */ 1399 &sc->alc_cdata.alc_tx_tag); 1400 if (error != 0) { 1401 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1402 goto fail; 1403 } 1404 1405 /* Create DMA tag for Rx buffers. */ 1406 error = bus_dma_tag_create( 1407 sc->alc_cdata.alc_buffer_tag, /* parent */ 1408 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1409 BUS_SPACE_MAXADDR, /* lowaddr */ 1410 BUS_SPACE_MAXADDR, /* highaddr */ 1411 NULL, NULL, /* filter, filterarg */ 1412 MCLBYTES, /* maxsize */ 1413 1, /* nsegments */ 1414 MCLBYTES, /* maxsegsize */ 1415 0, /* flags */ 1416 NULL, NULL, /* lockfunc, lockarg */ 1417 &sc->alc_cdata.alc_rx_tag); 1418 if (error != 0) { 1419 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1420 goto fail; 1421 } 1422 /* Create DMA maps for Tx buffers. */ 1423 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1424 txd = &sc->alc_cdata.alc_txdesc[i]; 1425 txd->tx_m = NULL; 1426 txd->tx_dmamap = NULL; 1427 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1428 &txd->tx_dmamap); 1429 if (error != 0) { 1430 device_printf(sc->alc_dev, 1431 "could not create Tx dmamap.\n"); 1432 goto fail; 1433 } 1434 } 1435 /* Create DMA maps for Rx buffers. */ 1436 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1437 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1438 device_printf(sc->alc_dev, 1439 "could not create spare Rx dmamap.\n"); 1440 goto fail; 1441 } 1442 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1443 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1444 rxd->rx_m = NULL; 1445 rxd->rx_dmamap = NULL; 1446 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1447 &rxd->rx_dmamap); 1448 if (error != 0) { 1449 device_printf(sc->alc_dev, 1450 "could not create Rx dmamap.\n"); 1451 goto fail; 1452 } 1453 } 1454 1455fail: 1456 return (error); 1457} 1458 1459static void 1460alc_dma_free(struct alc_softc *sc) 1461{ 1462 struct alc_txdesc *txd; 1463 struct alc_rxdesc *rxd; 1464 int i; 1465 1466 /* Tx buffers. */ 1467 if (sc->alc_cdata.alc_tx_tag != NULL) { 1468 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1469 txd = &sc->alc_cdata.alc_txdesc[i]; 1470 if (txd->tx_dmamap != NULL) { 1471 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1472 txd->tx_dmamap); 1473 txd->tx_dmamap = NULL; 1474 } 1475 } 1476 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1477 sc->alc_cdata.alc_tx_tag = NULL; 1478 } 1479 /* Rx buffers */ 1480 if (sc->alc_cdata.alc_rx_tag != NULL) { 1481 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1482 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1483 if (rxd->rx_dmamap != NULL) { 1484 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1485 rxd->rx_dmamap); 1486 rxd->rx_dmamap = NULL; 1487 } 1488 } 1489 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1490 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1491 sc->alc_cdata.alc_rx_sparemap); 1492 sc->alc_cdata.alc_rx_sparemap = NULL; 1493 } 1494 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1495 sc->alc_cdata.alc_rx_tag = NULL; 1496 } 1497 /* Tx descriptor ring. */ 1498 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1499 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1500 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1501 sc->alc_cdata.alc_tx_ring_map); 1502 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1503 sc->alc_rdata.alc_tx_ring != NULL) 1504 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1505 sc->alc_rdata.alc_tx_ring, 1506 sc->alc_cdata.alc_tx_ring_map); 1507 sc->alc_rdata.alc_tx_ring = NULL; 1508 sc->alc_cdata.alc_tx_ring_map = NULL; 1509 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1510 sc->alc_cdata.alc_tx_ring_tag = NULL; 1511 } 1512 /* Rx ring. */ 1513 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1514 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1515 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1516 sc->alc_cdata.alc_rx_ring_map); 1517 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1518 sc->alc_rdata.alc_rx_ring != NULL) 1519 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1520 sc->alc_rdata.alc_rx_ring, 1521 sc->alc_cdata.alc_rx_ring_map); 1522 sc->alc_rdata.alc_rx_ring = NULL; 1523 sc->alc_cdata.alc_rx_ring_map = NULL; 1524 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1525 sc->alc_cdata.alc_rx_ring_tag = NULL; 1526 } 1527 /* Rx return ring. */ 1528 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1529 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1530 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1531 sc->alc_cdata.alc_rr_ring_map); 1532 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1533 sc->alc_rdata.alc_rr_ring != NULL) 1534 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1535 sc->alc_rdata.alc_rr_ring, 1536 sc->alc_cdata.alc_rr_ring_map); 1537 sc->alc_rdata.alc_rr_ring = NULL; 1538 sc->alc_cdata.alc_rr_ring_map = NULL; 1539 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1540 sc->alc_cdata.alc_rr_ring_tag = NULL; 1541 } 1542 /* CMB block */ 1543 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1544 if (sc->alc_cdata.alc_cmb_map != NULL) 1545 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1546 sc->alc_cdata.alc_cmb_map); 1547 if (sc->alc_cdata.alc_cmb_map != NULL && 1548 sc->alc_rdata.alc_cmb != NULL) 1549 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1550 sc->alc_rdata.alc_cmb, 1551 sc->alc_cdata.alc_cmb_map); 1552 sc->alc_rdata.alc_cmb = NULL; 1553 sc->alc_cdata.alc_cmb_map = NULL; 1554 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1555 sc->alc_cdata.alc_cmb_tag = NULL; 1556 } 1557 /* SMB block */ 1558 if (sc->alc_cdata.alc_smb_tag != NULL) { 1559 if (sc->alc_cdata.alc_smb_map != NULL) 1560 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1561 sc->alc_cdata.alc_smb_map); 1562 if (sc->alc_cdata.alc_smb_map != NULL && 1563 sc->alc_rdata.alc_smb != NULL) 1564 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1565 sc->alc_rdata.alc_smb, 1566 sc->alc_cdata.alc_smb_map); 1567 sc->alc_rdata.alc_smb = NULL; 1568 sc->alc_cdata.alc_smb_map = NULL; 1569 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1570 sc->alc_cdata.alc_smb_tag = NULL; 1571 } 1572 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1573 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1574 sc->alc_cdata.alc_buffer_tag = NULL; 1575 } 1576 if (sc->alc_cdata.alc_parent_tag != NULL) { 1577 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1578 sc->alc_cdata.alc_parent_tag = NULL; 1579 } 1580} 1581 1582static int 1583alc_shutdown(device_t dev) 1584{ 1585 1586 return (alc_suspend(dev)); 1587} 1588 1589/* 1590 * Note, this driver resets the link speed to 10/100Mbps by 1591 * restarting auto-negotiation in suspend/shutdown phase but we 1592 * don't know whether that auto-negotiation would succeed or not 1593 * as driver has no control after powering off/suspend operation. 1594 * If the renegotiation fail WOL may not work. Running at 1Gbps 1595 * will draw more power than 375mA at 3.3V which is specified in 1596 * PCI specification and that would result in complete 1597 * shutdowning power to ethernet controller. 1598 * 1599 * TODO 1600 * Save current negotiated media speed/duplex/flow-control to 1601 * softc and restore the same link again after resuming. PHY 1602 * handling such as power down/resetting to 100Mbps may be better 1603 * handled in suspend method in phy driver. 1604 */ 1605static void 1606alc_setlinkspeed(struct alc_softc *sc) 1607{ 1608 struct mii_data *mii; 1609 int aneg, i; 1610 1611 mii = device_get_softc(sc->alc_miibus); 1612 mii_pollstat(mii); 1613 aneg = 0; 1614 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1615 (IFM_ACTIVE | IFM_AVALID)) { 1616 switch IFM_SUBTYPE(mii->mii_media_active) { 1617 case IFM_10_T: 1618 case IFM_100_TX: 1619 return; 1620 case IFM_1000_T: 1621 aneg++; 1622 break; 1623 default: 1624 break; 1625 } 1626 } 1627 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1628 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1629 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1630 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1631 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1632 DELAY(1000); 1633 if (aneg != 0) { 1634 /* 1635 * Poll link state until alc(4) get a 10/100Mbps link. 1636 */ 1637 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1638 mii_pollstat(mii); 1639 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1640 == (IFM_ACTIVE | IFM_AVALID)) { 1641 switch (IFM_SUBTYPE( 1642 mii->mii_media_active)) { 1643 case IFM_10_T: 1644 case IFM_100_TX: 1645 alc_mac_config(sc); 1646 return; 1647 default: 1648 break; 1649 } 1650 } 1651 ALC_UNLOCK(sc); 1652 pause("alclnk", hz); 1653 ALC_LOCK(sc); 1654 } 1655 if (i == MII_ANEGTICKS_GIGE) 1656 device_printf(sc->alc_dev, 1657 "establishing a link failed, WOL may not work!"); 1658 } 1659 /* 1660 * No link, force MAC to have 100Mbps, full-duplex link. 1661 * This is the last resort and may/may not work. 1662 */ 1663 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1664 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1665 alc_mac_config(sc); 1666} 1667 1668static void 1669alc_setwol(struct alc_softc *sc) 1670{ 1671 struct ifnet *ifp; 1672 uint32_t cap, reg, pmcs; 1673 uint16_t pmstat; 1674 int base, pmc; 1675 1676 ALC_LOCK_ASSERT(sc); 1677 1678 if (pci_find_extcap(sc->alc_dev, PCIY_EXPRESS, &base) == 0) { 1679 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 1680 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1681 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 1682 alc_disable_l0s_l1(sc); 1683 } 1684 } 1685 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) != 0) { 1686 /* Disable WOL. */ 1687 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1688 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1689 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1690 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1691 /* Force PHY power down. */ 1692 alc_phy_down(sc); 1693 return; 1694 } 1695 1696 ifp = sc->alc_ifp; 1697 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1698 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1699 alc_setlinkspeed(sc); 1700 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 1701 reg &= ~MASTER_CLK_SEL_DIS; 1702 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 1703 } 1704 1705 pmcs = 0; 1706 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1707 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1708 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1709 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1710 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1711 MAC_CFG_BCAST); 1712 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1713 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1714 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1715 reg |= MAC_CFG_RX_ENB; 1716 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1717 1718 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1719 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1720 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1721 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1722 /* WOL disabled, PHY power down. */ 1723 alc_phy_down(sc); 1724 } 1725 /* Request PME. */ 1726 pmstat = pci_read_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, 2); 1727 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1728 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1729 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1730 pci_write_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1731} 1732 1733static int 1734alc_suspend(device_t dev) 1735{ 1736 struct alc_softc *sc; 1737 1738 sc = device_get_softc(dev); 1739 1740 ALC_LOCK(sc); 1741 alc_stop(sc); 1742 alc_setwol(sc); 1743 ALC_UNLOCK(sc); 1744 1745 return (0); 1746} 1747 1748static int 1749alc_resume(device_t dev) 1750{ 1751 struct alc_softc *sc; 1752 struct ifnet *ifp; 1753 int pmc; 1754 uint16_t pmstat; 1755 1756 sc = device_get_softc(dev); 1757 1758 ALC_LOCK(sc); 1759 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) == 0) { 1760 /* Disable PME and clear PME status. */ 1761 pmstat = pci_read_config(sc->alc_dev, 1762 pmc + PCIR_POWER_STATUS, 2); 1763 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1764 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1765 pci_write_config(sc->alc_dev, 1766 pmc + PCIR_POWER_STATUS, pmstat, 2); 1767 } 1768 } 1769 /* Reset PHY. */ 1770 alc_phy_reset(sc); 1771 ifp = sc->alc_ifp; 1772 if ((ifp->if_flags & IFF_UP) != 0) { 1773 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1774 alc_init_locked(sc); 1775 } 1776 ALC_UNLOCK(sc); 1777 1778 return (0); 1779} 1780 1781static int 1782alc_encap(struct alc_softc *sc, struct mbuf **m_head) 1783{ 1784 struct alc_txdesc *txd, *txd_last; 1785 struct tx_desc *desc; 1786 struct mbuf *m; 1787 struct ip *ip; 1788 struct tcphdr *tcp; 1789 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 1790 bus_dmamap_t map; 1791 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1792 int error, idx, nsegs, prod; 1793 1794 ALC_LOCK_ASSERT(sc); 1795 1796 M_ASSERTPKTHDR((*m_head)); 1797 1798 m = *m_head; 1799 ip = NULL; 1800 tcp = NULL; 1801 ip_off = poff = 0; 1802 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 1803 /* 1804 * AR8131/AR8132 requires offset of TCP/UDP header in its 1805 * Tx descriptor to perform Tx checksum offloading. TSO 1806 * also requires TCP header offset and modification of 1807 * IP/TCP header. This kind of operation takes many CPU 1808 * cycles on FreeBSD so fast host CPU is required to get 1809 * smooth TSO performance. 1810 */ 1811 struct ether_header *eh; 1812 1813 if (M_WRITABLE(m) == 0) { 1814 /* Get a writable copy. */ 1815 m = m_dup(*m_head, M_DONTWAIT); 1816 /* Release original mbufs. */ 1817 m_freem(*m_head); 1818 if (m == NULL) { 1819 *m_head = NULL; 1820 return (ENOBUFS); 1821 } 1822 *m_head = m; 1823 } 1824 1825 ip_off = sizeof(struct ether_header); 1826 m = m_pullup(m, ip_off); 1827 if (m == NULL) { 1828 *m_head = NULL; 1829 return (ENOBUFS); 1830 } 1831 eh = mtod(m, struct ether_header *); 1832 /* 1833 * Check if hardware VLAN insertion is off. 1834 * Additional check for LLC/SNAP frame? 1835 */ 1836 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1837 ip_off = sizeof(struct ether_vlan_header); 1838 m = m_pullup(m, ip_off); 1839 if (m == NULL) { 1840 *m_head = NULL; 1841 return (ENOBUFS); 1842 } 1843 } 1844 m = m_pullup(m, ip_off + sizeof(struct ip)); 1845 if (m == NULL) { 1846 *m_head = NULL; 1847 return (ENOBUFS); 1848 } 1849 ip = (struct ip *)(mtod(m, char *) + ip_off); 1850 poff = ip_off + (ip->ip_hl << 2); 1851 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1852 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1853 if (m == NULL) { 1854 *m_head = NULL; 1855 return (ENOBUFS); 1856 } 1857 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1858 m = m_pullup(m, poff + (tcp->th_off << 2)); 1859 if (m == NULL) { 1860 *m_head = NULL; 1861 return (ENOBUFS); 1862 } 1863 /* 1864 * Due to strict adherence of Microsoft NDIS 1865 * Large Send specification, hardware expects 1866 * a pseudo TCP checksum inserted by upper 1867 * stack. Unfortunately the pseudo TCP 1868 * checksum that NDIS refers to does not include 1869 * TCP payload length so driver should recompute 1870 * the pseudo checksum here. Hopefully this 1871 * wouldn't be much burden on modern CPUs. 1872 * 1873 * Reset IP checksum and recompute TCP pseudo 1874 * checksum as NDIS specification said. 1875 */ 1876 ip->ip_sum = 0; 1877 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1878 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1879 } 1880 *m_head = m; 1881 } 1882 1883 prod = sc->alc_cdata.alc_tx_prod; 1884 txd = &sc->alc_cdata.alc_txdesc[prod]; 1885 txd_last = txd; 1886 map = txd->tx_dmamap; 1887 1888 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 1889 *m_head, txsegs, &nsegs, 0); 1890 if (error == EFBIG) { 1891 m = m_collapse(*m_head, M_DONTWAIT, ALC_MAXTXSEGS); 1892 if (m == NULL) { 1893 m_freem(*m_head); 1894 *m_head = NULL; 1895 return (ENOMEM); 1896 } 1897 *m_head = m; 1898 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 1899 *m_head, txsegs, &nsegs, 0); 1900 if (error != 0) { 1901 m_freem(*m_head); 1902 *m_head = NULL; 1903 return (error); 1904 } 1905 } else if (error != 0) 1906 return (error); 1907 if (nsegs == 0) { 1908 m_freem(*m_head); 1909 *m_head = NULL; 1910 return (EIO); 1911 } 1912 1913 /* Check descriptor overrun. */ 1914 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 1915 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 1916 return (ENOBUFS); 1917 } 1918 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 1919 1920 m = *m_head; 1921 cflags = TD_ETHERNET; 1922 vtag = 0; 1923 desc = NULL; 1924 idx = 0; 1925 /* Configure VLAN hardware tag insertion. */ 1926 if ((m->m_flags & M_VLANTAG) != 0) { 1927 vtag = htons(m->m_pkthdr.ether_vtag); 1928 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 1929 cflags |= TD_INS_VLAN_TAG; 1930 } 1931 /* Configure Tx checksum offload. */ 1932 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 1933#ifdef ALC_USE_CUSTOM_CSUM 1934 cflags |= TD_CUSTOM_CSUM; 1935 /* Set checksum start offset. */ 1936 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 1937 TD_PLOAD_OFFSET_MASK; 1938 /* Set checksum insertion position of TCP/UDP. */ 1939 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 1940 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 1941#else 1942 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1943 cflags |= TD_IPCSUM; 1944 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1945 cflags |= TD_TCPCSUM; 1946 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1947 cflags |= TD_UDPCSUM; 1948 /* Set TCP/UDP header offset. */ 1949 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 1950 TD_L4HDR_OFFSET_MASK; 1951#endif 1952 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1953 /* Request TSO and set MSS. */ 1954 cflags |= TD_TSO | TD_TSO_DESCV1; 1955 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 1956 TD_MSS_MASK; 1957 /* Set TCP header offset. */ 1958 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 1959 TD_TCPHDR_OFFSET_MASK; 1960 /* 1961 * AR8131/AR8132 requires the first buffer should 1962 * only hold IP/TCP header data. Payload should 1963 * be handled in other descriptors. 1964 */ 1965 hdrlen = poff + (tcp->th_off << 2); 1966 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1967 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 1968 desc->flags = htole32(cflags); 1969 desc->addr = htole64(txsegs[0].ds_addr); 1970 sc->alc_cdata.alc_tx_cnt++; 1971 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1972 if (m->m_len - hdrlen > 0) { 1973 /* Handle remaining payload of the first fragment. */ 1974 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1975 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 1976 vtag)); 1977 desc->flags = htole32(cflags); 1978 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1979 sc->alc_cdata.alc_tx_cnt++; 1980 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1981 } 1982 /* Handle remaining fragments. */ 1983 idx = 1; 1984 } 1985 for (; idx < nsegs; idx++) { 1986 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1987 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 1988 desc->flags = htole32(cflags); 1989 desc->addr = htole64(txsegs[idx].ds_addr); 1990 sc->alc_cdata.alc_tx_cnt++; 1991 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 1992 } 1993 /* Update producer index. */ 1994 sc->alc_cdata.alc_tx_prod = prod; 1995 1996 /* Finally set EOP on the last descriptor. */ 1997 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 1998 desc = &sc->alc_rdata.alc_tx_ring[prod]; 1999 desc->flags |= htole32(TD_EOP); 2000 2001 /* Swap dmamap of the first and the last. */ 2002 txd = &sc->alc_cdata.alc_txdesc[prod]; 2003 map = txd_last->tx_dmamap; 2004 txd_last->tx_dmamap = txd->tx_dmamap; 2005 txd->tx_dmamap = map; 2006 txd->tx_m = m; 2007 2008 return (0); 2009} 2010 2011static void 2012alc_tx_task(void *arg, int pending) 2013{ 2014 struct ifnet *ifp; 2015 2016 ifp = (struct ifnet *)arg; 2017 alc_start(ifp); 2018} 2019 2020static void 2021alc_start(struct ifnet *ifp) 2022{ 2023 struct alc_softc *sc; 2024 struct mbuf *m_head; 2025 int enq; 2026 2027 sc = ifp->if_softc; 2028 2029 ALC_LOCK(sc); 2030 2031 /* Reclaim transmitted frames. */ 2032 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2033 alc_txeof(sc); 2034 2035 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2036 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) { 2037 ALC_UNLOCK(sc); 2038 return; 2039 } 2040 2041 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2042 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2043 if (m_head == NULL) 2044 break; 2045 /* 2046 * Pack the data into the transmit ring. If we 2047 * don't have room, set the OACTIVE flag and wait 2048 * for the NIC to drain the ring. 2049 */ 2050 if (alc_encap(sc, &m_head)) { 2051 if (m_head == NULL) 2052 break; 2053 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2054 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2055 break; 2056 } 2057 2058 enq++; 2059 /* 2060 * If there's a BPF listener, bounce a copy of this frame 2061 * to him. 2062 */ 2063 ETHER_BPF_MTAP(ifp, m_head); 2064 } 2065 2066 if (enq > 0) { 2067 /* Sync descriptors. */ 2068 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2069 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2070 /* Kick. Assume we're using normal Tx priority queue. */ 2071 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2072 (sc->alc_cdata.alc_tx_prod << 2073 MBOX_TD_PROD_LO_IDX_SHIFT) & 2074 MBOX_TD_PROD_LO_IDX_MASK); 2075 /* Set a timeout in case the chip goes out to lunch. */ 2076 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2077 } 2078 2079 ALC_UNLOCK(sc); 2080} 2081 2082static void 2083alc_watchdog(struct alc_softc *sc) 2084{ 2085 struct ifnet *ifp; 2086 2087 ALC_LOCK_ASSERT(sc); 2088 2089 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2090 return; 2091 2092 ifp = sc->alc_ifp; 2093 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2094 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2095 ifp->if_oerrors++; 2096 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2097 alc_init_locked(sc); 2098 return; 2099 } 2100 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2101 ifp->if_oerrors++; 2102 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2103 alc_init_locked(sc); 2104 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2105 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2106} 2107 2108static int 2109alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2110{ 2111 struct alc_softc *sc; 2112 struct ifreq *ifr; 2113 struct mii_data *mii; 2114 int error, mask; 2115 2116 sc = ifp->if_softc; 2117 ifr = (struct ifreq *)data; 2118 error = 0; 2119 switch (cmd) { 2120 case SIOCSIFMTU: 2121 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALC_JUMBO_MTU || 2122 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2123 ifr->ifr_mtu > ETHERMTU)) 2124 error = EINVAL; 2125 else if (ifp->if_mtu != ifr->ifr_mtu) { 2126 ALC_LOCK(sc); 2127 ifp->if_mtu = ifr->ifr_mtu; 2128 /* AR8131/AR8132 has 13 bits MSS field. */ 2129 if (ifp->if_mtu > ALC_TSO_MTU && 2130 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2131 ifp->if_capenable &= ~IFCAP_TSO4; 2132 ifp->if_hwassist &= ~CSUM_TSO; 2133 VLAN_CAPABILITIES(ifp); 2134 } 2135 ALC_UNLOCK(sc); 2136 } 2137 break; 2138 case SIOCSIFFLAGS: 2139 ALC_LOCK(sc); 2140 if ((ifp->if_flags & IFF_UP) != 0) { 2141 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2142 ((ifp->if_flags ^ sc->alc_if_flags) & 2143 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2144 alc_rxfilter(sc); 2145 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2146 alc_init_locked(sc); 2147 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2148 alc_stop(sc); 2149 sc->alc_if_flags = ifp->if_flags; 2150 ALC_UNLOCK(sc); 2151 break; 2152 case SIOCADDMULTI: 2153 case SIOCDELMULTI: 2154 ALC_LOCK(sc); 2155 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2156 alc_rxfilter(sc); 2157 ALC_UNLOCK(sc); 2158 break; 2159 case SIOCSIFMEDIA: 2160 case SIOCGIFMEDIA: 2161 mii = device_get_softc(sc->alc_miibus); 2162 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2163 break; 2164 case SIOCSIFCAP: 2165 ALC_LOCK(sc); 2166 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2167 if ((mask & IFCAP_TXCSUM) != 0 && 2168 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2169 ifp->if_capenable ^= IFCAP_TXCSUM; 2170 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2171 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2172 else 2173 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2174 } 2175 if ((mask & IFCAP_TSO4) != 0 && 2176 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2177 ifp->if_capenable ^= IFCAP_TSO4; 2178 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2179 /* AR8131/AR8132 has 13 bits MSS field. */ 2180 if (ifp->if_mtu > ALC_TSO_MTU) { 2181 ifp->if_capenable &= ~IFCAP_TSO4; 2182 ifp->if_hwassist &= ~CSUM_TSO; 2183 } else 2184 ifp->if_hwassist |= CSUM_TSO; 2185 } else 2186 ifp->if_hwassist &= ~CSUM_TSO; 2187 } 2188 if ((mask & IFCAP_WOL_MCAST) != 0 && 2189 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2190 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2191 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2192 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2193 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2194 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2195 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2196 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2197 alc_rxvlan(sc); 2198 } 2199 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2200 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2201 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2202 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2203 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2204 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2205 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2206 ifp->if_capenable &= 2207 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2208 ALC_UNLOCK(sc); 2209 VLAN_CAPABILITIES(ifp); 2210 break; 2211 default: 2212 error = ether_ioctl(ifp, cmd, data); 2213 break; 2214 } 2215 2216 return (error); 2217} 2218 2219static void 2220alc_mac_config(struct alc_softc *sc) 2221{ 2222 struct mii_data *mii; 2223 uint32_t reg; 2224 2225 ALC_LOCK_ASSERT(sc); 2226 2227 mii = device_get_softc(sc->alc_miibus); 2228 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2229 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2230 MAC_CFG_SPEED_MASK); 2231 /* Reprogram MAC with resolved speed/duplex. */ 2232 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2233 case IFM_10_T: 2234 case IFM_100_TX: 2235 reg |= MAC_CFG_SPEED_10_100; 2236 break; 2237 case IFM_1000_T: 2238 reg |= MAC_CFG_SPEED_1000; 2239 break; 2240 } 2241 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2242 reg |= MAC_CFG_FULL_DUPLEX; 2243#ifdef notyet 2244 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2245 reg |= MAC_CFG_TX_FC; 2246 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2247 reg |= MAC_CFG_RX_FC; 2248#endif 2249 } 2250 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2251} 2252 2253static void 2254alc_stats_clear(struct alc_softc *sc) 2255{ 2256 struct smb sb, *smb; 2257 uint32_t *reg; 2258 int i; 2259 2260 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2261 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2262 sc->alc_cdata.alc_smb_map, 2263 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2264 smb = sc->alc_rdata.alc_smb; 2265 /* Update done, clear. */ 2266 smb->updated = 0; 2267 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2268 sc->alc_cdata.alc_smb_map, 2269 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2270 } else { 2271 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2272 reg++) { 2273 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2274 i += sizeof(uint32_t); 2275 } 2276 /* Read Tx statistics. */ 2277 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2278 reg++) { 2279 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2280 i += sizeof(uint32_t); 2281 } 2282 } 2283} 2284 2285static void 2286alc_stats_update(struct alc_softc *sc) 2287{ 2288 struct alc_hw_stats *stat; 2289 struct smb sb, *smb; 2290 struct ifnet *ifp; 2291 uint32_t *reg; 2292 int i; 2293 2294 ALC_LOCK_ASSERT(sc); 2295 2296 ifp = sc->alc_ifp; 2297 stat = &sc->alc_stats; 2298 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2299 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2300 sc->alc_cdata.alc_smb_map, 2301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2302 smb = sc->alc_rdata.alc_smb; 2303 if (smb->updated == 0) 2304 return; 2305 } else { 2306 smb = &sb; 2307 /* Read Rx statistics. */ 2308 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2309 reg++) { 2310 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2311 i += sizeof(uint32_t); 2312 } 2313 /* Read Tx statistics. */ 2314 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2315 reg++) { 2316 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2317 i += sizeof(uint32_t); 2318 } 2319 } 2320 2321 /* Rx stats. */ 2322 stat->rx_frames += smb->rx_frames; 2323 stat->rx_bcast_frames += smb->rx_bcast_frames; 2324 stat->rx_mcast_frames += smb->rx_mcast_frames; 2325 stat->rx_pause_frames += smb->rx_pause_frames; 2326 stat->rx_control_frames += smb->rx_control_frames; 2327 stat->rx_crcerrs += smb->rx_crcerrs; 2328 stat->rx_lenerrs += smb->rx_lenerrs; 2329 stat->rx_bytes += smb->rx_bytes; 2330 stat->rx_runts += smb->rx_runts; 2331 stat->rx_fragments += smb->rx_fragments; 2332 stat->rx_pkts_64 += smb->rx_pkts_64; 2333 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2334 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2335 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2336 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2337 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2338 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2339 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2340 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2341 stat->rx_rrs_errs += smb->rx_rrs_errs; 2342 stat->rx_alignerrs += smb->rx_alignerrs; 2343 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2344 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2345 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2346 2347 /* Tx stats. */ 2348 stat->tx_frames += smb->tx_frames; 2349 stat->tx_bcast_frames += smb->tx_bcast_frames; 2350 stat->tx_mcast_frames += smb->tx_mcast_frames; 2351 stat->tx_pause_frames += smb->tx_pause_frames; 2352 stat->tx_excess_defer += smb->tx_excess_defer; 2353 stat->tx_control_frames += smb->tx_control_frames; 2354 stat->tx_deferred += smb->tx_deferred; 2355 stat->tx_bytes += smb->tx_bytes; 2356 stat->tx_pkts_64 += smb->tx_pkts_64; 2357 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2358 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2359 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2360 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2361 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2362 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2363 stat->tx_single_colls += smb->tx_single_colls; 2364 stat->tx_multi_colls += smb->tx_multi_colls; 2365 stat->tx_late_colls += smb->tx_late_colls; 2366 stat->tx_excess_colls += smb->tx_excess_colls; 2367 stat->tx_abort += smb->tx_abort; 2368 stat->tx_underrun += smb->tx_underrun; 2369 stat->tx_desc_underrun += smb->tx_desc_underrun; 2370 stat->tx_lenerrs += smb->tx_lenerrs; 2371 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2372 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2373 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2374 2375 /* Update counters in ifnet. */ 2376 ifp->if_opackets += smb->tx_frames; 2377 2378 ifp->if_collisions += smb->tx_single_colls + 2379 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2380 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2381 2382 /* 2383 * XXX 2384 * tx_pkts_truncated counter looks suspicious. It constantly 2385 * increments with no sign of Tx errors. This may indicate 2386 * the counter name is not correct one so I've removed the 2387 * counter in output errors. 2388 */ 2389 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2390 smb->tx_underrun; 2391 2392 ifp->if_ipackets += smb->rx_frames; 2393 2394 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2395 smb->rx_runts + smb->rx_pkts_truncated + 2396 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2397 smb->rx_alignerrs; 2398 2399 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2400 /* Update done, clear. */ 2401 smb->updated = 0; 2402 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2403 sc->alc_cdata.alc_smb_map, 2404 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2405 } 2406} 2407 2408static int 2409alc_intr(void *arg) 2410{ 2411 struct alc_softc *sc; 2412 uint32_t status; 2413 2414 sc = (struct alc_softc *)arg; 2415 2416 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2417 if ((status & ALC_INTRS) == 0) 2418 return (FILTER_STRAY); 2419 /* Disable interrupts. */ 2420 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2421 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2422 2423 return (FILTER_HANDLED); 2424} 2425 2426static void 2427alc_int_task(void *arg, int pending) 2428{ 2429 struct alc_softc *sc; 2430 struct ifnet *ifp; 2431 uint32_t status; 2432 int more; 2433 2434 sc = (struct alc_softc *)arg; 2435 ifp = sc->alc_ifp; 2436 2437 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2438 more = atomic_readandclear_int(&sc->alc_morework); 2439 if (more != 0) 2440 status |= INTR_RX_PKT; 2441 if ((status & ALC_INTRS) == 0) 2442 goto done; 2443 2444 /* Acknowledge interrupts but still disable interrupts. */ 2445 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2446 2447 more = 0; 2448 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2449 if ((status & INTR_RX_PKT) != 0) { 2450 more = alc_rxintr(sc, sc->alc_process_limit); 2451 if (more == EAGAIN) 2452 atomic_set_int(&sc->alc_morework, 1); 2453 else if (more == EIO) { 2454 ALC_LOCK(sc); 2455 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2456 alc_init_locked(sc); 2457 ALC_UNLOCK(sc); 2458 return; 2459 } 2460 } 2461 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2462 INTR_TXQ_TO_RST)) != 0) { 2463 if ((status & INTR_DMA_RD_TO_RST) != 0) 2464 device_printf(sc->alc_dev, 2465 "DMA read error! -- resetting\n"); 2466 if ((status & INTR_DMA_WR_TO_RST) != 0) 2467 device_printf(sc->alc_dev, 2468 "DMA write error! -- resetting\n"); 2469 if ((status & INTR_TXQ_TO_RST) != 0) 2470 device_printf(sc->alc_dev, 2471 "TxQ reset! -- resetting\n"); 2472 ALC_LOCK(sc); 2473 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2474 alc_init_locked(sc); 2475 ALC_UNLOCK(sc); 2476 return; 2477 } 2478 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2479 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2480 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2481 } 2482 2483 if (more == EAGAIN || 2484 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2485 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2486 return; 2487 } 2488 2489done: 2490 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2491 /* Re-enable interrupts if we're running. */ 2492 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2493 } 2494} 2495 2496static void 2497alc_txeof(struct alc_softc *sc) 2498{ 2499 struct ifnet *ifp; 2500 struct alc_txdesc *txd; 2501 uint32_t cons, prod; 2502 int prog; 2503 2504 ALC_LOCK_ASSERT(sc); 2505 2506 ifp = sc->alc_ifp; 2507 2508 if (sc->alc_cdata.alc_tx_cnt == 0) 2509 return; 2510 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2511 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2512 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2513 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2514 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2515 prod = sc->alc_rdata.alc_cmb->cons; 2516 } else 2517 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2518 /* Assume we're using normal Tx priority queue. */ 2519 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2520 MBOX_TD_CONS_LO_IDX_SHIFT; 2521 cons = sc->alc_cdata.alc_tx_cons; 2522 /* 2523 * Go through our Tx list and free mbufs for those 2524 * frames which have been transmitted. 2525 */ 2526 for (prog = 0; cons != prod; prog++, 2527 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2528 if (sc->alc_cdata.alc_tx_cnt <= 0) 2529 break; 2530 prog++; 2531 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2532 sc->alc_cdata.alc_tx_cnt--; 2533 txd = &sc->alc_cdata.alc_txdesc[cons]; 2534 if (txd->tx_m != NULL) { 2535 /* Reclaim transmitted mbufs. */ 2536 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2537 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2538 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2539 txd->tx_dmamap); 2540 m_freem(txd->tx_m); 2541 txd->tx_m = NULL; 2542 } 2543 } 2544 2545 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2546 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2547 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2548 sc->alc_cdata.alc_tx_cons = cons; 2549 /* 2550 * Unarm watchdog timer only when there is no pending 2551 * frames in Tx queue. 2552 */ 2553 if (sc->alc_cdata.alc_tx_cnt == 0) 2554 sc->alc_watchdog_timer = 0; 2555} 2556 2557static int 2558alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2559{ 2560 struct mbuf *m; 2561 bus_dma_segment_t segs[1]; 2562 bus_dmamap_t map; 2563 int nsegs; 2564 2565 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2566 if (m == NULL) 2567 return (ENOBUFS); 2568 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2569#ifndef __NO_STRICT_ALIGNMENT 2570 m_adj(m, sizeof(uint64_t)); 2571#endif 2572 2573 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2574 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2575 m_freem(m); 2576 return (ENOBUFS); 2577 } 2578 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2579 2580 if (rxd->rx_m != NULL) { 2581 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2582 BUS_DMASYNC_POSTREAD); 2583 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2584 } 2585 map = rxd->rx_dmamap; 2586 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2587 sc->alc_cdata.alc_rx_sparemap = map; 2588 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2589 BUS_DMASYNC_PREREAD); 2590 rxd->rx_m = m; 2591 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2592 return (0); 2593} 2594 2595static int 2596alc_rxintr(struct alc_softc *sc, int count) 2597{ 2598 struct ifnet *ifp; 2599 struct rx_rdesc *rrd; 2600 uint32_t nsegs, status; 2601 int rr_cons, prog; 2602 2603 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2604 sc->alc_cdata.alc_rr_ring_map, 2605 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2606 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2607 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2608 rr_cons = sc->alc_cdata.alc_rr_cons; 2609 ifp = sc->alc_ifp; 2610 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2611 if (count-- <= 0) 2612 break; 2613 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2614 status = le32toh(rrd->status); 2615 if ((status & RRD_VALID) == 0) 2616 break; 2617 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2618 if (nsegs == 0) { 2619 /* This should not happen! */ 2620 device_printf(sc->alc_dev, 2621 "unexpected segment count -- resetting\n"); 2622 return (EIO); 2623 } 2624 alc_rxeof(sc, rrd); 2625 /* Clear Rx return status. */ 2626 rrd->status = 0; 2627 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2628 sc->alc_cdata.alc_rx_cons += nsegs; 2629 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2630 prog += nsegs; 2631 } 2632 2633 if (prog > 0) { 2634 /* Update the consumer index. */ 2635 sc->alc_cdata.alc_rr_cons = rr_cons; 2636 /* Sync Rx return descriptors. */ 2637 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2638 sc->alc_cdata.alc_rr_ring_map, 2639 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2640 /* 2641 * Sync updated Rx descriptors such that controller see 2642 * modified buffer addresses. 2643 */ 2644 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2645 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2646 /* 2647 * Let controller know availability of new Rx buffers. 2648 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2649 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2650 * only when Rx buffer pre-fetching is required. In 2651 * addition we already set ALC_RX_RD_FREE_THRESH to 2652 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2653 * it still seems that pre-fetching needs more 2654 * experimentation. 2655 */ 2656 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2657 sc->alc_cdata.alc_rx_cons); 2658 } 2659 2660 return (count > 0 ? 0 : EAGAIN); 2661} 2662 2663#ifndef __NO_STRICT_ALIGNMENT 2664static struct mbuf * 2665alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2666{ 2667 struct mbuf *n; 2668 int i; 2669 uint16_t *src, *dst; 2670 2671 src = mtod(m, uint16_t *); 2672 dst = src - 3; 2673 2674 if (m->m_next == NULL) { 2675 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2676 *dst++ = *src++; 2677 m->m_data -= 6; 2678 return (m); 2679 } 2680 /* 2681 * Append a new mbuf to received mbuf chain and copy ethernet 2682 * header from the mbuf chain. This can save lots of CPU 2683 * cycles for jumbo frame. 2684 */ 2685 MGETHDR(n, M_DONTWAIT, MT_DATA); 2686 if (n == NULL) { 2687 ifp->if_iqdrops++; 2688 m_freem(m); 2689 return (NULL); 2690 } 2691 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2692 m->m_data += ETHER_HDR_LEN; 2693 m->m_len -= ETHER_HDR_LEN; 2694 n->m_len = ETHER_HDR_LEN; 2695 M_MOVE_PKTHDR(n, m); 2696 n->m_next = m; 2697 return (n); 2698} 2699#endif 2700 2701/* Receive a frame. */ 2702static void 2703alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2704{ 2705 struct alc_rxdesc *rxd; 2706 struct ifnet *ifp; 2707 struct mbuf *mp, *m; 2708 uint32_t rdinfo, status, vtag; 2709 int count, nsegs, rx_cons; 2710 2711 ifp = sc->alc_ifp; 2712 status = le32toh(rrd->status); 2713 rdinfo = le32toh(rrd->rdinfo); 2714 rx_cons = RRD_RD_IDX(rdinfo); 2715 nsegs = RRD_RD_CNT(rdinfo); 2716 2717 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2718 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2719 /* 2720 * We want to pass the following frames to upper 2721 * layer regardless of error status of Rx return 2722 * ring. 2723 * 2724 * o IP/TCP/UDP checksum is bad. 2725 * o frame length and protocol specific length 2726 * does not match. 2727 * 2728 * Force network stack compute checksum for 2729 * errored frames. 2730 */ 2731 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2732 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 2733 RRD_ERR_RUNT) != 0) 2734 return; 2735 } 2736 2737 for (count = 0; count < nsegs; count++, 2738 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2739 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2740 mp = rxd->rx_m; 2741 /* Add a new receive buffer to the ring. */ 2742 if (alc_newbuf(sc, rxd) != 0) { 2743 ifp->if_iqdrops++; 2744 /* Reuse Rx buffers. */ 2745 if (sc->alc_cdata.alc_rxhead != NULL) 2746 m_freem(sc->alc_cdata.alc_rxhead); 2747 break; 2748 } 2749 2750 /* 2751 * Assume we've received a full sized frame. 2752 * Actual size is fixed when we encounter the end of 2753 * multi-segmented frame. 2754 */ 2755 mp->m_len = sc->alc_buf_size; 2756 2757 /* Chain received mbufs. */ 2758 if (sc->alc_cdata.alc_rxhead == NULL) { 2759 sc->alc_cdata.alc_rxhead = mp; 2760 sc->alc_cdata.alc_rxtail = mp; 2761 } else { 2762 mp->m_flags &= ~M_PKTHDR; 2763 sc->alc_cdata.alc_rxprev_tail = 2764 sc->alc_cdata.alc_rxtail; 2765 sc->alc_cdata.alc_rxtail->m_next = mp; 2766 sc->alc_cdata.alc_rxtail = mp; 2767 } 2768 2769 if (count == nsegs - 1) { 2770 /* Last desc. for this frame. */ 2771 m = sc->alc_cdata.alc_rxhead; 2772 m->m_flags |= M_PKTHDR; 2773 /* 2774 * It seems that L1C/L2C controller has no way 2775 * to tell hardware to strip CRC bytes. 2776 */ 2777 m->m_pkthdr.len = 2778 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 2779 if (nsegs > 1) { 2780 /* Set last mbuf size. */ 2781 mp->m_len = sc->alc_cdata.alc_rxlen - 2782 (nsegs - 1) * sc->alc_buf_size; 2783 /* Remove the CRC bytes in chained mbufs. */ 2784 if (mp->m_len <= ETHER_CRC_LEN) { 2785 sc->alc_cdata.alc_rxtail = 2786 sc->alc_cdata.alc_rxprev_tail; 2787 sc->alc_cdata.alc_rxtail->m_len -= 2788 (ETHER_CRC_LEN - mp->m_len); 2789 sc->alc_cdata.alc_rxtail->m_next = NULL; 2790 m_freem(mp); 2791 } else { 2792 mp->m_len -= ETHER_CRC_LEN; 2793 } 2794 } else 2795 m->m_len = m->m_pkthdr.len; 2796 m->m_pkthdr.rcvif = ifp; 2797 /* 2798 * Due to hardware bugs, Rx checksum offloading 2799 * was intentionally disabled. 2800 */ 2801 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2802 (status & RRD_VLAN_TAG) != 0) { 2803 vtag = RRD_VLAN(le32toh(rrd->vtag)); 2804 m->m_pkthdr.ether_vtag = ntohs(vtag); 2805 m->m_flags |= M_VLANTAG; 2806 } 2807#ifndef __NO_STRICT_ALIGNMENT 2808 m = alc_fixup_rx(ifp, m); 2809 if (m != NULL) 2810#endif 2811 { 2812 /* Pass it on. */ 2813 (*ifp->if_input)(ifp, m); 2814 } 2815 } 2816 } 2817 /* Reset mbuf chains. */ 2818 ALC_RXCHAIN_RESET(sc); 2819} 2820 2821static void 2822alc_tick(void *arg) 2823{ 2824 struct alc_softc *sc; 2825 struct mii_data *mii; 2826 2827 sc = (struct alc_softc *)arg; 2828 2829 ALC_LOCK_ASSERT(sc); 2830 2831 mii = device_get_softc(sc->alc_miibus); 2832 mii_tick(mii); 2833 alc_stats_update(sc); 2834 /* 2835 * alc(4) does not rely on Tx completion interrupts to reclaim 2836 * transferred buffers. Instead Tx completion interrupts are 2837 * used to hint for scheduling Tx task. So it's necessary to 2838 * release transmitted buffers by kicking Tx completion 2839 * handler. This limits the maximum reclamation delay to a hz. 2840 */ 2841 alc_txeof(sc); 2842 alc_watchdog(sc); 2843 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 2844} 2845 2846static void 2847alc_reset(struct alc_softc *sc) 2848{ 2849 uint32_t reg; 2850 int i; 2851 2852 CSR_WRITE_4(sc, ALC_MASTER_CFG, MASTER_RESET); 2853 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2854 DELAY(10); 2855 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 2856 break; 2857 } 2858 if (i == 0) 2859 device_printf(sc->alc_dev, "master reset timeout!\n"); 2860 2861 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 2862 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 2863 break; 2864 DELAY(10); 2865 } 2866 2867 if (i == 0) 2868 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 2869} 2870 2871static void 2872alc_init(void *xsc) 2873{ 2874 struct alc_softc *sc; 2875 2876 sc = (struct alc_softc *)xsc; 2877 ALC_LOCK(sc); 2878 alc_init_locked(sc); 2879 ALC_UNLOCK(sc); 2880} 2881 2882static void 2883alc_init_locked(struct alc_softc *sc) 2884{ 2885 struct ifnet *ifp; 2886 struct mii_data *mii; 2887 uint8_t eaddr[ETHER_ADDR_LEN]; 2888 bus_addr_t paddr; 2889 uint32_t reg, rxf_hi, rxf_lo; 2890 2891 ALC_LOCK_ASSERT(sc); 2892 2893 ifp = sc->alc_ifp; 2894 mii = device_get_softc(sc->alc_miibus); 2895 2896 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2897 return; 2898 /* 2899 * Cancel any pending I/O. 2900 */ 2901 alc_stop(sc); 2902 /* 2903 * Reset the chip to a known state. 2904 */ 2905 alc_reset(sc); 2906 2907 /* Initialize Rx descriptors. */ 2908 if (alc_init_rx_ring(sc) != 0) { 2909 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 2910 alc_stop(sc); 2911 return; 2912 } 2913 alc_init_rr_ring(sc); 2914 alc_init_tx_ring(sc); 2915 alc_init_cmb(sc); 2916 alc_init_smb(sc); 2917 2918 /* Reprogram the station address. */ 2919 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2920 CSR_WRITE_4(sc, ALC_PAR0, 2921 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2922 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 2923 /* 2924 * Clear WOL status and disable all WOL feature as WOL 2925 * would interfere Rx operation under normal environments. 2926 */ 2927 CSR_READ_4(sc, ALC_WOL_CFG); 2928 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2929 /* Set Tx descriptor base addresses. */ 2930 paddr = sc->alc_rdata.alc_tx_ring_paddr; 2931 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2932 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2933 /* We don't use high priority ring. */ 2934 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 2935 /* Set Tx descriptor counter. */ 2936 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 2937 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 2938 /* Set Rx descriptor base addresses. */ 2939 paddr = sc->alc_rdata.alc_rx_ring_paddr; 2940 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2941 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2942 /* We use one Rx ring. */ 2943 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 2944 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 2945 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 2946 /* Set Rx descriptor counter. */ 2947 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 2948 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 2949 2950 /* 2951 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 2952 * if it do not fit the buffer size. Rx return descriptor holds 2953 * a counter that indicates how many fragments were made by the 2954 * hardware. The buffer size should be multiple of 8 bytes. 2955 * Since hardware has limit on the size of buffer size, always 2956 * use the maximum value. 2957 * For strict-alignment architectures make sure to reduce buffer 2958 * size by 8 bytes to make room for alignment fixup. 2959 */ 2960#ifndef __NO_STRICT_ALIGNMENT 2961 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 2962#else 2963 sc->alc_buf_size = RX_BUF_SIZE_MAX; 2964#endif 2965 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 2966 2967 paddr = sc->alc_rdata.alc_rr_ring_paddr; 2968 /* Set Rx return descriptor base addresses. */ 2969 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 2970 /* We use one Rx return ring. */ 2971 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 2972 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 2973 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 2974 /* Set Rx return descriptor counter. */ 2975 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 2976 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 2977 paddr = sc->alc_rdata.alc_cmb_paddr; 2978 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2979 paddr = sc->alc_rdata.alc_smb_paddr; 2980 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 2981 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 2982 2983 /* Tell hardware that we're ready to load DMA blocks. */ 2984 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 2985 2986 /* Configure interrupt moderation timer. */ 2987 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 2988 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 2989 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 2990 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 2991 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2992 /* 2993 * We don't want to automatic interrupt clear as task queue 2994 * for the interrupt should know interrupt status. 2995 */ 2996 reg &= ~MASTER_INTR_RD_CLR; 2997 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2998 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 2999 reg |= MASTER_IM_RX_TIMER_ENB; 3000 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3001 reg |= MASTER_IM_TX_TIMER_ENB; 3002 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3003 /* 3004 * Disable interrupt re-trigger timer. We don't want automatic 3005 * re-triggering of un-ACKed interrupts. 3006 */ 3007 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3008 /* Configure CMB. */ 3009 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3010 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3011 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3012 else 3013 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3014 /* 3015 * Hardware can be configured to issue SMB interrupt based 3016 * on programmed interval. Since there is a callout that is 3017 * invoked for every hz in driver we use that instead of 3018 * relying on periodic SMB interrupt. 3019 */ 3020 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3021 /* Clear MAC statistics. */ 3022 alc_stats_clear(sc); 3023 3024 /* 3025 * Always use maximum frame size that controller can support. 3026 * Otherwise received frames that has larger frame length 3027 * than alc(4) MTU would be silently dropped in hardware. This 3028 * would make path-MTU discovery hard as sender wouldn't get 3029 * any responses from receiver. alc(4) supports 3030 * multi-fragmented frames on Rx path so it has no issue on 3031 * assembling fragmented frames. Using maximum frame size also 3032 * removes the need to reinitialize hardware when interface 3033 * MTU configuration was changed. 3034 * 3035 * Be conservative in what you do, be liberal in what you 3036 * accept from others - RFC 793. 3037 */ 3038 CSR_WRITE_4(sc, ALC_FRAME_SIZE, ALC_JUMBO_FRAMELEN); 3039 3040 /* Disable header split(?) */ 3041 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3042 3043 /* Configure IPG/IFG parameters. */ 3044 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3045 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3046 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3047 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3048 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3049 /* Set parameters for half-duplex media. */ 3050 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3051 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3052 HDPX_CFG_LCOL_MASK) | 3053 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3054 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3055 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3056 HDPX_CFG_ABEBT_MASK) | 3057 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3058 HDPX_CFG_JAMIPG_MASK)); 3059 /* 3060 * Set TSO/checksum offload threshold. For frames that is 3061 * larger than this threshold, hardware wouldn't do 3062 * TSO/checksum offloading. 3063 */ 3064 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3065 (ALC_JUMBO_FRAMELEN >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3066 TSO_OFFLOAD_THRESH_MASK); 3067 /* Configure TxQ. */ 3068 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3069 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3070 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3071 TXQ_CFG_TD_BURST_MASK; 3072 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3073 3074 /* Configure Rx free descriptor pre-fetching. */ 3075 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3076 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3077 RX_RD_FREE_THRESH_HI_MASK) | 3078 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3079 RX_RD_FREE_THRESH_LO_MASK)); 3080 3081 /* 3082 * Configure flow control parameters. 3083 * XON : 80% of Rx FIFO 3084 * XOFF : 30% of Rx FIFO 3085 */ 3086 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3087 rxf_hi = (reg * 8) / 10; 3088 rxf_lo = (reg * 3)/ 10; 3089 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3090 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3091 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3092 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3093 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3094 3095 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3096 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3097 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3098 3099 /* Configure RxQ. */ 3100 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3101 RXQ_CFG_RD_BURST_MASK; 3102 reg |= RXQ_CFG_RSS_MODE_DIS; 3103 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3104 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 3105 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3106 3107 /* Configure Rx DMAW request thresold. */ 3108 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 3109 ((RD_DMA_CFG_THRESH_DEFAULT << RD_DMA_CFG_THRESH_SHIFT) & 3110 RD_DMA_CFG_THRESH_MASK) | 3111 ((ALC_RD_DMA_CFG_USECS(0) << RD_DMA_CFG_TIMER_SHIFT) & 3112 RD_DMA_CFG_TIMER_MASK)); 3113 /* Configure DMA parameters. */ 3114 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3115 reg |= sc->alc_rcb; 3116 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3117 reg |= DMA_CFG_CMB_ENB; 3118 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3119 reg |= DMA_CFG_SMB_ENB; 3120 else 3121 reg |= DMA_CFG_SMB_DIS; 3122 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3123 DMA_CFG_RD_BURST_SHIFT; 3124 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3125 DMA_CFG_WR_BURST_SHIFT; 3126 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3127 DMA_CFG_RD_DELAY_CNT_MASK; 3128 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3129 DMA_CFG_WR_DELAY_CNT_MASK; 3130 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3131 3132 /* 3133 * Configure Tx/Rx MACs. 3134 * - Auto-padding for short frames. 3135 * - Enable CRC generation. 3136 * Actual reconfiguration of MAC for resolved speed/duplex 3137 * is followed after detection of link establishment. 3138 * AR8131/AR8132 always does checksum computation regardless 3139 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3140 * have bug in protocol field in Rx return structure so 3141 * these controllers can't handle fragmented frames. Disable 3142 * Rx checksum offloading until there is a newer controller 3143 * that has sane implementation. 3144 */ 3145 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3146 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3147 MAC_CFG_PREAMBLE_MASK); 3148 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3149 reg |= MAC_CFG_SPEED_10_100; 3150 else 3151 reg |= MAC_CFG_SPEED_1000; 3152 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3153 3154 /* Set up the receive filter. */ 3155 alc_rxfilter(sc); 3156 alc_rxvlan(sc); 3157 3158 /* Acknowledge all pending interrupts and clear it. */ 3159 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3160 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3161 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3162 3163 sc->alc_flags &= ~ALC_FLAG_LINK; 3164 /* Switch to the current media. */ 3165 mii_mediachg(mii); 3166 3167 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3168 3169 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3170 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3171} 3172 3173static void 3174alc_stop(struct alc_softc *sc) 3175{ 3176 struct ifnet *ifp; 3177 struct alc_txdesc *txd; 3178 struct alc_rxdesc *rxd; 3179 uint32_t reg; 3180 int i; 3181 3182 ALC_LOCK_ASSERT(sc); 3183 /* 3184 * Mark the interface down and cancel the watchdog timer. 3185 */ 3186 ifp = sc->alc_ifp; 3187 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3188 sc->alc_flags &= ~ALC_FLAG_LINK; 3189 callout_stop(&sc->alc_tick_ch); 3190 sc->alc_watchdog_timer = 0; 3191 alc_stats_update(sc); 3192 /* Disable interrupts. */ 3193 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3194 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3195 alc_stop_queue(sc); 3196 /* Disable DMA. */ 3197 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3198 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3199 reg |= DMA_CFG_SMB_DIS; 3200 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3201 DELAY(1000); 3202 /* Stop Rx/Tx MACs. */ 3203 alc_stop_mac(sc); 3204 /* Disable interrupts which might be touched in taskq handler. */ 3205 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3206 3207 /* Reclaim Rx buffers that have been processed. */ 3208 if (sc->alc_cdata.alc_rxhead != NULL) 3209 m_freem(sc->alc_cdata.alc_rxhead); 3210 ALC_RXCHAIN_RESET(sc); 3211 /* 3212 * Free Tx/Rx mbufs still in the queues. 3213 */ 3214 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3215 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3216 if (rxd->rx_m != NULL) { 3217 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3218 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3219 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3220 rxd->rx_dmamap); 3221 m_freem(rxd->rx_m); 3222 rxd->rx_m = NULL; 3223 } 3224 } 3225 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3226 txd = &sc->alc_cdata.alc_txdesc[i]; 3227 if (txd->tx_m != NULL) { 3228 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3229 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3230 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3231 txd->tx_dmamap); 3232 m_freem(txd->tx_m); 3233 txd->tx_m = NULL; 3234 } 3235 } 3236} 3237 3238static void 3239alc_stop_mac(struct alc_softc *sc) 3240{ 3241 uint32_t reg; 3242 int i; 3243 3244 ALC_LOCK_ASSERT(sc); 3245 3246 /* Disable Rx/Tx MAC. */ 3247 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3248 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3249 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 3250 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3251 } 3252 for (i = ALC_TIMEOUT; i > 0; i--) { 3253 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3254 if (reg == 0) 3255 break; 3256 DELAY(10); 3257 } 3258 if (i == 0) 3259 device_printf(sc->alc_dev, 3260 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3261} 3262 3263static void 3264alc_start_queue(struct alc_softc *sc) 3265{ 3266 uint32_t qcfg[] = { 3267 0, 3268 RXQ_CFG_QUEUE0_ENB, 3269 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3270 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3271 RXQ_CFG_ENB 3272 }; 3273 uint32_t cfg; 3274 3275 ALC_LOCK_ASSERT(sc); 3276 3277 /* Enable RxQ. */ 3278 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3279 cfg &= ~RXQ_CFG_ENB; 3280 cfg |= qcfg[1]; 3281 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3282 /* Enable TxQ. */ 3283 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3284 cfg |= TXQ_CFG_ENB; 3285 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3286} 3287 3288static void 3289alc_stop_queue(struct alc_softc *sc) 3290{ 3291 uint32_t reg; 3292 int i; 3293 3294 ALC_LOCK_ASSERT(sc); 3295 3296 /* Disable RxQ. */ 3297 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3298 if ((reg & RXQ_CFG_ENB) != 0) { 3299 reg &= ~RXQ_CFG_ENB; 3300 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3301 } 3302 /* Disable TxQ. */ 3303 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3304 if ((reg & TXQ_CFG_ENB) == 0) { 3305 reg &= ~TXQ_CFG_ENB; 3306 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3307 } 3308 for (i = ALC_TIMEOUT; i > 0; i--) { 3309 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3310 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3311 break; 3312 DELAY(10); 3313 } 3314 if (i == 0) 3315 device_printf(sc->alc_dev, 3316 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3317} 3318 3319static void 3320alc_init_tx_ring(struct alc_softc *sc) 3321{ 3322 struct alc_ring_data *rd; 3323 struct alc_txdesc *txd; 3324 int i; 3325 3326 ALC_LOCK_ASSERT(sc); 3327 3328 sc->alc_cdata.alc_tx_prod = 0; 3329 sc->alc_cdata.alc_tx_cons = 0; 3330 sc->alc_cdata.alc_tx_cnt = 0; 3331 3332 rd = &sc->alc_rdata; 3333 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3334 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3335 txd = &sc->alc_cdata.alc_txdesc[i]; 3336 txd->tx_m = NULL; 3337 } 3338 3339 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3340 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3341} 3342 3343static int 3344alc_init_rx_ring(struct alc_softc *sc) 3345{ 3346 struct alc_ring_data *rd; 3347 struct alc_rxdesc *rxd; 3348 int i; 3349 3350 ALC_LOCK_ASSERT(sc); 3351 3352 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3353 sc->alc_morework = 0; 3354 rd = &sc->alc_rdata; 3355 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3356 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3357 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3358 rxd->rx_m = NULL; 3359 rxd->rx_desc = &rd->alc_rx_ring[i]; 3360 if (alc_newbuf(sc, rxd) != 0) 3361 return (ENOBUFS); 3362 } 3363 3364 /* 3365 * Since controller does not update Rx descriptors, driver 3366 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3367 * is enough to ensure coherence. 3368 */ 3369 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3370 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3371 /* Let controller know availability of new Rx buffers. */ 3372 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3373 3374 return (0); 3375} 3376 3377static void 3378alc_init_rr_ring(struct alc_softc *sc) 3379{ 3380 struct alc_ring_data *rd; 3381 3382 ALC_LOCK_ASSERT(sc); 3383 3384 sc->alc_cdata.alc_rr_cons = 0; 3385 ALC_RXCHAIN_RESET(sc); 3386 3387 rd = &sc->alc_rdata; 3388 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3389 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3390 sc->alc_cdata.alc_rr_ring_map, 3391 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3392} 3393 3394static void 3395alc_init_cmb(struct alc_softc *sc) 3396{ 3397 struct alc_ring_data *rd; 3398 3399 ALC_LOCK_ASSERT(sc); 3400 3401 rd = &sc->alc_rdata; 3402 bzero(rd->alc_cmb, ALC_CMB_SZ); 3403 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3404 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3405} 3406 3407static void 3408alc_init_smb(struct alc_softc *sc) 3409{ 3410 struct alc_ring_data *rd; 3411 3412 ALC_LOCK_ASSERT(sc); 3413 3414 rd = &sc->alc_rdata; 3415 bzero(rd->alc_smb, ALC_SMB_SZ); 3416 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3417 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3418} 3419 3420static void 3421alc_rxvlan(struct alc_softc *sc) 3422{ 3423 struct ifnet *ifp; 3424 uint32_t reg; 3425 3426 ALC_LOCK_ASSERT(sc); 3427 3428 ifp = sc->alc_ifp; 3429 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3430 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3431 reg |= MAC_CFG_VLAN_TAG_STRIP; 3432 else 3433 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3434 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3435} 3436 3437static void 3438alc_rxfilter(struct alc_softc *sc) 3439{ 3440 struct ifnet *ifp; 3441 struct ifmultiaddr *ifma; 3442 uint32_t crc; 3443 uint32_t mchash[2]; 3444 uint32_t rxcfg; 3445 3446 ALC_LOCK_ASSERT(sc); 3447 3448 ifp = sc->alc_ifp; 3449 3450 bzero(mchash, sizeof(mchash)); 3451 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3452 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3453 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3454 rxcfg |= MAC_CFG_BCAST; 3455 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3456 if ((ifp->if_flags & IFF_PROMISC) != 0) 3457 rxcfg |= MAC_CFG_PROMISC; 3458 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3459 rxcfg |= MAC_CFG_ALLMULTI; 3460 mchash[0] = 0xFFFFFFFF; 3461 mchash[1] = 0xFFFFFFFF; 3462 goto chipit; 3463 } 3464 3465 if_maddr_rlock(ifp); 3466 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3467 if (ifma->ifma_addr->sa_family != AF_LINK) 3468 continue; 3469 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3470 ifma->ifma_addr), ETHER_ADDR_LEN); 3471 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3472 } 3473 if_maddr_runlock(ifp); 3474 3475chipit: 3476 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3477 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3478 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3479} 3480 3481static int 3482sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3483{ 3484 int error, value; 3485 3486 if (arg1 == NULL) 3487 return (EINVAL); 3488 value = *(int *)arg1; 3489 error = sysctl_handle_int(oidp, &value, 0, req); 3490 if (error || req->newptr == NULL) 3491 return (error); 3492 if (value < low || value > high) 3493 return (EINVAL); 3494 *(int *)arg1 = value; 3495 3496 return (0); 3497} 3498 3499static int 3500sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3501{ 3502 return (sysctl_int_range(oidp, arg1, arg2, req, 3503 ALC_PROC_MIN, ALC_PROC_MAX)); 3504} 3505 3506static int 3507sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3508{ 3509 3510 return (sysctl_int_range(oidp, arg1, arg2, req, 3511 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3512} 3513