aic7xxx_pci.c revision 72325
1238104Sdes/* 2238104Sdes * Product specific probe and attach routines for: 3238104Sdes * 3940, 2940, aic7895, aic7890, aic7880, 4238104Sdes * aic7870, aic7860 and aic7850 SCSI controllers 5238104Sdes * 6238104Sdes * Copyright (c) 1995-2000 Justin T. Gibbs 7238104Sdes * All rights reserved. 8238104Sdes * 9238104Sdes * Redistribution and use in source and binary forms, with or without 10238104Sdes * modification, are permitted provided that the following conditions 11238104Sdes * are met: 12238104Sdes * 1. Redistributions of source code must retain the above copyright 13238104Sdes * notice, this list of conditions, and the following disclaimer, 14238104Sdes * without modification, immediately at the beginning of the file. 15238104Sdes * 2. The name of the author may not be used to endorse or promote products 16238104Sdes * derived from this software without specific prior written permission. 17238104Sdes * 18238104Sdes * Alternatively, this software may be distributed under the terms of the 19238104Sdes * GNU Public License ("GPL"). 20238104Sdes * 21238104Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22238104Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23238104Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24238104Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25238104Sdes * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26238104Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27238104Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28238104Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29238104Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30238104Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31238104Sdes * SUCH DAMAGE. 32238104Sdes * 33238104Sdes * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#12 $ 34238104Sdes * 35238104Sdes * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_pci.c 72325 2001-02-10 18:04:27Z gibbs $ 36238104Sdes */ 37238104Sdes 38238104Sdes#ifdef __linux__ 39238104Sdes#include "aic7xxx_linux.h" 40238104Sdes#include "aic7xxx_inline.h" 41238104Sdes#include "aic7xxx_93cx6.h" 42238104Sdes#endif 43238104Sdes 44238104Sdes#ifdef __FreeBSD__ 45238104Sdes#include <dev/aic7xxx/aic7xxx_freebsd.h> 46238104Sdes#include <dev/aic7xxx/aic7xxx_inline.h> 47238104Sdes#include <dev/aic7xxx/aic7xxx_93cx6.h> 48238104Sdes#endif 49238104Sdes 50238104Sdes#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 51238104Sdes#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 52238104Sdes 53238104Sdesstatic __inline uint64_t 54238104Sdesahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 55238104Sdes{ 56238104Sdes uint64_t id; 57238104Sdes 58238104Sdes id = subvendor 59238104Sdes | (subdevice << 16) 60238104Sdes | ((uint64_t)vendor << 32) 61238104Sdes | ((uint64_t)device << 48); 62238104Sdes 63238104Sdes return (id); 64238104Sdes} 65238104Sdes 66238104Sdes#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 67238104Sdes#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 68238104Sdes#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 69238104Sdes#define ID_AIC7850 0x5078900400000000ull 70238104Sdes#define ID_AHA_2910_15_20_30C 0x5078900478509004ull 71238104Sdes#define ID_AIC7855 0x5578900400000000ull 72238104Sdes#define ID_AIC7859 0x3860900400000000ull 73238104Sdes#define ID_AHA_2930CU 0x3860900438699004ull 74238104Sdes#define ID_AIC7860 0x6078900400000000ull 75238104Sdes#define ID_AIC7860C 0x6078900478609004ull 76238104Sdes#define ID_AHA_1480A 0x6075900400000000ull 77238104Sdes#define ID_AHA_2940AU_0 0x6178900400000000ull 78238104Sdes#define ID_AHA_2940AU_1 0x6178900478619004ull 79238104Sdes#define ID_AHA_2940AU_CN 0x2178900478219004ull 80238104Sdes#define ID_AHA_2930C_VAR 0x6038900438689004ull 81238104Sdes 82238104Sdes#define ID_AIC7870 0x7078900400000000ull 83238104Sdes#define ID_AHA_2940 0x7178900400000000ull 84238104Sdes#define ID_AHA_3940 0x7278900400000000ull 85238104Sdes#define ID_AHA_398X 0x7378900400000000ull 86238104Sdes#define ID_AHA_2944 0x7478900400000000ull 87238104Sdes#define ID_AHA_3944 0x7578900400000000ull 88238104Sdes#define ID_AHA_4944 0x7678900400000000ull 89238104Sdes 90238104Sdes#define ID_AIC7880 0x8078900400000000ull 91238104Sdes#define ID_AIC7880_B 0x8078900478809004ull 92238104Sdes#define ID_AHA_2940U 0x8178900400000000ull 93238104Sdes#define ID_AHA_3940U 0x8278900400000000ull 94238104Sdes#define ID_AHA_2944U 0x8478900400000000ull 95238104Sdes#define ID_AHA_3944U 0x8578900400000000ull 96238104Sdes#define ID_AHA_398XU 0x8378900400000000ull 97238104Sdes#define ID_AHA_4944U 0x8678900400000000ull 98238104Sdes#define ID_AHA_2940UB 0x8178900478819004ull 99238104Sdes#define ID_AHA_2930U 0x8878900478889004ull 100238104Sdes#define ID_AHA_2940U_PRO 0x8778900478879004ull 101238104Sdes#define ID_AHA_2940U_CN 0x0078900478009004ull 102238104Sdes 103238104Sdes#define ID_AIC7895 0x7895900478959004ull 104238104Sdes#define ID_AIC7895_RAID_PORT 0x7893900478939004ull 105238104Sdes#define ID_AHA_2940U_DUAL 0x7895900478919004ull 106238104Sdes#define ID_AHA_3940AU 0x7895900478929004ull 107238104Sdes#define ID_AHA_3944AU 0x7895900478949004ull 108238104Sdes 109238104Sdes#define ID_AIC7890 0x001F9005000F9005ull 110238104Sdes#define ID_AAA_131U2 0x0013900500039005ull 111238104Sdes#define ID_AHA_2930U2 0x0011900501819005ull 112238104Sdes#define ID_AHA_2940U2B 0x00109005A1009005ull 113238104Sdes#define ID_AHA_2940U2_OEM 0x0010900521809005ull 114238104Sdes#define ID_AHA_2940U2 0x00109005A1809005ull 115238104Sdes#define ID_AHA_2950U2B 0x00109005E1009005ull 116238104Sdes 117238104Sdes#define ID_AIC7892 0x008F9005FFFF9005ull 118238104Sdes#define ID_AHA_29160 0x00809005E2A09005ull 119238104Sdes#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 120238104Sdes#define ID_AHA_29160N 0x0080900562A09005ull 121238104Sdes#define ID_AHA_29160C 0x0080900562209005ull 122238104Sdes#define ID_AHA_29160B 0x00809005E2209005ull 123238104Sdes#define ID_AHA_19160B 0x0081900562A19005ull 124238104Sdes 125238104Sdes#define ID_AIC7896 0x005F9005FFFF9005ull 126238104Sdes#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 127238104Sdes#define ID_AHA_3950U2B_1 0x00509005F5009005ull 128238104Sdes#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 129238104Sdes#define ID_AHA_3950U2D_1 0x00519005B5009005ull 130238104Sdes 131238104Sdes#define ID_AIC7899 0x00CF9005FFFF9005ull 132238104Sdes#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 133238104Sdes#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 134238104Sdes 135238104Sdes#define ID_AIC7810 0x1078900400000000ull 136238104Sdes#define ID_AIC7815 0x7815900400000000ull 137238104Sdes 138238104Sdes#define DEVID_9005_TYPE(id) ((id) & 0xF) 139238104Sdes#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 140238104Sdes#define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 141238104Sdes#define DEVID_9005_TYPE_SISL 0x5 /* Low Cost Card */ 142238104Sdes#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 143238104Sdes 144238104Sdes#define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 145238104Sdes#define DEVID_9005_MAXRATE_U160 0x0 146238104Sdes#define DEVID_9005_MAXRATE_ULTRA2 0x1 147238104Sdes#define DEVID_9005_MAXRATE_ULTRA 0x2 148238104Sdes#define DEVID_9005_MAXRATE_FAST 0x3 149238104Sdes 150238104Sdes#define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 151238104Sdes 152238104Sdes#define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 153238104Sdes#define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 154238104Sdes 155238104Sdes#define SUBID_9005_TYPE(id) ((id) & 0xF) 156238104Sdes#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 157238104Sdes#define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 158238104Sdes#define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 159238104Sdes#define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 160238104Sdes 161238104Sdes#define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 162238104Sdes#define SUBID_9005_MAXRATE_ULTRA2 0x0 163238104Sdes#define SUBID_9005_MAXRATE_ULTRA 0x1 164238104Sdes#define SUBID_9005_MAXRATE_U160 0x2 165238104Sdes#define SUBID_9005_MAXRATE_RESERVED 0x3 166238104Sdes 167238104Sdes#define SUBID_9005_SEEPTYPE(id) \ 168238104Sdes ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 169238104Sdes ? ((id) & 0xC0) >> 6 \ 170238104Sdes : ((id) & 0x300) >> 8) 171238104Sdes#define SUBID_9005_SEEPTYPE_NONE 0x0 172238104Sdes#define SUBID_9005_SEEPTYPE_1K 0x1 173238104Sdes#define SUBID_9005_SEEPTYPE_2K_4K 0x2 174238104Sdes#define SUBID_9005_SEEPTYPE_RESERVED 0x3 175238104Sdes#define SUBID_9005_AUTOTERM(id) \ 176238104Sdes ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 177 ? (((id) & 0x400) >> 10) == 0 \ 178 : (((id) & 0x40) >> 6) == 0) 179 180#define SUBID_9005_NUMCHAN(id) \ 181 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 182 ? ((id) & 0x300) >> 8 \ 183 : ((id) & 0xC00) >> 10) 184 185#define SUBID_9005_LEGACYCONN(id) \ 186 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 187 ? 0 \ 188 : ((id) & 0x80) >> 7) 189 190#define SUBID_9005_MFUNCENB(id) \ 191 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 192 ? ((id) & 0x800) >> 11 \ 193 : ((id) & 0x1000) >> 12) 194/* 195 * Informational only. Should use chip register to be 196 * ceratian, but may be use in identification strings. 197 */ 198#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 199#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 200#define SUBID_9005_CARD_SEDIFF_MASK 0x8000 201 202static ahc_device_setup_t ahc_aic7850_setup; 203static ahc_device_setup_t ahc_aic7855_setup; 204static ahc_device_setup_t ahc_aic7860_setup; 205static ahc_device_setup_t ahc_apa1480_setup; 206static ahc_device_setup_t ahc_aic7870_setup; 207static ahc_device_setup_t ahc_aha394X_setup; 208static ahc_device_setup_t ahc_aha494X_setup; 209static ahc_device_setup_t ahc_aha398X_setup; 210static ahc_device_setup_t ahc_aic7880_setup; 211static ahc_device_setup_t ahc_aha2940Pro_setup; 212static ahc_device_setup_t ahc_aha394XU_setup; 213static ahc_device_setup_t ahc_aha398XU_setup; 214static ahc_device_setup_t ahc_aic7890_setup; 215static ahc_device_setup_t ahc_aic7892_setup; 216static ahc_device_setup_t ahc_aic7895_setup; 217static ahc_device_setup_t ahc_aic7896_setup; 218static ahc_device_setup_t ahc_aic7899_setup; 219static ahc_device_setup_t ahc_aha29160C_setup; 220static ahc_device_setup_t ahc_raid_setup; 221static ahc_device_setup_t ahc_aha394XX_setup; 222static ahc_device_setup_t ahc_aha494XX_setup; 223static ahc_device_setup_t ahc_aha398XX_setup; 224 225struct ahc_pci_identity ahc_pci_ident_table [] = 226{ 227 /* aic7850 based controllers */ 228 { 229 ID_AHA_2910_15_20_30C, 230 ID_ALL_MASK, 231 "Adaptec 2910/15/20/30C SCSI adapter", 232 ahc_aic7850_setup 233 }, 234 /* aic7860 based controllers */ 235 { 236 ID_AHA_2930CU, 237 ID_ALL_MASK, 238 "Adaptec 2930CU SCSI adapter", 239 ahc_aic7860_setup 240 }, 241 { 242 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 243 ID_DEV_VENDOR_MASK, 244 "Adaptec 1480A Ultra SCSI adapter", 245 ahc_apa1480_setup 246 }, 247 { 248 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 249 ID_DEV_VENDOR_MASK, 250 "Adaptec 2940A Ultra SCSI adapter", 251 ahc_aic7860_setup 252 }, 253 { 254 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 255 ID_DEV_VENDOR_MASK, 256 "Adaptec 2940A/CN Ultra SCSI adapter", 257 ahc_aic7860_setup 258 }, 259 { 260 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 261 ID_DEV_VENDOR_MASK, 262 "Adaptec 2930C SCSI adapter (VAR)", 263 ahc_aic7860_setup 264 }, 265 /* aic7870 based controllers */ 266 { 267 ID_AHA_2940, 268 ID_ALL_MASK, 269 "Adaptec 2940 SCSI adapter", 270 ahc_aic7870_setup 271 }, 272 { 273 ID_AHA_3940, 274 ID_ALL_MASK, 275 "Adaptec 3940 SCSI adapter", 276 ahc_aha394X_setup 277 }, 278 { 279 ID_AHA_398X, 280 ID_ALL_MASK, 281 "Adaptec 398X SCSI RAID adapter", 282 ahc_aha398X_setup 283 }, 284 { 285 ID_AHA_2944, 286 ID_ALL_MASK, 287 "Adaptec 2944 SCSI adapter", 288 ahc_aic7870_setup 289 }, 290 { 291 ID_AHA_3944, 292 ID_ALL_MASK, 293 "Adaptec 3944 SCSI adapter", 294 ahc_aha394X_setup 295 }, 296 { 297 ID_AHA_4944, 298 ID_ALL_MASK, 299 "Adaptec 4944 SCSI adapter", 300 ahc_aha494X_setup 301 }, 302 /* aic7880 based controllers */ 303 { 304 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 305 ID_DEV_VENDOR_MASK, 306 "Adaptec 2940 Ultra SCSI adapter", 307 ahc_aic7880_setup 308 }, 309 { 310 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 311 ID_DEV_VENDOR_MASK, 312 "Adaptec 3940 Ultra SCSI adapter", 313 ahc_aha394XU_setup 314 }, 315 { 316 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 317 ID_DEV_VENDOR_MASK, 318 "Adaptec 2944 Ultra SCSI adapter", 319 ahc_aic7880_setup 320 }, 321 { 322 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 323 ID_DEV_VENDOR_MASK, 324 "Adaptec 3944 Ultra SCSI adapter", 325 ahc_aha394XU_setup 326 }, 327 { 328 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 329 ID_DEV_VENDOR_MASK, 330 "Adaptec 398X Ultra SCSI RAID adapter", 331 ahc_aha398XU_setup 332 }, 333 { 334 /* 335 * XXX Don't know the slot numbers 336 * so we can't identify channels 337 */ 338 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 339 ID_DEV_VENDOR_MASK, 340 "Adaptec 4944 Ultra SCSI adapter", 341 ahc_aic7880_setup 342 }, 343 { 344 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 345 ID_DEV_VENDOR_MASK, 346 "Adaptec 2930 Ultra SCSI adapter", 347 ahc_aic7880_setup 348 }, 349 { 350 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 351 ID_DEV_VENDOR_MASK, 352 "Adaptec 2940 Pro Ultra SCSI adapter", 353 ahc_aha2940Pro_setup 354 }, 355 { 356 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 357 ID_DEV_VENDOR_MASK, 358 "Adaptec 2940/CN Ultra SCSI adapter", 359 ahc_aic7880_setup 360 }, 361 /* aic7890 based controllers */ 362 { 363 ID_AHA_2930U2, 364 ID_ALL_MASK, 365 "Adaptec 2930 Ultra2 SCSI adapter", 366 ahc_aic7890_setup 367 }, 368 { 369 ID_AHA_2940U2B, 370 ID_ALL_MASK, 371 "Adaptec 2940B Ultra2 SCSI adapter", 372 ahc_aic7890_setup 373 }, 374 { 375 ID_AHA_2940U2_OEM, 376 ID_ALL_MASK, 377 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 378 ahc_aic7890_setup 379 }, 380 { 381 ID_AHA_2940U2, 382 ID_ALL_MASK, 383 "Adaptec 2940 Ultra2 SCSI adapter", 384 ahc_aic7890_setup 385 }, 386 { 387 ID_AHA_2950U2B, 388 ID_ALL_MASK, 389 "Adaptec 2950 Ultra2 SCSI adapter", 390 ahc_aic7890_setup 391 }, 392 { 393 ID_AAA_131U2, 394 ID_ALL_MASK, 395 "Adaptec AAA-131 Ultra2 RAID adapter", 396 ahc_aic7890_setup 397 }, 398 /* aic7892 based controllers */ 399 { 400 ID_AHA_29160, 401 ID_ALL_MASK, 402 "Adaptec 29160 Ultra160 SCSI adapter", 403 ahc_aic7892_setup 404 }, 405 { 406 ID_AHA_29160_CPQ, 407 ID_ALL_MASK, 408 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 409 ahc_aic7892_setup 410 }, 411 { 412 ID_AHA_29160N, 413 ID_ALL_MASK, 414 "Adaptec 29160N Ultra160 SCSI adapter", 415 ahc_aic7892_setup 416 }, 417 { 418 ID_AHA_29160C, 419 ID_ALL_MASK, 420 "Adaptec 29160C Ultra160 SCSI adapter", 421 ahc_aha29160C_setup 422 }, 423 { 424 ID_AHA_29160B, 425 ID_ALL_MASK, 426 "Adaptec 29160B Ultra160 SCSI adapter", 427 ahc_aic7892_setup 428 }, 429 { 430 ID_AHA_19160B, 431 ID_ALL_MASK, 432 "Adaptec 19160B Ultra160 SCSI adapter", 433 ahc_aic7892_setup 434 }, 435 /* aic7895 based controllers */ 436 { 437 ID_AHA_2940U_DUAL, 438 ID_ALL_MASK, 439 "Adaptec 2940/DUAL Ultra SCSI adapter", 440 ahc_aic7895_setup 441 }, 442 { 443 ID_AHA_3940AU, 444 ID_ALL_MASK, 445 "Adaptec 3940A Ultra SCSI adapter", 446 ahc_aic7895_setup 447 }, 448 { 449 ID_AHA_3944AU, 450 ID_ALL_MASK, 451 "Adaptec 3944A Ultra SCSI adapter", 452 ahc_aic7895_setup 453 }, 454 /* aic7896/97 based controllers */ 455 { 456 ID_AHA_3950U2B_0, 457 ID_ALL_MASK, 458 "Adaptec 3950B Ultra2 SCSI adapter", 459 ahc_aic7896_setup 460 }, 461 { 462 ID_AHA_3950U2B_1, 463 ID_ALL_MASK, 464 "Adaptec 3950B Ultra2 SCSI adapter", 465 ahc_aic7896_setup 466 }, 467 { 468 ID_AHA_3950U2D_0, 469 ID_ALL_MASK, 470 "Adaptec 3950D Ultra2 SCSI adapter", 471 ahc_aic7896_setup 472 }, 473 { 474 ID_AHA_3950U2D_1, 475 ID_ALL_MASK, 476 "Adaptec 3950D Ultra2 SCSI adapter", 477 ahc_aic7896_setup 478 }, 479 /* aic7899 based controllers */ 480 { 481 ID_AHA_3960D, 482 ID_ALL_MASK, 483 "Adaptec 3960D Ultra160 SCSI adapter", 484 ahc_aic7899_setup 485 }, 486 { 487 ID_AHA_3960D_CPQ, 488 ID_ALL_MASK, 489 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 490 ahc_aic7899_setup 491 }, 492 /* Generic chip probes for devices we don't know 'exactly' */ 493 { 494 ID_AIC7850 & ID_DEV_VENDOR_MASK, 495 ID_DEV_VENDOR_MASK, 496 "Adaptec aic7850 SCSI adapter", 497 ahc_aic7850_setup 498 }, 499 { 500 ID_AIC7855 & ID_DEV_VENDOR_MASK, 501 ID_DEV_VENDOR_MASK, 502 "Adaptec aic7855 SCSI adapter", 503 ahc_aic7855_setup 504 }, 505 { 506 ID_AIC7859 & ID_DEV_VENDOR_MASK, 507 ID_DEV_VENDOR_MASK, 508 "Adaptec aic7859 Ultra SCSI adapter", 509 ahc_aic7860_setup 510 }, 511 { 512 ID_AIC7860 & ID_DEV_VENDOR_MASK, 513 ID_DEV_VENDOR_MASK, 514 "Adaptec aic7860 SCSI adapter", 515 ahc_aic7860_setup 516 }, 517 { 518 ID_AIC7870 & ID_DEV_VENDOR_MASK, 519 ID_DEV_VENDOR_MASK, 520 "Adaptec aic7870 SCSI adapter", 521 ahc_aic7870_setup 522 }, 523 { 524 ID_AIC7880 & ID_DEV_VENDOR_MASK, 525 ID_DEV_VENDOR_MASK, 526 "Adaptec aic7880 Ultra SCSI adapter", 527 ahc_aic7880_setup 528 }, 529 { 530 ID_AIC7890 & ID_9005_GENERIC_MASK, 531 ID_9005_GENERIC_MASK, 532 "Adaptec aic7890/91 Ultra2 SCSI adapter", 533 ahc_aic7890_setup 534 }, 535 { 536 ID_AIC7892 & ID_9005_GENERIC_MASK, 537 ID_9005_GENERIC_MASK, 538 "Adaptec aic7892 Ultra160 SCSI adapter", 539 ahc_aic7892_setup 540 }, 541 { 542 ID_AIC7895 & ID_DEV_VENDOR_MASK, 543 ID_DEV_VENDOR_MASK, 544 "Adaptec aic7895 Ultra SCSI adapter", 545 ahc_aic7895_setup 546 }, 547 { 548 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 549 ID_DEV_VENDOR_MASK, 550 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 551 ahc_aic7895_setup 552 }, 553 { 554 ID_AIC7896 & ID_9005_GENERIC_MASK, 555 ID_9005_GENERIC_MASK, 556 "Adaptec aic7896/97 Ultra2 SCSI adapter", 557 ahc_aic7896_setup 558 }, 559 { 560 ID_AIC7899 & ID_9005_GENERIC_MASK, 561 ID_9005_GENERIC_MASK, 562 "Adaptec aic7899 Ultra160 SCSI adapter", 563 ahc_aic7899_setup 564 }, 565 { 566 ID_AIC7810 & ID_DEV_VENDOR_MASK, 567 ID_DEV_VENDOR_MASK, 568 "Adaptec aic7810 RAID memory controller", 569 ahc_raid_setup 570 }, 571 { 572 ID_AIC7815 & ID_DEV_VENDOR_MASK, 573 ID_DEV_VENDOR_MASK, 574 "Adaptec aic7815 RAID memory controller", 575 ahc_raid_setup 576 } 577}; 578 579const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 580 581#define AHC_394X_SLOT_CHANNEL_A 4 582#define AHC_394X_SLOT_CHANNEL_B 5 583 584#define AHC_398X_SLOT_CHANNEL_A 4 585#define AHC_398X_SLOT_CHANNEL_B 8 586#define AHC_398X_SLOT_CHANNEL_C 12 587 588#define AHC_494X_SLOT_CHANNEL_A 4 589#define AHC_494X_SLOT_CHANNEL_B 5 590#define AHC_494X_SLOT_CHANNEL_C 6 591#define AHC_494X_SLOT_CHANNEL_D 7 592 593#define DEVCONFIG 0x40 594#define SCBSIZE32 0x00010000ul /* aic789X only */ 595#define MPORTMODE 0x00000400ul /* aic7870 only */ 596#define RAMPSM 0x00000200ul /* aic7870 only */ 597#define VOLSENSE 0x00000100ul 598#define SCBRAMSEL 0x00000080ul 599#define MRDCEN 0x00000040ul 600#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 601#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 602#define BERREN 0x00000008ul 603#define DACEN 0x00000004ul 604#define STPWLEVEL 0x00000002ul 605#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 606 607#define CSIZE_LATTIME 0x0c 608#define CACHESIZE 0x0000003ful /* only 5 bits */ 609#define LATTIME 0x0000ff00ul 610 611typedef enum 612{ 613 AHC_POWER_STATE_D0, 614 AHC_POWER_STATE_D1, 615 AHC_POWER_STATE_D2, 616 AHC_POWER_STATE_D3 617} ahc_power_state; 618 619static void ahc_power_state_change(struct ahc_softc *ahc, 620 ahc_power_state new_state); 621static int ahc_ext_scbram_present(struct ahc_softc *ahc); 622static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 623 int pcheck, int fast, int large); 624static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 625static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 626static void configure_termination(struct ahc_softc *ahc, 627 struct seeprom_descriptor *sd, 628 u_int adapter_control, 629 u_int *sxfrctl1); 630 631static void ahc_new_term_detect(struct ahc_softc *ahc, 632 int *enableSEC_low, 633 int *enableSEC_high, 634 int *enablePRI_low, 635 int *enablePRI_high, 636 int *eeprom_present); 637static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 638 int *internal68_present, 639 int *externalcable_present, 640 int *eeprom_present); 641static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 642 int *externalcable_present, 643 int *eeprom_present); 644static int acquire_seeprom(struct ahc_softc *ahc, 645 struct seeprom_descriptor *sd); 646static void release_seeprom(struct seeprom_descriptor *sd); 647static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 648static uint8_t read_brdctl(struct ahc_softc *ahc); 649 650struct ahc_pci_identity * 651ahc_find_pci_device(ahc_dev_softc_t pci) 652{ 653 uint64_t full_id; 654 uint16_t device; 655 uint16_t vendor; 656 uint16_t subdevice; 657 uint16_t subvendor; 658 struct ahc_pci_identity *entry; 659 u_int i; 660 661 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 662 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 663 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 664 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 665 full_id = ahc_compose_id(device, 666 vendor, 667 subdevice, 668 subvendor); 669 670 /* If the second function is not hooked up, ignore it. */ 671 if (ahc_get_pci_function(pci) > 0 672 && subvendor == 0x9005 673 && SUBID_9005_MFUNCENB(subdevice) == 0) 674 return (NULL); 675 676 for (i = 0; i < ahc_num_pci_devs; i++) { 677 entry = &ahc_pci_ident_table[i]; 678 if (entry->full_id == (full_id & entry->id_mask)) 679 return (entry); 680 } 681 return (NULL); 682} 683 684int 685ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 686{ 687 struct ahc_probe_config probe_config; 688 struct scb_data *shared_scb_data; 689 u_int command; 690 u_int our_id = 0; 691 u_int sxfrctl1; 692 u_int scsiseq; 693 u_int dscommand0; 694 int error; 695 uint8_t sblkctl; 696 697 shared_scb_data = NULL; 698 ahc_init_probe_config(&probe_config); 699 error = entry->setup(ahc->dev_softc, &probe_config); 700 if (error != 0) 701 return (error); 702 probe_config.chip |= AHC_PCI; 703 probe_config.description = entry->name; 704 705 error = ahc_pci_map_registers(ahc); 706 if (error != 0) 707 return (error); 708 709 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 710 711 /* Ensure busmastering is enabled */ 712 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 713 command |= PCIM_CMD_BUSMASTEREN; 714 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 715 716 /* On all PCI adapters, we allow SCB paging */ 717 probe_config.flags |= AHC_PAGESCBS; 718 719 error = ahc_softc_init(ahc, &probe_config); 720 if (error != 0) 721 return (error); 722 723 /* Remeber how the card was setup in case there is no SEEPROM */ 724 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 725 pause_sequencer(ahc); 726 if ((ahc->features & AHC_ULTRA2) != 0) 727 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 728 else 729 our_id = ahc_inb(ahc, SCSIID) & OID; 730 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 731 scsiseq = ahc_inb(ahc, SCSISEQ); 732 } else { 733 sxfrctl1 = STPWEN; 734 our_id = 7; 735 scsiseq = 0; 736 } 737 738 error = ahc_reset(ahc); 739 if (error != 0) 740 return (ENXIO); 741 742 if ((ahc->features & AHC_DT) != 0) { 743 u_int sfunct; 744 745 /* Perform ALT-Mode Setup */ 746 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 747 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 748 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 749 ahc_outb(ahc, SFUNCT, sfunct); 750 751 /* Normal mode setup */ 752 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 753 |TARGCRCENDEN); 754 } 755 756 error = ahc_pci_map_int(ahc); 757 if (error != 0) 758 return (error); 759 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 760 dscommand0 |= MPARCKEN|CACHETHEN; 761 if ((ahc->features & AHC_ULTRA2) != 0) { 762 763 /* 764 * DPARCKEN doesn't work correctly on 765 * some MBs so don't use it. 766 */ 767 dscommand0 &= ~DPARCKEN; 768 } 769 770 /* 771 * Handle chips that must have cache line 772 * streaming (dis/en)abled. 773 */ 774 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 775 dscommand0 |= CACHETHEN; 776 777 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 778 dscommand0 &= ~CACHETHEN; 779 780 ahc_outb(ahc, DSCOMMAND0, dscommand0); 781 782 ahc->pci_cachesize = 783 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 784 /*bytes*/1) & CACHESIZE; 785 ahc->pci_cachesize *= 4; 786 787 /* See if we have a SEEPROM and perform auto-term */ 788 check_extport(ahc, &sxfrctl1); 789 790 /* 791 * Take the LED out of diagnostic mode 792 */ 793 sblkctl = ahc_inb(ahc, SBLKCTL); 794 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 795 796 if ((ahc->features & AHC_ULTRA2) != 0) { 797 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 798 } else { 799 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 800 } 801 802 if (ahc->flags & AHC_USEDEFAULTS) { 803 /* 804 * PCI Adapter default setup 805 * Should only be used if the adapter does not have 806 * a SEEPROM. 807 */ 808 /* See if someone else set us up already */ 809 if (scsiseq != 0) { 810 printf("%s: Using left over BIOS settings\n", 811 ahc_name(ahc)); 812 ahc->flags &= ~AHC_USEDEFAULTS; 813 ahc->flags |= AHC_BIOS_ENABLED; 814 } else { 815 /* 816 * Assume only one connector and always turn 817 * on termination. 818 */ 819 our_id = 0x07; 820 sxfrctl1 = STPWEN; 821 } 822 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 823 824 ahc->our_id = our_id; 825 } 826 827 /* 828 * Take a look to see if we have external SRAM. 829 * We currently do not attempt to use SRAM that is 830 * shared among multiple controllers. 831 */ 832 ahc_probe_ext_scbram(ahc); 833 834 /* 835 * Record our termination setting for the 836 * generic initialization routine. 837 */ 838 if ((sxfrctl1 & STPWEN) != 0) 839 ahc->flags |= AHC_TERM_ENB_A; 840 841 /* Core initialization */ 842 error = ahc_init(ahc); 843 if (error != 0) 844 return (error); 845 846 /* 847 * Link this softc in with all other ahc instances. 848 */ 849 ahc_softc_insert(ahc); 850 851 return (0); 852} 853 854static void 855ahc_power_state_change(struct ahc_softc *ahc, ahc_power_state new_state) 856{ 857 uint32_t cap; 858 u_int cap_offset; 859 860 /* 861 * Traverse the capability list looking for 862 * the power management capability. 863 */ 864 cap = 0; 865 cap_offset = ahc_pci_read_config(ahc->dev_softc, 866 PCIR_CAP_PTR, /*bytes*/1); 867 while (cap_offset != 0) { 868 869 cap = ahc_pci_read_config(ahc->dev_softc, 870 cap_offset, /*bytes*/4); 871 if ((cap & 0xFF) == 1 872 && ((cap >> 16) & 0x3) > 0) { 873 uint32_t pm_control; 874 875 pm_control = ahc_pci_read_config(ahc->dev_softc, 876 cap_offset + 4, 877 /*bytes*/4); 878 pm_control &= ~0x3; 879 pm_control |= new_state; 880 ahc_pci_write_config(ahc->dev_softc, 881 cap_offset + 4, 882 pm_control, /*bytes*/2); 883 break; 884 } 885 cap_offset = (cap >> 8) & 0xFF; 886 } 887} 888 889/* 890 * Test for the presense of external sram in an 891 * "unshared" configuration. 892 */ 893static int 894ahc_ext_scbram_present(struct ahc_softc *ahc) 895{ 896 u_int chip; 897 int ramps; 898 int single_user; 899 uint32_t devconfig; 900 901 chip = ahc->chip & AHC_CHIPID_MASK; 902 devconfig = ahc_pci_read_config(ahc->dev_softc, 903 DEVCONFIG, /*bytes*/4); 904 single_user = (devconfig & MPORTMODE) != 0; 905 906 if ((ahc->features & AHC_ULTRA2) != 0) 907 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 908 else if (chip >= AHC_AIC7870) 909 ramps = (devconfig & RAMPSM) != 0; 910 else 911 ramps = 0; 912 913 if (ramps && single_user) 914 return (1); 915 return (0); 916} 917 918/* 919 * Enable external scbram. 920 */ 921static void 922ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 923 int fast, int large) 924{ 925 uint32_t devconfig; 926 927 if (ahc->features & AHC_MULTI_FUNC) { 928 /* 929 * Set the SCB Base addr (highest address bit) 930 * depending on which channel we are. 931 */ 932 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 933 } 934 935 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 936 if ((ahc->features & AHC_ULTRA2) != 0) { 937 u_int dscommand0; 938 939 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 940 if (enable) 941 dscommand0 &= ~INTSCBRAMSEL; 942 else 943 dscommand0 |= INTSCBRAMSEL; 944 if (large) 945 dscommand0 &= ~USCBSIZE32; 946 else 947 dscommand0 |= USCBSIZE32; 948 ahc_outb(ahc, DSCOMMAND0, dscommand0); 949 } else { 950 if (fast) 951 devconfig &= ~EXTSCBTIME; 952 else 953 devconfig |= EXTSCBTIME; 954 if (enable) 955 devconfig &= ~SCBRAMSEL; 956 else 957 devconfig |= SCBRAMSEL; 958 if (large) 959 devconfig &= ~SCBSIZE32; 960 else 961 devconfig |= SCBSIZE32; 962 } 963 if (pcheck) 964 devconfig |= EXTSCBPEN; 965 else 966 devconfig &= ~EXTSCBPEN; 967 968 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 969} 970 971/* 972 * Take a look to see if we have external SRAM. 973 * We currently do not attempt to use SRAM that is 974 * shared among multiple controllers. 975 */ 976static void 977ahc_probe_ext_scbram(struct ahc_softc *ahc) 978{ 979 int num_scbs; 980 int test_num_scbs; 981 int enable; 982 int pcheck; 983 int fast; 984 int large; 985 986 enable = FALSE; 987 pcheck = FALSE; 988 fast = FALSE; 989 large = FALSE; 990 num_scbs = 0; 991 992 if (ahc_ext_scbram_present(ahc) == 0) 993 goto done; 994 995 /* 996 * Probe for the best parameters to use. 997 */ 998 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 999 num_scbs = ahc_probe_scbs(ahc); 1000 if (num_scbs == 0) { 1001 /* The SRAM wasn't really present. */ 1002 goto done; 1003 } 1004 enable = TRUE; 1005 1006 /* 1007 * Clear any outstanding parity error 1008 * and ensure that parity error reporting 1009 * is enabled. 1010 */ 1011 ahc_outb(ahc, SEQCTL, 0); 1012 ahc_outb(ahc, CLRINT, CLRPARERR); 1013 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1014 1015 /* Now see if we can do parity */ 1016 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1017 num_scbs = ahc_probe_scbs(ahc); 1018 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1019 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1020 pcheck = TRUE; 1021 1022 /* Clear any resulting parity error */ 1023 ahc_outb(ahc, CLRINT, CLRPARERR); 1024 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1025 1026 /* Now see if we can do fast timing */ 1027 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1028 test_num_scbs = ahc_probe_scbs(ahc); 1029 if (test_num_scbs == num_scbs 1030 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1031 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1032 fast = TRUE; 1033 1034 /* 1035 * See if we can use large SCBs and still maintain 1036 * the same overall count of SCBs. 1037 */ 1038 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1039 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1040 test_num_scbs = ahc_probe_scbs(ahc); 1041 if (test_num_scbs >= num_scbs) { 1042 large = TRUE; 1043 num_scbs = test_num_scbs; 1044 if (num_scbs >= 64) { 1045 /* 1046 * We have enough space to move the 1047 * "busy targets table" into SCB space 1048 * and make it qualify all the way to the 1049 * lun level. 1050 */ 1051 ahc->flags |= AHC_SCB_BTT; 1052 } 1053 } 1054 } 1055done: 1056 /* 1057 * Disable parity error reporting until we 1058 * can load instruction ram. 1059 */ 1060 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1061 /* Clear any latched parity error */ 1062 ahc_outb(ahc, CLRINT, CLRPARERR); 1063 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1064 if (bootverbose && enable) { 1065 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1066 ahc_name(ahc), fast ? "fast" : "slow", 1067 pcheck ? ", parity checking enabled" : "", 1068 large ? 64 : 32); 1069 } 1070 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1071} 1072 1073/* 1074 * Check the external port logic for a serial eeprom 1075 * and termination/cable detection contrls. 1076 */ 1077static void 1078check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1079{ 1080 struct seeprom_descriptor sd; 1081 struct seeprom_config sc; 1082 u_int scsi_conf; 1083 u_int adapter_control; 1084 int have_seeprom; 1085 int have_autoterm; 1086 1087 sd.sd_ahc = ahc; 1088 sd.sd_control_offset = SEECTL; 1089 sd.sd_status_offset = SEECTL; 1090 sd.sd_dataout_offset = SEECTL; 1091 1092 /* 1093 * For some multi-channel devices, the c46 is simply too 1094 * small to work. For the other controller types, we can 1095 * get our information from either SEEPROM type. Set the 1096 * type to start our probe with accordingly. 1097 */ 1098 if (ahc->flags & AHC_LARGE_SEEPROM) 1099 sd.sd_chip = C56_66; 1100 else 1101 sd.sd_chip = C46; 1102 1103 sd.sd_MS = SEEMS; 1104 sd.sd_RDY = SEERDY; 1105 sd.sd_CS = SEECS; 1106 sd.sd_CK = SEECK; 1107 sd.sd_DO = SEEDO; 1108 sd.sd_DI = SEEDI; 1109 1110 have_seeprom = acquire_seeprom(ahc, &sd); 1111 if (have_seeprom) { 1112 1113 if (bootverbose) 1114 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1115 1116 for (;;) { 1117 u_int start_addr; 1118 1119 start_addr = 32 * (ahc->channel - 'A'); 1120 1121 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 1122 start_addr, sizeof(sc)/2); 1123 1124 if (have_seeprom) 1125 have_seeprom = verify_cksum(&sc); 1126 1127 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1128 if (bootverbose) { 1129 if (have_seeprom == 0) 1130 printf ("checksum error\n"); 1131 else 1132 printf ("done.\n"); 1133 } 1134 break; 1135 } 1136 sd.sd_chip = C56_66; 1137 } 1138 } 1139 1140#if 0 1141 if (!have_seeprom) { 1142 /* 1143 * Pull scratch ram settings and treat them as 1144 * if they are the contents of an seeprom if 1145 * the 'ADPT' signature is found in SCB2. 1146 */ 1147 ahc_outb(ahc, SCBPTR, 2); 1148 if (ahc_inb(ahc, SCB_BASE) == 'A' 1149 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1150 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1151 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1152 uint8_t *sc_bytes; 1153 int i; 1154 1155 sc_bytes = (uint8_t *)≻ 1156 for (i = 0; i < 64; i++) 1157 sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i); 1158 /* Byte 0x1c is stored in byte 4 of SCB2 */ 1159 sc_bytes[0x1c] = ahc_inb(ahc, SCB_BASE + 4); 1160 have_seeprom = verify_cksum(&sc); 1161 } 1162 } 1163#endif 1164 1165 if (!have_seeprom) { 1166 if (bootverbose) 1167 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1168 ahc->flags |= AHC_USEDEFAULTS; 1169 } else { 1170 /* 1171 * Put the data we've collected down into SRAM 1172 * where ahc_init will find it. 1173 */ 1174 int i; 1175 int max_targ = sc.max_targets & CFMAXTARG; 1176 uint16_t discenable; 1177 uint16_t ultraenb; 1178 1179 discenable = 0; 1180 ultraenb = 0; 1181 if ((sc.adapter_control & CFULTRAEN) != 0) { 1182 /* 1183 * Determine if this adapter has a "newstyle" 1184 * SEEPROM format. 1185 */ 1186 for (i = 0; i < max_targ; i++) { 1187 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1188 ahc->flags |= AHC_NEWEEPROM_FMT; 1189 break; 1190 } 1191 } 1192 } 1193 1194 for (i = 0; i < max_targ; i++) { 1195 u_int scsirate; 1196 uint16_t target_mask; 1197 1198 target_mask = 0x01 << i; 1199 if (sc.device_flags[i] & CFDISC) 1200 discenable |= target_mask; 1201 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1202 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1203 ultraenb |= target_mask; 1204 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1205 ultraenb |= target_mask; 1206 } 1207 if ((sc.device_flags[i] & CFXFER) == 0x04 1208 && (ultraenb & target_mask) != 0) { 1209 /* Treat 10MHz as a non-ultra speed */ 1210 sc.device_flags[i] &= ~CFXFER; 1211 ultraenb &= ~target_mask; 1212 } 1213 if ((ahc->features & AHC_ULTRA2) != 0) { 1214 u_int offset; 1215 1216 if (sc.device_flags[i] & CFSYNCH) 1217 offset = MAX_OFFSET_ULTRA2; 1218 else 1219 offset = 0; 1220 ahc_outb(ahc, TARG_OFFSET + i, offset); 1221 1222 /* 1223 * The ultra enable bits contain the 1224 * high bit of the ultra2 sync rate 1225 * field. 1226 */ 1227 scsirate = (sc.device_flags[i] & CFXFER) 1228 | ((ultraenb & target_mask) 1229 ? 0x8 : 0x0); 1230 if (sc.device_flags[i] & CFWIDEB) 1231 scsirate |= WIDEXFER; 1232 } else { 1233 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1234 if (sc.device_flags[i] & CFSYNCH) 1235 scsirate |= SOFS; 1236 if (sc.device_flags[i] & CFWIDEB) 1237 scsirate |= WIDEXFER; 1238 } 1239 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1240 } 1241 ahc->our_id = sc.brtime_id & CFSCSIID; 1242 1243 scsi_conf = (ahc->our_id & 0x7); 1244 if (sc.adapter_control & CFSPARITY) 1245 scsi_conf |= ENSPCHK; 1246 if (sc.adapter_control & CFRESETB) 1247 scsi_conf |= RESET_SCSI; 1248 1249 if ((sc.adapter_control & CFCHNLBPRIMARY) != 0 1250 && (ahc->features & AHC_MULTI_FUNC) != 0) 1251 ahc->flags |= AHC_CHANNEL_B_PRIMARY; 1252 1253 if (sc.bios_control & CFEXTEND) 1254 ahc->flags |= AHC_EXTENDED_TRANS_A; 1255 1256 if (sc.bios_control & CFBIOSEN) 1257 ahc->flags |= AHC_BIOS_ENABLED; 1258 if (ahc->features & AHC_ULTRA 1259 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1260 /* Should we enable Ultra mode? */ 1261 if (!(sc.adapter_control & CFULTRAEN)) 1262 /* Treat us as a non-ultra card */ 1263 ultraenb = 0; 1264 } 1265 1266 if (sc.signature == CFSIGNATURE) { 1267 uint32_t devconfig; 1268 1269 /* Honor the STPWLEVEL settings */ 1270 devconfig = ahc_pci_read_config(ahc->dev_softc, 1271 DEVCONFIG, /*bytes*/4); 1272 devconfig &= ~STPWLEVEL; 1273 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1274 devconfig |= STPWLEVEL; 1275 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1276 devconfig, /*bytes*/4); 1277 } 1278 /* Set SCSICONF info */ 1279 ahc_outb(ahc, SCSICONF, scsi_conf); 1280 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1281 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1282 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1283 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1284 } 1285 1286 /* 1287 * Cards that have the external logic necessary to talk to 1288 * a SEEPROM, are almost certain to have the remaining logic 1289 * necessary for auto-termination control. This assumption 1290 * hasn't failed yet... 1291 */ 1292 have_autoterm = have_seeprom; 1293 if (have_seeprom) 1294 adapter_control = sc.adapter_control; 1295 else 1296 adapter_control = CFAUTOTERM; 1297 1298 /* 1299 * Some low-cost chips have SEEPROM and auto-term control built 1300 * in, instead of using a GAL. They can tell us directly 1301 * if the termination logic is enabled. 1302 */ 1303 if ((ahc->features & AHC_SPIOCAP) != 0) { 1304 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1305 have_autoterm = TRUE; 1306 else 1307 have_autoterm = FALSE; 1308 } 1309 1310 if (have_autoterm) 1311 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1312 1313 release_seeprom(&sd); 1314} 1315 1316static void 1317configure_termination(struct ahc_softc *ahc, 1318 struct seeprom_descriptor *sd, 1319 u_int adapter_control, 1320 u_int *sxfrctl1) 1321{ 1322 uint8_t brddat; 1323 1324 brddat = 0; 1325 1326 /* 1327 * Update the settings in sxfrctl1 to match the 1328 * termination settings 1329 */ 1330 *sxfrctl1 = 0; 1331 1332 /* 1333 * SEECS must be on for the GALS to latch 1334 * the data properly. Be sure to leave MS 1335 * on or we will release the seeprom. 1336 */ 1337 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1338 if ((adapter_control & CFAUTOTERM) != 0 1339 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1340 int internal50_present; 1341 int internal68_present; 1342 int externalcable_present; 1343 int eeprom_present; 1344 int enableSEC_low; 1345 int enableSEC_high; 1346 int enablePRI_low; 1347 int enablePRI_high; 1348 int sum; 1349 1350 enableSEC_low = 0; 1351 enableSEC_high = 0; 1352 enablePRI_low = 0; 1353 enablePRI_high = 0; 1354 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1355 ahc_new_term_detect(ahc, &enableSEC_low, 1356 &enableSEC_high, 1357 &enablePRI_low, 1358 &enablePRI_high, 1359 &eeprom_present); 1360 if ((adapter_control & CFSEAUTOTERM) == 0) { 1361 if (bootverbose) 1362 printf("%s: Manual SE Termination\n", 1363 ahc_name(ahc)); 1364 enableSEC_low = (adapter_control & CFSELOWTERM); 1365 enableSEC_high = 1366 (adapter_control & CFSEHIGHTERM); 1367 } 1368 if ((adapter_control & CFAUTOTERM) == 0) { 1369 if (bootverbose) 1370 printf("%s: Manual LVD Termination\n", 1371 ahc_name(ahc)); 1372 enablePRI_low = (adapter_control & CFSTERM); 1373 enablePRI_high = (adapter_control & CFWSTERM); 1374 } 1375 /* Make the table calculations below happy */ 1376 internal50_present = 0; 1377 internal68_present = 1; 1378 externalcable_present = 1; 1379 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1380 aic785X_cable_detect(ahc, &internal50_present, 1381 &externalcable_present, 1382 &eeprom_present); 1383 } else { 1384 aic787X_cable_detect(ahc, &internal50_present, 1385 &internal68_present, 1386 &externalcable_present, 1387 &eeprom_present); 1388 } 1389 1390 if ((ahc->features & AHC_WIDE) == 0) 1391 internal68_present = 0; 1392 1393 if (bootverbose 1394 && (ahc->features & AHC_ULTRA2) == 0) { 1395 printf("%s: internal 50 cable %s present", 1396 ahc_name(ahc), 1397 internal50_present ? "is":"not"); 1398 1399 if ((ahc->features & AHC_WIDE) != 0) 1400 printf(", internal 68 cable %s present", 1401 internal68_present ? "is":"not"); 1402 printf("\n%s: external cable %s present\n", 1403 ahc_name(ahc), 1404 externalcable_present ? "is":"not"); 1405 } 1406 if (bootverbose) 1407 printf("%s: BIOS eeprom %s present\n", 1408 ahc_name(ahc), eeprom_present ? "is" : "not"); 1409 1410 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1411 /* 1412 * The 50 pin connector is a separate bus, 1413 * so force it to always be terminated. 1414 * In the future, perform current sensing 1415 * to determine if we are in the middle of 1416 * a properly terminated bus. 1417 */ 1418 internal50_present = 0; 1419 } 1420 1421 /* 1422 * Now set the termination based on what 1423 * we found. 1424 * Flash Enable = BRDDAT7 1425 * Secondary High Term Enable = BRDDAT6 1426 * Secondary Low Term Enable = BRDDAT5 (7890) 1427 * Primary High Term Enable = BRDDAT4 (7890) 1428 */ 1429 if ((ahc->features & AHC_ULTRA2) == 0 1430 && (internal50_present != 0) 1431 && (internal68_present != 0) 1432 && (externalcable_present != 0)) { 1433 printf("%s: Illegal cable configuration!!. " 1434 "Only two connectors on the " 1435 "adapter may be used at a " 1436 "time!\n", ahc_name(ahc)); 1437 } 1438 1439 if ((ahc->features & AHC_WIDE) != 0 1440 && ((externalcable_present == 0) 1441 || (internal68_present == 0) 1442 || (enableSEC_high != 0))) { 1443 brddat |= BRDDAT6; 1444 if (bootverbose) { 1445 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1446 printf("%s: 68 pin termination " 1447 "Enabled\n", ahc_name(ahc)); 1448 else 1449 printf("%s: %sHigh byte termination " 1450 "Enabled\n", ahc_name(ahc), 1451 enableSEC_high ? "Secondary " 1452 : ""); 1453 } 1454 } 1455 1456 sum = internal50_present + internal68_present 1457 + externalcable_present; 1458 if (sum < 2 || (enableSEC_low != 0)) { 1459 if ((ahc->features & AHC_ULTRA2) != 0) 1460 brddat |= BRDDAT5; 1461 else 1462 *sxfrctl1 |= STPWEN; 1463 if (bootverbose) { 1464 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1465 printf("%s: 50 pin termination " 1466 "Enabled\n", ahc_name(ahc)); 1467 else 1468 printf("%s: %sLow byte termination " 1469 "Enabled\n", ahc_name(ahc), 1470 enableSEC_low ? "Secondary " 1471 : ""); 1472 } 1473 } 1474 1475 if (enablePRI_low != 0) { 1476 *sxfrctl1 |= STPWEN; 1477 if (bootverbose) 1478 printf("%s: Primary Low Byte termination " 1479 "Enabled\n", ahc_name(ahc)); 1480 } 1481 1482 /* 1483 * Setup STPWEN before setting up the rest of 1484 * the termination per the tech note on the U160 cards. 1485 */ 1486 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1487 1488 if (enablePRI_high != 0) { 1489 brddat |= BRDDAT4; 1490 if (bootverbose) 1491 printf("%s: Primary High Byte " 1492 "termination Enabled\n", 1493 ahc_name(ahc)); 1494 } 1495 1496 write_brdctl(ahc, brddat); 1497 1498 } else { 1499 if ((adapter_control & CFSTERM) != 0) { 1500 *sxfrctl1 |= STPWEN; 1501 1502 if (bootverbose) 1503 printf("%s: %sLow byte termination Enabled\n", 1504 ahc_name(ahc), 1505 (ahc->features & AHC_ULTRA2) ? "Primary " 1506 : ""); 1507 } 1508 1509 if ((adapter_control & CFWSTERM) != 0 1510 && (ahc->features & AHC_WIDE) != 0) { 1511 brddat |= BRDDAT6; 1512 if (bootverbose) 1513 printf("%s: %sHigh byte termination Enabled\n", 1514 ahc_name(ahc), 1515 (ahc->features & AHC_ULTRA2) 1516 ? "Secondary " : ""); 1517 } 1518 1519 /* 1520 * Setup STPWEN before setting up the rest of 1521 * the termination per the tech note on the U160 cards. 1522 */ 1523 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1524 1525 if ((ahc->features & AHC_WIDE) != 0) 1526 write_brdctl(ahc, brddat); 1527 } 1528 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1529} 1530 1531static void 1532ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1533 int *enableSEC_high, int *enablePRI_low, 1534 int *enablePRI_high, int *eeprom_present) 1535{ 1536 uint8_t brdctl; 1537 1538 /* 1539 * BRDDAT7 = Eeprom 1540 * BRDDAT6 = Enable Secondary High Byte termination 1541 * BRDDAT5 = Enable Secondary Low Byte termination 1542 * BRDDAT4 = Enable Primary high byte termination 1543 * BRDDAT3 = Enable Primary low byte termination 1544 */ 1545 brdctl = read_brdctl(ahc); 1546 *eeprom_present = brdctl & BRDDAT7; 1547 *enableSEC_high = (brdctl & BRDDAT6); 1548 *enableSEC_low = (brdctl & BRDDAT5); 1549 *enablePRI_high = (brdctl & BRDDAT4); 1550 *enablePRI_low = (brdctl & BRDDAT3); 1551} 1552 1553static void 1554aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1555 int *internal68_present, int *externalcable_present, 1556 int *eeprom_present) 1557{ 1558 uint8_t brdctl; 1559 1560 /* 1561 * First read the status of our cables. 1562 * Set the rom bank to 0 since the 1563 * bank setting serves as a multiplexor 1564 * for the cable detection logic. 1565 * BRDDAT5 controls the bank switch. 1566 */ 1567 write_brdctl(ahc, 0); 1568 1569 /* 1570 * Now read the state of the internal 1571 * connectors. BRDDAT6 is INT50 and 1572 * BRDDAT7 is INT68. 1573 */ 1574 brdctl = read_brdctl(ahc); 1575 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1576 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1577 1578 /* 1579 * Set the rom bank to 1 and determine 1580 * the other signals. 1581 */ 1582 write_brdctl(ahc, BRDDAT5); 1583 1584 /* 1585 * Now read the state of the external 1586 * connectors. BRDDAT6 is EXT68 and 1587 * BRDDAT7 is EPROMPS. 1588 */ 1589 brdctl = read_brdctl(ahc); 1590 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1591 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1592} 1593 1594static void 1595aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1596 int *externalcable_present, int *eeprom_present) 1597{ 1598 uint8_t brdctl; 1599 1600 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1601 ahc_outb(ahc, BRDCTL, 0); 1602 brdctl = ahc_inb(ahc, BRDCTL); 1603 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1604 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1605 1606 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1607} 1608 1609static int 1610acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1611{ 1612 int wait; 1613 1614 if ((ahc->features & AHC_SPIOCAP) != 0 1615 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1616 return (0); 1617 1618 /* 1619 * Request access of the memory port. When access is 1620 * granted, SEERDY will go high. We use a 1 second 1621 * timeout which should be near 1 second more than 1622 * is needed. Reason: after the chip reset, there 1623 * should be no contention. 1624 */ 1625 SEEPROM_OUTB(sd, sd->sd_MS); 1626 wait = 1000; /* 1 second timeout in msec */ 1627 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1628 ahc_delay(1000); /* delay 1 msec */ 1629 } 1630 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1631 SEEPROM_OUTB(sd, 0); 1632 return (0); 1633 } 1634 return(1); 1635} 1636 1637static void 1638release_seeprom(struct seeprom_descriptor *sd) 1639{ 1640 /* Release access to the memory port and the serial EEPROM. */ 1641 SEEPROM_OUTB(sd, 0); 1642} 1643 1644static void 1645write_brdctl(struct ahc_softc *ahc, uint8_t value) 1646{ 1647 uint8_t brdctl; 1648 1649 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1650 brdctl = BRDSTB; 1651 if (ahc->channel == 'B') 1652 brdctl |= BRDCS; 1653 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1654 brdctl = 0; 1655 } else { 1656 brdctl = BRDSTB|BRDCS; 1657 } 1658 ahc_outb(ahc, BRDCTL, brdctl); 1659 ahc_flush_device_writes(ahc); 1660 brdctl |= value; 1661 ahc_outb(ahc, BRDCTL, brdctl); 1662 ahc_flush_device_writes(ahc); 1663 if ((ahc->features & AHC_ULTRA2) != 0) 1664 brdctl |= BRDSTB_ULTRA2; 1665 else 1666 brdctl &= ~BRDSTB; 1667 ahc_outb(ahc, BRDCTL, brdctl); 1668 ahc_flush_device_writes(ahc); 1669 if ((ahc->features & AHC_ULTRA2) != 0) 1670 brdctl = 0; 1671 else 1672 brdctl &= ~BRDCS; 1673 ahc_outb(ahc, BRDCTL, brdctl); 1674} 1675 1676static uint8_t 1677read_brdctl(ahc) 1678 struct ahc_softc *ahc; 1679{ 1680 uint8_t brdctl; 1681 uint8_t value; 1682 1683 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1684 brdctl = BRDRW; 1685 if (ahc->channel == 'B') 1686 brdctl |= BRDCS; 1687 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1688 brdctl = BRDRW_ULTRA2; 1689 } else { 1690 brdctl = BRDRW|BRDCS; 1691 } 1692 ahc_outb(ahc, BRDCTL, brdctl); 1693 ahc_flush_device_writes(ahc); 1694 value = ahc_inb(ahc, BRDCTL); 1695 ahc_outb(ahc, BRDCTL, 0); 1696 return (value); 1697} 1698 1699#define DPE 0x80 1700#define SSE 0x40 1701#define RMA 0x20 1702#define RTA 0x10 1703#define STA 0x08 1704#define DPR 0x01 1705 1706void 1707ahc_pci_intr(struct ahc_softc *ahc) 1708{ 1709 u_int error; 1710 u_int status1; 1711 1712 error = ahc_inb(ahc, ERROR); 1713 if ((error & PCIERRSTAT) == 0) 1714 return; 1715 1716 status1 = ahc_pci_read_config(ahc->dev_softc, 1717 PCIR_STATUS + 1, /*bytes*/1); 1718 1719 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1720 ahc_name(ahc), 1721 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1722 1723 if (status1 & DPE) { 1724 printf("%s: Data Parity Error Detected during address " 1725 "or write data phase\n", ahc_name(ahc)); 1726 } 1727 if (status1 & SSE) { 1728 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1729 } 1730 if (status1 & RMA) { 1731 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1732 } 1733 if (status1 & RTA) { 1734 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1735 } 1736 if (status1 & STA) { 1737 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1738 } 1739 if (status1 & DPR) { 1740 printf("%s: Data Parity Error has been reported via PERR#\n", 1741 ahc_name(ahc)); 1742 } 1743 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1744 printf("%s: Latched PCIERR interrupt with " 1745 "no status bits set\n", ahc_name(ahc)); 1746 } 1747 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1748 status1, /*bytes*/1); 1749 1750 if (status1 & (DPR|RMA|RTA)) { 1751 ahc_outb(ahc, CLRINT, CLRPARERR); 1752 } 1753 1754 unpause_sequencer(ahc); 1755} 1756 1757static int 1758ahc_aic7850_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1759{ 1760 probe_config->channel = 'A'; 1761 probe_config->chip = AHC_AIC7850; 1762 probe_config->features = AHC_AIC7850_FE; 1763 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1764 | AHC_PCI_MWI_BUG; 1765 return (0); 1766} 1767 1768static int 1769ahc_aic7855_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1770{ 1771 probe_config->channel = 'A'; 1772 probe_config->chip = AHC_AIC7855; 1773 probe_config->features = AHC_AIC7855_FE; 1774 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1775 | AHC_PCI_MWI_BUG; 1776 return (0); 1777} 1778 1779static int 1780ahc_aic7860_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1781{ 1782 uint8_t rev; 1783 1784 probe_config->channel = 'A'; 1785 probe_config->chip = AHC_AIC7860; 1786 probe_config->features = AHC_AIC7860_FE; 1787 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1788 | AHC_PCI_MWI_BUG; 1789 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1790 if (rev >= 1) 1791 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1792 return (0); 1793} 1794 1795static int 1796ahc_apa1480_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1797{ 1798 int error; 1799 1800 error = ahc_aic7860_setup(pci, probe_config); 1801 if (error != 0) 1802 return (error); 1803 probe_config->features |= AHC_REMOVABLE; 1804 return (0); 1805} 1806 1807static int 1808ahc_aic7870_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1809{ 1810 probe_config->channel = 'A'; 1811 probe_config->chip = AHC_AIC7870; 1812 probe_config->features = AHC_AIC7870_FE; 1813 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1814 | AHC_PCI_MWI_BUG; 1815 return (0); 1816} 1817 1818static int 1819ahc_aha394X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1820{ 1821 int error; 1822 1823 error = ahc_aic7870_setup(pci, probe_config); 1824 if (error == 0) 1825 error = ahc_aha394XX_setup(pci, probe_config); 1826 return (error); 1827} 1828 1829static int 1830ahc_aha398X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1831{ 1832 int error; 1833 1834 error = ahc_aic7870_setup(pci, probe_config); 1835 if (error == 0) 1836 error = ahc_aha398XX_setup(pci, probe_config); 1837 return (error); 1838} 1839 1840static int 1841ahc_aha494X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1842{ 1843 int error; 1844 1845 error = ahc_aic7870_setup(pci, probe_config); 1846 if (error == 0) 1847 error = ahc_aha494XX_setup(pci, probe_config); 1848 return (error); 1849} 1850 1851static int 1852ahc_aic7880_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1853{ 1854 uint8_t rev; 1855 1856 probe_config->channel = 'A'; 1857 probe_config->chip = AHC_AIC7880; 1858 probe_config->features = AHC_AIC7880_FE; 1859 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1860 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1861 if (rev >= 1) { 1862 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1863 } else { 1864 probe_config->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1865 } 1866 return (0); 1867} 1868 1869static int 1870ahc_aha2940Pro_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1871{ 1872 int error; 1873 1874 probe_config->flags |= AHC_INT50_SPEEDFLEX; 1875 error = ahc_aic7880_setup(pci, probe_config); 1876 return (0); 1877} 1878 1879static int 1880ahc_aha394XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1881{ 1882 int error; 1883 1884 error = ahc_aic7880_setup(pci, probe_config); 1885 if (error == 0) 1886 error = ahc_aha394XX_setup(pci, probe_config); 1887 return (error); 1888} 1889 1890static int 1891ahc_aha398XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1892{ 1893 int error; 1894 1895 error = ahc_aic7880_setup(pci, probe_config); 1896 if (error == 0) 1897 error = ahc_aha398XX_setup(pci, probe_config); 1898 return (error); 1899} 1900 1901static int 1902ahc_aic7890_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1903{ 1904 uint8_t rev; 1905 1906 probe_config->channel = 'A'; 1907 probe_config->chip = AHC_AIC7890; 1908 probe_config->features = AHC_AIC7890_FE; 1909 probe_config->flags |= AHC_NEWEEPROM_FMT; 1910 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1911 if (rev == 0) 1912 probe_config->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1913 return (0); 1914} 1915 1916static int 1917ahc_aic7892_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1918{ 1919 probe_config->channel = 'A'; 1920 probe_config->chip = AHC_AIC7892; 1921 probe_config->features = AHC_AIC7892_FE; 1922 probe_config->flags |= AHC_NEWEEPROM_FMT; 1923 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1924 return (0); 1925} 1926 1927static int 1928ahc_aic7895_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1929{ 1930 uint8_t rev; 1931 1932 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1933 /* 1934 * The 'C' revision of the aic7895 has a few additional features. 1935 */ 1936 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1937 if (rev >= 4) { 1938 probe_config->chip = AHC_AIC7895C; 1939 probe_config->features = AHC_AIC7895C_FE; 1940 } else { 1941 u_int command; 1942 1943 probe_config->chip = AHC_AIC7895; 1944 probe_config->features = AHC_AIC7895_FE; 1945 1946 /* 1947 * The BIOS disables the use of MWI transactions 1948 * since it does not have the MWI bug work around 1949 * we have. Disabling MWI reduces performance, so 1950 * turn it on again. 1951 */ 1952 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 1953 command |= PCIM_CMD_MWRICEN; 1954 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 1955 probe_config->bugs |= AHC_PCI_MWI_BUG; 1956 } 1957 /* 1958 * XXX Does CACHETHEN really not work??? What about PCI retry? 1959 * on C level chips. Need to test, but for now, play it safe. 1960 */ 1961 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1962 | AHC_CACHETHEN_BUG; 1963 1964#if 0 1965 uint32_t devconfig; 1966 1967 /* 1968 * Cachesize must also be zero due to stray DAC 1969 * problem when sitting behind some bridges. 1970 */ 1971 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 1972 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 1973 devconfig |= MRDCEN; 1974 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 1975#endif 1976 probe_config->flags |= AHC_NEWEEPROM_FMT; 1977 return (0); 1978} 1979 1980static int 1981ahc_aic7896_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1982{ 1983 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1984 probe_config->chip = AHC_AIC7896; 1985 probe_config->features = AHC_AIC7896_FE; 1986 probe_config->flags |= AHC_NEWEEPROM_FMT; 1987 probe_config->bugs |= AHC_CACHETHEN_DIS_BUG; 1988 return (0); 1989} 1990 1991static int 1992ahc_aic7899_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1993{ 1994 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1995 probe_config->chip = AHC_AIC7899; 1996 probe_config->features = AHC_AIC7899_FE; 1997 probe_config->flags |= AHC_NEWEEPROM_FMT; 1998 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1999 return (0); 2000} 2001 2002static int 2003ahc_aha29160C_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2004{ 2005 int error; 2006 2007 error = ahc_aic7899_setup(pci, probe_config); 2008 if (error != 0) 2009 return (error); 2010 probe_config->features |= AHC_REMOVABLE; 2011 return (0); 2012} 2013 2014static int 2015ahc_raid_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2016{ 2017 printf("RAID functionality unsupported\n"); 2018 return (ENXIO); 2019} 2020 2021static int 2022ahc_aha394XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2023{ 2024 switch (ahc_get_pci_slot(pci)) { 2025 case AHC_394X_SLOT_CHANNEL_A: 2026 probe_config->channel = 'A'; 2027 break; 2028 case AHC_394X_SLOT_CHANNEL_B: 2029 probe_config->channel = 'B'; 2030 break; 2031 default: 2032 printf("adapter at unexpected slot %d\n" 2033 "unable to map to a channel\n", 2034 ahc_get_pci_slot(pci)); 2035 probe_config->channel = 'A'; 2036 } 2037 return (0); 2038} 2039 2040static int 2041ahc_aha398XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2042{ 2043 switch (ahc_get_pci_slot(pci)) { 2044 case AHC_398X_SLOT_CHANNEL_A: 2045 probe_config->channel = 'A'; 2046 break; 2047 case AHC_398X_SLOT_CHANNEL_B: 2048 probe_config->channel = 'B'; 2049 break; 2050 case AHC_398X_SLOT_CHANNEL_C: 2051 probe_config->channel = 'C'; 2052 break; 2053 default: 2054 printf("adapter at unexpected slot %d\n" 2055 "unable to map to a channel\n", 2056 ahc_get_pci_slot(pci)); 2057 probe_config->channel = 'A'; 2058 break; 2059 } 2060 probe_config->flags |= AHC_LARGE_SEEPROM; 2061 return (0); 2062} 2063 2064static int 2065ahc_aha494XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2066{ 2067 switch (ahc_get_pci_slot(pci)) { 2068 case AHC_494X_SLOT_CHANNEL_A: 2069 probe_config->channel = 'A'; 2070 break; 2071 case AHC_494X_SLOT_CHANNEL_B: 2072 probe_config->channel = 'B'; 2073 break; 2074 case AHC_494X_SLOT_CHANNEL_C: 2075 probe_config->channel = 'C'; 2076 break; 2077 case AHC_494X_SLOT_CHANNEL_D: 2078 probe_config->channel = 'D'; 2079 break; 2080 default: 2081 printf("adapter at unexpected slot %d\n" 2082 "unable to map to a channel\n", 2083 ahc_get_pci_slot(pci)); 2084 probe_config->channel = 'A'; 2085 } 2086 probe_config->flags |= AHC_LARGE_SEEPROM; 2087 return (0); 2088} 2089