aic7xxx_pci.c revision 71717
1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995-2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $Id: //depot/src/aic7xxx/aic7xxx_pci.c#12 $ 34 * 35 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_pci.c 71717 2001-01-27 20:54:24Z gibbs $ 36 */ 37 38#ifdef __linux__ 39#include "aic7xxx_linux.h" 40#include "aic7xxx_inline.h" 41#include "aic7xxx_93cx6.h" 42#endif 43 44#ifdef __FreeBSD__ 45#include <dev/aic7xxx/aic7xxx_freebsd.h> 46#include <dev/aic7xxx/aic7xxx_inline.h> 47#include <dev/aic7xxx/aic7xxx_93cx6.h> 48#endif 49 50#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 51#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 52 53static __inline uint64_t 54ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 55{ 56 uint64_t id; 57 58 id = subvendor 59 | (subdevice << 16) 60 | ((uint64_t)vendor << 32) 61 | ((uint64_t)device << 48); 62 63 return (id); 64} 65 66#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 67#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 68#define ID_AIC7850 0x5078900400000000ull 69#define ID_AHA_2910_15_20_30C 0x5078900478509004ull 70#define ID_AIC7855 0x5578900400000000ull 71#define ID_AIC7859 0x3860900400000000ull 72#define ID_AHA_2930CU 0x3860900438699004ull 73#define ID_AIC7860 0x6078900400000000ull 74#define ID_AIC7860C 0x6078900478609004ull 75#define ID_AHA_1480A 0x6075900400000000ull 76#define ID_AHA_2940AU_0 0x6178900400000000ull 77#define ID_AHA_2940AU_1 0x6178900478619004ull 78#define ID_AHA_2940AU_CN 0x2178900478219004ull 79#define ID_AHA_2930C_VAR 0x6038900438689004ull 80 81#define ID_AIC7870 0x7078900400000000ull 82#define ID_AHA_2940 0x7178900400000000ull 83#define ID_AHA_3940 0x7278900400000000ull 84#define ID_AHA_398X 0x7378900400000000ull 85#define ID_AHA_2944 0x7478900400000000ull 86#define ID_AHA_3944 0x7578900400000000ull 87#define ID_AHA_4944 0x7678900400000000ull 88 89#define ID_AIC7880 0x8078900400000000ull 90#define ID_AIC7880_B 0x8078900478809004ull 91#define ID_AHA_2940U 0x8178900400000000ull 92#define ID_AHA_3940U 0x8278900400000000ull 93#define ID_AHA_2944U 0x8478900400000000ull 94#define ID_AHA_3944U 0x8578900400000000ull 95#define ID_AHA_398XU 0x8378900400000000ull 96#define ID_AHA_4944U 0x8678900400000000ull 97#define ID_AHA_2940UB 0x8178900478819004ull 98#define ID_AHA_2930U 0x8878900478889004ull 99#define ID_AHA_2940U_PRO 0x8778900478879004ull 100#define ID_AHA_2940U_CN 0x0078900478009004ull 101 102#define ID_AIC7895 0x7895900478959004ull 103#define ID_AIC7895_RAID_PORT 0x7893900478939004ull 104#define ID_AHA_2940U_DUAL 0x7895900478919004ull 105#define ID_AHA_3940AU 0x7895900478929004ull 106#define ID_AHA_3944AU 0x7895900478949004ull 107 108#define ID_AIC7890 0x001F9005000F9005ull 109#define ID_AAA_131U2 0x0013900500039005ull 110#define ID_AHA_2930U2 0x0011900501819005ull 111#define ID_AHA_2940U2B 0x00109005A1009005ull 112#define ID_AHA_2940U2_OEM 0x0010900521809005ull 113#define ID_AHA_2940U2 0x00109005A1809005ull 114#define ID_AHA_2950U2B 0x00109005E1009005ull 115 116#define ID_AIC7892 0x008F9005FFFF9005ull 117#define ID_AHA_29160 0x00809005E2A09005ull 118#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 119#define ID_AHA_29160N 0x0080900562A09005ull 120#define ID_AHA_29160C 0x0080900562209005ull 121#define ID_AHA_29160B 0x00809005E2209005ull 122#define ID_AHA_19160B 0x0081900562A19005ull 123 124#define ID_AIC7896 0x005F9005FFFF9005ull 125#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 126#define ID_AHA_3950U2B_1 0x00509005F5009005ull 127#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 128#define ID_AHA_3950U2D_1 0x00519005B5009005ull 129 130#define ID_AIC7899 0x00CF9005FFFF9005ull 131#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 132#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 133 134#define ID_AIC7810 0x1078900400000000ull 135#define ID_AIC7815 0x7815900400000000ull 136 137#define SUBID_9005_TYPE(id) ((id) & 0xF) 138#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 139#define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 140#define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 141#define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 142 143#define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 144#define SUBID_9005_MAXRATE_ULTRA2 0x0 145#define SUBID_9005_MAXRATE_ULTRA 0x1 146#define SUBID_9005_MAXRATE_U160 0x2 147#define SUBID_9005_MAXRATE_RESERVED 0x3 148 149#define SUBID_9005_SEEPTYPE(id) \ 150 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 151 ? ((id) & 0xC0) >> 6 \ 152 : ((id) & 0x300) >> 8) 153#define SUBID_9005_SEEPTYPE_NONE 0x0 154#define SUBID_9005_SEEPTYPE_1K 0x1 155#define SUBID_9005_SEEPTYPE_2K_4K 0x2 156#define SUBID_9005_SEEPTYPE_RESERVED 0x3 157#define SUBID_9005_AUTOTERM(id) \ 158 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 159 ? (((id) & 0x400) >> 10) == 0 \ 160 : (((id) & 0x40) >> 6) == 0) 161 162#define SUBID_9005_NUMCHAN(id) \ 163 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 164 ? ((id) & 0x300) >> 8 \ 165 : ((id) & 0xC00) >> 10) 166 167#define SUBID_9005_LEGACYCONN(id) \ 168 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 169 ? 0 \ 170 : ((id) & 0x80) >> 7) 171 172#define SUBID_9005_MFUNCENB(id) \ 173 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 174 ? ((id) & 0x800) >> 11 \ 175 : ((id) & 0x1000) >> 12) 176/* 177 * Informational only. Should use chip register to be 178 * ceratian, but may be use in identification strings. 179 */ 180#define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 181#define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 182#define SUBID_9005_CARD_SEDIFF_MASK 0x8000 183 184static ahc_device_setup_t ahc_aic7850_setup; 185static ahc_device_setup_t ahc_aic7855_setup; 186static ahc_device_setup_t ahc_aic7860_setup; 187static ahc_device_setup_t ahc_apa1480_setup; 188static ahc_device_setup_t ahc_aic7870_setup; 189static ahc_device_setup_t ahc_aha394X_setup; 190static ahc_device_setup_t ahc_aha494X_setup; 191static ahc_device_setup_t ahc_aha398X_setup; 192static ahc_device_setup_t ahc_aic7880_setup; 193static ahc_device_setup_t ahc_aha2940Pro_setup; 194static ahc_device_setup_t ahc_aha394XU_setup; 195static ahc_device_setup_t ahc_aha398XU_setup; 196static ahc_device_setup_t ahc_aic7890_setup; 197static ahc_device_setup_t ahc_aic7892_setup; 198static ahc_device_setup_t ahc_aic7895_setup; 199static ahc_device_setup_t ahc_aic7896_setup; 200static ahc_device_setup_t ahc_aic7899_setup; 201static ahc_device_setup_t ahc_aha29160C_setup; 202static ahc_device_setup_t ahc_raid_setup; 203static ahc_device_setup_t ahc_aha394XX_setup; 204static ahc_device_setup_t ahc_aha494XX_setup; 205static ahc_device_setup_t ahc_aha398XX_setup; 206 207struct ahc_pci_identity ahc_pci_ident_table [] = 208{ 209 /* aic7850 based controllers */ 210 { 211 ID_AHA_2910_15_20_30C, 212 ID_ALL_MASK, 213 "Adaptec 2910/15/20/30C SCSI adapter", 214 ahc_aic7850_setup 215 }, 216 /* aic7860 based controllers */ 217 { 218 ID_AHA_2930CU, 219 ID_ALL_MASK, 220 "Adaptec 2930CU SCSI adapter", 221 ahc_aic7860_setup 222 }, 223 { 224 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 225 ID_DEV_VENDOR_MASK, 226 "Adaptec 1480A Ultra SCSI adapter", 227 ahc_apa1480_setup 228 }, 229 { 230 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 231 ID_DEV_VENDOR_MASK, 232 "Adaptec 2940A Ultra SCSI adapter", 233 ahc_aic7860_setup 234 }, 235 { 236 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 237 ID_DEV_VENDOR_MASK, 238 "Adaptec 2940A/CN Ultra SCSI adapter", 239 ahc_aic7860_setup 240 }, 241 { 242 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 243 ID_DEV_VENDOR_MASK, 244 "Adaptec 2930C SCSI adapter (VAR)", 245 ahc_aic7860_setup 246 }, 247 /* aic7870 based controllers */ 248 { 249 ID_AHA_2940, 250 ID_ALL_MASK, 251 "Adaptec 2940 SCSI adapter", 252 ahc_aic7870_setup 253 }, 254 { 255 ID_AHA_3940, 256 ID_ALL_MASK, 257 "Adaptec 3940 SCSI adapter", 258 ahc_aha394X_setup 259 }, 260 { 261 ID_AHA_398X, 262 ID_ALL_MASK, 263 "Adaptec 398X SCSI RAID adapter", 264 ahc_aha398X_setup 265 }, 266 { 267 ID_AHA_2944, 268 ID_ALL_MASK, 269 "Adaptec 2944 SCSI adapter", 270 ahc_aic7870_setup 271 }, 272 { 273 ID_AHA_3944, 274 ID_ALL_MASK, 275 "Adaptec 3944 SCSI adapter", 276 ahc_aha394X_setup 277 }, 278 { 279 ID_AHA_4944, 280 ID_ALL_MASK, 281 "Adaptec 4944 SCSI adapter", 282 ahc_aha494X_setup 283 }, 284 /* aic7880 based controllers */ 285 { 286 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 2940 Ultra SCSI adapter", 289 ahc_aic7880_setup 290 }, 291 { 292 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 3940 Ultra SCSI adapter", 295 ahc_aha394XU_setup 296 }, 297 { 298 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2944 Ultra SCSI adapter", 301 ahc_aic7880_setup 302 }, 303 { 304 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 305 ID_DEV_VENDOR_MASK, 306 "Adaptec 3944 Ultra SCSI adapter", 307 ahc_aha394XU_setup 308 }, 309 { 310 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 311 ID_DEV_VENDOR_MASK, 312 "Adaptec 398X Ultra SCSI RAID adapter", 313 ahc_aha398XU_setup 314 }, 315 { 316 /* 317 * XXX Don't know the slot numbers 318 * so we can't identify channels 319 */ 320 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 321 ID_DEV_VENDOR_MASK, 322 "Adaptec 4944 Ultra SCSI adapter", 323 ahc_aic7880_setup 324 }, 325 { 326 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 327 ID_DEV_VENDOR_MASK, 328 "Adaptec 2930 Ultra SCSI adapter", 329 ahc_aic7880_setup 330 }, 331 { 332 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 333 ID_DEV_VENDOR_MASK, 334 "Adaptec 2940 Pro Ultra SCSI adapter", 335 ahc_aha2940Pro_setup 336 }, 337 { 338 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 339 ID_DEV_VENDOR_MASK, 340 "Adaptec 2940/CN Ultra SCSI adapter", 341 ahc_aic7880_setup 342 }, 343 /* aic7890 based controllers */ 344 { 345 ID_AHA_2930U2, 346 ID_ALL_MASK, 347 "Adaptec 2930 Ultra2 SCSI adapter", 348 ahc_aic7890_setup 349 }, 350 { 351 ID_AHA_2940U2B, 352 ID_ALL_MASK, 353 "Adaptec 2940B Ultra2 SCSI adapter", 354 ahc_aic7890_setup 355 }, 356 { 357 ID_AHA_2940U2_OEM, 358 ID_ALL_MASK, 359 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 360 ahc_aic7890_setup 361 }, 362 { 363 ID_AHA_2940U2, 364 ID_ALL_MASK, 365 "Adaptec 2940 Ultra2 SCSI adapter", 366 ahc_aic7890_setup 367 }, 368 { 369 ID_AHA_2950U2B, 370 ID_ALL_MASK, 371 "Adaptec 2950 Ultra2 SCSI adapter", 372 ahc_aic7890_setup 373 }, 374 { 375 ID_AAA_131U2, 376 ID_ALL_MASK, 377 "Adaptec AAA-131 Ultra2 RAID adapter", 378 ahc_aic7890_setup 379 }, 380 /* aic7892 based controllers */ 381 { 382 ID_AHA_29160, 383 ID_ALL_MASK, 384 "Adaptec 29160 Ultra160 SCSI adapter", 385 ahc_aic7892_setup 386 }, 387 { 388 ID_AHA_29160_CPQ, 389 ID_ALL_MASK, 390 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 391 ahc_aic7892_setup 392 }, 393 { 394 ID_AHA_29160N, 395 ID_ALL_MASK, 396 "Adaptec 29160N Ultra160 SCSI adapter", 397 ahc_aic7892_setup 398 }, 399 { 400 ID_AHA_29160C, 401 ID_ALL_MASK, 402 "Adaptec 29160C Ultra160 SCSI adapter", 403 ahc_aha29160C_setup 404 }, 405 { 406 ID_AHA_29160B, 407 ID_ALL_MASK, 408 "Adaptec 29160B Ultra160 SCSI adapter", 409 ahc_aic7892_setup 410 }, 411 { 412 ID_AHA_19160B, 413 ID_ALL_MASK, 414 "Adaptec 19160B Ultra160 SCSI adapter", 415 ahc_aic7892_setup 416 }, 417 /* aic7895 based controllers */ 418 { 419 ID_AHA_2940U_DUAL, 420 ID_ALL_MASK, 421 "Adaptec 2940/DUAL Ultra SCSI adapter", 422 ahc_aic7895_setup 423 }, 424 { 425 ID_AHA_3940AU, 426 ID_ALL_MASK, 427 "Adaptec 3940A Ultra SCSI adapter", 428 ahc_aic7895_setup 429 }, 430 { 431 ID_AHA_3944AU, 432 ID_ALL_MASK, 433 "Adaptec 3944A Ultra SCSI adapter", 434 ahc_aic7895_setup 435 }, 436 /* aic7896/97 based controllers */ 437 { 438 ID_AHA_3950U2B_0, 439 ID_ALL_MASK, 440 "Adaptec 3950B Ultra2 SCSI adapter", 441 ahc_aic7896_setup 442 }, 443 { 444 ID_AHA_3950U2B_1, 445 ID_ALL_MASK, 446 "Adaptec 3950B Ultra2 SCSI adapter", 447 ahc_aic7896_setup 448 }, 449 { 450 ID_AHA_3950U2D_0, 451 ID_ALL_MASK, 452 "Adaptec 3950D Ultra2 SCSI adapter", 453 ahc_aic7896_setup 454 }, 455 { 456 ID_AHA_3950U2D_1, 457 ID_ALL_MASK, 458 "Adaptec 3950D Ultra2 SCSI adapter", 459 ahc_aic7896_setup 460 }, 461 /* aic7899 based controllers */ 462 { 463 ID_AHA_3960D, 464 ID_ALL_MASK, 465 "Adaptec 3960D Ultra160 SCSI adapter", 466 ahc_aic7899_setup 467 }, 468 { 469 ID_AHA_3960D_CPQ, 470 ID_ALL_MASK, 471 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 472 ahc_aic7899_setup 473 }, 474 /* Generic chip probes for devices we don't know 'exactly' */ 475 { 476 ID_AIC7850 & ID_DEV_VENDOR_MASK, 477 ID_DEV_VENDOR_MASK, 478 "Adaptec aic7850 SCSI adapter", 479 ahc_aic7850_setup 480 }, 481 { 482 ID_AIC7855 & ID_DEV_VENDOR_MASK, 483 ID_DEV_VENDOR_MASK, 484 "Adaptec aic7855 SCSI adapter", 485 ahc_aic7855_setup 486 }, 487 { 488 ID_AIC7859 & ID_DEV_VENDOR_MASK, 489 ID_DEV_VENDOR_MASK, 490 "Adaptec aic7859 Ultra SCSI adapter", 491 ahc_aic7860_setup 492 }, 493 { 494 ID_AIC7860 & ID_DEV_VENDOR_MASK, 495 ID_DEV_VENDOR_MASK, 496 "Adaptec aic7860 SCSI adapter", 497 ahc_aic7860_setup 498 }, 499 { 500 ID_AIC7870 & ID_DEV_VENDOR_MASK, 501 ID_DEV_VENDOR_MASK, 502 "Adaptec aic7870 SCSI adapter", 503 ahc_aic7870_setup 504 }, 505 { 506 ID_AIC7880 & ID_DEV_VENDOR_MASK, 507 ID_DEV_VENDOR_MASK, 508 "Adaptec aic7880 Ultra SCSI adapter", 509 ahc_aic7880_setup 510 }, 511 { 512 ID_AIC7890 & ID_DEV_VENDOR_MASK, 513 ID_DEV_VENDOR_MASK, 514 "Adaptec aic7890/91 Ultra2 SCSI adapter", 515 ahc_aic7890_setup 516 }, 517 { 518 ID_AIC7892 & ID_DEV_VENDOR_MASK, 519 ID_DEV_VENDOR_MASK, 520 "Adaptec aic7892 Ultra160 SCSI adapter", 521 ahc_aic7892_setup 522 }, 523 { 524 ID_AIC7895 & ID_DEV_VENDOR_MASK, 525 ID_DEV_VENDOR_MASK, 526 "Adaptec aic7895 Ultra SCSI adapter", 527 ahc_aic7895_setup 528 }, 529 { 530 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 531 ID_DEV_VENDOR_MASK, 532 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 533 ahc_aic7895_setup 534 }, 535 { 536 ID_AIC7896 & ID_DEV_VENDOR_MASK, 537 ID_DEV_VENDOR_MASK, 538 "Adaptec aic7896/97 Ultra2 SCSI adapter", 539 ahc_aic7896_setup 540 }, 541 { 542 ID_AIC7899 & ID_DEV_VENDOR_MASK, 543 ID_DEV_VENDOR_MASK, 544 "Adaptec aic7899 Ultra160 SCSI adapter", 545 ahc_aic7899_setup 546 }, 547 { 548 ID_AIC7810 & ID_DEV_VENDOR_MASK, 549 ID_DEV_VENDOR_MASK, 550 "Adaptec aic7810 RAID memory controller", 551 ahc_raid_setup 552 }, 553 { 554 ID_AIC7815 & ID_DEV_VENDOR_MASK, 555 ID_DEV_VENDOR_MASK, 556 "Adaptec aic7815 RAID memory controller", 557 ahc_raid_setup 558 } 559}; 560 561const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 562 563#define AHC_394X_SLOT_CHANNEL_A 4 564#define AHC_394X_SLOT_CHANNEL_B 5 565 566#define AHC_398X_SLOT_CHANNEL_A 4 567#define AHC_398X_SLOT_CHANNEL_B 8 568#define AHC_398X_SLOT_CHANNEL_C 12 569 570#define AHC_494X_SLOT_CHANNEL_A 4 571#define AHC_494X_SLOT_CHANNEL_B 5 572#define AHC_494X_SLOT_CHANNEL_C 6 573#define AHC_494X_SLOT_CHANNEL_D 7 574 575#define DEVCONFIG 0x40 576#define SCBSIZE32 0x00010000ul /* aic789X only */ 577#define MPORTMODE 0x00000400ul /* aic7870 only */ 578#define RAMPSM 0x00000200ul /* aic7870 only */ 579#define VOLSENSE 0x00000100ul 580#define SCBRAMSEL 0x00000080ul 581#define MRDCEN 0x00000040ul 582#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 583#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 584#define BERREN 0x00000008ul 585#define DACEN 0x00000004ul 586#define STPWLEVEL 0x00000002ul 587#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 588 589#define CSIZE_LATTIME 0x0c 590#define CACHESIZE 0x0000003ful /* only 5 bits */ 591#define LATTIME 0x0000ff00ul 592 593typedef enum 594{ 595 AHC_POWER_STATE_D0, 596 AHC_POWER_STATE_D1, 597 AHC_POWER_STATE_D2, 598 AHC_POWER_STATE_D3 599} ahc_power_state; 600 601static void ahc_power_state_change(struct ahc_softc *ahc, 602 ahc_power_state new_state); 603static int ahc_ext_scbram_present(struct ahc_softc *ahc); 604static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 605 int pcheck, int fast, int large); 606static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 607static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 608static void configure_termination(struct ahc_softc *ahc, 609 struct seeprom_descriptor *sd, 610 u_int adapter_control, 611 u_int *sxfrctl1); 612 613static void ahc_new_term_detect(struct ahc_softc *ahc, 614 int *enableSEC_low, 615 int *enableSEC_high, 616 int *enablePRI_low, 617 int *enablePRI_high, 618 int *eeprom_present); 619static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 620 int *internal68_present, 621 int *externalcable_present, 622 int *eeprom_present); 623static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 624 int *externalcable_present, 625 int *eeprom_present); 626static int acquire_seeprom(struct ahc_softc *ahc, 627 struct seeprom_descriptor *sd); 628static void release_seeprom(struct seeprom_descriptor *sd); 629static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 630static uint8_t read_brdctl(struct ahc_softc *ahc); 631 632struct ahc_pci_identity * 633ahc_find_pci_device(ahc_dev_softc_t pci) 634{ 635 uint64_t full_id; 636 uint16_t device; 637 uint16_t vendor; 638 uint16_t subdevice; 639 uint16_t subvendor; 640 struct ahc_pci_identity *entry; 641 u_int i; 642 643 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 644 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 645 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 646 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 647 full_id = ahc_compose_id(device, 648 vendor, 649 subdevice, 650 subvendor); 651 652 /* If the second function is not hooked up, ignore it. */ 653 if (ahc_get_pci_function(pci) > 0 654 && subvendor == 0x9005 655 && SUBID_9005_MFUNCENB(subdevice) == 0) 656 return (NULL); 657 658 for (i = 0; i < ahc_num_pci_devs; i++) { 659 entry = &ahc_pci_ident_table[i]; 660 if (entry->full_id == (full_id & entry->id_mask)) 661 return (entry); 662 } 663 return (NULL); 664} 665 666int 667ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 668{ 669 struct ahc_probe_config probe_config; 670 struct scb_data *shared_scb_data; 671 u_int command; 672 u_int our_id = 0; 673 u_int sxfrctl1; 674 u_int scsiseq; 675 u_int dscommand0; 676 int error; 677 uint8_t sblkctl; 678 679 shared_scb_data = NULL; 680 ahc_init_probe_config(&probe_config); 681 error = entry->setup(ahc->dev_softc, &probe_config); 682 if (error != 0) 683 return (error); 684 probe_config.chip |= AHC_PCI; 685 probe_config.description = entry->name; 686 687 error = ahc_pci_map_registers(ahc); 688 if (error != 0) 689 return (error); 690 691 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 692 693 /* Ensure busmastering is enabled */ 694 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 695 command |= PCIM_CMD_BUSMASTEREN; 696 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 697 698 /* On all PCI adapters, we allow SCB paging */ 699 probe_config.flags |= AHC_PAGESCBS; 700 701 error = ahc_softc_init(ahc, &probe_config); 702 if (error != 0) 703 return (error); 704 705 /* Remeber how the card was setup in case there is no SEEPROM */ 706 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 707 pause_sequencer(ahc); 708 if ((ahc->features & AHC_ULTRA2) != 0) 709 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 710 else 711 our_id = ahc_inb(ahc, SCSIID) & OID; 712 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 713 scsiseq = ahc_inb(ahc, SCSISEQ); 714 } else { 715 sxfrctl1 = STPWEN; 716 our_id = 7; 717 scsiseq = 0; 718 } 719 720 error = ahc_reset(ahc); 721 if (error != 0) 722 return (ENXIO); 723 724 if ((ahc->features & AHC_DT) != 0) { 725 u_int sfunct; 726 727 /* Perform ALT-Mode Setup */ 728 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 729 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 730 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 731 ahc_outb(ahc, SFUNCT, sfunct); 732 733 /* Normal mode setup */ 734 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 735 |TARGCRCENDEN); 736 } 737 738 error = ahc_pci_map_int(ahc); 739 if (error != 0) 740 return (error); 741 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 742 dscommand0 |= MPARCKEN|CACHETHEN; 743 if ((ahc->features & AHC_ULTRA2) != 0) { 744 745 /* 746 * DPARCKEN doesn't work correctly on 747 * some MBs so don't use it. 748 */ 749 dscommand0 &= ~DPARCKEN; 750 } 751 752 /* 753 * Handle chips that must have cache line 754 * streaming (dis/en)abled. 755 */ 756 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 757 dscommand0 |= CACHETHEN; 758 759 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 760 dscommand0 &= ~CACHETHEN; 761 762 ahc_outb(ahc, DSCOMMAND0, dscommand0); 763 764 ahc->pci_cachesize = 765 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 766 /*bytes*/1) & CACHESIZE; 767 ahc->pci_cachesize *= 4; 768 769 /* See if we have a SEEPROM and perform auto-term */ 770 check_extport(ahc, &sxfrctl1); 771 772 /* 773 * Take the LED out of diagnostic mode 774 */ 775 sblkctl = ahc_inb(ahc, SBLKCTL); 776 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 777 778 if ((ahc->features & AHC_ULTRA2) != 0) { 779 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 780 } else { 781 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 782 } 783 784 if (ahc->flags & AHC_USEDEFAULTS) { 785 /* 786 * PCI Adapter default setup 787 * Should only be used if the adapter does not have 788 * a SEEPROM. 789 */ 790 /* See if someone else set us up already */ 791 if (scsiseq != 0) { 792 printf("%s: Using left over BIOS settings\n", 793 ahc_name(ahc)); 794 ahc->flags &= ~AHC_USEDEFAULTS; 795 } else { 796 /* 797 * Assume only one connector and always turn 798 * on termination. 799 */ 800 our_id = 0x07; 801 sxfrctl1 = STPWEN; 802 } 803 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 804 805 ahc->our_id = our_id; 806 } 807 808 /* 809 * Take a look to see if we have external SRAM. 810 * We currently do not attempt to use SRAM that is 811 * shared among multiple controllers. 812 */ 813 ahc_probe_ext_scbram(ahc); 814 815 /* 816 * Record our termination setting for the 817 * generic initialization routine. 818 */ 819 if ((sxfrctl1 & STPWEN) != 0) 820 ahc->flags |= AHC_TERM_ENB_A; 821 822 /* Core initialization */ 823 error = ahc_init(ahc); 824 if (error != 0) 825 return (error); 826 827 /* 828 * Link this softc in with all other ahc instances. 829 */ 830 ahc_softc_insert(ahc); 831 832 return (0); 833} 834 835static void 836ahc_power_state_change(struct ahc_softc *ahc, ahc_power_state new_state) 837{ 838 uint32_t cap; 839 u_int cap_offset; 840 841 /* 842 * Traverse the capability list looking for 843 * the power management capability. 844 */ 845 cap = 0; 846 cap_offset = ahc_pci_read_config(ahc->dev_softc, 847 PCIR_CAP_PTR, /*bytes*/1); 848 while (cap_offset != 0) { 849 850 cap = ahc_pci_read_config(ahc->dev_softc, 851 cap_offset, /*bytes*/4); 852 if ((cap & 0xFF) == 1 853 && ((cap >> 16) & 0x3) > 0) { 854 uint32_t pm_control; 855 856 pm_control = ahc_pci_read_config(ahc->dev_softc, 857 cap_offset + 4, 858 /*bytes*/4); 859 pm_control &= ~0x3; 860 pm_control |= new_state; 861 ahc_pci_write_config(ahc->dev_softc, 862 cap_offset + 4, 863 pm_control, /*bytes*/2); 864 break; 865 } 866 cap_offset = (cap >> 8) & 0xFF; 867 } 868} 869 870/* 871 * Test for the presense of external sram in an 872 * "unshared" configuration. 873 */ 874static int 875ahc_ext_scbram_present(struct ahc_softc *ahc) 876{ 877 u_int chip; 878 int ramps; 879 int single_user; 880 uint32_t devconfig; 881 882 chip = ahc->chip & AHC_CHIPID_MASK; 883 devconfig = ahc_pci_read_config(ahc->dev_softc, 884 DEVCONFIG, /*bytes*/4); 885 single_user = (devconfig & MPORTMODE) != 0; 886 887 if ((ahc->features & AHC_ULTRA2) != 0) 888 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 889 else if (chip >= AHC_AIC7870) 890 ramps = (devconfig & RAMPSM) != 0; 891 else 892 ramps = 0; 893 894 if (ramps && single_user) 895 return (1); 896 return (0); 897} 898 899/* 900 * Enable external scbram. 901 */ 902static void 903ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 904 int fast, int large) 905{ 906 uint32_t devconfig; 907 908 if (ahc->features & AHC_MULTI_FUNC) { 909 /* 910 * Set the SCB Base addr (highest address bit) 911 * depending on which channel we are. 912 */ 913 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 914 } 915 916 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 917 if ((ahc->features & AHC_ULTRA2) != 0) { 918 u_int dscommand0; 919 920 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 921 if (enable) 922 dscommand0 &= ~INTSCBRAMSEL; 923 else 924 dscommand0 |= INTSCBRAMSEL; 925 if (large) 926 dscommand0 &= ~USCBSIZE32; 927 else 928 dscommand0 |= USCBSIZE32; 929 ahc_outb(ahc, DSCOMMAND0, dscommand0); 930 } else { 931 if (fast) 932 devconfig &= ~EXTSCBTIME; 933 else 934 devconfig |= EXTSCBTIME; 935 if (enable) 936 devconfig &= ~SCBRAMSEL; 937 else 938 devconfig |= SCBRAMSEL; 939 if (large) 940 devconfig &= ~SCBSIZE32; 941 else 942 devconfig |= SCBSIZE32; 943 } 944 if (pcheck) 945 devconfig |= EXTSCBPEN; 946 else 947 devconfig &= ~EXTSCBPEN; 948 949 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 950} 951 952/* 953 * Take a look to see if we have external SRAM. 954 * We currently do not attempt to use SRAM that is 955 * shared among multiple controllers. 956 */ 957static void 958ahc_probe_ext_scbram(struct ahc_softc *ahc) 959{ 960 int num_scbs; 961 int test_num_scbs; 962 int enable; 963 int pcheck; 964 int fast; 965 int large; 966 967 enable = FALSE; 968 pcheck = FALSE; 969 fast = FALSE; 970 large = FALSE; 971 num_scbs = 0; 972 973 if (ahc_ext_scbram_present(ahc) == 0) 974 goto done; 975 976 /* 977 * Probe for the best parameters to use. 978 */ 979 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 980 num_scbs = ahc_probe_scbs(ahc); 981 if (num_scbs == 0) { 982 /* The SRAM wasn't really present. */ 983 goto done; 984 } 985 enable = TRUE; 986 987 /* 988 * Clear any outstanding parity error 989 * and ensure that parity error reporting 990 * is enabled. 991 */ 992 ahc_outb(ahc, SEQCTL, 0); 993 ahc_outb(ahc, CLRINT, CLRPARERR); 994 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 995 996 /* Now see if we can do parity */ 997 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 998 num_scbs = ahc_probe_scbs(ahc); 999 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1000 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1001 pcheck = TRUE; 1002 1003 /* Clear any resulting parity error */ 1004 ahc_outb(ahc, CLRINT, CLRPARERR); 1005 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1006 1007 /* Now see if we can do fast timing */ 1008 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1009 test_num_scbs = ahc_probe_scbs(ahc); 1010 if (test_num_scbs == num_scbs 1011 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1012 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1013 fast = TRUE; 1014 1015 /* 1016 * See if we can use large SCBs and still maintain 1017 * the same overall count of SCBs. 1018 */ 1019 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1020 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1021 test_num_scbs = ahc_probe_scbs(ahc); 1022 if (test_num_scbs >= num_scbs) { 1023 large = TRUE; 1024 num_scbs = test_num_scbs; 1025 if (num_scbs >= 64) { 1026 /* 1027 * We have enough space to move the 1028 * "busy targets table" into SCB space 1029 * and make it qualify all the way to the 1030 * lun level. 1031 */ 1032 ahc->flags |= AHC_SCB_BTT; 1033 } 1034 } 1035 } 1036done: 1037 /* 1038 * Disable parity error reporting until we 1039 * can load instruction ram. 1040 */ 1041 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1042 /* Clear any latched parity error */ 1043 ahc_outb(ahc, CLRINT, CLRPARERR); 1044 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1045 if (bootverbose && enable) { 1046 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1047 ahc_name(ahc), fast ? "fast" : "slow", 1048 pcheck ? ", parity checking enabled" : "", 1049 large ? 64 : 32); 1050 } 1051 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1052} 1053 1054/* 1055 * Check the external port logic for a serial eeprom 1056 * and termination/cable detection contrls. 1057 */ 1058static void 1059check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1060{ 1061 struct seeprom_descriptor sd; 1062 struct seeprom_config sc; 1063 u_int scsi_conf; 1064 u_int adapter_control; 1065 int have_seeprom; 1066 int have_autoterm; 1067 1068 sd.sd_ahc = ahc; 1069 sd.sd_control_offset = SEECTL; 1070 sd.sd_status_offset = SEECTL; 1071 sd.sd_dataout_offset = SEECTL; 1072 1073 /* 1074 * For some multi-channel devices, the c46 is simply too 1075 * small to work. For the other controller types, we can 1076 * get our information from either SEEPROM type. Set the 1077 * type to start our probe with accordingly. 1078 */ 1079 if (ahc->flags & AHC_LARGE_SEEPROM) 1080 sd.sd_chip = C56_66; 1081 else 1082 sd.sd_chip = C46; 1083 1084 sd.sd_MS = SEEMS; 1085 sd.sd_RDY = SEERDY; 1086 sd.sd_CS = SEECS; 1087 sd.sd_CK = SEECK; 1088 sd.sd_DO = SEEDO; 1089 sd.sd_DI = SEEDI; 1090 1091 have_seeprom = acquire_seeprom(ahc, &sd); 1092 if (have_seeprom) { 1093 1094 if (bootverbose) 1095 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1096 1097 for (;;) { 1098 u_int start_addr; 1099 1100 start_addr = 32 * (ahc->channel - 'A'); 1101 1102 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 1103 start_addr, sizeof(sc)/2); 1104 1105 if (have_seeprom) 1106 have_seeprom = verify_cksum(&sc); 1107 1108 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1109 if (bootverbose) { 1110 if (have_seeprom == 0) 1111 printf ("checksum error\n"); 1112 else 1113 printf ("done.\n"); 1114 } 1115 break; 1116 } 1117 sd.sd_chip = C56_66; 1118 } 1119 } 1120 1121#if 0 1122 if (!have_seeprom) { 1123 /* 1124 * Pull scratch ram settings and treat them as 1125 * if they are the contents of an seeprom if 1126 * the 'ADPT' signature is found in SCB2. 1127 */ 1128 ahc_outb(ahc, SCBPTR, 2); 1129 if (ahc_inb(ahc, SCB_BASE) == 'A' 1130 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1131 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1132 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1133 uint8_t *sc_bytes; 1134 int i; 1135 1136 sc_bytes = (uint8_t *)≻ 1137 for (i = 0; i < 64; i++) 1138 sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i); 1139 /* Byte 0x1c is stored in byte 4 of SCB2 */ 1140 sc_bytes[0x1c] = ahc_inb(ahc, SCB_BASE + 4); 1141 have_seeprom = verify_cksum(&sc); 1142 } 1143 } 1144#endif 1145 1146 if (!have_seeprom) { 1147 if (bootverbose) 1148 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1149 ahc->flags |= AHC_USEDEFAULTS; 1150 } else { 1151 /* 1152 * Put the data we've collected down into SRAM 1153 * where ahc_init will find it. 1154 */ 1155 int i; 1156 int max_targ = sc.max_targets & CFMAXTARG; 1157 uint16_t discenable; 1158 uint16_t ultraenb; 1159 1160 discenable = 0; 1161 ultraenb = 0; 1162 if ((sc.adapter_control & CFULTRAEN) != 0) { 1163 /* 1164 * Determine if this adapter has a "newstyle" 1165 * SEEPROM format. 1166 */ 1167 for (i = 0; i < max_targ; i++) { 1168 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1169 ahc->flags |= AHC_NEWEEPROM_FMT; 1170 break; 1171 } 1172 } 1173 } 1174 1175 for (i = 0; i < max_targ; i++) { 1176 u_int scsirate; 1177 uint16_t target_mask; 1178 1179 target_mask = 0x01 << i; 1180 if (sc.device_flags[i] & CFDISC) 1181 discenable |= target_mask; 1182 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1183 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1184 ultraenb |= target_mask; 1185 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1186 ultraenb |= target_mask; 1187 } 1188 if ((sc.device_flags[i] & CFXFER) == 0x04 1189 && (ultraenb & target_mask) != 0) { 1190 /* Treat 10MHz as a non-ultra speed */ 1191 sc.device_flags[i] &= ~CFXFER; 1192 ultraenb &= ~target_mask; 1193 } 1194 if ((ahc->features & AHC_ULTRA2) != 0) { 1195 u_int offset; 1196 1197 if (sc.device_flags[i] & CFSYNCH) 1198 offset = MAX_OFFSET_ULTRA2; 1199 else 1200 offset = 0; 1201 ahc_outb(ahc, TARG_OFFSET + i, offset); 1202 1203 /* 1204 * The ultra enable bits contain the 1205 * high bit of the ultra2 sync rate 1206 * field. 1207 */ 1208 scsirate = (sc.device_flags[i] & CFXFER) 1209 | ((ultraenb & target_mask) 1210 ? 0x8 : 0x0); 1211 if (sc.device_flags[i] & CFWIDEB) 1212 scsirate |= WIDEXFER; 1213 } else { 1214 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1215 if (sc.device_flags[i] & CFSYNCH) 1216 scsirate |= SOFS; 1217 if (sc.device_flags[i] & CFWIDEB) 1218 scsirate |= WIDEXFER; 1219 } 1220 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1221 } 1222 ahc->our_id = sc.brtime_id & CFSCSIID; 1223 1224 scsi_conf = (ahc->our_id & 0x7); 1225 if (sc.adapter_control & CFSPARITY) 1226 scsi_conf |= ENSPCHK; 1227 if (sc.adapter_control & CFRESETB) 1228 scsi_conf |= RESET_SCSI; 1229 1230 if (sc.bios_control & CFEXTEND) 1231 ahc->flags |= AHC_EXTENDED_TRANS_A; 1232 if (ahc->features & AHC_ULTRA 1233 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1234 /* Should we enable Ultra mode? */ 1235 if (!(sc.adapter_control & CFULTRAEN)) 1236 /* Treat us as a non-ultra card */ 1237 ultraenb = 0; 1238 } 1239 1240 if (sc.signature == CFSIGNATURE) { 1241 uint32_t devconfig; 1242 1243 /* Honor the STPWLEVEL settings */ 1244 devconfig = ahc_pci_read_config(ahc->dev_softc, 1245 DEVCONFIG, /*bytes*/4); 1246 devconfig &= ~STPWLEVEL; 1247 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1248 devconfig |= STPWLEVEL; 1249 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1250 devconfig, /*bytes*/4); 1251 } 1252 /* Set SCSICONF info */ 1253 ahc_outb(ahc, SCSICONF, scsi_conf); 1254 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1255 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1256 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1257 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1258 } 1259 1260 /* 1261 * Cards that have the external logic necessary to talk to 1262 * a SEEPROM, are almost certain to have the remaining logic 1263 * necessary for auto-termination control. This assumption 1264 * hasn't failed yet... 1265 */ 1266 have_autoterm = have_seeprom; 1267 if (have_seeprom) 1268 adapter_control = sc.adapter_control; 1269 else 1270 adapter_control = CFAUTOTERM; 1271 1272 /* 1273 * Some low-cost chips have SEEPROM and auto-term control built 1274 * in, instead of using a GAL. They can tell us directly 1275 * if the termination logic is enabled. 1276 */ 1277 if ((ahc->features & AHC_SPIOCAP) != 0) { 1278 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1279 have_autoterm = TRUE; 1280 else 1281 have_autoterm = FALSE; 1282 } 1283 1284 if (have_autoterm) 1285 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1286 1287 release_seeprom(&sd); 1288} 1289 1290static void 1291configure_termination(struct ahc_softc *ahc, 1292 struct seeprom_descriptor *sd, 1293 u_int adapter_control, 1294 u_int *sxfrctl1) 1295{ 1296 uint8_t brddat; 1297 1298 brddat = 0; 1299 1300 /* 1301 * Update the settings in sxfrctl1 to match the 1302 * termination settings 1303 */ 1304 *sxfrctl1 = 0; 1305 1306 /* 1307 * SEECS must be on for the GALS to latch 1308 * the data properly. Be sure to leave MS 1309 * on or we will release the seeprom. 1310 */ 1311 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1312 if ((adapter_control & CFAUTOTERM) != 0 1313 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1314 int internal50_present; 1315 int internal68_present; 1316 int externalcable_present; 1317 int eeprom_present; 1318 int enableSEC_low; 1319 int enableSEC_high; 1320 int enablePRI_low; 1321 int enablePRI_high; 1322 int sum; 1323 1324 enableSEC_low = 0; 1325 enableSEC_high = 0; 1326 enablePRI_low = 0; 1327 enablePRI_high = 0; 1328 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1329 ahc_new_term_detect(ahc, &enableSEC_low, 1330 &enableSEC_high, 1331 &enablePRI_low, 1332 &enablePRI_high, 1333 &eeprom_present); 1334 if ((adapter_control & CFSEAUTOTERM) == 0) { 1335 if (bootverbose) 1336 printf("%s: Manual SE Termination\n", 1337 ahc_name(ahc)); 1338 enableSEC_low = (adapter_control & CFSELOWTERM); 1339 enableSEC_high = 1340 (adapter_control & CFSEHIGHTERM); 1341 } 1342 if ((adapter_control & CFAUTOTERM) == 0) { 1343 if (bootverbose) 1344 printf("%s: Manual LVD Termination\n", 1345 ahc_name(ahc)); 1346 enablePRI_low = (adapter_control & CFSTERM); 1347 enablePRI_high = (adapter_control & CFWSTERM); 1348 } 1349 /* Make the table calculations below happy */ 1350 internal50_present = 0; 1351 internal68_present = 1; 1352 externalcable_present = 1; 1353 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1354 aic785X_cable_detect(ahc, &internal50_present, 1355 &externalcable_present, 1356 &eeprom_present); 1357 } else { 1358 aic787X_cable_detect(ahc, &internal50_present, 1359 &internal68_present, 1360 &externalcable_present, 1361 &eeprom_present); 1362 } 1363 1364 if ((ahc->features & AHC_WIDE) == 0) 1365 internal68_present = 0; 1366 1367 if (bootverbose 1368 && (ahc->features & AHC_ULTRA2) == 0) { 1369 printf("%s: internal 50 cable %s present", 1370 ahc_name(ahc), 1371 internal50_present ? "is":"not"); 1372 1373 if ((ahc->features & AHC_WIDE) != 0) 1374 printf(", internal 68 cable %s present", 1375 internal68_present ? "is":"not"); 1376 printf("\n%s: external cable %s present\n", 1377 ahc_name(ahc), 1378 externalcable_present ? "is":"not"); 1379 } 1380 if (bootverbose) 1381 printf("%s: BIOS eeprom %s present\n", 1382 ahc_name(ahc), eeprom_present ? "is" : "not"); 1383 1384 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1385 /* 1386 * The 50 pin connector is a separate bus, 1387 * so force it to always be terminated. 1388 * In the future, perform current sensing 1389 * to determine if we are in the middle of 1390 * a properly terminated bus. 1391 */ 1392 internal50_present = 0; 1393 } 1394 1395 /* 1396 * Now set the termination based on what 1397 * we found. 1398 * Flash Enable = BRDDAT7 1399 * Secondary High Term Enable = BRDDAT6 1400 * Secondary Low Term Enable = BRDDAT5 (7890) 1401 * Primary High Term Enable = BRDDAT4 (7890) 1402 */ 1403 if ((ahc->features & AHC_ULTRA2) == 0 1404 && (internal50_present != 0) 1405 && (internal68_present != 0) 1406 && (externalcable_present != 0)) { 1407 printf("%s: Illegal cable configuration!!. " 1408 "Only two connectors on the " 1409 "adapter may be used at a " 1410 "time!\n", ahc_name(ahc)); 1411 } 1412 1413 if ((ahc->features & AHC_WIDE) != 0 1414 && ((externalcable_present == 0) 1415 || (internal68_present == 0) 1416 || (enableSEC_high != 0))) { 1417 brddat |= BRDDAT6; 1418 if (bootverbose) { 1419 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1420 printf("%s: 68 pin termination " 1421 "Enabled\n", ahc_name(ahc)); 1422 else 1423 printf("%s: %sHigh byte termination " 1424 "Enabled\n", ahc_name(ahc), 1425 enableSEC_high ? "Secondary " 1426 : ""); 1427 } 1428 } 1429 1430 sum = internal50_present + internal68_present 1431 + externalcable_present; 1432 if (sum < 2 || (enableSEC_low != 0)) { 1433 if ((ahc->features & AHC_ULTRA2) != 0) 1434 brddat |= BRDDAT5; 1435 else 1436 *sxfrctl1 |= STPWEN; 1437 if (bootverbose) { 1438 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1439 printf("%s: 50 pin termination " 1440 "Enabled\n", ahc_name(ahc)); 1441 else 1442 printf("%s: %sLow byte termination " 1443 "Enabled\n", ahc_name(ahc), 1444 enableSEC_low ? "Secondary " 1445 : ""); 1446 } 1447 } 1448 1449 if (enablePRI_low != 0) { 1450 *sxfrctl1 |= STPWEN; 1451 if (bootverbose) 1452 printf("%s: Primary Low Byte termination " 1453 "Enabled\n", ahc_name(ahc)); 1454 } 1455 1456 /* 1457 * Setup STPWEN before setting up the rest of 1458 * the termination per the tech note on the U160 cards. 1459 */ 1460 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1461 1462 if (enablePRI_high != 0) { 1463 brddat |= BRDDAT4; 1464 if (bootverbose) 1465 printf("%s: Primary High Byte " 1466 "termination Enabled\n", 1467 ahc_name(ahc)); 1468 } 1469 1470 write_brdctl(ahc, brddat); 1471 1472 } else { 1473 if ((adapter_control & CFSTERM) != 0) { 1474 *sxfrctl1 |= STPWEN; 1475 1476 if (bootverbose) 1477 printf("%s: %sLow byte termination Enabled\n", 1478 ahc_name(ahc), 1479 (ahc->features & AHC_ULTRA2) ? "Primary " 1480 : ""); 1481 } 1482 1483 if ((adapter_control & CFWSTERM) != 0 1484 && (ahc->features & AHC_WIDE) != 0) { 1485 brddat |= BRDDAT6; 1486 if (bootverbose) 1487 printf("%s: %sHigh byte termination Enabled\n", 1488 ahc_name(ahc), 1489 (ahc->features & AHC_ULTRA2) 1490 ? "Secondary " : ""); 1491 } 1492 1493 /* 1494 * Setup STPWEN before setting up the rest of 1495 * the termination per the tech note on the U160 cards. 1496 */ 1497 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1498 1499 if ((ahc->features & AHC_WIDE) != 0) 1500 write_brdctl(ahc, brddat); 1501 } 1502 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1503} 1504 1505static void 1506ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1507 int *enableSEC_high, int *enablePRI_low, 1508 int *enablePRI_high, int *eeprom_present) 1509{ 1510 uint8_t brdctl; 1511 1512 /* 1513 * BRDDAT7 = Eeprom 1514 * BRDDAT6 = Enable Secondary High Byte termination 1515 * BRDDAT5 = Enable Secondary Low Byte termination 1516 * BRDDAT4 = Enable Primary high byte termination 1517 * BRDDAT3 = Enable Primary low byte termination 1518 */ 1519 brdctl = read_brdctl(ahc); 1520 *eeprom_present = brdctl & BRDDAT7; 1521 *enableSEC_high = (brdctl & BRDDAT6); 1522 *enableSEC_low = (brdctl & BRDDAT5); 1523 *enablePRI_high = (brdctl & BRDDAT4); 1524 *enablePRI_low = (brdctl & BRDDAT3); 1525} 1526 1527static void 1528aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1529 int *internal68_present, int *externalcable_present, 1530 int *eeprom_present) 1531{ 1532 uint8_t brdctl; 1533 1534 /* 1535 * First read the status of our cables. 1536 * Set the rom bank to 0 since the 1537 * bank setting serves as a multiplexor 1538 * for the cable detection logic. 1539 * BRDDAT5 controls the bank switch. 1540 */ 1541 write_brdctl(ahc, 0); 1542 1543 /* 1544 * Now read the state of the internal 1545 * connectors. BRDDAT6 is INT50 and 1546 * BRDDAT7 is INT68. 1547 */ 1548 brdctl = read_brdctl(ahc); 1549 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1550 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1551 1552 /* 1553 * Set the rom bank to 1 and determine 1554 * the other signals. 1555 */ 1556 write_brdctl(ahc, BRDDAT5); 1557 1558 /* 1559 * Now read the state of the external 1560 * connectors. BRDDAT6 is EXT68 and 1561 * BRDDAT7 is EPROMPS. 1562 */ 1563 brdctl = read_brdctl(ahc); 1564 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1565 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1566} 1567 1568static void 1569aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1570 int *externalcable_present, int *eeprom_present) 1571{ 1572 uint8_t brdctl; 1573 1574 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1575 ahc_outb(ahc, BRDCTL, 0); 1576 brdctl = ahc_inb(ahc, BRDCTL); 1577 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1578 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1579 1580 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1581} 1582 1583static int 1584acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1585{ 1586 int wait; 1587 1588 if ((ahc->features & AHC_SPIOCAP) != 0 1589 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1590 return (0); 1591 1592 /* 1593 * Request access of the memory port. When access is 1594 * granted, SEERDY will go high. We use a 1 second 1595 * timeout which should be near 1 second more than 1596 * is needed. Reason: after the chip reset, there 1597 * should be no contention. 1598 */ 1599 SEEPROM_OUTB(sd, sd->sd_MS); 1600 wait = 1000; /* 1 second timeout in msec */ 1601 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1602 ahc_delay(1000); /* delay 1 msec */ 1603 } 1604 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1605 SEEPROM_OUTB(sd, 0); 1606 return (0); 1607 } 1608 return(1); 1609} 1610 1611static void 1612release_seeprom(struct seeprom_descriptor *sd) 1613{ 1614 /* Release access to the memory port and the serial EEPROM. */ 1615 SEEPROM_OUTB(sd, 0); 1616} 1617 1618static void 1619write_brdctl(struct ahc_softc *ahc, uint8_t value) 1620{ 1621 uint8_t brdctl; 1622 1623 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1624 brdctl = BRDSTB; 1625 if (ahc->channel == 'B') 1626 brdctl |= BRDCS; 1627 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1628 brdctl = 0; 1629 } else { 1630 brdctl = BRDSTB|BRDCS; 1631 } 1632 ahc_outb(ahc, BRDCTL, brdctl); 1633 ahc_flush_device_writes(ahc); 1634 brdctl |= value; 1635 ahc_outb(ahc, BRDCTL, brdctl); 1636 ahc_flush_device_writes(ahc); 1637 if ((ahc->features & AHC_ULTRA2) != 0) 1638 brdctl |= BRDSTB_ULTRA2; 1639 else 1640 brdctl &= ~BRDSTB; 1641 ahc_outb(ahc, BRDCTL, brdctl); 1642 ahc_flush_device_writes(ahc); 1643 if ((ahc->features & AHC_ULTRA2) != 0) 1644 brdctl = 0; 1645 else 1646 brdctl &= ~BRDCS; 1647 ahc_outb(ahc, BRDCTL, brdctl); 1648} 1649 1650static uint8_t 1651read_brdctl(ahc) 1652 struct ahc_softc *ahc; 1653{ 1654 uint8_t brdctl; 1655 uint8_t value; 1656 1657 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1658 brdctl = BRDRW; 1659 if (ahc->channel == 'B') 1660 brdctl |= BRDCS; 1661 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1662 brdctl = BRDRW_ULTRA2; 1663 } else { 1664 brdctl = BRDRW|BRDCS; 1665 } 1666 ahc_outb(ahc, BRDCTL, brdctl); 1667 ahc_flush_device_writes(ahc); 1668 value = ahc_inb(ahc, BRDCTL); 1669 ahc_outb(ahc, BRDCTL, 0); 1670 return (value); 1671} 1672 1673#define DPE 0x80 1674#define SSE 0x40 1675#define RMA 0x20 1676#define RTA 0x10 1677#define STA 0x08 1678#define DPR 0x01 1679 1680void 1681ahc_pci_intr(struct ahc_softc *ahc) 1682{ 1683 u_int error; 1684 u_int status1; 1685 1686 error = ahc_inb(ahc, ERROR); 1687 if ((error & PCIERRSTAT) == 0) 1688 return; 1689 1690 status1 = ahc_pci_read_config(ahc->dev_softc, 1691 PCIR_STATUS + 1, /*bytes*/1); 1692 1693 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1694 ahc_name(ahc), 1695 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1696 1697 if (status1 & DPE) { 1698 printf("%s: Data Parity Error Detected during address " 1699 "or write data phase\n", ahc_name(ahc)); 1700 } 1701 if (status1 & SSE) { 1702 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1703 } 1704 if (status1 & RMA) { 1705 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1706 } 1707 if (status1 & RTA) { 1708 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1709 } 1710 if (status1 & STA) { 1711 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1712 } 1713 if (status1 & DPR) { 1714 printf("%s: Data Parity Error has been reported via PERR#\n", 1715 ahc_name(ahc)); 1716 } 1717 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1718 printf("%s: Latched PCIERR interrupt with " 1719 "no status bits set\n", ahc_name(ahc)); 1720 } 1721 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1722 status1, /*bytes*/1); 1723 1724 if (status1 & (DPR|RMA|RTA)) { 1725 ahc_outb(ahc, CLRINT, CLRPARERR); 1726 } 1727 1728 unpause_sequencer(ahc); 1729} 1730 1731static int 1732ahc_aic7850_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1733{ 1734 probe_config->channel = 'A'; 1735 probe_config->chip = AHC_AIC7850; 1736 probe_config->features = AHC_AIC7850_FE; 1737 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1738 | AHC_PCI_MWI_BUG; 1739 return (0); 1740} 1741 1742static int 1743ahc_aic7855_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1744{ 1745 probe_config->channel = 'A'; 1746 probe_config->chip = AHC_AIC7855; 1747 probe_config->features = AHC_AIC7855_FE; 1748 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1749 | AHC_PCI_MWI_BUG; 1750 return (0); 1751} 1752 1753static int 1754ahc_aic7860_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1755{ 1756 uint8_t rev; 1757 1758 probe_config->channel = 'A'; 1759 probe_config->chip = AHC_AIC7860; 1760 probe_config->features = AHC_AIC7860_FE; 1761 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1762 | AHC_PCI_MWI_BUG; 1763 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1764 if (rev >= 1) 1765 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1766 return (0); 1767} 1768 1769static int 1770ahc_apa1480_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1771{ 1772 int error; 1773 1774 error = ahc_aic7860_setup(pci, probe_config); 1775 if (error != 0) 1776 return (error); 1777 probe_config->features |= AHC_REMOVABLE; 1778 return (0); 1779} 1780 1781static int 1782ahc_aic7870_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1783{ 1784 probe_config->channel = 'A'; 1785 probe_config->chip = AHC_AIC7870; 1786 probe_config->features = AHC_AIC7870_FE; 1787 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG 1788 | AHC_PCI_MWI_BUG; 1789 return (0); 1790} 1791 1792static int 1793ahc_aha394X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1794{ 1795 int error; 1796 1797 error = ahc_aic7870_setup(pci, probe_config); 1798 if (error == 0) 1799 error = ahc_aha394XX_setup(pci, probe_config); 1800 return (error); 1801} 1802 1803static int 1804ahc_aha398X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1805{ 1806 int error; 1807 1808 error = ahc_aic7870_setup(pci, probe_config); 1809 if (error == 0) 1810 error = ahc_aha398XX_setup(pci, probe_config); 1811 return (error); 1812} 1813 1814static int 1815ahc_aha494X_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1816{ 1817 int error; 1818 1819 error = ahc_aic7870_setup(pci, probe_config); 1820 if (error == 0) 1821 error = ahc_aha494XX_setup(pci, probe_config); 1822 return (error); 1823} 1824 1825static int 1826ahc_aic7880_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1827{ 1828 uint8_t rev; 1829 1830 probe_config->channel = 'A'; 1831 probe_config->chip = AHC_AIC7880; 1832 probe_config->features = AHC_AIC7880_FE; 1833 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1834 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1835 if (rev >= 1) { 1836 probe_config->bugs |= AHC_PCI_2_1_RETRY_BUG; 1837 } else { 1838 probe_config->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1839 } 1840 return (0); 1841} 1842 1843static int 1844ahc_aha2940Pro_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1845{ 1846 int error; 1847 1848 probe_config->flags |= AHC_INT50_SPEEDFLEX; 1849 error = ahc_aic7880_setup(pci, probe_config); 1850 return (0); 1851} 1852 1853static int 1854ahc_aha394XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1855{ 1856 int error; 1857 1858 error = ahc_aic7880_setup(pci, probe_config); 1859 if (error == 0) 1860 error = ahc_aha394XX_setup(pci, probe_config); 1861 return (error); 1862} 1863 1864static int 1865ahc_aha398XU_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1866{ 1867 int error; 1868 1869 error = ahc_aic7880_setup(pci, probe_config); 1870 if (error == 0) 1871 error = ahc_aha398XX_setup(pci, probe_config); 1872 return (error); 1873} 1874 1875static int 1876ahc_aic7890_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1877{ 1878 uint8_t rev; 1879 1880 probe_config->channel = 'A'; 1881 probe_config->chip = AHC_AIC7890; 1882 probe_config->features = AHC_AIC7890_FE; 1883 probe_config->flags |= AHC_NEWEEPROM_FMT; 1884 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1885 if (rev == 0) 1886 probe_config->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1887 return (0); 1888} 1889 1890static int 1891ahc_aic7892_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1892{ 1893 probe_config->channel = 'A'; 1894 probe_config->chip = AHC_AIC7892; 1895 probe_config->features = AHC_AIC7892_FE; 1896 probe_config->flags |= AHC_NEWEEPROM_FMT; 1897 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1898 return (0); 1899} 1900 1901static int 1902ahc_aic7895_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1903{ 1904 uint8_t rev; 1905 1906 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1907 /* 1908 * The 'C' revision of the aic7895 has a few additional features. 1909 */ 1910 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 1911 if (rev >= 4) { 1912 probe_config->chip = AHC_AIC7895C; 1913 probe_config->features = AHC_AIC7895C_FE; 1914 } else { 1915 u_int command; 1916 1917 probe_config->chip = AHC_AIC7895; 1918 probe_config->features = AHC_AIC7895_FE; 1919 1920 /* 1921 * The BIOS disables the use of MWI transactions 1922 * since it does not have the MWI bug work around 1923 * we have. Disabling MWI reduces performance, so 1924 * turn it on again. 1925 */ 1926 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 1927 command |= PCIM_CMD_MWRICEN; 1928 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 1929 probe_config->bugs |= AHC_PCI_MWI_BUG; 1930 } 1931 /* 1932 * XXX Does CACHETHEN really not work??? What about PCI retry? 1933 * on C level chips. Need to test, but for now, play it safe. 1934 */ 1935 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1936 | AHC_CACHETHEN_BUG; 1937 1938#if 0 1939 uint32_t devconfig; 1940 1941 /* 1942 * Cachesize must also be zero due to stray DAC 1943 * problem when sitting behind some bridges. 1944 */ 1945 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 1946 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 1947 devconfig |= MRDCEN; 1948 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 1949#endif 1950 probe_config->flags |= AHC_NEWEEPROM_FMT; 1951 return (0); 1952} 1953 1954static int 1955ahc_aic7896_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1956{ 1957 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1958 probe_config->chip = AHC_AIC7896; 1959 probe_config->features = AHC_AIC7896_FE; 1960 probe_config->flags |= AHC_NEWEEPROM_FMT; 1961 probe_config->bugs |= AHC_CACHETHEN_DIS_BUG; 1962 return (0); 1963} 1964 1965static int 1966ahc_aic7899_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1967{ 1968 probe_config->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 1969 probe_config->chip = AHC_AIC7899; 1970 probe_config->features = AHC_AIC7899_FE; 1971 probe_config->flags |= AHC_NEWEEPROM_FMT; 1972 probe_config->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1973 return (0); 1974} 1975 1976static int 1977ahc_aha29160C_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1978{ 1979 int error; 1980 1981 error = ahc_aic7899_setup(pci, probe_config); 1982 if (error != 0) 1983 return (error); 1984 probe_config->features |= AHC_REMOVABLE; 1985 return (0); 1986} 1987 1988static int 1989ahc_raid_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1990{ 1991 printf("RAID functionality unsupported\n"); 1992 return (ENXIO); 1993} 1994 1995static int 1996ahc_aha394XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 1997{ 1998 switch (ahc_get_pci_slot(pci)) { 1999 case AHC_394X_SLOT_CHANNEL_A: 2000 probe_config->channel = 'A'; 2001 break; 2002 case AHC_394X_SLOT_CHANNEL_B: 2003 probe_config->channel = 'B'; 2004 break; 2005 default: 2006 printf("adapter at unexpected slot %d\n" 2007 "unable to map to a channel\n", 2008 ahc_get_pci_slot(pci)); 2009 probe_config->channel = 'A'; 2010 } 2011 return (0); 2012} 2013 2014static int 2015ahc_aha398XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2016{ 2017 switch (ahc_get_pci_slot(pci)) { 2018 case AHC_398X_SLOT_CHANNEL_A: 2019 probe_config->channel = 'A'; 2020 break; 2021 case AHC_398X_SLOT_CHANNEL_B: 2022 probe_config->channel = 'B'; 2023 break; 2024 case AHC_398X_SLOT_CHANNEL_C: 2025 probe_config->channel = 'C'; 2026 break; 2027 default: 2028 printf("adapter at unexpected slot %d\n" 2029 "unable to map to a channel\n", 2030 ahc_get_pci_slot(pci)); 2031 probe_config->channel = 'A'; 2032 break; 2033 } 2034 probe_config->flags |= AHC_LARGE_SEEPROM; 2035 return (0); 2036} 2037 2038static int 2039ahc_aha494XX_setup(ahc_dev_softc_t pci, struct ahc_probe_config *probe_config) 2040{ 2041 switch (ahc_get_pci_slot(pci)) { 2042 case AHC_494X_SLOT_CHANNEL_A: 2043 probe_config->channel = 'A'; 2044 break; 2045 case AHC_494X_SLOT_CHANNEL_B: 2046 probe_config->channel = 'B'; 2047 break; 2048 case AHC_494X_SLOT_CHANNEL_C: 2049 probe_config->channel = 'C'; 2050 break; 2051 case AHC_494X_SLOT_CHANNEL_D: 2052 probe_config->channel = 'D'; 2053 break; 2054 default: 2055 printf("adapter at unexpected slot %d\n" 2056 "unable to map to a channel\n", 2057 ahc_get_pci_slot(pci)); 2058 probe_config->channel = 'A'; 2059 } 2060 probe_config->flags |= AHC_LARGE_SEEPROM; 2061 return (0); 2062} 2063