aic7xxx_inline.h revision 74972
1/* 2 * Inline routines shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx_inline.h#19 $ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_inline.h 74972 2001-03-29 00:36:35Z gibbs $ 34 */ 35 36#ifndef _AIC7XXX_INLINE_H_ 37#define _AIC7XXX_INLINE_H_ 38 39/************************* Sequencer Execution Control ************************/ 40static __inline int ahc_is_paused(struct ahc_softc *ahc); 41static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); 42static __inline void ahc_pause(struct ahc_softc *ahc); 43static __inline void ahc_unpause(struct ahc_softc *ahc); 44 45/* 46 * Work around any chip bugs related to halting sequencer execution. 47 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by 48 * reading a register that will set this signal and deassert it. 49 * Without this workaround, if the chip is paused, by an interrupt or 50 * manual pause while accessing scb ram, accesses to certain registers 51 * will hang the system (infinite pci retries). 52 */ 53static __inline void 54ahc_pause_bug_fix(struct ahc_softc *ahc) 55{ 56 if ((ahc->features & AHC_ULTRA2) != 0) 57 (void)ahc_inb(ahc, CCSCBCTL); 58} 59 60/* 61 * Determine whether the sequencer has halted code execution. 62 * Returns non-zero status if the sequencer is stopped. 63 */ 64static __inline int 65ahc_is_paused(struct ahc_softc *ahc) 66{ 67 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 68} 69 70/* 71 * Request that the sequencer stop and wait, indefinitely, for it 72 * to stop. The sequencer will only acknowledge that it is paused 73 * once it has reached an instruction boundary and PAUSEDIS is 74 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS 75 * for critical sections. 76 */ 77static __inline void 78ahc_pause(struct ahc_softc *ahc) 79{ 80 ahc_outb(ahc, HCNTRL, ahc->pause); 81 82 /* 83 * Since the sequencer can disable pausing in a critical section, we 84 * must loop until it actually stops. 85 */ 86 while (ahc_is_paused(ahc) == 0) 87 ; 88 89 ahc_pause_bug_fix(ahc); 90} 91 92/* 93 * Allow the sequencer to continue program execution. 94 * We check here to ensure that no additional interrupt 95 * sources that would cause the sequencer to halt have been 96 * asserted. If, for example, a SCSI bus reset is detected 97 * while we are fielding a different, pausing, interrupt type, 98 * we don't want to release the sequencer before going back 99 * into our interrupt handler and dealing with this new 100 * condition. 101 */ 102static __inline void 103ahc_unpause(struct ahc_softc *ahc) 104{ 105 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 106 ahc_outb(ahc, HCNTRL, ahc->unpause); 107} 108 109/*********************** Untagged Transaction Routines ************************/ 110static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc); 111static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc); 112 113/* 114 * Block our completion routine from starting the next untagged 115 * transaction for this target or target lun. 116 */ 117static __inline void 118ahc_freeze_untagged_queues(struct ahc_softc *ahc) 119{ 120 if ((ahc->flags & AHC_SCB_BTT) == 0) 121 ahc->untagged_queue_lock++; 122} 123 124/* 125 * Allow the next untagged transaction for this target or target lun 126 * to be executed. We use a counting semaphore to allow the lock 127 * to be acquired recursively. Once the count drops to zero, the 128 * transaction queues will be run. 129 */ 130static __inline void 131ahc_release_untagged_queues(struct ahc_softc *ahc) 132{ 133 if ((ahc->flags & AHC_SCB_BTT) == 0) { 134 ahc->untagged_queue_lock--; 135 if (ahc->untagged_queue_lock == 0) 136 ahc_run_untagged_queues(ahc); 137 } 138} 139 140/************************** Memory mapping routines ***************************/ 141static __inline struct ahc_dma_seg * 142 ahc_sg_bus_to_virt(struct scb *scb, 143 uint32_t sg_busaddr); 144static __inline uint32_t 145 ahc_sg_virt_to_bus(struct scb *scb, 146 struct ahc_dma_seg *sg); 147static __inline uint32_t 148 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index); 149 150static __inline struct ahc_dma_seg * 151ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr) 152{ 153 int sg_index; 154 155 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg); 156 /* sg_list_phys points to entry 1, not 0 */ 157 sg_index++; 158 159 return (&scb->sg_list[sg_index]); 160} 161 162static __inline uint32_t 163ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg) 164{ 165 int sg_index; 166 167 /* sg_list_phys points to entry 1, not 0 */ 168 sg_index = sg - &scb->sg_list[1]; 169 170 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list))); 171} 172 173static __inline uint32_t 174ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 175{ 176 return (ahc->scb_data->hscb_busaddr 177 + (sizeof(struct hardware_scb) * index)); 178} 179 180/******************************** Debugging ***********************************/ 181static __inline char *ahc_name(struct ahc_softc *ahc); 182 183static __inline char * 184ahc_name(struct ahc_softc *ahc) 185{ 186 return (ahc->name); 187} 188 189/*********************** Miscelaneous Support Functions ***********************/ 190 191static __inline int ahc_check_residual(struct scb *scb); 192static __inline struct ahc_initiator_tinfo * 193 ahc_fetch_transinfo(struct ahc_softc *ahc, 194 char channel, u_int our_id, 195 u_int remote_id, 196 struct ahc_tmode_tstate **tstate); 197static __inline struct scb* 198 ahc_get_scb(struct ahc_softc *ahc); 199static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); 200static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc, 201 struct scb *scb); 202static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb); 203static __inline struct scsi_sense_data * 204 ahc_get_sense_buf(struct ahc_softc *ahc, 205 struct scb *scb); 206static __inline uint32_t 207 ahc_get_sense_bufaddr(struct ahc_softc *ahc, 208 struct scb *scb); 209 210/* 211 * Determine whether the sequencer reported a residual 212 * for this SCB/transaction. 213 */ 214static __inline int 215ahc_check_residual(struct scb *scb) 216{ 217 struct status_pkt *sp; 218 219 sp = &scb->hscb->shared_data.status; 220 if ((scb->hscb->sgptr & SG_RESID_VALID) != 0) 221 return (1); 222 return (0); 223} 224 225/* 226 * Return pointers to the transfer negotiation information 227 * for the specified our_id/remote_id pair. 228 */ 229static __inline struct ahc_initiator_tinfo * 230ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 231 u_int remote_id, struct ahc_tmode_tstate **tstate) 232{ 233 /* 234 * Transfer data structures are stored from the perspective 235 * of the target role. Since the parameters for a connection 236 * in the initiator role to a given target are the same as 237 * when the roles are reversed, we pretend we are the target. 238 */ 239 if (channel == 'B') 240 our_id += 8; 241 *tstate = ahc->enabled_targets[our_id]; 242 return (&(*tstate)->transinfo[remote_id]); 243} 244 245/* 246 * Get a free scb. If there are none, see if we can allocate a new SCB. 247 */ 248static __inline struct scb * 249ahc_get_scb(struct ahc_softc *ahc) 250{ 251 struct scb *scb; 252 253 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) { 254 ahc_alloc_scbs(ahc); 255 scb = SLIST_FIRST(&ahc->scb_data->free_scbs); 256 if (scb == NULL) 257 return (NULL); 258 } 259 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); 260 return (scb); 261} 262 263/* 264 * Return an SCB resource to the free list. 265 */ 266static __inline void 267ahc_free_scb(struct ahc_softc *ahc, struct scb *scb) 268{ 269 struct hardware_scb *hscb; 270 271 hscb = scb->hscb; 272 /* Clean up for the next user */ 273 ahc->scb_data->scbindex[hscb->tag] = NULL; 274 scb->flags = SCB_FREE; 275 hscb->control = 0; 276 277 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle); 278 279 /* Notify the OSM that a resource is now available. */ 280 ahc_platform_scb_free(ahc, scb); 281} 282 283static __inline struct scb * 284ahc_lookup_scb(struct ahc_softc *ahc, u_int tag) 285{ 286 return (ahc->scb_data->scbindex[tag]); 287 288} 289 290static __inline void 291ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb) 292{ 293 struct hardware_scb *q_hscb; 294 u_int saved_tag; 295 296 /* 297 * Our queuing method is a bit tricky. The card 298 * knows in advance which HSCB to download, and we 299 * can't disappoint it. To achieve this, the next 300 * SCB to download is saved off in ahc->next_queued_scb. 301 * When we are called to queue "an arbitrary scb", 302 * we copy the contents of the incoming HSCB to the one 303 * the sequencer knows about, swap HSCB pointers and 304 * finally assign the SCB to the tag indexed location 305 * in the scb_array. This makes sure that we can still 306 * locate the correct SCB by SCB_TAG. 307 */ 308 q_hscb = ahc->next_queued_scb->hscb; 309 saved_tag = q_hscb->tag; 310 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb)); 311 if ((scb->flags & SCB_CDB32_PTR) != 0) { 312 q_hscb->shared_data.cdb_ptr = 313 ahc_hscb_busaddr(ahc, q_hscb->tag) 314 + offsetof(struct hardware_scb, cdb32); 315 } 316 q_hscb->tag = saved_tag; 317 q_hscb->next = scb->hscb->tag; 318 319 /* Now swap HSCB pointers. */ 320 ahc->next_queued_scb->hscb = scb->hscb; 321 scb->hscb = q_hscb; 322 323 /* Now define the mapping from tag to SCB in the scbindex */ 324 ahc->scb_data->scbindex[scb->hscb->tag] = scb; 325} 326 327/* 328 * Tell the sequencer about a new transaction to execute. 329 */ 330static __inline void 331ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb) 332{ 333 ahc_swap_with_next_hscb(ahc, scb); 334 335 if (scb->hscb->tag == SCB_LIST_NULL 336 || scb->hscb->next == SCB_LIST_NULL) 337 panic("Attempt to queue invalid SCB tag %x:%x\n", 338 scb->hscb->tag, scb->hscb->next); 339 340 /* 341 * Keep a history of SCBs we've downloaded in the qinfifo. 342 */ 343 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 344 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 345 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 346 } else { 347 if ((ahc->features & AHC_AUTOPAUSE) == 0) 348 ahc_pause(ahc); 349 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 350 if ((ahc->features & AHC_AUTOPAUSE) == 0) 351 ahc_unpause(ahc); 352 } 353} 354 355static __inline struct scsi_sense_data * 356ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb) 357{ 358 int offset; 359 360 offset = scb - ahc->scb_data->scbarray; 361 return (&ahc->scb_data->sense[offset]); 362} 363 364static __inline uint32_t 365ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb) 366{ 367 int offset; 368 369 offset = scb - ahc->scb_data->scbarray; 370 return (ahc->scb_data->sense_busaddr 371 + (offset * sizeof(struct scsi_sense_data))); 372} 373 374/************************** Interrupt Processing ******************************/ 375static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc); 376static __inline void ahc_intr(struct ahc_softc *ahc); 377 378/* 379 * See if the firmware has posted any completed commands 380 * into our in-core command complete fifos. 381 */ 382#define AHC_RUN_QOUTFIFO 0x1 383#define AHC_RUN_TQINFIFO 0x2 384static __inline u_int 385ahc_check_cmdcmpltqueues(struct ahc_softc *ahc) 386{ 387 u_int retval; 388 389 retval = 0; 390 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) 391 retval |= AHC_RUN_QOUTFIFO; 392#ifdef AHC_TARGET_MODE 393 if ((ahc->flags & AHC_TARGETROLE) != 0 394 && ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0) 395 retval |= AHC_RUN_TQINFIFO; 396#endif 397 return (retval); 398} 399 400/* 401 * Catch an interrupt from the adapter 402 */ 403static __inline void 404ahc_intr(struct ahc_softc *ahc) 405{ 406 u_int intstat; 407 u_int queuestat; 408 409 /* 410 * Instead of directly reading the interrupt status register, 411 * infer the cause of the interrupt by checking our in-core 412 * completion queues. This avoids a costly PCI bus read in 413 * most cases. 414 */ 415 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0 416 && (queuestat = ahc_check_cmdcmpltqueues(ahc)) != 0) 417 intstat = CMDCMPLT; 418 else { 419 intstat = ahc_inb(ahc, INTSTAT); 420 /* 421 * We can't generate queuestat once above 422 * or we are exposed to a race when our 423 * interrupt is shared with another device. 424 * if instat showed a command complete interrupt, 425 * but our first generation of queue stat 426 * "just missed" the delivery of this transaction, 427 * we would clear the command complete interrupt 428 * below without ever servicing the completed 429 * command. 430 */ 431 queuestat = ahc_check_cmdcmpltqueues(ahc); 432#if AHC_PCI_CONFIG > 0 433 if (ahc->unsolicited_ints > 500 434 && (ahc->chip & AHC_PCI) != 0 435 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) 436 ahc->bus_intr(ahc); 437#endif 438 } 439 440 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 441 /* Hot eject */ 442 return; 443 444 if ((intstat & INT_PEND) == 0) { 445 ahc->unsolicited_ints++; 446 return; 447 } 448 ahc->unsolicited_ints = 0; 449 450 if (intstat & CMDCMPLT) { 451 ahc_outb(ahc, CLRINT, CLRCMDINT); 452 453 /* 454 * Ensure that the chip sees that we've cleared 455 * this interrupt before we walk the output fifo. 456 * Otherwise, we may, due to posted bus writes, 457 * clear the interrupt after we finish the scan, 458 * and after the sequencer has added new entries 459 * and asserted the interrupt again. 460 */ 461 ahc_flush_device_writes(ahc); 462#ifdef AHC_TARGET_MODE 463 if ((queuestat & AHC_RUN_QOUTFIFO) != 0) 464#endif 465 ahc_run_qoutfifo(ahc); 466#ifdef AHC_TARGET_MODE 467 if ((queuestat & AHC_RUN_TQINFIFO) != 0) 468 ahc_run_tqinfifo(ahc, /*paused*/FALSE); 469#endif 470 } 471 if (intstat & BRKADRINT) { 472 ahc_handle_brkadrint(ahc); 473 /* Fatal error, no more interrupts to handle. */ 474 return; 475 } 476 477 if ((intstat & (SEQINT|SCSIINT)) != 0) 478 ahc_pause_bug_fix(ahc); 479 480 if ((intstat & SEQINT) != 0) 481 ahc_handle_seqint(ahc, intstat); 482 483 if ((intstat & SCSIINT) != 0) 484 ahc_handle_scsiint(ahc, intstat); 485} 486 487#endif /* _AIC7XXX_INLINE_H_ */ 488