aic7xxx_inline.h revision 102678
1/* 2 * Inline routines shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#38 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_inline.h 102678 2002-08-31 06:46:37Z gibbs $ 43 */ 44 45#ifndef _AIC7XXX_INLINE_H_ 46#define _AIC7XXX_INLINE_H_ 47 48/************************* Sequencer Execution Control ************************/ 49static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); 50static __inline int ahc_is_paused(struct ahc_softc *ahc); 51static __inline void ahc_pause(struct ahc_softc *ahc); 52static __inline void ahc_unpause(struct ahc_softc *ahc); 53 54/* 55 * Work around any chip bugs related to halting sequencer execution. 56 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by 57 * reading a register that will set this signal and deassert it. 58 * Without this workaround, if the chip is paused, by an interrupt or 59 * manual pause while accessing scb ram, accesses to certain registers 60 * will hang the system (infinite pci retries). 61 */ 62static __inline void 63ahc_pause_bug_fix(struct ahc_softc *ahc) 64{ 65 if ((ahc->features & AHC_ULTRA2) != 0) 66 (void)ahc_inb(ahc, CCSCBCTL); 67} 68 69/* 70 * Determine whether the sequencer has halted code execution. 71 * Returns non-zero status if the sequencer is stopped. 72 */ 73static __inline int 74ahc_is_paused(struct ahc_softc *ahc) 75{ 76 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 77} 78 79/* 80 * Request that the sequencer stop and wait, indefinitely, for it 81 * to stop. The sequencer will only acknowledge that it is paused 82 * once it has reached an instruction boundary and PAUSEDIS is 83 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS 84 * for critical sections. 85 */ 86static __inline void 87ahc_pause(struct ahc_softc *ahc) 88{ 89 ahc_outb(ahc, HCNTRL, ahc->pause); 90 91 /* 92 * Since the sequencer can disable pausing in a critical section, we 93 * must loop until it actually stops. 94 */ 95 while (ahc_is_paused(ahc) == 0) 96 ; 97 98 ahc_pause_bug_fix(ahc); 99} 100 101/* 102 * Allow the sequencer to continue program execution. 103 * We check here to ensure that no additional interrupt 104 * sources that would cause the sequencer to halt have been 105 * asserted. If, for example, a SCSI bus reset is detected 106 * while we are fielding a different, pausing, interrupt type, 107 * we don't want to release the sequencer before going back 108 * into our interrupt handler and dealing with this new 109 * condition. 110 */ 111static __inline void 112ahc_unpause(struct ahc_softc *ahc) 113{ 114 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 115 ahc_outb(ahc, HCNTRL, ahc->unpause); 116} 117 118/*********************** Untagged Transaction Routines ************************/ 119static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc); 120static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc); 121 122/* 123 * Block our completion routine from starting the next untagged 124 * transaction for this target or target lun. 125 */ 126static __inline void 127ahc_freeze_untagged_queues(struct ahc_softc *ahc) 128{ 129 if ((ahc->flags & AHC_SCB_BTT) == 0) 130 ahc->untagged_queue_lock++; 131} 132 133/* 134 * Allow the next untagged transaction for this target or target lun 135 * to be executed. We use a counting semaphore to allow the lock 136 * to be acquired recursively. Once the count drops to zero, the 137 * transaction queues will be run. 138 */ 139static __inline void 140ahc_release_untagged_queues(struct ahc_softc *ahc) 141{ 142 if ((ahc->flags & AHC_SCB_BTT) == 0) { 143 ahc->untagged_queue_lock--; 144 if (ahc->untagged_queue_lock == 0) 145 ahc_run_untagged_queues(ahc); 146 } 147} 148 149/************************** Memory mapping routines ***************************/ 150static __inline struct ahc_dma_seg * 151 ahc_sg_bus_to_virt(struct scb *scb, 152 uint32_t sg_busaddr); 153static __inline uint32_t 154 ahc_sg_virt_to_bus(struct scb *scb, 155 struct ahc_dma_seg *sg); 156static __inline uint32_t 157 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index); 158static __inline void ahc_sync_scb(struct ahc_softc *ahc, 159 struct scb *scb, int op); 160static __inline void ahc_sync_sglist(struct ahc_softc *ahc, 161 struct scb *scb, int op); 162static __inline uint32_t 163 ahc_targetcmd_offset(struct ahc_softc *ahc, 164 u_int index); 165 166static __inline struct ahc_dma_seg * 167ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr) 168{ 169 int sg_index; 170 171 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg); 172 /* sg_list_phys points to entry 1, not 0 */ 173 sg_index++; 174 175 return (&scb->sg_list[sg_index]); 176} 177 178static __inline uint32_t 179ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg) 180{ 181 int sg_index; 182 183 /* sg_list_phys points to entry 1, not 0 */ 184 sg_index = sg - &scb->sg_list[1]; 185 186 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list))); 187} 188 189static __inline uint32_t 190ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 191{ 192 return (ahc->scb_data->hscb_busaddr 193 + (sizeof(struct hardware_scb) * index)); 194} 195 196static __inline void 197ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op) 198{ 199 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat, 200 ahc->scb_data->hscb_dmamap, 201 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb), 202 /*len*/sizeof(*scb->hscb), op); 203} 204 205static __inline void 206ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op) 207{ 208 if (scb->sg_count == 0) 209 return; 210 211 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap, 212 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr) 213 * sizeof(struct ahc_dma_seg), 214 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op); 215} 216 217static __inline uint32_t 218ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index) 219{ 220 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo); 221} 222 223/******************************** Debugging ***********************************/ 224static __inline char *ahc_name(struct ahc_softc *ahc); 225 226static __inline char * 227ahc_name(struct ahc_softc *ahc) 228{ 229 return (ahc->name); 230} 231 232/*********************** Miscelaneous Support Functions ***********************/ 233 234static __inline void ahc_update_residual(struct ahc_softc *ahc, 235 struct scb *scb); 236static __inline struct ahc_initiator_tinfo * 237 ahc_fetch_transinfo(struct ahc_softc *ahc, 238 char channel, u_int our_id, 239 u_int remote_id, 240 struct ahc_tmode_tstate **tstate); 241static __inline struct scb* 242 ahc_get_scb(struct ahc_softc *ahc); 243static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); 244static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc, 245 struct scb *scb); 246static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb); 247static __inline struct scsi_sense_data * 248 ahc_get_sense_buf(struct ahc_softc *ahc, 249 struct scb *scb); 250static __inline uint32_t 251 ahc_get_sense_bufaddr(struct ahc_softc *ahc, 252 struct scb *scb); 253 254/* 255 * Determine whether the sequencer reported a residual 256 * for this SCB/transaction. 257 */ 258static __inline void 259ahc_update_residual(struct ahc_softc *ahc, struct scb *scb) 260{ 261 uint32_t sgptr; 262 263 sgptr = ahc_le32toh(scb->hscb->sgptr); 264 if ((sgptr & SG_RESID_VALID) != 0) 265 ahc_calc_residual(ahc, scb); 266} 267 268/* 269 * Return pointers to the transfer negotiation information 270 * for the specified our_id/remote_id pair. 271 */ 272static __inline struct ahc_initiator_tinfo * 273ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 274 u_int remote_id, struct ahc_tmode_tstate **tstate) 275{ 276 /* 277 * Transfer data structures are stored from the perspective 278 * of the target role. Since the parameters for a connection 279 * in the initiator role to a given target are the same as 280 * when the roles are reversed, we pretend we are the target. 281 */ 282 if (channel == 'B') 283 our_id += 8; 284 *tstate = ahc->enabled_targets[our_id]; 285 return (&(*tstate)->transinfo[remote_id]); 286} 287 288/* 289 * Get a free scb. If there are none, see if we can allocate a new SCB. 290 */ 291static __inline struct scb * 292ahc_get_scb(struct ahc_softc *ahc) 293{ 294 struct scb *scb; 295 296 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) { 297 ahc_alloc_scbs(ahc); 298 scb = SLIST_FIRST(&ahc->scb_data->free_scbs); 299 if (scb == NULL) 300 return (NULL); 301 } 302 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); 303 return (scb); 304} 305 306/* 307 * Return an SCB resource to the free list. 308 */ 309static __inline void 310ahc_free_scb(struct ahc_softc *ahc, struct scb *scb) 311{ 312 struct hardware_scb *hscb; 313 314 hscb = scb->hscb; 315 /* Clean up for the next user */ 316 ahc->scb_data->scbindex[hscb->tag] = NULL; 317 scb->flags = SCB_FREE; 318 hscb->control = 0; 319 320 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle); 321 322 /* Notify the OSM that a resource is now available. */ 323 ahc_platform_scb_free(ahc, scb); 324} 325 326static __inline struct scb * 327ahc_lookup_scb(struct ahc_softc *ahc, u_int tag) 328{ 329 struct scb* scb; 330 331 scb = ahc->scb_data->scbindex[tag]; 332 if (scb != NULL) 333 ahc_sync_scb(ahc, scb, 334 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 335 return (scb); 336} 337 338static __inline void 339ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb) 340{ 341 struct hardware_scb *q_hscb; 342 u_int saved_tag; 343 344 /* 345 * Our queuing method is a bit tricky. The card 346 * knows in advance which HSCB to download, and we 347 * can't disappoint it. To achieve this, the next 348 * SCB to download is saved off in ahc->next_queued_scb. 349 * When we are called to queue "an arbitrary scb", 350 * we copy the contents of the incoming HSCB to the one 351 * the sequencer knows about, swap HSCB pointers and 352 * finally assign the SCB to the tag indexed location 353 * in the scb_array. This makes sure that we can still 354 * locate the correct SCB by SCB_TAG. 355 */ 356 q_hscb = ahc->next_queued_scb->hscb; 357 saved_tag = q_hscb->tag; 358 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb)); 359 if ((scb->flags & SCB_CDB32_PTR) != 0) { 360 q_hscb->shared_data.cdb_ptr = 361 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag) 362 + offsetof(struct hardware_scb, cdb32)); 363 } 364 q_hscb->tag = saved_tag; 365 q_hscb->next = scb->hscb->tag; 366 367 /* Now swap HSCB pointers. */ 368 ahc->next_queued_scb->hscb = scb->hscb; 369 scb->hscb = q_hscb; 370 371 /* Now define the mapping from tag to SCB in the scbindex */ 372 ahc->scb_data->scbindex[scb->hscb->tag] = scb; 373} 374 375/* 376 * Tell the sequencer about a new transaction to execute. 377 */ 378static __inline void 379ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb) 380{ 381 ahc_swap_with_next_hscb(ahc, scb); 382 383 if (scb->hscb->tag == SCB_LIST_NULL 384 || scb->hscb->next == SCB_LIST_NULL) 385 panic("Attempt to queue invalid SCB tag %x:%x\n", 386 scb->hscb->tag, scb->hscb->next); 387 388 /* 389 * Keep a history of SCBs we've downloaded in the qinfifo. 390 */ 391 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 392 393 /* 394 * Make sure our data is consistant from the 395 * perspective of the adapter. 396 */ 397 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 398 399 /* Tell the adapter about the newly queued SCB */ 400 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 401 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 402 } else { 403 if ((ahc->features & AHC_AUTOPAUSE) == 0) 404 ahc_pause(ahc); 405 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 406 if ((ahc->features & AHC_AUTOPAUSE) == 0) 407 ahc_unpause(ahc); 408 } 409} 410 411static __inline struct scsi_sense_data * 412ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb) 413{ 414 int offset; 415 416 offset = scb - ahc->scb_data->scbarray; 417 return (&ahc->scb_data->sense[offset]); 418} 419 420static __inline uint32_t 421ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb) 422{ 423 int offset; 424 425 offset = scb - ahc->scb_data->scbarray; 426 return (ahc->scb_data->sense_busaddr 427 + (offset * sizeof(struct scsi_sense_data))); 428} 429 430/************************** Interrupt Processing ******************************/ 431static __inline void ahc_sync_qoutfifo(struct ahc_softc *ahc, int op); 432static __inline void ahc_sync_tqinfifo(struct ahc_softc *ahc, int op); 433static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc); 434static __inline void ahc_intr(struct ahc_softc *ahc); 435 436static __inline void 437ahc_sync_qoutfifo(struct ahc_softc *ahc, int op) 438{ 439 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 440 /*offset*/0, /*len*/256, op); 441} 442 443static __inline void 444ahc_sync_tqinfifo(struct ahc_softc *ahc, int op) 445{ 446#ifdef AHC_TARGET_MODE 447 if ((ahc->flags & AHC_TARGETROLE) != 0) { 448 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 449 ahc->shared_data_dmamap, 450 ahc_targetcmd_offset(ahc, 0), 451 sizeof(struct target_cmd) * AHC_TMODE_CMDS, 452 op); 453 } 454#endif 455} 456 457/* 458 * See if the firmware has posted any completed commands 459 * into our in-core command complete fifos. 460 */ 461#define AHC_RUN_QOUTFIFO 0x1 462#define AHC_RUN_TQINFIFO 0x2 463static __inline u_int 464ahc_check_cmdcmpltqueues(struct ahc_softc *ahc) 465{ 466 u_int retval; 467 468 retval = 0; 469 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 470 /*offset*/ahc->qoutfifonext, /*len*/1, 471 BUS_DMASYNC_POSTREAD); 472 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) 473 retval |= AHC_RUN_QOUTFIFO; 474#ifdef AHC_TARGET_MODE 475 if ((ahc->flags & AHC_TARGETROLE) != 0 476 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) { 477 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 478 ahc->shared_data_dmamap, 479 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext), 480 /*len*/sizeof(struct target_cmd), 481 BUS_DMASYNC_POSTREAD); 482 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0) 483 retval |= AHC_RUN_TQINFIFO; 484 } 485#endif 486 return (retval); 487} 488 489/* 490 * Catch an interrupt from the adapter 491 */ 492static __inline void 493ahc_intr(struct ahc_softc *ahc) 494{ 495 u_int intstat; 496 497 if ((ahc->pause & INTEN) == 0) { 498 /* 499 * Our interrupt is not enabled on the chip 500 * and may be disabled for re-entrancy reasons, 501 * so just return. This is likely just a shared 502 * interrupt. 503 */ 504 return; 505 } 506 /* 507 * Instead of directly reading the interrupt status register, 508 * infer the cause of the interrupt by checking our in-core 509 * completion queues. This avoids a costly PCI bus read in 510 * most cases. 511 */ 512 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0 513 && (ahc_check_cmdcmpltqueues(ahc) != 0)) 514 intstat = CMDCMPLT; 515 else { 516 intstat = ahc_inb(ahc, INTSTAT); 517 } 518 519 if (intstat & CMDCMPLT) { 520 ahc_outb(ahc, CLRINT, CLRCMDINT); 521 522 /* 523 * Ensure that the chip sees that we've cleared 524 * this interrupt before we walk the output fifo. 525 * Otherwise, we may, due to posted bus writes, 526 * clear the interrupt after we finish the scan, 527 * and after the sequencer has added new entries 528 * and asserted the interrupt again. 529 */ 530 ahc_flush_device_writes(ahc); 531 ahc_run_qoutfifo(ahc); 532#ifdef AHC_TARGET_MODE 533 if ((ahc->flags & AHC_TARGETROLE) != 0) 534 ahc_run_tqinfifo(ahc, /*paused*/FALSE); 535#endif 536 } 537 538 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 539 /* Hot eject */ 540 return; 541 542 if ((intstat & INT_PEND) == 0) { 543#if AHC_PCI_CONFIG > 0 544 if (ahc->unsolicited_ints > 500) { 545 ahc->unsolicited_ints = 0; 546 if ((ahc->chip & AHC_PCI) != 0 547 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) 548 ahc->bus_intr(ahc); 549 } 550#endif 551 ahc->unsolicited_ints++; 552 return; 553 } 554 ahc->unsolicited_ints = 0; 555 556 if (intstat & BRKADRINT) { 557 ahc_handle_brkadrint(ahc); 558 /* Fatal error, no more interrupts to handle. */ 559 return; 560 } 561 562 if ((intstat & (SEQINT|SCSIINT)) != 0) 563 ahc_pause_bug_fix(ahc); 564 565 if ((intstat & SEQINT) != 0) 566 ahc_handle_seqint(ahc, intstat); 567 568 if ((intstat & SCSIINT) != 0) 569 ahc_handle_scsiint(ahc, intstat); 570} 571 572#endif /* _AIC7XXX_INLINE_H_ */ 573