1139757Sscottl/*- 239220Sgibbs * Interface for the 93C66/56/46/26/06 serial eeprom parts. 339220Sgibbs * 439220Sgibbs * Copyright (c) 1995, 1996 Daniel M. Eischen 539220Sgibbs * All rights reserved. 639220Sgibbs * 739220Sgibbs * Redistribution and use in source and binary forms, with or without 839220Sgibbs * modification, are permitted provided that the following conditions 939220Sgibbs * are met: 1039220Sgibbs * 1. Redistributions of source code must retain the above copyright 1165942Sgibbs * notice, this list of conditions, and the following disclaimer, 1265942Sgibbs * without modification. 1365942Sgibbs * 2. The name of the author may not be used to endorse or promote products 1465942Sgibbs * derived from this software without specific prior written permission. 1539220Sgibbs * 1665942Sgibbs * Alternatively, this software may be distributed under the terms of the 1795378Sgibbs * GNU General Public License ("GPL"). 1865942Sgibbs * 1965942Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2065942Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2165942Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2265942Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2365942Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2465942Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2565942Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2665942Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2765942Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2865942Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2965942Sgibbs * SUCH DAMAGE. 3065942Sgibbs * 31123579Sgibbs * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_93cx6.c#19 $ 3239220Sgibbs */ 3339220Sgibbs 3439220Sgibbs/* 3539220Sgibbs * The instruction set of the 93C66/56/46/26/06 chips are as follows: 3639220Sgibbs * 3739220Sgibbs * Start OP * 3839220Sgibbs * Function Bit Code Address** Data Description 3939220Sgibbs * ------------------------------------------------------------------- 4039220Sgibbs * READ 1 10 A5 - A0 Reads data stored in memory, 4139220Sgibbs * starting at specified address 4272640Sasmodai * EWEN 1 00 11XXXX Write enable must precede 4339220Sgibbs * all programming modes 4439220Sgibbs * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A0 4539220Sgibbs * WRITE 1 01 A5 - A0 D15 - D0 Writes register 4639220Sgibbs * ERAL 1 00 10XXXX Erase all registers 4739220Sgibbs * WRAL 1 00 01XXXX D15 - D0 Writes to all registers 4839220Sgibbs * EWDS 1 00 00XXXX Disables all programming 4939220Sgibbs * instructions 5039220Sgibbs * *Note: A value of X for address is a don't care condition. 5139220Sgibbs * **Note: There are 8 address bits for the 93C56/66 chips unlike 5239220Sgibbs * the 93C46/26/06 chips which have 6 address bits. 5339220Sgibbs * 5439220Sgibbs * The 93C46 has a four wire interface: clock, chip select, data in, and 5539220Sgibbs * data out. In order to perform one of the above functions, you need 5639220Sgibbs * to enable the chip select for a clock period (typically a minimum of 5739220Sgibbs * 1 usec, with the clock high and low a minimum of 750 and 250 nsec 5839220Sgibbs * respectively). While the chip select remains high, you can clock in 5939220Sgibbs * the instructions (above) starting with the start bit, followed by the 6039220Sgibbs * OP code, Address, and Data (if needed). For the READ instruction, the 6139220Sgibbs * requested 16-bit register contents is read from the data out line but 6239220Sgibbs * is preceded by an initial zero (leading 0, followed by 16-bits, MSB 6339220Sgibbs * first). The clock cycling from low to high initiates the next data 6439220Sgibbs * bit to be sent from the chip. 6539220Sgibbs */ 6639220Sgibbs 6795378Sgibbs#ifdef __linux__ 6895378Sgibbs#include "aic7xxx_osm.h" 6995378Sgibbs#include "aic7xxx_inline.h" 7095378Sgibbs#include "aic7xxx_93cx6.h" 7195378Sgibbs#else 72123579Sgibbs#include <sys/cdefs.h> 73123579Sgibbs__FBSDID("$FreeBSD$"); 7495378Sgibbs#include <dev/aic7xxx/aic7xxx_osm.h> 7565942Sgibbs#include <dev/aic7xxx/aic7xxx_inline.h> 7665942Sgibbs#include <dev/aic7xxx/aic7xxx_93cx6.h> 7795378Sgibbs#endif 7839220Sgibbs 7939220Sgibbs/* 8039220Sgibbs * Right now, we only have to read the SEEPROM. But we make it easier to 8139220Sgibbs * add other 93Cx6 functions. 8239220Sgibbs */ 83123579Sgibbsstruct seeprom_cmd { 8465942Sgibbs uint8_t len; 85123579Sgibbs uint8_t bits[11]; 86123579Sgibbs}; 8739220Sgibbs 88123579Sgibbs/* Short opcodes for the c46 */ 8995378Sgibbsstatic struct seeprom_cmd seeprom_ewen = {9, {1, 0, 0, 1, 1, 0, 0, 0, 0}}; 9095378Sgibbsstatic struct seeprom_cmd seeprom_ewds = {9, {1, 0, 0, 0, 0, 0, 0, 0, 0}}; 91123579Sgibbs 92123579Sgibbs/* Long opcodes for the C56/C66 */ 93123579Sgibbsstatic struct seeprom_cmd seeprom_long_ewen = {11, {1, 0, 0, 1, 1, 0, 0, 0, 0}}; 94123579Sgibbsstatic struct seeprom_cmd seeprom_long_ewds = {11, {1, 0, 0, 0, 0, 0, 0, 0, 0}}; 95123579Sgibbs 96123579Sgibbs/* Common opcodes */ 9795378Sgibbsstatic struct seeprom_cmd seeprom_write = {3, {1, 0, 1}}; 98123579Sgibbsstatic struct seeprom_cmd seeprom_read = {3, {1, 1, 0}}; 9995378Sgibbs 10039220Sgibbs/* 10139220Sgibbs * Wait for the SEERDY to go high; about 800 ns. 10239220Sgibbs */ 10339220Sgibbs#define CLOCK_PULSE(sd, rdy) \ 10439220Sgibbs while ((SEEPROM_STATUS_INB(sd) & rdy) == 0) { \ 10539220Sgibbs ; /* Do nothing */ \ 10639220Sgibbs } \ 10739220Sgibbs (void)SEEPROM_INB(sd); /* Clear clock */ 10839220Sgibbs 10939220Sgibbs/* 11095378Sgibbs * Send a START condition and the given command 11195378Sgibbs */ 11295378Sgibbsstatic void 11395378Sgibbssend_seeprom_cmd(struct seeprom_descriptor *sd, struct seeprom_cmd *cmd) 11495378Sgibbs{ 11595378Sgibbs uint8_t temp; 11695378Sgibbs int i = 0; 11795378Sgibbs 11895378Sgibbs /* Send chip select for one clock cycle. */ 11995378Sgibbs temp = sd->sd_MS ^ sd->sd_CS; 12095378Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 12195378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 12295378Sgibbs 12395378Sgibbs for (i = 0; i < cmd->len; i++) { 12495378Sgibbs if (cmd->bits[i] != 0) 12595378Sgibbs temp ^= sd->sd_DO; 12695378Sgibbs SEEPROM_OUTB(sd, temp); 12795378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 12895378Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 12995378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 13095378Sgibbs if (cmd->bits[i] != 0) 13195378Sgibbs temp ^= sd->sd_DO; 13295378Sgibbs } 13395378Sgibbs} 13495378Sgibbs 13595378Sgibbs/* 13695378Sgibbs * Clear CS put the chip in the reset state, where it can wait for new commands. 13795378Sgibbs */ 13895378Sgibbsstatic void 13995378Sgibbsreset_seeprom(struct seeprom_descriptor *sd) 14095378Sgibbs{ 14195378Sgibbs uint8_t temp; 14295378Sgibbs 14395378Sgibbs temp = sd->sd_MS; 14495378Sgibbs SEEPROM_OUTB(sd, temp); 14595378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 14695378Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 14795378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 14895378Sgibbs SEEPROM_OUTB(sd, temp); 14995378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 15095378Sgibbs} 15195378Sgibbs 15295378Sgibbs/* 15339220Sgibbs * Read the serial EEPROM and returns 1 if successful and 0 if 15439220Sgibbs * not successful. 15539220Sgibbs */ 15639220Sgibbsint 15795378Sgibbsahc_read_seeprom(struct seeprom_descriptor *sd, uint16_t *buf, 15895378Sgibbs u_int start_addr, u_int count) 15939220Sgibbs{ 16039220Sgibbs int i = 0; 16139220Sgibbs u_int k = 0; 16263457Sgibbs uint16_t v; 16363457Sgibbs uint8_t temp; 16439220Sgibbs 16539220Sgibbs /* 16639220Sgibbs * Read the requested registers of the seeprom. The loop 16739220Sgibbs * will range from 0 to count-1. 16839220Sgibbs */ 16939220Sgibbs for (k = start_addr; k < count + start_addr; k++) { 17039220Sgibbs /* 17139220Sgibbs * Now we're ready to send the read command followed by the 17239220Sgibbs * address of the 16-bit register we want to read. 17339220Sgibbs */ 17495378Sgibbs send_seeprom_cmd(sd, &seeprom_read); 17595378Sgibbs 17639220Sgibbs /* Send the 6 or 8 bit address (MSB first, LSB last). */ 17795378Sgibbs temp = sd->sd_MS ^ sd->sd_CS; 17839220Sgibbs for (i = (sd->sd_chip - 1); i >= 0; i--) { 17939220Sgibbs if ((k & (1 << i)) != 0) 18039220Sgibbs temp ^= sd->sd_DO; 18139220Sgibbs SEEPROM_OUTB(sd, temp); 18239220Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 18339220Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 18439220Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 18539220Sgibbs if ((k & (1 << i)) != 0) 18639220Sgibbs temp ^= sd->sd_DO; 18739220Sgibbs } 18839220Sgibbs 18939220Sgibbs /* 19039220Sgibbs * Now read the 16 bit register. An initial 0 precedes the 19139220Sgibbs * register contents which begins with bit 15 (MSB) and ends 19239220Sgibbs * with bit 0 (LSB). The initial 0 will be shifted off the 19339220Sgibbs * top of our word as we let the loop run from 0 to 16. 19439220Sgibbs */ 19539220Sgibbs v = 0; 19639220Sgibbs for (i = 16; i >= 0; i--) { 19739220Sgibbs SEEPROM_OUTB(sd, temp); 19839220Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 19939220Sgibbs v <<= 1; 20039220Sgibbs if (SEEPROM_DATA_INB(sd) & sd->sd_DI) 20139220Sgibbs v |= 1; 20239220Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 20339220Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 20439220Sgibbs } 20539220Sgibbs 20639220Sgibbs buf[k - start_addr] = v; 20739220Sgibbs 20839220Sgibbs /* Reset the chip select for the next command cycle. */ 20995378Sgibbs reset_seeprom(sd); 21039220Sgibbs } 21147507Sgibbs#ifdef AHC_DUMP_EEPROM 21255581Sgibbs printf("\nSerial EEPROM:\n\t"); 21339220Sgibbs for (k = 0; k < count; k = k + 1) { 21439220Sgibbs if (((k % 8) == 0) && (k != 0)) { 21555581Sgibbs printf ("\n\t"); 21639220Sgibbs } 21739220Sgibbs printf (" 0x%x", buf[k]); 21839220Sgibbs } 21939220Sgibbs printf ("\n"); 22039220Sgibbs#endif 22139220Sgibbs return (1); 22239220Sgibbs} 22365942Sgibbs 22495378Sgibbs/* 22595378Sgibbs * Write the serial EEPROM and return 1 if successful and 0 if 22695378Sgibbs * not successful. 22795378Sgibbs */ 22865942Sgibbsint 22995378Sgibbsahc_write_seeprom(struct seeprom_descriptor *sd, uint16_t *buf, 23095378Sgibbs u_int start_addr, u_int count) 23165942Sgibbs{ 232123579Sgibbs struct seeprom_cmd *ewen, *ewds; 23395378Sgibbs uint16_t v; 23495378Sgibbs uint8_t temp; 23595378Sgibbs int i, k; 23695378Sgibbs 23795378Sgibbs /* Place the chip into write-enable mode */ 238123579Sgibbs if (sd->sd_chip == C46) { 239123579Sgibbs ewen = &seeprom_ewen; 240123579Sgibbs ewds = &seeprom_ewds; 241123579Sgibbs } else if (sd->sd_chip == C56_66) { 242123579Sgibbs ewen = &seeprom_long_ewen; 243123579Sgibbs ewds = &seeprom_long_ewds; 244123579Sgibbs } else { 245123579Sgibbs printf("ahc_write_seeprom: unsupported seeprom type %d\n", 246123579Sgibbs sd->sd_chip); 247123579Sgibbs return (0); 248123579Sgibbs } 249123579Sgibbs 250123579Sgibbs send_seeprom_cmd(sd, ewen); 25195378Sgibbs reset_seeprom(sd); 25295378Sgibbs 25395378Sgibbs /* Write all requested data out to the seeprom. */ 25495378Sgibbs temp = sd->sd_MS ^ sd->sd_CS; 25595378Sgibbs for (k = start_addr; k < count + start_addr; k++) { 25695378Sgibbs /* Send the write command */ 25795378Sgibbs send_seeprom_cmd(sd, &seeprom_write); 25895378Sgibbs 25995378Sgibbs /* Send the 6 or 8 bit address (MSB first). */ 26095378Sgibbs for (i = (sd->sd_chip - 1); i >= 0; i--) { 26195378Sgibbs if ((k & (1 << i)) != 0) 26295378Sgibbs temp ^= sd->sd_DO; 26395378Sgibbs SEEPROM_OUTB(sd, temp); 26495378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 26595378Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 26695378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 26795378Sgibbs if ((k & (1 << i)) != 0) 26895378Sgibbs temp ^= sd->sd_DO; 26995378Sgibbs } 27095378Sgibbs 27195378Sgibbs /* Write the 16 bit value, MSB first */ 27295378Sgibbs v = buf[k - start_addr]; 27395378Sgibbs for (i = 15; i >= 0; i--) { 27495378Sgibbs if ((v & (1 << i)) != 0) 27595378Sgibbs temp ^= sd->sd_DO; 27695378Sgibbs SEEPROM_OUTB(sd, temp); 27795378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 27895378Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 27995378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 28095378Sgibbs if ((v & (1 << i)) != 0) 28195378Sgibbs temp ^= sd->sd_DO; 28295378Sgibbs } 28395378Sgibbs 28495378Sgibbs /* Wait for the chip to complete the write */ 28595378Sgibbs temp = sd->sd_MS; 28695378Sgibbs SEEPROM_OUTB(sd, temp); 28795378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 28895378Sgibbs temp = sd->sd_MS ^ sd->sd_CS; 28995378Sgibbs do { 29095378Sgibbs SEEPROM_OUTB(sd, temp); 29195378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 29295378Sgibbs SEEPROM_OUTB(sd, temp ^ sd->sd_CK); 29395378Sgibbs CLOCK_PULSE(sd, sd->sd_RDY); 29495378Sgibbs } while ((SEEPROM_DATA_INB(sd) & sd->sd_DI) == 0); 29595378Sgibbs 29695378Sgibbs reset_seeprom(sd); 29795378Sgibbs } 29895378Sgibbs 29995378Sgibbs /* Put the chip back into write-protect mode */ 300123579Sgibbs send_seeprom_cmd(sd, ewds); 30195378Sgibbs reset_seeprom(sd); 30295378Sgibbs 30395378Sgibbs return (1); 30495378Sgibbs} 30595378Sgibbs 30695378Sgibbsint 30795378Sgibbsahc_verify_cksum(struct seeprom_config *sc) 30895378Sgibbs{ 30965942Sgibbs int i; 31065942Sgibbs int maxaddr; 31165942Sgibbs uint32_t checksum; 31265942Sgibbs uint16_t *scarray; 31365942Sgibbs 31465942Sgibbs maxaddr = (sizeof(*sc)/2) - 1; 31565942Sgibbs checksum = 0; 31665942Sgibbs scarray = (uint16_t *)sc; 31765942Sgibbs 31865942Sgibbs for (i = 0; i < maxaddr; i++) 31965942Sgibbs checksum = checksum + scarray[i]; 32065942Sgibbs if (checksum == 0 32165942Sgibbs || (checksum & 0xFFFF) != sc->checksum) { 32265942Sgibbs return (0); 32365942Sgibbs } else { 32465942Sgibbs return(1); 32565942Sgibbs } 32665942Sgibbs} 327