aic7xxx.h revision 71717
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.h#17 $ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 71717 2001-01-27 20:54:24Z gibbs $ 34 */ 35 36#ifndef _AIC7XXX_H_ 37#define _AIC7XXX_H_ 38 39/* Register Definitions */ 40#include "aic7xxx_reg.h" 41 42/************************* Forward Declarations *******************************/ 43struct ahc_platform_data; 44struct scb_platform_data; 45 46/****************************** Useful Macros *********************************/ 47#ifndef MAX 48#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 49#endif 50 51#ifndef MIN 52#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 53#endif 54 55#ifndef TRUE 56#define TRUE 1 57#endif 58#ifndef FALSE 59#define FALSE 0 60#endif 61 62#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 63 64#define ALL_CHANNELS '\0' 65#define ALL_TARGETS_MASK 0xFFFF 66#define INITIATOR_WILDCARD (~0) 67 68#define SCSIID_TARGET(ahc, scsiid) \ 69 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 70 >> TID_SHIFT) 71#define SCSIID_OUR_ID(scsiid) \ 72 ((scsiid) & OID) 73#define SCSIID_CHANNEL(ahc, scsiid) \ 74 ((((ahc)->features & AHC_TWIN) != 0) \ 75 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 76 : 'A') 77#define SCB_IS_SCSIBUS_B(ahc, scb) \ 78 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 79#define SCB_GET_OUR_ID(scb) \ 80 SCSIID_OUR_ID((scb)->hscb->scsiid) 81#define SCB_GET_TARGET(ahc, scb) \ 82 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 83#define SCB_GET_CHANNEL(ahc, scb) \ 84 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 85#define SCB_GET_LUN(scb) \ 86 ((scb)->hscb->lun) 87#define SCB_GET_TARGET_OFFSET(ahc, scb) \ 88 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 89#define SCB_GET_TARGET_MASK(ahc, scb) \ 90 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 91#define TCL_TARGET_OFFSET(tcl) \ 92 ((((tcl) >> 4) & TID) >> 4) 93#define TCL_LUN(tcl) \ 94 (tcl & (AHC_NUM_LUNS - 1)) 95#define BUILD_TCL(scsiid, lun) \ 96 ((lun) | (((scsiid) & TID) << 4)) 97 98#ifndef AHC_TARGET_MODE 99#undef AHC_TMODE_ENABLE 100#define AHC_TMODE_ENABLE 0 101#endif 102 103/**************************** Driver Constants ********************************/ 104/* 105 * The maximum number of supported targets. 106 */ 107#define AHC_NUM_TARGETS 16 108 109/* 110 * The maximum number of supported luns. 111 * The identify message only supports 64 luns in SPI3. 112 * You can have 2^64 luns when information unit transfers are enabled, 113 * but it is doubtful this driver will ever support IUTs. 114 */ 115#define AHC_NUM_LUNS 64 116 117/* 118 * The maximum transfer per S/G segment. 119 */ 120#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 121 122/* 123 * The maximum amount of SCB storage in hardware on a controller. 124 * This value represents an upper bound. Controllers vary in the number 125 * they actually support. 126 */ 127#define AHC_SCB_MAX 255 128 129/* 130 * The maximum number of concurrent transactions supported per driver instance. 131 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 132 * the space for SCBs on the host adapter varies by model, the driver will 133 * page the SCBs between host and controller memory as needed. We are limited 134 * to 253 because: 135 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 136 * 2) We reserve one value, 255, to represent the invalid element. 137 * 3) Our input queue scheme requires one SCB to always be reserved 138 * in advance of queuing any SCBs. This takes us down to 254. 139 * 4) To handle our output queue correctly on machines that only 140 * support 32bit stores, we must clear the array 4 bytes at a 141 * time. To avoid colliding with a DMA write from the sequencer, 142 * we must be sure that 4 slots are empty when we write to clear 143 * the queue. This reduces us to 253 SCBs: 1 that just completed 144 * and the known three additional empty slots in the queue that 145 * preceed it. 146 */ 147#define AHC_MAX_QUEUE 253 148 149/* 150 * Ring Buffer of incoming target commands. 151 * We allocate 256 to simplify the logic in the sequencer 152 * by using the natural wrap point of an 8bit counter. 153 */ 154#define AHC_TMODE_CMDS 256 155 156/* Reset line assertion time in us */ 157#define AHC_BUSRESET_DELAY 250 158 159/******************* Chip Characteristics/Operating Settings *****************/ 160/* 161 * Chip Type 162 * The chip order is from least sophisticated to most sophisticated. 163 */ 164typedef enum { 165 AHC_NONE = 0x0000, 166 AHC_CHIPID_MASK = 0x00FF, 167 AHC_AIC7770 = 0x0001, 168 AHC_AIC7850 = 0x0002, 169 AHC_AIC7855 = 0x0003, 170 AHC_AIC7859 = 0x0004, 171 AHC_AIC7860 = 0x0005, 172 AHC_AIC7870 = 0x0006, 173 AHC_AIC7880 = 0x0007, 174 AHC_AIC7895 = 0x0008, 175 AHC_AIC7895C = 0x0009, 176 AHC_AIC7890 = 0x000a, 177 AHC_AIC7896 = 0x000b, 178 AHC_AIC7892 = 0x000c, 179 AHC_AIC7899 = 0x000d, 180 AHC_VL = 0x0100, /* Bus type VL */ 181 AHC_EISA = 0x0200, /* Bus type EISA */ 182 AHC_PCI = 0x0400, /* Bus type PCI */ 183 AHC_BUS_MASK = 0x0F00 184} ahc_chip; 185 186/* 187 * Features available in each chip type. 188 */ 189typedef enum { 190 AHC_FENONE = 0x00000, 191 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 192 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 193 AHC_WIDE = 0x00004, /* Wide Channel */ 194 AHC_TWIN = 0x00008, /* Twin Channel */ 195 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 196 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 197 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 198 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 199 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 200 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 201 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 202 AHC_DT = 0x00800, /* Double Transition transfers */ 203 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 204 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 205 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 206 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 207 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 208 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 209 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 210 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 211 AHC_AIC7770_FE = AHC_FENONE, 212 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE, 213 AHC_AIC7855_FE = AHC_AIC7850_FE, 214 AHC_AIC7860_FE = AHC_AIC7850_FE|AHC_ULTRA, 215 AHC_AIC7870_FE = AHC_TARGETMODE, 216 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 217 /* 218 * Although we have space for both the initiator and 219 * target roles on ULTRA2 chips, we currently disable 220 * the initiator role to allow multi-scsi-id target mode 221 * configurations. We can only respond on the same SCSI 222 * ID as our initiator role if we allow initiator operation. 223 * At some point, we should add a configuration knob to 224 * allow both roles to be loaded. 225 */ 226 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 227 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 228 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 229 |AHC_TARGETMODE, 230 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 231 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 232 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 233 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 234 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 235 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 236} ahc_feature; 237 238/* 239 * Bugs in the silicon that we work around in software. 240 */ 241typedef enum { 242 AHC_BUGNONE = 0x00, 243 /* 244 * On all chips prior to the U2 product line, 245 * the WIDEODD S/G segment feature does not 246 * work during scsi->HostBus transfers. 247 */ 248 AHC_TMODE_WIDEODD_BUG = 0x01, 249 /* 250 * On the aic7890/91 Rev 0 chips, the autoflush 251 * feature does not work. A manual flush of 252 * the DMA FIFO is required. 253 */ 254 AHC_AUTOFLUSH_BUG = 0x02, 255 /* 256 * On many chips, cacheline streaming does not work. 257 */ 258 AHC_CACHETHEN_BUG = 0x04, 259 /* 260 * On the aic7896/97 chips, cacheline 261 * streaming must be enabled. 262 */ 263 AHC_CACHETHEN_DIS_BUG = 0x08, 264 /* 265 * PCI 2.1 Retry failure on non-empty data fifo. 266 */ 267 AHC_PCI_2_1_RETRY_BUG = 0x10, 268 /* 269 * Controller does not handle cacheline residuals 270 * properly on S/G segments if PCI MWI instructions 271 * are allowed. 272 */ 273 AHC_PCI_MWI_BUG = 0x20, 274 /* 275 * An SCB upload using the SCB channel's 276 * auto array entry copy feature may 277 * corrupt data. This appears to only 278 * occur on 66MHz systems. 279 */ 280 AHC_SCBCHAN_UPLOAD_BUG = 0x40 281} ahc_bug; 282 283/* 284 * Configuration specific settings. 285 * The driver determines these settings by probing the 286 * chip/controller's configuration. 287 */ 288typedef enum { 289 AHC_FNONE = 0x000, 290 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 291 AHC_CHANNEL_B_PRIMARY = 0x002,/* 292 * On twin channel adapters, probe 293 * channel B first since it is the 294 * primary bus. 295 */ 296 AHC_USEDEFAULTS = 0x004,/* 297 * For cards without an seeprom 298 * or a BIOS to initialize the chip's 299 * SRAM, we use the default target 300 * settings. 301 */ 302 AHC_SEQUENCER_DEBUG = 0x008, 303 AHC_SHARED_SRAM = 0x010, 304 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 305 AHC_RESET_BUS_A = 0x040, 306 AHC_RESET_BUS_B = 0x080, 307 AHC_EXTENDED_TRANS_A = 0x100, 308 AHC_EXTENDED_TRANS_B = 0x200, 309 AHC_TERM_ENB_A = 0x400, 310 AHC_TERM_ENB_B = 0x800, 311 AHC_INITIATORROLE = 0x1000,/* 312 * Allow initiator operations on 313 * this controller. 314 */ 315 AHC_TARGETROLE = 0x2000,/* 316 * Allow target operations on this 317 * controller. 318 */ 319 AHC_NEWEEPROM_FMT = 0x4000, 320 AHC_RESOURCE_SHORTAGE = 0x8000, 321 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 322 AHC_INT50_SPEEDFLEX = 0x20000,/* 323 * Internal 50pin connector 324 * sits behind an aic3860 325 */ 326 AHC_SCB_BTT = 0x40000,/* 327 * The busy targets table is 328 * stored in SCB space rather 329 * than SRAM. 330 */ 331 AHC_BIOS_ENABLED = 0x80000, 332 AHC_ALL_INTERRUPTS = 0x100000 333} ahc_flag; 334 335/* 336 * Controller Information composed at probe time. 337 */ 338struct ahc_probe_config { 339 const char *description; 340 char channel; 341 char channel_b; 342 ahc_chip chip; 343 ahc_feature features; 344 ahc_bug bugs; 345 ahc_flag flags; 346}; 347 348/************************* Hardware SCB Definition ***************************/ 349 350/* 351 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 352 * consists of a "hardware SCB" mirroring the fields availible on the card 353 * and additional information the kernel stores for each transaction. 354 * 355 * To minimize space utilization, a portion of the hardware scb stores 356 * different data during different portions of a SCSI transaction. 357 * As initialized by the host driver for the initiator role, this area 358 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 359 * the cdb has been presented to the target, this area serves to store 360 * residual transfer information and the SCSI status byte. 361 * For the target role, the contents of this area do not change, but 362 * still serve a different purpose than for the initiator role. See 363 * struct target_data for details. 364 */ 365 366/* 367 * Status information embedded in the shared poriton of 368 * an SCB after passing the cdb to the target. The kernel 369 * driver will only read this data for transactions that 370 * complete abnormally (non-zero status byte). 371 */ 372struct status_pkt { 373 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 374 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 375 uint8_t scsi_status; /* Standard SCSI status byte */ 376}; 377 378/* 379 * Target mode version of the shared data SCB segment. 380 */ 381struct target_data { 382 uint8_t target_phases; /* Bitmap of phases to execute */ 383 uint8_t data_phase; /* Data-In or Data-Out */ 384 uint8_t scsi_status; /* SCSI status to give to initiator */ 385 uint8_t initiator_tag; /* Initiator's transaction tag */ 386}; 387 388struct hardware_scb { 389/*0*/ union { 390 /* 391 * If the cdb is 12 bytes or less, we embed it directly 392 * in the SCB. For longer cdbs, we embed the address 393 * of the cdb payload as seen by the chip and a DMA 394 * is used to pull it in. 395 */ 396 uint8_t cdb[12]; 397 uint32_t cdb_ptr; 398 struct status_pkt status; 399 struct target_data tdata; 400 } shared_data; 401/* 402 * A word about residuals. 403 * The scb is presented to the sequencer with the dataptr and datacnt 404 * fields initialized to the contents of the first S/G element to 405 * transfer. The sgptr field is initialized to the bus address for 406 * the S/G element that follows the first in the in core S/G array 407 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 408 * S/G entry for this transfer (single S/G element transfer with the 409 * first elements address and length preloaded in the dataptr/datacnt 410 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 411 * The SG_FULL_RESID flag ensures that the residual will be correctly 412 * noted even if no data transfers occur. Once the data phase is entered, 413 * the residual sgptr and datacnt are loaded from the sgptr and the 414 * datacnt fields. After each S/G element's dataptr and length are 415 * loaded into the hardware, the residual sgptr is advanced. After 416 * each S/G element is expired, its datacnt field is checked to see 417 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 418 * residual sg ptr and the transfer is considered complete. If the 419 * sequencer determines that there is a residual in the tranfer, it 420 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 421 * host memory. To sumarize: 422 * 423 * Sequencer: 424 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 425 * or residual_sgptr does not have SG_LIST_NULL set. 426 * 427 * o We are transfering the last segment if residual_datacnt has 428 * the SG_LAST_SEG flag set. 429 * 430 * Host: 431 * o A residual has occurred if a completed scb has the 432 * SG_RESID_VALID flag set. 433 * 434 * o residual_sgptr and sgptr refer to the "next" sg entry 435 * and so may point beyond the last valid sg entry for the 436 * transfer. 437 */ 438/*12*/ uint32_t dataptr; 439/*16*/ uint32_t datacnt; /* 440 * Byte 3 (numbered from 0) of 441 * the datacnt is really the 442 * 4th byte in that data address. 443 */ 444/*20*/ uint32_t sgptr; 445#define SG_PTR_MASK 0xFFFFFFF8 446/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 447/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 448/*26*/ uint8_t lun; 449/*27*/ uint8_t tag; /* 450 * Index into our kernel SCB array. 451 * Also used as the tag for tagged I/O 452 */ 453/*28*/ uint8_t cdb_len; 454/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 455/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 456/*31*/ uint8_t next; /* 457 * Used for threading SCBs in the 458 * "Waiting for Selection" and 459 * "Disconnected SCB" lists down 460 * in the sequencer. 461 */ 462/*32*/ uint8_t cdb32[32]; /* 463 * CDB storage for cdbs of size 464 * 13->32. We store them here 465 * because hardware scbs are 466 * allocated from DMA safe 467 * memory so we are guaranteed 468 * the controller can access 469 * this data. 470 */ 471}; 472 473/************************ Kernel SCB Definitions ******************************/ 474/* 475 * Some fields of the SCB are OS dependent. Here we collect the 476 * definitions for elements that all OS platforms need to include 477 * in there SCB definition. 478 */ 479 480/* 481 * Definition of a scatter/gather element as transfered to the controller. 482 * The aic7xxx chips only support a 24bit length. We use the top byte of 483 * the length to store additional address bits and a flag to indicate 484 * that a given segment terminates the transfer. This gives us an 485 * addressable range of 512GB on machines with 64bit PCI or with chips 486 * that can support dual address cycles on 32bit PCI busses. 487 */ 488struct ahc_dma_seg { 489 uint32_t addr; 490 uint32_t len; 491#define AHC_DMA_LAST_SEG 0x80000000 492#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 493#define AHC_SG_LEN_MASK 0x00FFFFFF 494}; 495 496/* 497 * The current state of this SCB. 498 */ 499typedef enum { 500 SCB_FREE = 0x0000, 501 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 502 * Another device was active 503 * during the first timeout for 504 * this SCB so we gave ourselves 505 * an additional timeout period 506 * in case it was hogging the 507 * bus. 508 */ 509 SCB_DEVICE_RESET = 0x0004, 510 SCB_SENSE = 0x0008, 511 SCB_CDB32_PTR = 0x0010, 512 SCB_RECOVERY_SCB = 0x0040, 513 SCB_NEGOTIATE = 0x0080, 514 SCB_ABORT = 0x1000, 515 SCB_UNTAGGEDQ = 0x2000, 516 SCB_ACTIVE = 0x4000, 517 SCB_TARGET_IMMEDIATE = 0x8000 518} scb_flag; 519 520struct scb { 521 struct hardware_scb *hscb; 522 union { 523 SLIST_ENTRY(scb) sle; 524 TAILQ_ENTRY(scb) tqe; 525 } links; 526 LIST_ENTRY(scb) pending_links; 527 ahc_io_ctx_t io_ctx; 528 struct ahc_softc *ahc_softc; 529 scb_flag flags; 530#ifndef __linux__ 531 bus_dmamap_t dmamap; 532#endif 533 struct scb_platform_data *platform_data; 534 struct ahc_dma_seg *sg_list; 535 bus_addr_t sg_list_phys; 536 u_int sg_count;/* How full ahc_dma_seg is */ 537}; 538 539struct sg_map_node { 540 bus_dmamap_t sg_dmamap; 541 bus_addr_t sg_physaddr; 542 struct ahc_dma_seg* sg_vaddr; 543 SLIST_ENTRY(sg_map_node) links; 544}; 545 546struct scb_data { 547 SLIST_HEAD(, scb) free_scbs; /* 548 * Pool of SCBs ready to be assigned 549 * commands to execute. 550 */ 551 struct scb *scbindex[AHC_SCB_MAX + 1];/* Mapping from tag to SCB */ 552 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 553 struct scb *scbarray; /* Array of kernel SCBs */ 554 struct scsi_sense_data *sense; /* Per SCB sense data */ 555 556 /* 557 * "Bus" addresses of our data structures. 558 */ 559 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 560 bus_dmamap_t hscb_dmamap; 561 bus_addr_t hscb_busaddr; 562 bus_dma_tag_t sense_dmat; 563 bus_dmamap_t sense_dmamap; 564 bus_addr_t sense_busaddr; 565 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 566 SLIST_HEAD(, sg_map_node) sg_maps; 567 uint8_t numscbs; 568 uint8_t maxhscbs; /* Number of SCBs on the card */ 569 uint8_t init_level; /* 570 * How far we've initialized 571 * this structure. 572 */ 573}; 574 575/************************ Target Mode Definitions *****************************/ 576 577/* 578 * Connection desciptor for select-in requests in target mode. 579 */ 580struct target_cmd { 581 uint8_t scsiid; /* Our ID and the initiator's ID */ 582 uint8_t identify; /* Identify message */ 583 uint8_t bytes[22]; /* 584 * Bytes contains any additional message 585 * bytes terminated by 0xFF. The remainder 586 * is the cdb to execute. 587 */ 588 uint8_t cmd_valid; /* 589 * When a command is complete, the firmware 590 * will set cmd_valid to all bits set. 591 * After the host has seen the command, 592 * the bits are cleared. This allows us 593 * to just peek at host memory to determine 594 * if more work is complete. cmd_valid is on 595 * an 8 byte boundary to simplify setting 596 * it on aic7880 hardware which only has 597 * limited direct access to the DMA FIFO. 598 */ 599 uint8_t pad[7]; 600}; 601 602/* 603 * Number of events we can buffer up if we run out 604 * of immediate notify ccbs. 605 */ 606#define AHC_TMODE_EVENT_BUFFER_SIZE 8 607struct ahc_tmode_event { 608 uint8_t initiator_id; 609 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 610#define EVENT_TYPE_BUS_RESET 0xFF 611 uint8_t event_arg; 612}; 613 614/* 615 * Per enabled lun target mode state. 616 * As this state is directly influenced by the host OS'es target mode 617 * environment, we let the OS module define it. Forward declare the 618 * structure here so we can store arrays of them, etc. in OS neutral 619 * data structures. 620 */ 621#ifdef AHC_TARGET_MODE 622struct tmode_lstate { 623 struct cam_path *path; 624 struct ccb_hdr_slist accept_tios; 625 struct ccb_hdr_slist immed_notifies; 626 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 627 uint8_t event_r_idx; 628 uint8_t event_w_idx; 629}; 630#else 631struct tmode_lstate; 632#endif 633 634/******************** Transfer Negotiation Datastructures *********************/ 635#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 636#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 637#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 638#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 639 640/* 641 * Transfer Negotiation Information. 642 */ 643struct ahc_transinfo { 644 uint8_t protocol_version; /* SCSI Revision level */ 645 uint8_t transport_version; /* SPI Revision level */ 646 uint8_t width; /* Bus width */ 647 uint8_t period; /* Sync rate factor */ 648 uint8_t offset; /* Sync offset */ 649 uint8_t ppr_options; /* Parallel Protocol Request options */ 650}; 651 652/* 653 * Per-initiator current, goal and user transfer negotiation information. */ 654struct ahc_initiator_tinfo { 655 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 656 struct ahc_transinfo current; 657 struct ahc_transinfo goal; 658 struct ahc_transinfo user; 659}; 660 661/* 662 * Per enabled target ID state. 663 * Pointers to lun target state as well as sync/wide negotiation information 664 * for each initiator<->target mapping. For the initiator role we pretend 665 * that we are the target and the targets are the initiators since the 666 * negotiation is the same regardless of role. 667 */ 668struct tmode_tstate { 669 struct tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 670 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 671 672 /* 673 * Per initiator state bitmasks. 674 */ 675 uint16_t ultraenb; /* Using ultra sync rate */ 676 uint16_t discenable; /* Disconnection allowed */ 677 uint16_t tagenable; /* Tagged Queuing allowed */ 678}; 679 680/* 681 * Data structure for our table of allowed synchronous transfer rates. 682 */ 683struct ahc_syncrate { 684 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 685 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 686#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 687#define ST_SXFR 0x010 /* Rate Single Transition Only */ 688#define DT_SXFR 0x040 /* Rate Double Transition Only */ 689 uint8_t period; /* Period to send to SCSI target */ 690 char *rate; 691}; 692 693/* 694 * The synchronouse transfer rate table. 695 */ 696extern struct ahc_syncrate ahc_syncrates[]; 697 698/* 699 * Indexes into our table of syncronous transfer rates. 700 */ 701#define AHC_SYNCRATE_DT 0 702#define AHC_SYNCRATE_ULTRA2 1 703#define AHC_SYNCRATE_ULTRA 3 704#define AHC_SYNCRATE_FAST 6 705 706/***************************** Lookup Tables **********************************/ 707/* 708 * Textual descriptions of the different chips indexed by chip type. 709 */ 710extern char *ahc_chip_names[]; 711extern const u_int num_chip_names; 712 713/* 714 * Hardware error codes. 715 */ 716struct hard_error_entry { 717 uint8_t errno; 718 char *errmesg; 719}; 720extern struct hard_error_entry hard_error[]; 721extern const u_int num_errors; 722 723/* 724 * Phase -> name and message out response 725 * to parity errors in each phase table. 726 */ 727struct phase_table_entry { 728 uint8_t phase; 729 uint8_t mesg_out; /* Message response to parity errors */ 730 char *phasemsg; 731}; 732extern struct phase_table_entry phase_table[]; 733extern const u_int num_phases; 734 735/************************** Serial EEPROM Format ******************************/ 736 737struct seeprom_config { 738/* 739 * Per SCSI ID Configuration Flags 740 */ 741 uint16_t device_flags[16]; /* words 0-15 */ 742#define CFXFER 0x0007 /* synchronous transfer rate */ 743#define CFSYNCH 0x0008 /* enable synchronous transfer */ 744#define CFDISC 0x0010 /* enable disconnection */ 745#define CFWIDEB 0x0020 /* wide bus device */ 746#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 747#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 748#define CFSTART 0x0100 /* send start unit SCSI command */ 749#define CFINCBIOS 0x0200 /* include in BIOS scan */ 750#define CFRNFOUND 0x0400 /* report even if not found */ 751#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 752#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 753#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 754 755/* 756 * BIOS Control Bits 757 */ 758 uint16_t bios_control; /* word 16 */ 759#define CFSUPREM 0x0001 /* support all removeable drives */ 760#define CFSUPREMB 0x0002 /* support removeable boot drives */ 761#define CFBIOSEN 0x0004 /* BIOS enabled */ 762/* UNUSED 0x0008 */ 763#define CFSM2DRV 0x0010 /* support more than two drives */ 764#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 765#define CFSTPWLEVEL 0x0010 /* Termination level control */ 766#define CFEXTEND 0x0080 /* extended translation enabled */ 767#define CFSCAMEN 0x0100 /* SCAM enable */ 768/* UNUSED 0xff00 */ 769 770/* 771 * Host Adapter Control Bits 772 */ 773 uint16_t adapter_control; /* word 17 */ 774#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 775#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 776#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 777#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 778#define CFSTERM 0x0004 /* SCSI low byte termination */ 779#define CFWSTERM 0x0008 /* SCSI high byte termination */ 780#define CFSPARITY 0x0010 /* SCSI parity */ 781#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 782#define CFMULTILUN 0x0020 /* SCSI low byte term (284x cards) */ 783#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 784#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 785#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 786#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 787#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 788#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 789#define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 790 791/* 792 * Bus Release Time, Host Adapter ID 793 */ 794 uint16_t brtime_id; /* word 18 */ 795#define CFSCSIID 0x000f /* host adapter SCSI ID */ 796/* UNUSED 0x00f0 */ 797#define CFBRTIME 0xff00 /* bus release time */ 798 799/* 800 * Maximum targets 801 */ 802 uint16_t max_targets; /* word 19 */ 803#define CFMAXTARG 0x00ff /* maximum targets */ 804#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 805#define CFBOOTID 0xf000 /* Target to boot from */ 806 uint16_t res_1[10]; /* words 20-29 */ 807 uint16_t signature; /* Signature == 0x250 */ 808#define CFSIGNATURE 0x250 809 uint16_t checksum; /* word 31 */ 810}; 811 812/**************************** Message Buffer *********************************/ 813typedef enum { 814 MSG_TYPE_NONE = 0x00, 815 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 816 MSG_TYPE_INITIATOR_MSGIN = 0x02, 817 MSG_TYPE_TARGET_MSGOUT = 0x03, 818 MSG_TYPE_TARGET_MSGIN = 0x04 819} ahc_msg_type; 820 821typedef enum { 822 MSGLOOP_IN_PROG, 823 MSGLOOP_MSGCOMPLETE, 824 MSGLOOP_TERMINATED 825} msg_loop_stat; 826 827/*********************** Software Configuration Structure *********************/ 828TAILQ_HEAD(scb_tailq, scb); 829 830struct ahc_suspend_channel_state { 831 uint8_t scsiseq; 832 uint8_t sxfrctl0; 833 uint8_t sxfrctl1; 834 uint8_t simode0; 835 uint8_t simode1; 836 uint8_t seltimer; 837 uint8_t seqctl; 838}; 839 840struct ahc_suspend_state { 841 struct ahc_suspend_channel_state channel[2]; 842 uint8_t optionmode; 843 uint8_t dscommand0; 844 uint8_t dspcistatus; 845 /* hsmailbox */ 846 uint8_t crccontrol1; 847 uint8_t scbbaddr; 848 /* Host and sequencer SCB counts */ 849 uint8_t dff_thrsh; 850 uint8_t *scratch_ram; 851 uint8_t *btt; 852}; 853 854struct ahc_softc { 855 bus_space_tag_t tag; 856 bus_space_handle_t bsh; 857#ifndef __linux__ 858 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 859#endif 860 struct scb_data *scb_data; 861 862 struct scb *next_queued_scb; 863 864 /* 865 * SCBs that have been sent to the controller 866 */ 867 LIST_HEAD(, scb) pending_scbs; 868 869 /* 870 * Counting lock for deferring the release of additional 871 * untagged transactions from the untagged_queues. When 872 * the lock is decremented to 0, all queues in the 873 * untagged_queues array are run. 874 */ 875 u_int untagged_queue_lock; 876 877 /* 878 * Per-target queue of untagged-transactions. The 879 * transaction at the head of the queue is the 880 * currently pending untagged transaction for the 881 * target. The driver only allows a single untagged 882 * transaction per target. 883 */ 884 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 885 886 /* 887 * Platform specific data. 888 */ 889 struct ahc_platform_data *platform_data; 890 891 /* 892 * Platform specific device information. 893 */ 894 ahc_dev_softc_t dev_softc; 895 896 /* 897 * Target mode related state kept on a per enabled lun basis. 898 * Targets that are not enabled will have null entries. 899 * As an initiator, we keep one target entry for our initiator 900 * ID to store our sync/wide transfer settings. 901 */ 902 struct tmode_tstate* enabled_targets[AHC_NUM_TARGETS]; 903 904 /* 905 * The black hole device responsible for handling requests for 906 * disabled luns on enabled targets. 907 */ 908 struct tmode_lstate* black_hole; 909 910 /* 911 * Device instance currently on the bus awaiting a continue TIO 912 * for a command that was not given the disconnect priveledge. 913 */ 914 struct tmode_lstate* pending_device; 915 916 /* 917 * Card characteristics 918 */ 919 ahc_chip chip; 920 ahc_feature features; 921 ahc_bug bugs; 922 ahc_flag flags; 923 924 /* Values to store in the SEQCTL register for pause and unpause */ 925 uint8_t unpause; 926 uint8_t pause; 927 928 /* Command Queues */ 929 uint8_t qoutfifonext; 930 uint8_t qinfifonext; 931 uint8_t *qoutfifo; 932 uint8_t *qinfifo; 933 934 /* Critical Section Data */ 935 struct cs *critical_sections; 936 u_int num_critical_sections; 937 938 /* Links for chaining softcs */ 939 TAILQ_ENTRY(ahc_softc) links; 940 941 /* Channel Names ('A', 'B', etc.) */ 942 char channel; 943 char channel_b; 944 945 /* Initiator Bus ID */ 946 uint8_t our_id; 947 uint8_t our_id_b; 948 949 /* Targets that need negotiation messages */ 950 uint16_t targ_msg_req; 951 952 /* 953 * PCI error detection. 954 */ 955 int unsolicited_ints; 956 957 /* 958 * Target incoming command FIFO. 959 */ 960 struct target_cmd *targetcmds; 961 uint8_t tqinfifonext; 962 963 /* 964 * Incoming and outgoing message handling. 965 */ 966 uint8_t send_msg_perror; 967 ahc_msg_type msg_type; 968 uint8_t msgout_buf[12];/* Message we are sending */ 969 uint8_t msgin_buf[12];/* Message we are receiving */ 970 u_int msgout_len; /* Length of message to send */ 971 u_int msgout_index; /* Current index in msgout */ 972 u_int msgin_index; /* Current index in msgin */ 973 974 /* 975 * Mapping information for data structures shared 976 * between the sequencer and kernel. 977 */ 978 bus_dma_tag_t parent_dmat; 979 bus_dma_tag_t shared_data_dmat; 980 bus_dmamap_t shared_data_dmamap; 981 bus_addr_t shared_data_busaddr; 982 983 /* 984 * Bus address of the one byte buffer used to 985 * work-around a DMA bug for chips <= aic7880 986 * in target mode. 987 */ 988 bus_addr_t dma_bug_buf; 989 990 /* Information saved through suspend/resume cycles */ 991 struct ahc_suspend_state suspend_state; 992 993 /* Number of enabled target mode device on this card */ 994 u_int enabled_luns; 995 996 /* Initialization level of this data structure */ 997 u_int init_level; 998 999 /* PCI cacheline size. */ 1000 u_int pci_cachesize; 1001 1002 /* Per-Unit descriptive information */ 1003 const char *description; 1004 char *name; 1005 int unit; 1006 1007 /* Selection Timer settings */ 1008 int seltime; 1009 int seltime_b; 1010 1011 uint16_t user_discenable;/* Disconnection allowed */ 1012 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1013}; 1014 1015TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1016extern struct ahc_softc_tailq ahc_tailq; 1017 1018/************************ Active Device Information ***************************/ 1019typedef enum { 1020 ROLE_UNKNOWN, 1021 ROLE_INITIATOR, 1022 ROLE_TARGET 1023} role_t; 1024 1025struct ahc_devinfo { 1026 int our_scsiid; 1027 int target_offset; 1028 uint16_t target_mask; 1029 u_int target; 1030 u_int lun; 1031 char channel; 1032 role_t role; /* 1033 * Only guaranteed to be correct if not 1034 * in the busfree state. 1035 */ 1036}; 1037 1038/****************************** PCI Structures ********************************/ 1039typedef int (ahc_device_setup_t)(ahc_dev_softc_t, 1040 struct ahc_probe_config *); 1041 1042struct ahc_pci_identity { 1043 uint64_t full_id; 1044 uint64_t id_mask; 1045 char *name; 1046 ahc_device_setup_t *setup; 1047}; 1048extern struct ahc_pci_identity ahc_pci_ident_table []; 1049extern const u_int ahc_num_pci_devs; 1050 1051/***************************** VL/EISA Declarations ***************************/ 1052struct aic7770_identity { 1053 uint32_t full_id; 1054 uint32_t id_mask; 1055 char *name; 1056 ahc_device_setup_t *setup; 1057}; 1058extern struct aic7770_identity aic7770_ident_table []; 1059extern const int ahc_num_aic7770_devs; 1060 1061#define AHC_EISA_SLOT_OFFSET 0xc00 1062#define AHC_EISA_IOSIZE 0x100 1063 1064/*************************** Function Declarations ****************************/ 1065/******************************************************************************/ 1066u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1067void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1068void ahc_busy_tcl(struct ahc_softc *ahc, 1069 u_int tcl, u_int busyid); 1070 1071/***************************** PCI Front End *********************************/ 1072struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1073int ahc_pci_config(struct ahc_softc *, 1074 struct ahc_pci_identity *); 1075 1076/*************************** EISA/VL Front End ********************************/ 1077struct aic7770_identity *aic7770_find_device(uint32_t); 1078int aic7770_config(struct ahc_softc *ahc, 1079 struct aic7770_identity *); 1080 1081/************************** SCB and SCB queue management **********************/ 1082int ahc_probe_scbs(struct ahc_softc *); 1083void ahc_run_untagged_queues(struct ahc_softc *ahc); 1084void ahc_run_untagged_queue(struct ahc_softc *ahc, 1085 struct scb_tailq *queue); 1086void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1087 struct scb *scb); 1088int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1089 int target, char channel, int lun, 1090 u_int tag, role_t role); 1091 1092/****************************** Initialization ********************************/ 1093void ahc_init_probe_config(struct ahc_probe_config *); 1094struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1095int ahc_softc_init(struct ahc_softc *, 1096 struct ahc_probe_config*); 1097void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1098int ahc_init(struct ahc_softc *ahc); 1099void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1100int ahc_suspend(struct ahc_softc *ahc); 1101int ahc_resume(struct ahc_softc *ahc); 1102void ahc_softc_insert(struct ahc_softc *); 1103void ahc_set_unit(struct ahc_softc *, int); 1104void ahc_set_name(struct ahc_softc *, char *); 1105void ahc_alloc_scbs(struct ahc_softc *ahc); 1106void ahc_free(struct ahc_softc *ahc); 1107int ahc_reset(struct ahc_softc *ahc); 1108void ahc_shutdown(void *arg); 1109 1110/*************************** Interrupt Services *******************************/ 1111void ahc_pci_intr(struct ahc_softc *ahc); 1112void ahc_clear_intstat(struct ahc_softc *ahc); 1113void ahc_run_qoutfifo(struct ahc_softc *ahc); 1114#ifdef AHC_TARGET_MODE 1115void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1116#endif 1117void ahc_handle_brkadrint(struct ahc_softc *ahc); 1118void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1119void ahc_handle_scsiint(struct ahc_softc *ahc, 1120 u_int intstat); 1121void ahc_clear_critical_section(struct ahc_softc *ahc); 1122 1123/***************************** Error Recovery *********************************/ 1124typedef enum { 1125 SEARCH_COMPLETE, 1126 SEARCH_COUNT, 1127 SEARCH_REMOVE 1128} ahc_search_action; 1129int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1130 char channel, int lun, u_int tag, 1131 role_t role, uint32_t status, 1132 ahc_search_action action); 1133int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1134 char channel, int lun, u_int tag, 1135 int stop_on_first, int remove, 1136 int save_state); 1137void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1138int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1139 int initiate_reset); 1140void restart_sequencer(struct ahc_softc *ahc); 1141/*************************** Utility Functions ********************************/ 1142void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1143 u_int our_id, u_int target, 1144 u_int lun, char channel, 1145 role_t role); 1146/************************** Transfer Negotiation ******************************/ 1147struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1148 u_int *ppr_options, u_int maxsync); 1149u_int ahc_find_period(struct ahc_softc *ahc, 1150 u_int scsirate, u_int maxsync); 1151void ahc_validate_offset(struct ahc_softc *ahc, 1152 struct ahc_initiator_tinfo *tinfo, 1153 struct ahc_syncrate *syncrate, 1154 u_int *offset, int wide, 1155 role_t role); 1156void ahc_validate_width(struct ahc_softc *ahc, 1157 struct ahc_initiator_tinfo *tinfo, 1158 u_int *bus_width, 1159 role_t role); 1160void ahc_update_target_msg_request(struct ahc_softc *ahc, 1161 struct ahc_devinfo *dinfo, 1162 struct ahc_initiator_tinfo *tinfo, 1163 int force, int paused); 1164void ahc_set_width(struct ahc_softc *ahc, 1165 struct ahc_devinfo *devinfo, 1166 u_int width, u_int type, int paused); 1167void ahc_set_syncrate(struct ahc_softc *ahc, 1168 struct ahc_devinfo *devinfo, 1169 struct ahc_syncrate *syncrate, 1170 u_int period, u_int offset, 1171 u_int ppr_options, 1172 u_int type, int paused); 1173void ahc_set_tags(struct ahc_softc *ahc, 1174 struct ahc_devinfo *devinfo, int enable); 1175 1176/**************************** Target Mode *************************************/ 1177#ifdef AHC_TARGET_MODE 1178void ahc_send_lstate_events(struct ahc_softc *, 1179 struct tmode_lstate *); 1180void ahc_handle_en_lun(struct ahc_softc *ahc, 1181 struct cam_sim *sim, union ccb *ccb); 1182cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1183 struct cam_sim *sim, union ccb *ccb, 1184 struct tmode_tstate **tstate, 1185 struct tmode_lstate **lstate, 1186 int notfound_failure); 1187void ahc_setup_target_msgin(struct ahc_softc *ahc, 1188 struct ahc_devinfo *devinfo); 1189#ifndef AHC_TMODE_ENABLE 1190#define AHC_TMODE_ENABLE 0 1191#endif 1192#endif 1193/******************************* Debug ***************************************/ 1194void ahc_print_scb(struct scb *scb); 1195void ahc_dump_card_state(struct ahc_softc *ahc); 1196#endif /* _AIC7XXX_H_ */ 1197