aic7xxx.h revision 66269
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.h#4 $ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 66269 2000-09-22 22:18:05Z gibbs $ 34 */ 35 36#ifndef _AIC7XXX_H_ 37#define _AIC7XXX_H_ 38 39/* Register Definitions */ 40#include "aic7xxx_reg.h" 41 42/************************* Forward Declarations *******************************/ 43struct ahc_platform_data; 44struct scb_platform_data; 45 46/****************************** Useful Macros *********************************/ 47#ifndef MAX 48#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 49#endif 50 51#ifndef MIN 52#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 53#endif 54 55#ifndef TRUE 56#define TRUE 1 57#endif 58#ifndef FALSE 59#define FALSE 0 60#endif 61 62#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 63 64#define ALL_CHANNELS '\0' 65#define ALL_TARGETS_MASK 0xFFFF 66#define INITIATOR_WILDCARD (~0) 67 68#define SCSIID_TARGET(ahc, scsiid) \ 69 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 70 >> TID_SHIFT) 71#define SCSIID_OUR_ID(scsiid) \ 72 ((scsiid) & OID) 73#define SCSIID_CHANNEL(ahc, scsiid) \ 74 ((((ahc)->features & AHC_TWIN) != 0) \ 75 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 76 : 'A') 77#define SCB_IS_SCSIBUS_B(ahc, scb) \ 78 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 79#define SCB_GET_OUR_ID(scb) \ 80 SCSIID_OUR_ID((scb)->hscb->scsiid) 81#define SCB_GET_TARGET(ahc, scb) \ 82 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 83#define SCB_GET_CHANNEL(ahc, scb) \ 84 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 85#define SCB_GET_LUN(scb) \ 86 ((scb)->hscb->lun) 87#define SCB_GET_TARGET_OFFSET(ahc, scb) \ 88 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 89#define SCB_GET_TARGET_MASK(ahc, scb) \ 90 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 91#define TCL_TARGET_OFFSET(tcl) \ 92 ((((tcl) >> 4) & TID) >> 4) 93#define TCL_LUN(tcl) \ 94 (tcl & (AHC_NUM_LUNS - 1)) 95#define BUILD_TCL(scsiid, lun) \ 96 ((lun) | (((scsiid) & TID) << 4)) 97 98/**************************** Driver Constants ********************************/ 99/* 100 * The maximum number of supported targets. 101 */ 102#define AHC_NUM_TARGETS 16 103 104/* 105 * The maximum number of supported luns. 106 * Although the identify message only supports 64 luns in SPI3, you 107 * can have 2^64 luns when information unit transfers are enabled. 108 * The max we can do sanely given the 8bit nature of the RISC engine 109 * on these chips is 256. 110 */ 111#define AHC_NUM_LUNS 256 112 113/* 114 * The maximum transfer per S/G segment. 115 */ 116#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 117 118/* 119 * The maximum number of concurrent transactions supported per driver instance. 120 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 121 * the space for SCBs on the host adapter varies by model, the driver will 122 * page the SCBs between host and controller memory as needed. We are limited 123 * to 255 because of the 8bit nature of the RISC engine and the need to 124 * reserve the value of 255 as a "No Transaction" value. 125 */ 126#define AHC_SCB_MAX 255 127 128/* 129 * Ring Buffer of incoming target commands. 130 * We allocate 256 to simplify the logic in the sequencer 131 * by using the natural wrap point of an 8bit counter. 132 */ 133#define AHC_TMODE_CMDS 256 134 135/* Reset line assertion time in us */ 136#define AHC_BUSRESET_DELAY 250 137 138/******************* Chip Characteristics/Operating Settings *****************/ 139/* 140 * Chip Type 141 * The chip order is from least sophisticated to most sophisticated. 142 */ 143typedef enum { 144 AHC_NONE = 0x0000, 145 AHC_CHIPID_MASK = 0x00FF, 146 AHC_AIC7770 = 0x0001, 147 AHC_AIC7850 = 0x0002, 148 AHC_AIC7855 = 0x0003, 149 AHC_AIC7859 = 0x0004, 150 AHC_AIC7860 = 0x0005, 151 AHC_AIC7870 = 0x0006, 152 AHC_AIC7880 = 0x0007, 153 AHC_AIC7895 = 0x0008, 154 AHC_AIC7895C = 0x0009, 155 AHC_AIC7890 = 0x000a, 156 AHC_AIC7896 = 0x000b, 157 AHC_AIC7892 = 0x000c, 158 AHC_AIC7899 = 0x000d, 159 AHC_VL = 0x0100, /* Bus type VL */ 160 AHC_EISA = 0x0200, /* Bus type EISA */ 161 AHC_PCI = 0x0400, /* Bus type PCI */ 162 AHC_BUS_MASK = 0x0F00 163} ahc_chip; 164 165/* 166 * Features available in each chip type. 167 */ 168typedef enum { 169 AHC_FENONE = 0x00000, 170 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 171 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 172 AHC_WIDE = 0x00004, /* Wide Channel */ 173 AHC_TWIN = 0x00008, /* Twin Channel */ 174 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 175 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 176 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 177 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 178 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 179 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 180 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 181 AHC_DT = 0x00800, /* Double Transition transfers */ 182 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 183 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 184 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 185 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 186 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 187 AHC_AIC7770_FE = AHC_FENONE, 188 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE, 189 AHC_AIC7855_FE = AHC_AIC7850_FE, 190 AHC_AIC7860_FE = AHC_AIC7850_FE|AHC_ULTRA, 191 AHC_AIC7870_FE = AHC_FENONE, 192 AHC_AIC7880_FE = AHC_ULTRA, 193 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 194 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 195 |AHC_NEW_TERMCTL|AHC_LARGE_SCBS, 196 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 197 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 198 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 199 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 200 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 201 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 202} ahc_feature; 203 204/* 205 * Bugs in the silicon that we work around in software. 206 */ 207typedef enum { 208 AHC_BUGNONE = 0x00, 209 /* 210 * On all chips prior to the U2 product line, 211 * the WIDEODD S/G segment feature does not 212 * work during scsi->HostBus transfers. 213 */ 214 AHC_TMODE_WIDEODD_BUG = 0x01, 215 /* 216 * On the aic7890/91 Rev 0 chips, the autoflush 217 * feature does not work. A manual flush of 218 * the DMA FIFO is required. 219 */ 220 AHC_AUTOFLUSH_BUG = 0x02, 221 /* 222 * On many chips, cacheline streaming does not work. 223 */ 224 AHC_CACHETHEN_BUG = 0x04, 225 /* 226 * On the aic7896/97 chips, cacheline 227 * streaming must be enabled. 228 */ 229 AHC_CACHETHEN_DIS_BUG = 0x08, 230 /* 231 * PCI 2.1 Retry failure on non-empty data fifo. 232 */ 233 AHC_PCI_2_1_RETRY_BUG = 0x10, 234 /* 235 * Controller does not handle cacheline residuals 236 * properly on S/G segments if PCI MWI instructions 237 * are allowed. 238 */ 239 AHC_PCI_MWI_BUG = 0x20, 240 /* 241 * An SCB upload using the SCB channel's 242 * auto array entry copy feature may 243 * corrupt data. This appears to only 244 * occur on 66MHz systems. 245 */ 246 AHC_SCBCHAN_UPLOAD_BUG = 0x40 247} ahc_bug; 248 249/* 250 * Configuration specific settings. 251 * The driver determines these settings by probing the 252 * chip/controller's configuration. 253 */ 254typedef enum { 255 AHC_FNONE = 0x000, 256 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 257 AHC_CHANNEL_B_PRIMARY = 0x002,/* 258 * On twin channel adapters, probe 259 * channel B first since it is the 260 * primary bus. 261 */ 262 AHC_USEDEFAULTS = 0x004,/* 263 * For cards without an seeprom 264 * or a BIOS to initialize the chip's 265 * SRAM, we use the default target 266 * settings. 267 */ 268 AHC_SHARED_SRAM = 0x010, 269 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 270 AHC_RESET_BUS_A = 0x040, 271 AHC_RESET_BUS_B = 0x080, 272 AHC_EXTENDED_TRANS_A = 0x100, 273 AHC_EXTENDED_TRANS_B = 0x200, 274 AHC_TERM_ENB_A = 0x400, 275 AHC_TERM_ENB_B = 0x800, 276 AHC_INITIATORMODE = 0x1000,/* 277 * Allow initiator operations on 278 * this controller. 279 */ 280 AHC_TARGETMODE = 0x2000,/* 281 * Allow target operations on this 282 * controller. 283 */ 284 AHC_NEWEEPROM_FMT = 0x4000, 285 AHC_RESOURCE_SHORTAGE = 0x8000, 286 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 287 AHC_INT50_SPEEDFLEX = 0x20000,/* 288 * Internal 50pin connector 289 * sits behind an aic3860 290 */ 291 AHC_SCB_BTT = 0x40000,/* 292 * The busy targets table is 293 * stored in SCB space rather 294 * than SRAM. 295 */ 296 AHC_BIOS_ENABLED = 0x80000 297} ahc_flag; 298 299/* 300 * Controller Information composed at probe time. 301 */ 302struct ahc_probe_config { 303 const char *description; 304 char channel; 305 char channel_b; 306 ahc_chip chip; 307 ahc_feature features; 308 ahc_bug bugs; 309 ahc_flag flags; 310}; 311 312/************************* Hardware SCB Definition ***************************/ 313 314/* 315 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 316 * consists of a "hardware SCB" mirroring the fields availible on the card 317 * and additional information the kernel stores for each transaction. 318 * 319 * To minimize space utilization, a portion of the hardware scb stores 320 * different data during different portions of a SCSI transaction. 321 * As initialized by the host driver for the initiator role, this area 322 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 323 * the cdb has been presented to the target, this area serves to store 324 * residual transfer information and the SCSI status byte. 325 * For the target role, the contents of this area do not change, but 326 * still serve a different purpose than for the initiator role. See 327 * struct target_data for details. 328 */ 329 330/* 331 * Status information embedded in the shared poriton of 332 * an SCB after passing the cdb to the target. The kernel 333 * driver will only read this data for transactions that 334 * complete abnormally (non-zero status byte). 335 */ 336struct status_pkt { 337 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 338 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 339 uint8_t scsi_status; /* Standard SCSI status byte */ 340}; 341 342/* 343 * Target mode version of the shared data SCB segment. 344 */ 345struct target_data { 346 uint8_t target_phases; /* Bitmap of phases to execute */ 347 uint8_t data_phase; /* Data-In or Data-Out */ 348 uint8_t scsi_status; /* SCSI status to give to initiator */ 349 uint8_t initiator_tag; /* Initiator's transaction tag */ 350}; 351 352struct hardware_scb { 353/*0*/ union { 354 /* 355 * If the cdb is 12 bytes or less, we embed it directly 356 * in the SCB. For longer cdbs, we embed the address 357 * of the cdb payload as seen by the chip and a DMA 358 * is used to pull it in. 359 */ 360 uint8_t cdb[12]; 361 uint32_t cdb_ptr; 362 struct status_pkt status; 363 struct target_data tdata; 364 } shared_data; 365/* 366 * A word about residuals. 367 * The scb is presented to the sequencer with the dataptr and datacnt 368 * fields initialized to the contents of the first S/G element to 369 * transfer. The sgptr field is initialized to the bus address for 370 * the S/G element that follows the first in the in core S/G array 371 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 372 * S/G entry for this transfer (single S/G element transfer with the 373 * first elements address and length preloaded in the dataptr/datacnt 374 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 375 * The SG_FULL_RESID flag ensures that the residual will be correctly 376 * noted even if no data transfers occur. Once the data phase is entered, 377 * the residual sgptr and datacnt are loaded from the sgptr and the 378 * datacnt fields. After each S/G element's dataptr and length are 379 * loaded into the hardware, the residual sgptr is advanced. After 380 * each S/G element is expired, its datacnt field is checked to see 381 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 382 * residual sg ptr and the transfer is considered complete. If the 383 * sequencer determines that there is a residual in the tranfer, it 384 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 385 * host memory. To sumarize: 386 * 387 * Sequencer: 388 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 389 * or residual_sgptr does not have SG_LIST_NULL set. 390 * 391 * o We are transfering the last segment if residual_datacnt has 392 * the SG_LAST_SEG flag set. 393 * 394 * Host: 395 * o A residual has occurred if a completed scb has the 396 * SG_RESID_VALID flag set. 397 * 398 * o residual_sgptr and sgptr refer to the "next" sg entry 399 * and so may point beyond the last valid sg entry for the 400 * transfer. 401 */ 402/*12*/ uint32_t dataptr; 403/*16*/ uint32_t datacnt; /* 404 * Byte 3 (numbered from 0) of 405 * the datacnt is really the 406 * 4th byte in that data address. 407 */ 408/*20*/ uint32_t sgptr; 409#define SG_PTR_MASK 0xFFFFFFF8 410/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 411/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 412/*26*/ uint8_t lun; 413/*27*/ uint8_t tag; /* 414 * Index into our kernel SCB array. 415 * Also used as the tag for tagged I/O 416 */ 417/*28*/ uint8_t cdb_len; 418/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 419/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 420/*31*/ uint8_t next; /* 421 * Used for threading SCBs in the 422 * "Waiting for Selection" and 423 * "Disconnected SCB" lists down 424 * in the sequencer. 425 */ 426/*32*/ uint8_t cdb32[32]; /* 427 * CDB storage for cdbs of size 428 * 13->32. We store them here 429 * because hardware scbs are 430 * allocated from DMA safe 431 * memory so we are guaranteed 432 * the controller can access 433 * this data. 434 */ 435}; 436 437/************************ Kernel SCB Definitions ******************************/ 438/* 439 * Some fields of the SCB are OS dependent. Here we collect the 440 * definitions for elements that all OS platforms need to include 441 * in there SCB definition. 442 */ 443 444/* 445 * Definition of a scatter/gather element as transfered to the controller. 446 * The aic7xxx chips only support a 24bit length. We use the top byte of 447 * the length to store additional address bits and a flag to indicate 448 * that a given segment terminates the transfer. This gives us an 449 * addressable range of 512GB on machines with 64bit PCI or with chips 450 * that can support dual address cycles on 32bit PCI busses. 451 */ 452struct ahc_dma_seg { 453 uint32_t addr; 454 uint32_t len; 455#define AHC_DMA_LAST_SEG 0x80000000 456#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 457#define AHC_SG_LEN_MASK 0x00FFFFFF 458}; 459 460/* 461 * The current state of this SCB. 462 */ 463typedef enum { 464 SCB_FREE = 0x0000, 465 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 466 * Another device was active 467 * during the first timeout for 468 * this SCB so we gave ourselves 469 * an additional timeout period 470 * in case it was hogging the 471 * bus. 472 */ 473 SCB_DEVICE_RESET = 0x0004, 474 SCB_SENSE = 0x0008, 475 SCB_RECOVERY_SCB = 0x0040, 476 SCB_NEGOTIATE = 0x0080, 477 SCB_ABORT = 0x1000, 478 SCB_QUEUED_MSG = 0x2000, 479 SCB_ACTIVE = 0x4000, 480 SCB_TARGET_IMMEDIATE = 0x8000 481} scb_flag; 482 483struct scb { 484 struct hardware_scb *hscb; 485 union { 486 SLIST_ENTRY(scb) sle; 487 TAILQ_ENTRY(scb) tqe; 488 } links; 489 LIST_ENTRY(scb) pending_links; 490 ahc_io_ctx_t io_ctx; 491 scb_flag flags; 492#ifndef __linux__ 493 bus_dmamap_t dmamap; 494#endif 495 struct scb_platform_data *platform_data; 496 struct ahc_dma_seg *sg_list; 497 bus_addr_t sg_list_phys; 498 bus_addr_t cdb32_busaddr; 499 u_int sg_count;/* How full ahc_dma_seg is */ 500}; 501 502struct sg_map_node { 503 bus_dmamap_t sg_dmamap; 504 bus_addr_t sg_physaddr; 505 struct ahc_dma_seg* sg_vaddr; 506 SLIST_ENTRY(sg_map_node) links; 507}; 508 509struct scb_data { 510 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 511 struct scb *scbarray; /* Array of kernel SCBs */ 512 SLIST_HEAD(, scb) free_scbs; /* 513 * Pool of SCBs ready to be assigned 514 * commands to execute. 515 */ 516 struct scsi_sense_data *sense; /* Per SCB sense data */ 517 518 /* 519 * "Bus" addresses of our data structures. 520 */ 521 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 522 bus_dmamap_t hscb_dmamap; 523 bus_addr_t hscb_busaddr; 524 bus_dma_tag_t sense_dmat; 525 bus_dmamap_t sense_dmamap; 526 bus_addr_t sense_busaddr; 527 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 528 SLIST_HEAD(, sg_map_node) sg_maps; 529 uint8_t numscbs; 530 uint8_t maxhscbs; /* Number of SCBs on the card */ 531 uint8_t init_level; /* 532 * How far we've initialized 533 * this structure. 534 */ 535}; 536 537/************************ Target Mode Definitions *****************************/ 538 539/* 540 * Connection desciptor for select-in requests in target mode. 541 */ 542struct target_cmd { 543 uint8_t scsiid; /* Our ID and the initiator's ID */ 544 uint8_t identify; /* Identify message */ 545 uint8_t bytes[22]; /* 546 * Bytes contains any additional message 547 * bytes terminated by 0xFF. The remainder 548 * is the cdb to execute. 549 */ 550 uint8_t cmd_valid; /* 551 * When a command is complete, the firmware 552 * will set cmd_valid to all bits set. 553 * After the host has seen the command, 554 * the bits are cleared. This allows us 555 * to just peek at host memory to determine 556 * if more work is complete. cmd_valid is on 557 * an 8 byte boundary to simplify setting 558 * it on aic7880 hardware which only has 559 * limited direct access to the DMA FIFO. 560 */ 561 uint8_t pad[7]; 562}; 563 564/* 565 * Number of events we can buffer up if we run out 566 * of immediate notify ccbs. 567 */ 568#define AHC_TMODE_EVENT_BUFFER_SIZE 8 569struct ahc_tmode_event { 570 uint8_t initiator_id; 571 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 572#define EVENT_TYPE_BUS_RESET 0xFF 573 uint8_t event_arg; 574}; 575 576/* 577 * Per enabled lun target mode state. 578 * As this state is directly influenced by the host OS'es target mode 579 * environment, we let the OS module define it. Forward declare the 580 * structure here so we can store arrays of them, etc. in OS neutral 581 * data structures. 582 */ 583#ifdef AHC_TARGET_MODE 584struct tmode_lstate { 585 struct cam_path *path; 586 struct ccb_hdr_slist accept_tios; 587 struct ccb_hdr_slist immed_notifies; 588 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 589 uint8_t event_r_idx; 590 uint8_t event_w_idx; 591}; 592#else 593struct tmode_lstate; 594#endif 595 596/******************** Transfer Negotiation Datastructures *********************/ 597#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 598#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 599#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 600#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 601 602/* 603 * Transfer Negotiation Information. 604 */ 605struct ahc_transinfo { 606 uint8_t protocol_version; /* SCSI Revision level */ 607 uint8_t transport_version; /* SPI Revision level */ 608 uint8_t width; /* Bus width */ 609 uint8_t period; /* Sync rate factor */ 610 uint8_t offset; /* Sync offset */ 611 uint8_t ppr_options; /* Parallel Protocol Request options */ 612}; 613 614/* 615 * Per-initiator current, goal and user transfer negotiation information. */ 616struct ahc_initiator_tinfo { 617 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 618 struct ahc_transinfo current; 619 struct ahc_transinfo goal; 620 struct ahc_transinfo user; 621}; 622 623/* 624 * Per enabled target ID state. 625 * Pointers to lun target state as well as sync/wide negotiation information 626 * for each initiator<->target mapping. For the initiator role we pretend 627 * that we are the target and the targets are the initiators since the 628 * negotiation is the same regardless of role. 629 */ 630struct tmode_tstate { 631 struct tmode_lstate* enabled_luns[64]; /* NULL == disabled */ 632 struct ahc_initiator_tinfo transinfo[16]; 633 634 /* 635 * Per initiator state bitmasks. 636 */ 637 uint16_t ultraenb; /* Using ultra sync rate */ 638 uint16_t discenable; /* Disconnection allowed */ 639 uint16_t tagenable; /* Tagged Queuing allowed */ 640}; 641 642/* 643 * Data structure for our table of allowed synchronous transfer rates. 644 */ 645struct ahc_syncrate { 646 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 647 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 648#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 649#define ST_SXFR 0x010 /* Rate Single Transition Only */ 650#define DT_SXFR 0x040 /* Rate Double Transition Only */ 651 uint8_t period; /* Period to send to SCSI target */ 652 char *rate; 653}; 654 655/* 656 * The synchronouse transfer rate table. 657 */ 658extern struct ahc_syncrate ahc_syncrates[]; 659 660/* 661 * Indexes into our table of syncronous transfer rates. 662 */ 663#define AHC_SYNCRATE_DT 0 664#define AHC_SYNCRATE_ULTRA2 1 665#define AHC_SYNCRATE_ULTRA 3 666#define AHC_SYNCRATE_FAST 6 667 668/***************************** Lookup Tables **********************************/ 669/* 670 * Textual descriptions of the different chips indexed by chip type. 671 */ 672extern char *ahc_chip_names[]; 673extern const u_int num_chip_names; 674 675/* 676 * Hardware error codes. 677 */ 678struct hard_error_entry { 679 uint8_t errno; 680 char *errmesg; 681}; 682extern struct hard_error_entry hard_error[]; 683extern const u_int num_errors; 684 685/* 686 * Phase -> name and message out response 687 * to parity errors in each phase table. 688 */ 689struct phase_table_entry { 690 uint8_t phase; 691 uint8_t mesg_out; /* Message response to parity errors */ 692 char *phasemsg; 693}; 694extern struct phase_table_entry phase_table[]; 695extern const u_int num_phases; 696 697/************************** Serial EEPROM Format ******************************/ 698 699struct seeprom_config { 700/* 701 * Per SCSI ID Configuration Flags 702 */ 703 uint16_t device_flags[16]; /* words 0-15 */ 704#define CFXFER 0x0007 /* synchronous transfer rate */ 705#define CFSYNCH 0x0008 /* enable synchronous transfer */ 706#define CFDISC 0x0010 /* enable disconnection */ 707#define CFWIDEB 0x0020 /* wide bus device */ 708#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 709#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 710#define CFSTART 0x0100 /* send start unit SCSI command */ 711#define CFINCBIOS 0x0200 /* include in BIOS scan */ 712#define CFRNFOUND 0x0400 /* report even if not found */ 713#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 714#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 715#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 716 717/* 718 * BIOS Control Bits 719 */ 720 uint16_t bios_control; /* word 16 */ 721#define CFSUPREM 0x0001 /* support all removeable drives */ 722#define CFSUPREMB 0x0002 /* support removeable boot drives */ 723#define CFBIOSEN 0x0004 /* BIOS enabled */ 724/* UNUSED 0x0008 */ 725#define CFSM2DRV 0x0010 /* support more than two drives */ 726#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 727#define CFSTPWLEVEL 0x0010 /* Termination level control */ 728#define CFEXTEND 0x0080 /* extended translation enabled */ 729#define CFSCAMEN 0x0100 /* SCAM enable */ 730/* UNUSED 0xff00 */ 731 732/* 733 * Host Adapter Control Bits 734 */ 735 uint16_t adapter_control; /* word 17 */ 736#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 737#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 738#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 739#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 740#define CFSTERM 0x0004 /* SCSI low byte termination */ 741#define CFWSTERM 0x0008 /* SCSI high byte termination */ 742#define CFSPARITY 0x0010 /* SCSI parity */ 743#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 744#define CFMULTILUN 0x0020 /* SCSI low byte term (284x cards) */ 745#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 746#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 747#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 748#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 749#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 750#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 751#define CFDOMAINVAL 0x4000 /* Perform Domain Validation*/ 752 753/* 754 * Bus Release Time, Host Adapter ID 755 */ 756 uint16_t brtime_id; /* word 18 */ 757#define CFSCSIID 0x000f /* host adapter SCSI ID */ 758/* UNUSED 0x00f0 */ 759#define CFBRTIME 0xff00 /* bus release time */ 760 761/* 762 * Maximum targets 763 */ 764 uint16_t max_targets; /* word 19 */ 765#define CFMAXTARG 0x00ff /* maximum targets */ 766#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 767#define CFBOOTID 0xf000 /* Target to boot from */ 768 uint16_t res_1[10]; /* words 20-29 */ 769 uint16_t signature; /* Signature == 0x250 */ 770#define CFSIGNATURE 0x250 771 uint16_t checksum; /* word 31 */ 772}; 773 774/**************************** Message Buffer *********************************/ 775typedef enum { 776 MSG_TYPE_NONE = 0x00, 777 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 778 MSG_TYPE_INITIATOR_MSGIN = 0x02, 779 MSG_TYPE_TARGET_MSGOUT = 0x03, 780 MSG_TYPE_TARGET_MSGIN = 0x04 781} ahc_msg_type; 782 783typedef enum { 784 MSGLOOP_IN_PROG, 785 MSGLOOP_MSGCOMPLETE, 786 MSGLOOP_TERMINATED 787} msg_loop_stat; 788 789/*********************** Software Configuration Structure *********************/ 790TAILQ_HEAD(scb_tailq, scb); 791 792struct ahc_softc { 793 bus_space_tag_t tag; 794 bus_space_handle_t bsh; 795#ifndef __linux__ 796 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 797#endif 798 struct scb_data *scb_data; 799 800 /* 801 * SCBs that have been sent to the controller 802 */ 803 LIST_HEAD(, scb) pending_scbs; 804 805 /* 806 * Counting lock for deferring the release of additional 807 * untagged transactions from the untagged_queues. When 808 * the lock is decremented to 0, all queues in the 809 * untagged_queues array are run. 810 */ 811 u_int untagged_queue_lock; 812 813 /* 814 * Per-target queue of untagged-transactions. The 815 * transaction at the head of the queue is the 816 * currently pending untagged transaction for the 817 * target. The driver only allows a single untagged 818 * transaction per target. 819 */ 820 struct scb_tailq untagged_queues[16]; 821 822 /* 823 * Platform specific data. 824 */ 825 struct ahc_platform_data *platform_data; 826 827 /* 828 * Platform specific device information. 829 */ 830 ahc_dev_softc_t dev_softc; 831 832 /* 833 * Target mode related state kept on a per enabled lun basis. 834 * Targets that are not enabled will have null entries. 835 * As an initiator, we keep one target entry for our initiator 836 * ID to store our sync/wide transfer settings. 837 */ 838 struct tmode_tstate* enabled_targets[16]; 839 840 /* 841 * The black hole device responsible for handling requests for 842 * disabled luns on enabled targets. 843 */ 844 struct tmode_lstate* black_hole; 845 846 /* 847 * Device instance currently on the bus awaiting a continue TIO 848 * for a command that was not given the disconnect priveledge. 849 */ 850 struct tmode_lstate* pending_device; 851 852 /* 853 * Card characteristics 854 */ 855 ahc_chip chip; 856 ahc_feature features; 857 ahc_bug bugs; 858 ahc_flag flags; 859 860 /* Values to store in the SEQCTL register for pause and unpause */ 861 uint8_t unpause; 862 uint8_t pause; 863 864 /* Command Queues */ 865 uint8_t qoutfifonext; 866 uint8_t qinfifonext; 867 uint8_t *qoutfifo; 868 uint8_t *qinfifo; 869 870 /* Links for chaining softcs */ 871 TAILQ_ENTRY(ahc_softc) links; 872 873 /* Channel Names ('A', 'B', etc.) */ 874 char channel; 875 char channel_b; 876 877 /* Initiator Bus ID */ 878 uint8_t our_id; 879 uint8_t our_id_b; 880 881 /* Targets that need negotiation messages */ 882 uint16_t targ_msg_req; 883 884 /* 885 * PCI error detection. 886 */ 887 int unsolicited_ints; 888 889 /* 890 * Target incoming command FIFO. 891 */ 892 struct target_cmd *targetcmds; 893 uint8_t tqinfifonext; 894 895 /* 896 * Incoming and outgoing message handling. 897 */ 898 uint8_t send_msg_perror; 899 ahc_msg_type msg_type; 900 uint8_t msgout_buf[12];/* Message we are sending */ 901 uint8_t msgin_buf[12];/* Message we are receiving */ 902 u_int msgout_len; /* Length of message to send */ 903 u_int msgout_index; /* Current index in msgout */ 904 u_int msgin_index; /* Current index in msgin */ 905 906 /* 907 * Mapping information for data structures shared 908 * between the sequencer and kernel. 909 */ 910 bus_dma_tag_t parent_dmat; 911 bus_dma_tag_t shared_data_dmat; 912 bus_dmamap_t shared_data_dmamap; 913 bus_addr_t shared_data_busaddr; 914 915 /* 916 * Bus address of the one byte buffer used to 917 * work-around a DMA bug for chips <= aic7880 918 * in target mode. 919 */ 920 bus_addr_t dma_bug_buf; 921 922 /* Number of enabled target mode device on this card */ 923 u_int enabled_luns; 924 925 /* Initialization level of this data structure */ 926 u_int init_level; 927 928 /* PCI cacheline size. */ 929 u_int pci_cachesize; 930 931 /* Per-Unit descriptive information */ 932 const char *description; 933 char *name; 934 int unit; 935 936 uint16_t user_discenable;/* Disconnection allowed */ 937 uint16_t user_tagenable;/* Tagged Queuing allowed */ 938}; 939 940TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 941extern struct ahc_softc_tailq ahc_tailq; 942 943/************************ Active Device Information ***************************/ 944typedef enum { 945 ROLE_UNKNOWN, 946 ROLE_INITIATOR, 947 ROLE_TARGET 948} role_t; 949 950struct ahc_devinfo { 951 int our_scsiid; 952 int target_offset; 953 uint16_t target_mask; 954 u_int target; 955 u_int lun; 956 char channel; 957 role_t role; /* 958 * Only guaranteed to be correct if not 959 * in the busfree state. 960 */ 961}; 962 963/****************************** PCI Structures ********************************/ 964typedef int (ahc_device_setup_t)(ahc_dev_softc_t, 965 struct ahc_probe_config *); 966 967struct ahc_pci_identity { 968 uint64_t full_id; 969 uint64_t id_mask; 970 char *name; 971 ahc_device_setup_t *setup; 972}; 973extern struct ahc_pci_identity ahc_pci_ident_table []; 974extern const int ahc_num_pci_devs; 975 976/***************************** VL/EISA Declarations ***************************/ 977struct aic7770_identity { 978 uint32_t full_id; 979 uint32_t id_mask; 980 char *name; 981 ahc_device_setup_t *setup; 982}; 983extern struct aic7770_identity aic7770_ident_table []; 984extern const int ahc_num_aic7770_devs; 985 986#define AHC_EISA_SLOT_OFFSET 0xc00 987#define AHC_EISA_IOSIZE 0x100 988 989/*************************** Function Declarations ****************************/ 990/******************************************************************************/ 991 992/***************************** PCI Front End *********************************/ 993struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 994int ahc_pci_config(struct ahc_softc *, 995 struct ahc_pci_identity *); 996 997/*************************** EISA/VL Front End ********************************/ 998struct aic7770_identity *aic7770_find_device(uint32_t); 999int aic7770_config(struct ahc_softc *ahc, 1000 struct aic7770_identity *); 1001 1002/************************** SCB and SCB queue management **********************/ 1003int ahc_probe_scbs(struct ahc_softc *); 1004void ahc_run_untagged_queues(struct ahc_softc *ahc); 1005void ahc_run_untagged_queue(struct ahc_softc *ahc, 1006 struct scb_tailq *queue); 1007 1008/****************************** Initialization ********************************/ 1009void ahc_init_probe_config(struct ahc_probe_config *); 1010struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1011int ahc_softc_init(struct ahc_softc *, 1012 struct ahc_probe_config*); 1013void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1014int ahc_init(struct ahc_softc *ahc); 1015void ahc_softc_insert(struct ahc_softc *); 1016void ahc_set_unit(struct ahc_softc *, int); 1017void ahc_set_name(struct ahc_softc *, char *); 1018void ahc_alloc_scbs(struct ahc_softc *ahc); 1019void ahc_free(struct ahc_softc *ahc); 1020int ahc_reset(struct ahc_softc *ahc); 1021void ahc_shutdown(void *arg); 1022 1023/*************************** Interrupt Services *******************************/ 1024void ahc_pci_intr(struct ahc_softc *ahc); 1025void ahc_clear_intstat(struct ahc_softc *ahc); 1026void ahc_run_qoutfifo(struct ahc_softc *ahc); 1027#ifdef AHC_TARGET_MODE 1028void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1029#endif 1030void ahc_handle_brkadrint(struct ahc_softc *ahc); 1031void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1032void ahc_handle_scsiint(struct ahc_softc *ahc, 1033 u_int intstat); 1034 1035/***************************** Error Recovery *********************************/ 1036typedef enum { 1037 SEARCH_COMPLETE, 1038 SEARCH_COUNT, 1039 SEARCH_REMOVE 1040} ahc_search_action; 1041int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1042 char channel, int lun, u_int tag, 1043 role_t role, uint32_t status, 1044 ahc_search_action action); 1045int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1046 char channel, int lun, u_int tag, 1047 int stop_on_first, int remove, 1048 int save_state); 1049void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1050int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1051 int initiate_reset); 1052void restart_sequencer(struct ahc_softc *ahc); 1053/*************************** Utility Functions ********************************/ 1054void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1055 u_int our_id, u_int target, 1056 u_int lun, char channel, 1057 role_t role); 1058/************************** Transfer Negotiation ******************************/ 1059struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1060 u_int *ppr_options, u_int maxsync); 1061u_int ahc_find_period(struct ahc_softc *ahc, 1062 u_int scsirate, u_int maxsync); 1063void ahc_validate_offset(struct ahc_softc *ahc, 1064 struct ahc_syncrate *syncrate, 1065 u_int *offset, int wide); 1066void ahc_validate_width(struct ahc_softc *ahc, 1067 u_int *bus_width); 1068void ahc_set_width(struct ahc_softc *ahc, 1069 struct ahc_devinfo *devinfo, 1070 u_int width, u_int type, int paused); 1071void ahc_set_syncrate(struct ahc_softc *ahc, 1072 struct ahc_devinfo *devinfo, 1073 struct ahc_syncrate *syncrate, 1074 u_int period, u_int offset, 1075 u_int ppr_options, 1076 u_int type, int paused); 1077void ahc_set_tags(struct ahc_softc *ahc, 1078 struct ahc_devinfo *devinfo, int enable); 1079 1080/**************************** Target Mode *************************************/ 1081#ifdef AHC_TARGET_MODE 1082void ahc_send_lstate_events(struct ahc_softc *, 1083 struct tmode_lstate *); 1084void ahc_handle_en_lun(struct ahc_softc *ahc, 1085 struct cam_sim *sim, union ccb *ccb); 1086cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1087 struct cam_sim *sim, union ccb *ccb, 1088 struct tmode_tstate **tstate, 1089 struct tmode_lstate **lstate, 1090 int notfound_failure); 1091void ahc_setup_target_msgin(struct ahc_softc *ahc, 1092 struct ahc_devinfo *devinfo); 1093#endif 1094/******************************* Debug ***************************************/ 1095void ahc_print_scb(struct scb *scb); 1096void ahc_dump_card_state(struct ahc_softc *ahc); 1097#endif /* _AIC7XXX_H_ */ 1098