aic7xxx.h revision 50477
1/* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 50477 1999-08-28 01:08:13Z peter $ 38 */ 39 40#ifndef _AIC7XXX_H_ 41#define _AIC7XXX_H_ 42 43#include "ahc.h" /* for NAHC from config */ 44#include "opt_aic7xxx.h" /* for config options */ 45 46#include <sys/bus.h> /* For device_t */ 47 48#ifndef MAX 49#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 50#endif 51 52#ifndef MIN 53#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 54#endif 55 56/* 57 * The maximum transfer per S/G segment. 58 */ 59#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 60 61/* 62 * The number of dma segments supported. The current implementation limits 63 * us to 255 S/G entries (this may change to be unlimited at some point). 64 * To reduce the driver's memory consumption, we further limit the number 65 * supported to be sufficient to handle the largest mapping supported by 66 * the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible 67 * and unaligned, this turns out to be the number of paged sized transfers 68 * in MAXPHYS plus an extra element to handle any unaligned residual. 69 */ 70#define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255)) 71 72#define AHC_SCB_MAX 255 /* 73 * Up to 255 SCBs on some types of aic7xxx 74 * based boards. The aic7870 have 16 internal 75 * SCBs, but external SRAM bumps this to 255. 76 * The aic7770 family have only 4, and the 77 * aic7850 has only 3. 78 */ 79 80#define AHC_TMODE_CMDS 256 /* 81 * Ring Buffer of incoming target commands. 82 * We allocate 256 to simplify the logic 83 * in the sequencer by using the natural 84 * wrap point of an 8bit counter. 85 */ 86 87struct ahc_dma_seg { 88 u_int32_t addr; 89 u_int32_t len; 90}; 91 92typedef enum { 93 AHC_NONE = 0x0000, 94 AHC_CHIPID_MASK = 0x00FF, 95 AHC_AIC7770 = 0x0001, 96 AHC_AIC7850 = 0x0002, 97 AHC_AIC7860 = 0x0003, 98 AHC_AIC7870 = 0x0004, 99 AHC_AIC7880 = 0x0005, 100 AHC_AIC7890 = 0x0006, 101 AHC_AIC7895 = 0x0007, 102 AHC_AIC7896 = 0x0008, 103 AHC_VL = 0x0100, /* Bus type VL */ 104 AHC_EISA = 0x0200, /* Bus type EISA */ 105 AHC_PCI = 0x0400, /* Bus type PCI */ 106} ahc_chip; 107 108typedef enum { 109 AHC_FENONE = 0x0000, 110 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 111 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 112 AHC_WIDE = 0x0004, /* Wide Channel */ 113 AHC_TWIN = 0x0008, /* Twin Channel */ 114 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 115 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 116 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 117 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 118 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 119 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 120 AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */ 121 AHC_AIC7770_FE = AHC_FENONE, 122 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 123 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 124 AHC_AIC7870_FE = AHC_FENONE, 125 AHC_AIC7880_FE = AHC_ULTRA, 126 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 127 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX, 128 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 129 AHC_AIC7895C_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA|AHC_MULTI_TID, 130 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 131 |AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX 132} ahc_feature; 133 134typedef enum { 135 AHC_FNONE = 0x000, 136 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 137 AHC_CHANNEL_B_PRIMARY = 0x002,/* 138 * On twin channel adapters, probe 139 * channel B first since it is the 140 * primary bus. 141 */ 142 AHC_USEDEFAULTS = 0x004,/* 143 * For cards without an seeprom 144 * or a BIOS to initialize the chip's 145 * SRAM, we use the default target 146 * settings. 147 */ 148 AHC_SHARED_SRAM = 0x010, 149 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 150 AHC_RESET_BUS_A = 0x040, 151 AHC_RESET_BUS_B = 0x080, 152 AHC_EXTENDED_TRANS_A = 0x100, 153 AHC_EXTENDED_TRANS_B = 0x200, 154 AHC_TERM_ENB_A = 0x400, 155 AHC_TERM_ENB_B = 0x800, 156 AHC_INITIATORMODE = 0x1000,/* 157 * Allow initiator operations on 158 * this controller. 159 */ 160 AHC_TARGETMODE = 0x2000,/* 161 * Allow target operations on this 162 * controller. 163 */ 164 AHC_NEWEEPROM_FMT = 0x4000, 165 AHC_RESOURCE_SHORTAGE = 0x8000, 166 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 167} ahc_flag; 168 169typedef enum { 170 SCB_FREE = 0x0000, 171 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 172 * Another device was active 173 * during the first timeout for 174 * this SCB so we gave ourselves 175 * an additional timeout period 176 * in case it was hogging the 177 * bus. 178 */ 179 SCB_DEVICE_RESET = 0x0004, 180 SCB_SENSE = 0x0008, 181 SCB_RECOVERY_SCB = 0x0040, 182 SCB_ABORT = 0x1000, 183 SCB_QUEUED_MSG = 0x2000, 184 SCB_ACTIVE = 0x4000, 185 SCB_TARGET_IMMEDIATE = 0x8000 186} scb_flag; 187 188/* 189 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 190 * consists of a "hardware SCB" mirroring the fields availible on the card 191 * and additional information the kernel stores for each transaction. 192 */ 193struct hardware_scb { 194/*0*/ u_int8_t control; 195/*1*/ u_int8_t tcl; /* 4/1/3 bits */ 196/*2*/ u_int8_t status; 197/*3*/ u_int8_t SG_count; 198/*4*/ u_int32_t SG_pointer; 199/*8*/ u_int8_t residual_SG_count; 200/*9*/ u_int8_t residual_data_count[3]; 201/*12*/ u_int32_t data; 202/*16*/ u_int32_t datalen; /* Really only three bytes, but its 203 * faster to treat it as a long on 204 * a quad boundary. 205 */ 206/*20*/ u_int32_t cmdpointer; 207/*24*/ u_int8_t cmdlen; 208/*25*/ u_int8_t tag; /* Index into our kernel SCB array. 209 * Also used as the tag for tagged I/O 210 */ 211/*26*/ u_int8_t next; /* Used for threading SCBs in the 212 * "Waiting for Selection" and 213 * "Disconnected SCB" lists down 214 * in the sequencer. 215 */ 216/*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 217/*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 218/*29*/ u_int8_t spare[3]; /* 219 * Spare space available on 220 * all controller types. 221 */ 222/*32*/ u_int8_t cmdstore[16]; /* 223 * CDB storage for controllers 224 * supporting 64 byte SCBs. 225 */ 226/*48*/ u_int32_t cmdstore_busaddr; /* 227 * Address of command store for 228 * 32byte SCB adapters 229 */ 230/*48*/ u_int8_t spare_64[12]; /* 231 * Pad to 64 bytes. 232 */ 233}; 234 235struct scb { 236 struct hardware_scb *hscb; 237 SLIST_ENTRY(scb) links; /* for chaining */ 238 union ccb *ccb; /* the ccb for this cmd */ 239 scb_flag flags; 240 bus_dmamap_t dmamap; 241 struct ahc_dma_seg *sg_list; 242 bus_addr_t sg_list_phys; 243 u_int sg_count;/* How full ahc_dma_seg is */ 244}; 245 246/* 247 * Connection desciptor for select-in requests in target mode. 248 * The first byte is the connecting target, followed by identify 249 * message and optional tag information, terminated by 0xFF. The 250 * remainder is the command to execute. The cmd_valid byte is on 251 * an 8 byte boundary to simplify setting it on aic7880 hardware 252 * which only has limited direct access to the DMA FIFO. 253 */ 254struct target_cmd { 255 u_int8_t initiator_channel; 256 u_int8_t targ_id; /* Target ID we were selected at */ 257 u_int8_t identify; /* Identify message */ 258 u_int8_t bytes[21]; 259 u_int8_t cmd_valid; 260 u_int8_t pad[7]; 261}; 262 263/* 264 * Number of events we can buffer up if we run out 265 * of immediate notify ccbs. 266 */ 267#define AHC_TMODE_EVENT_BUFFER_SIZE 8 268struct ahc_tmode_event { 269 u_int8_t initiator_id; 270 u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 271#define EVENT_TYPE_BUS_RESET 0xFF 272 u_int8_t event_arg; 273}; 274 275/* 276 * Per lun target mode state including accept TIO CCB 277 * and immediate notify CCB pools. 278 */ 279struct tmode_lstate { 280 struct cam_path *path; 281 struct ccb_hdr_slist accept_tios; 282 struct ccb_hdr_slist immed_notifies; 283 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 284 u_int8_t event_r_idx; 285 u_int8_t event_w_idx; 286}; 287 288#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 289#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 290#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 291#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 292 293struct ahc_transinfo { 294 u_int8_t width; 295 u_int8_t period; 296 u_int8_t offset; 297}; 298 299struct ahc_initiator_tinfo { 300 u_int8_t scsirate; 301 struct ahc_transinfo current; 302 struct ahc_transinfo goal; 303 struct ahc_transinfo user; 304}; 305 306/* 307 * Per target mode enabled target state. Esentially just an array of 308 * pointers to lun target state as well as sync/wide negotiation information 309 * for each initiator<->target mapping (including the mapping for when we 310 * are the initiator). 311 */ 312struct tmode_tstate { 313 struct tmode_lstate* enabled_luns[8]; 314 struct ahc_initiator_tinfo transinfo[16]; 315 316 /* 317 * Per initiator state bitmasks. 318 */ 319 u_int16_t ultraenb; /* Using ultra sync rate */ 320 u_int16_t discenable; /* Disconnection allowed */ 321 u_int16_t tagenable; /* Tagged Queuing allowed */ 322}; 323 324/* 325 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 326 */ 327 328struct seeprom_config { 329/* 330 * SCSI ID Configuration Flags 331 */ 332 u_int16_t device_flags[16]; /* words 0-15 */ 333#define CFXFER 0x0007 /* synchronous transfer rate */ 334#define CFSYNCH 0x0008 /* enable synchronous transfer */ 335#define CFDISC 0x0010 /* enable disconnection */ 336#define CFWIDEB 0x0020 /* wide bus device */ 337#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 338/* UNUSED 0x0080 */ 339#define CFSTART 0x0100 /* send start unit SCSI command */ 340#define CFINCBIOS 0x0200 /* include in BIOS scan */ 341#define CFRNFOUND 0x0400 /* report even if not found */ 342#define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 343/* UNUSED 0xf000 */ 344 345/* 346 * BIOS Control Bits 347 */ 348 u_int16_t bios_control; /* word 16 */ 349#define CFSUPREM 0x0001 /* support all removeable drives */ 350#define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 351#define CFBIOSEN 0x0004 /* BIOS enabled */ 352/* UNUSED 0x0008 */ 353#define CFSM2DRV 0x0010 /* support more than two drives */ 354#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 355/* UNUSED 0x0060 */ 356#define CFEXTEND 0x0080 /* extended translation enabled */ 357/* UNUSED 0xff00 */ 358 359/* 360 * Host Adapter Control Bits 361 */ 362 u_int16_t adapter_control; /* word 17 */ 363#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 364#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 365#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 366#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 367#define CFSTERM 0x0004 /* SCSI low byte termination */ 368#define CFWSTERM 0x0008 /* SCSI high byte termination */ 369#define CFSPARITY 0x0010 /* SCSI parity */ 370#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 371#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 372#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 373#define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 374#define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 375/* UNUSED 0xf080 */ 376 377/* 378 * Bus Release, Host Adapter ID 379 */ 380 u_int16_t brtime_id; /* word 18 */ 381#define CFSCSIID 0x000f /* host adapter SCSI ID */ 382/* UNUSED 0x00f0 */ 383#define CFBRTIME 0xff00 /* bus release time */ 384 385/* 386 * Maximum targets 387 */ 388 u_int16_t max_targets; /* word 19 */ 389#define CFMAXTARG 0x00ff /* maximum targets */ 390/* UNUSED 0xff00 */ 391 u_int16_t res_1[11]; /* words 20-30 */ 392 u_int16_t checksum; /* word 31 */ 393}; 394 395struct ahc_syncrate { 396 int sxfr_ultra2; 397 int sxfr; 398 /* Rates in Ultra mode have bit 8 of sxfr set */ 399#define ULTRA_SXFR 0x100 400 u_int8_t period; /* Period to send to SCSI target */ 401 char *rate; 402}; 403 404typedef enum { 405 MSG_TYPE_NONE = 0x00, 406 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 407 MSG_TYPE_INITIATOR_MSGIN = 0x02, 408 MSG_TYPE_TARGET_MSGOUT = 0x03, 409 MSG_TYPE_TARGET_MSGIN = 0x04 410} ahc_msg_type; 411 412struct sg_map_node { 413 bus_dmamap_t sg_dmamap; 414 bus_addr_t sg_physaddr; 415 struct ahc_dma_seg* sg_vaddr; 416 SLIST_ENTRY(sg_map_node) links; 417}; 418 419struct scb_data { 420 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 421 struct scb *scbarray; /* Array of kernel SCBs */ 422 SLIST_HEAD(, scb) free_scbs; /* 423 * Pool of SCBs ready to be assigned 424 * commands to execute. 425 */ 426 struct scsi_sense_data *sense; /* Per SCB sense data */ 427 428 /* 429 * "Bus" addresses of our data structures. 430 */ 431 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 432 bus_dmamap_t hscb_dmamap; 433 bus_addr_t hscb_busaddr; 434 bus_dma_tag_t sense_dmat; 435 bus_dmamap_t sense_dmamap; 436 bus_addr_t sense_busaddr; 437 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 438 SLIST_HEAD(, sg_map_node) sg_maps; 439 u_int8_t numscbs; 440 u_int8_t maxhscbs; /* Number of SCBs on the card */ 441 u_int8_t init_level; /* 442 * How far we've initialized 443 * this structure. 444 */ 445}; 446 447struct ahc_softc { 448 bus_space_tag_t tag; 449 bus_space_handle_t bsh; 450 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 451 struct scb_data *scb_data; 452 453 /* 454 * CCBs that have been send to the controller 455 */ 456 LIST_HEAD(, ccb_hdr) pending_ccbs; 457 458 /* 459 * Target mode related state kept on a per enabled lun basis. 460 * Targets that are not enabled will have null entries. 461 * As an initiator, we keep one target entry for our initiator 462 * ID to store our sync/wide transfer settings. 463 */ 464 struct tmode_tstate* enabled_targets[16]; 465 466 /* 467 * The black hole device responsible for handling requests for 468 * disabled luns on enabled targets. 469 */ 470 struct tmode_lstate* black_hole; 471 472 /* 473 * Device instance currently on the bus awaiting a continue TIO 474 * for a command that was not given the disconnect priveledge. 475 */ 476 struct tmode_lstate* pending_device; 477 478 /* 479 * Card characteristics 480 */ 481 ahc_chip chip; 482 ahc_feature features; 483 ahc_flag flags; 484 485 /* Values to store in the SEQCTL register for pause and unpause */ 486 u_int8_t unpause; 487 u_int8_t pause; 488 489 /* Command Queues */ 490 u_int8_t qoutfifonext; 491 u_int8_t qinfifonext; 492 u_int8_t *qoutfifo; 493 u_int8_t *qinfifo; 494 495 /* 496 * 256 byte array storing the SCBID of outstanding 497 * untagged SCBs indexed by TCL. 498 */ 499 u_int8_t *untagged_scbs; 500 501 /* 502 * Hooks into the XPT. 503 */ 504 struct cam_sim *sim; 505 struct cam_sim *sim_b; 506 struct cam_path *path; 507 struct cam_path *path_b; 508 509 int unit; 510 511 /* Channel Names ('A', 'B', etc.) */ 512 char channel; 513 char channel_b; 514 515 /* Initiator Bus ID */ 516 u_int8_t our_id; 517 u_int8_t our_id_b; 518 519 /* Targets that need negotiation messages */ 520 u_int16_t targ_msg_req; 521 522 /* 523 * PCI error detection and data for running the 524 * PCI error interrupt handler. 525 */ 526 int unsolicited_ints; 527 device_t device; 528 529 /* 530 * Target incoming command FIFO. 531 */ 532 struct target_cmd *targetcmds; 533 u_int8_t tqinfifonext; 534 535 /* 536 * Incoming and outgoing message handling. 537 */ 538 u_int8_t send_msg_perror; 539 ahc_msg_type msg_type; 540 u_int8_t msgout_buf[8]; /* Message we are sending */ 541 u_int8_t msgin_buf[8]; /* Message we are receiving */ 542 u_int msgout_len; /* Length of message to send */ 543 u_int msgout_index; /* Current index in msgout */ 544 u_int msgin_index; /* Current index in msgin */ 545 546 int regs_res_type; 547 int regs_res_id; 548 int irq_res_type; 549 struct resource *regs; 550 struct resource *irq; 551 void *ih; 552 bus_dma_tag_t parent_dmat; 553 bus_dma_tag_t shared_data_dmat; 554 bus_dmamap_t shared_data_dmamap; 555 bus_addr_t shared_data_busaddr; 556 557 /* Number of enabled target mode device on this card */ 558 u_int enabled_luns; 559 560 /* Initialization level of this data structure */ 561 u_int init_level; 562 563 u_int16_t user_discenable;/* Disconnection allowed */ 564 u_int16_t user_tagenable;/* Tagged Queuing allowed */ 565}; 566 567struct full_ahc_softc { 568 struct ahc_softc softc; 569 struct scb_data scb_data_storage; 570}; 571 572/* #define AHC_DEBUG */ 573#ifdef AHC_DEBUG 574/* Different debugging levels used when AHC_DEBUG is defined */ 575#define AHC_SHOWMISC 0x0001 576#define AHC_SHOWCMDS 0x0002 577#define AHC_SHOWSCBS 0x0004 578#define AHC_SHOWABORTS 0x0008 579#define AHC_SHOWSENSE 0x0010 580#define AHC_SHOWSCBCNT 0x0020 581 582extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 583#endif 584 585char *ahc_name(struct ahc_softc *ahc); 586 587struct ahc_softc* 588 ahc_alloc(device_t dev, struct resource *regs, int regs_type, 589 int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip, 590 ahc_feature features, ahc_flag flags, 591 struct scb_data *scb_data); 592int ahc_reset(struct ahc_softc *ahc); 593void ahc_free(struct ahc_softc *); 594int ahc_probe_scbs(struct ahc_softc *); 595int ahc_init(struct ahc_softc *); 596int ahc_attach(struct ahc_softc *); 597void ahc_intr(void *arg); 598 599#define ahc_inb(ahc, port) \ 600 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 601 602#define ahc_outb(ahc, port, value) \ 603 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 604 605#define ahc_outsb(ahc, port, valp, count) \ 606 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 607 608#endif /* _AIC7XXX_H_ */ 609