aic7xxx.h revision 44507
1/* 2 * Interface to the generic driver for the aic7xxx based adaptec 3 * SCSI controllers. This is used to implement product specific 4 * probe and attach routines. 5 * 6 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id: aic7xxx.h,v 1.5 1999/01/14 06:14:15 gibbs Exp $ 38 */ 39 40#ifndef _AIC7XXX_H_ 41#define _AIC7XXX_H_ 42 43#include "ahc.h" /* for NAHC from config */ 44#include "opt_aic7xxx.h" /* for config options */ 45 46#include <pci/pcivar.h> /* for pcici_t */ 47 48#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 49#define AHC_NSEG 32 /* The number of dma segments supported. 50 * AHC_NSEG can be maxed out at 256 entries, 51 * but the kernel will never need to transfer 52 * such a large (1MB) request. To reduce the 53 * driver's memory consumption, we reduce the 54 * max to 32. 16 would work if all transfers 55 * are paged alined since the kernel will only 56 * generate at most a 64k transfer, but to 57 * handle non-page aligned transfers, you need 58 * 17, so we round to the next power of two 59 * to make allocating SG space easy and 60 * efficient. 61 */ 62 63#define AHC_SCB_MAX 255 /* 64 * Up to 255 SCBs on some types of aic7xxx 65 * based boards. The aic7870 have 16 internal 66 * SCBs, but external SRAM bumps this to 255. 67 * The aic7770 family have only 4, and the 68 * aic7850 has only 3. 69 */ 70 71#define AHC_TMODE_CMDS 256 /* 72 * Ring Buffer of incoming target commands. 73 * We allocate 256 to simplify the logic 74 * in the sequencer by using the natural 75 * wrap point of an 8bit counter. 76 */ 77 78#if defined(__FreeBSD__) 79extern u_long ahc_unit; 80#endif 81 82struct ahc_dma_seg { 83 u_int32_t addr; 84 u_int32_t len; 85}; 86 87typedef enum { 88 AHC_NONE = 0x0000, 89 AHC_CHIPID_MASK = 0x00FF, 90 AHC_AIC7770 = 0x0001, 91 AHC_AIC7850 = 0x0002, 92 AHC_AIC7860 = 0x0003, 93 AHC_AIC7870 = 0x0004, 94 AHC_AIC7880 = 0x0005, 95 AHC_AIC7890 = 0x0006, 96 AHC_AIC7895 = 0x0007, 97 AHC_AIC7896 = 0x0008, 98 AHC_VL = 0x0100, /* Bus type VL */ 99 AHC_EISA = 0x0200, /* Bus type EISA */ 100 AHC_PCI = 0x0400, /* Bus type PCI */ 101} ahc_chip; 102 103typedef enum { 104 AHC_FENONE = 0x0000, 105 AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */ 106 AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */ 107 AHC_WIDE = 0x0004, /* Wide Channel */ 108 AHC_TWIN = 0x0008, /* Twin Channel */ 109 AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */ 110 AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */ 111 AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */ 112 AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */ 113 AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */ 114 AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */ 115 AHC_AIC7770_FE = AHC_FENONE, 116 AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP, 117 AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP, 118 AHC_AIC7870_FE = AHC_FENONE, 119 AHC_AIC7880_FE = AHC_ULTRA, 120 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 121 |AHC_SG_PRELOAD|AHC_MULTI_TID, 122 AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA, 123 AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS 124 |AHC_SG_PRELOAD|AHC_MULTI_TID, 125} ahc_feature; 126 127typedef enum { 128 AHC_FNONE = 0x000, 129 AHC_PAGESCBS = 0x001,/* Enable SCB paging */ 130 AHC_CHANNEL_B_PRIMARY = 0x002,/* 131 * On twin channel adapters, probe 132 * channel B first since it is the 133 * primary bus. 134 */ 135 AHC_USEDEFAULTS = 0x004,/* 136 * For cards without an seeprom 137 * or a BIOS to initialize the chip's 138 * SRAM, we use the default target 139 * settings. 140 */ 141 AHC_INDIRECT_PAGING = 0x008, 142 AHC_SHARED_SRAM = 0x010, 143 AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */ 144 AHC_RESET_BUS_A = 0x040, 145 AHC_RESET_BUS_B = 0x080, 146 AHC_EXTENDED_TRANS_A = 0x100, 147 AHC_EXTENDED_TRANS_B = 0x200, 148 AHC_TERM_ENB_A = 0x400, 149 AHC_TERM_ENB_B = 0x800, 150 AHC_INITIATORMODE = 0x1000,/* 151 * Allow initiator operations on 152 * this controller. 153 */ 154 AHC_TARGETMODE = 0x2000,/* 155 * Allow target operations on this 156 * controller. 157 */ 158 AHC_NEWEEPROM_FMT = 0x4000, 159 AHC_RESOURCE_SHORTAGE = 0x8000, 160 AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */ 161} ahc_flag; 162 163typedef enum { 164 SCB_FREE = 0x0000, 165 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 166 * Another device was active 167 * during the first timeout for 168 * this SCB so we gave ourselves 169 * an additional timeout period 170 * in case it was hogging the 171 * bus. 172 */ 173 SCB_DEVICE_RESET = 0x0004, 174 SCB_SENSE = 0x0008, 175 SCB_RECOVERY_SCB = 0x0040, 176 SCB_ABORT = 0x1000, 177 SCB_QUEUED_MSG = 0x2000, 178 SCB_ACTIVE = 0x4000, 179 SCB_TARGET_IMMEDIATE = 0x8000 180} scb_flag; 181 182/* 183 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 184 * consists of a "hardware SCB" mirroring the fields availible on the card 185 * and additional information the kernel stores for each transaction. 186 */ 187struct hardware_scb { 188/*0*/ u_int8_t control; 189/*1*/ u_int8_t tcl; /* 4/1/3 bits */ 190/*2*/ u_int8_t status; 191/*3*/ u_int8_t SG_count; 192/*4*/ u_int32_t SG_pointer; 193/*8*/ u_int8_t residual_SG_count; 194/*9*/ u_int8_t residual_data_count[3]; 195/*12*/ u_int32_t data; 196/*16*/ u_int32_t datalen; /* Really only three bytes, but its 197 * faster to treat it as a long on 198 * a quad boundary. 199 */ 200/*20*/ u_int32_t cmdpointer; 201/*24*/ u_int8_t cmdlen; 202/*25*/ u_int8_t tag; /* Index into our kernel SCB array. 203 * Also used as the tag for tagged I/O 204 */ 205/*26*/ u_int8_t next; /* Used for threading SCBs in the 206 * "Waiting for Selection" and 207 * "Disconnected SCB" lists down 208 * in the sequencer. 209 */ 210/*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */ 211/*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */ 212/*29*/ u_int8_t spare[3]; /* 213 * Spare space available on 214 * all controller types. 215 */ 216/*32*/ u_int8_t cmdstore[16]; /* 217 * CDB storage for controllers 218 * supporting 64 byte SCBs. 219 */ 220/*48*/ u_int32_t cmdstore_busaddr; /* 221 * Address of command store for 222 * 32byte SCB adapters 223 */ 224/*48*/ u_int8_t spare_64[12]; /* 225 * Pad to 64 bytes. 226 */ 227}; 228 229struct scb { 230 struct hardware_scb *hscb; 231 STAILQ_ENTRY(scb) links; /* for chaining */ 232 union ccb *ccb; /* the ccb for this cmd */ 233 scb_flag flags; 234 bus_dmamap_t dmamap; 235 struct ahc_dma_seg *ahc_dma;/* Pointer to SG segments */ 236 u_int32_t ahc_dmaphys;/* Phsical address of SG list */ 237 u_int sg_count;/* How full ahc_dma_seg is */ 238}; 239 240struct scb_data { 241 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 242 struct scb *scbarray[AHC_SCB_MAX]; /* Array of kernel SCBs */ 243 STAILQ_HEAD(, scb) free_scbs; /* 244 * Pool of SCBs ready to be assigned 245 * commands to execute. 246 */ 247 u_int8_t numscbs; 248 u_int8_t maxhscbs; /* Number of SCBs on the card */ 249 u_int8_t maxscbs; /* 250 * Max SCBs we allocate total including 251 * any that will force us to page SCBs 252 */ 253}; 254 255/* 256 * Connection desciptor for select-in requests in target mode. 257 * The first byte is the connecting target, followed by identify 258 * message and optional tag information, terminated by 0xFF. The 259 * remainder is the command to execute. The cmd_valid byte is on 260 * an 8 byte boundary to simplify setting it on aic7880 hardware 261 * which only has limited direct access to the DMA FIFO. 262 */ 263struct target_cmd { 264 u_int8_t initiator_channel; 265 u_int8_t targ_id; /* Target ID we were selected at */ 266 u_int8_t identify; /* Identify message */ 267 u_int8_t bytes[21]; 268 u_int8_t cmd_valid; 269 u_int8_t pad[7]; 270}; 271 272/* 273 * Per lun target mode state including accept TIO CCB 274 * and immediate notify CCB pools. 275 */ 276struct tmode_lstate { 277 struct ccb_hdr_slist accept_tios; 278 struct ccb_hdr_slist immed_notifies; 279}; 280 281#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 282#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 283#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 284#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 285 286struct ahc_transinfo { 287 u_int8_t width; 288 u_int8_t period; 289 u_int8_t offset; 290}; 291 292struct ahc_initiator_tinfo { 293 u_int8_t scsirate; 294 struct ahc_transinfo current; 295 struct ahc_transinfo goal; 296 struct ahc_transinfo user; 297}; 298 299/* 300 * Per target mode enabled target state. Esentially just an array of 301 * pointers to lun target state as well as sync/wide negotiation information 302 * for each initiator<->target mapping (including the mapping for when we 303 * are the initiator). 304 */ 305struct tmode_tstate { 306 struct tmode_lstate* enabled_luns[8]; 307 struct ahc_initiator_tinfo transinfo[16]; 308 309 /* 310 * Per initiator state bitmasks. 311 */ 312 u_int16_t ultraenb; /* Using ultra sync rate */ 313 u_int16_t discenable; /* Disconnection allowed */ 314 u_int16_t tagenable; /* Tagged Queuing allowed */ 315}; 316 317/* 318 * Define the format of the aic7XX0 SEEPROM registers (16 bits). 319 */ 320 321struct seeprom_config { 322/* 323 * SCSI ID Configuration Flags 324 */ 325 u_int16_t device_flags[16]; /* words 0-15 */ 326#define CFXFER 0x0007 /* synchronous transfer rate */ 327#define CFSYNCH 0x0008 /* enable synchronous transfer */ 328#define CFDISC 0x0010 /* enable disconnection */ 329#define CFWIDEB 0x0020 /* wide bus device */ 330#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 331/* UNUSED 0x0080 */ 332#define CFSTART 0x0100 /* send start unit SCSI command */ 333#define CFINCBIOS 0x0200 /* include in BIOS scan */ 334#define CFRNFOUND 0x0400 /* report even if not found */ 335#define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */ 336/* UNUSED 0xf000 */ 337 338/* 339 * BIOS Control Bits 340 */ 341 u_int16_t bios_control; /* word 16 */ 342#define CFSUPREM 0x0001 /* support all removeable drives */ 343#define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 344#define CFBIOSEN 0x0004 /* BIOS enabled */ 345/* UNUSED 0x0008 */ 346#define CFSM2DRV 0x0010 /* support more than two drives */ 347#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 348/* UNUSED 0x0060 */ 349#define CFEXTEND 0x0080 /* extended translation enabled */ 350/* UNUSED 0xff00 */ 351 352/* 353 * Host Adapter Control Bits 354 */ 355 u_int16_t adapter_control; /* word 17 */ 356#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 357#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 358#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 359#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 360#define CFSTERM 0x0004 /* SCSI low byte termination */ 361#define CFWSTERM 0x0008 /* SCSI high byte termination */ 362#define CFSPARITY 0x0010 /* SCSI parity */ 363#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 364#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 365#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */ 366#define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/ 367#define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */ 368/* UNUSED 0xf080 */ 369 370/* 371 * Bus Release, Host Adapter ID 372 */ 373 u_int16_t brtime_id; /* word 18 */ 374#define CFSCSIID 0x000f /* host adapter SCSI ID */ 375/* UNUSED 0x00f0 */ 376#define CFBRTIME 0xff00 /* bus release time */ 377 378/* 379 * Maximum targets 380 */ 381 u_int16_t max_targets; /* word 19 */ 382#define CFMAXTARG 0x00ff /* maximum targets */ 383/* UNUSED 0xff00 */ 384 u_int16_t res_1[11]; /* words 20-30 */ 385 u_int16_t checksum; /* word 31 */ 386}; 387 388struct ahc_syncrate { 389 int sxfr_ultra2; 390 int sxfr; 391 /* Rates in Ultra mode have bit 8 of sxfr set */ 392#define ULTRA_SXFR 0x100 393 u_int8_t period; /* Period to send to SCSI target */ 394 char *rate; 395}; 396 397typedef enum { 398 MSG_TYPE_NONE = 0x00, 399 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 400 MSG_TYPE_INITIATOR_MSGIN = 0x02, 401 MSG_TYPE_TARGET_MSGOUT = 0x03, 402 MSG_TYPE_TARGET_MSGIN = 0x04 403} ahc_msg_type; 404 405struct ahc_softc { 406 bus_space_tag_t tag; 407 bus_space_handle_t bsh; 408 bus_dma_tag_t dmat; 409 struct scb_data *scb_data; 410 411 /* 412 * CCBs that have been send to the controller 413 */ 414 LIST_HEAD(, ccb_hdr) pending_ccbs; 415 416 /* 417 * Target mode related state kept on a per enabled lun basis. 418 * Targets that are not enabled will have null entries. 419 * As an initiator, we keep one target entry for our initiator 420 * ID to store our sync/wide transfer settings. 421 */ 422 struct tmode_tstate* enabled_targets[16]; 423 424 /* 425 * The black hole device responsible for handling requests for 426 * disabled luns on enabled targets. 427 */ 428 struct tmode_lstate* black_hole; 429 430 /* 431 * Device instance currently on the bus awaiting a continue TIO 432 * for a command that was not given the disconnect priveledge. 433 */ 434 struct tmode_lstate* pending_device; 435 436 /* 437 * Card characteristics 438 */ 439 ahc_chip chip; 440 ahc_feature features; 441 ahc_flag flags; 442 443 /* Values to store in the SEQCTL register for pause and unpause */ 444 u_int8_t unpause; 445 u_int8_t pause; 446 447 /* Command Queues */ 448 u_int8_t qoutfifonext; 449 u_int8_t qinfifonext; 450 u_int8_t qoutfifo[256]; 451 u_int8_t qinfifo[256]; 452 453 /* 454 * 256 byte array storing the SCBID of outstanding 455 * untagged SCBs indexed by TCL. 456 */ 457 u_int8_t untagged_scbs[256]; 458 459 /* 460 * Hooks into the XPT. 461 */ 462 struct cam_sim *sim; 463 struct cam_sim *sim_b; 464 struct cam_path *path; 465 struct cam_path *path_b; 466 467 int unit; 468 469 /* Channel Names ('A', 'B', etc.) */ 470 char channel; 471 char channel_b; 472 473 /* Initiator Bus ID */ 474 u_int8_t our_id; 475 u_int8_t our_id_b; 476 477 /* Targets that need negotiation messages */ 478 u_int16_t targ_msg_req; 479 480 /* 481 * PCI error detection and data for running the 482 * PCI error interrupt handler. 483 */ 484 int unsolicited_ints; 485 pcici_t pci_config_id; 486 487 /* 488 * Target incoming command FIFO. 489 */ 490 struct target_cmd *targetcmds; 491 u_int8_t tqinfifonext; 492 493 /* 494 * Incoming and outgoing message handling. 495 */ 496 u_int8_t send_msg_perror; 497 ahc_msg_type msg_type; 498 u_int8_t msgout_buf[8]; /* Message we are sending */ 499 u_int8_t msgin_buf[8]; /* Message we are receiving */ 500 u_int msgout_len; /* Length of message to send */ 501 u_int msgout_index; /* Current index in msgout */ 502 u_int msgin_index; /* Current index in msgin */ 503 504 /* Number of enabled target mode device on this card */ 505 u_int enabled_luns; 506 507 /* 508 * "Bus" addresses of our data structures. 509 */ 510 u_int32_t hscb_busaddr; 511}; 512 513struct full_ahc_softc { 514 struct ahc_softc softc; 515 struct scb_data scb_data_storage; 516}; 517 518/* #define AHC_DEBUG */ 519#ifdef AHC_DEBUG 520/* Different debugging levels used when AHC_DEBUG is defined */ 521#define AHC_SHOWMISC 0x0001 522#define AHC_SHOWCMDS 0x0002 523#define AHC_SHOWSCBS 0x0004 524#define AHC_SHOWABORTS 0x0008 525#define AHC_SHOWSENSE 0x0010 526#define AHC_SHOWSCBCNT 0x0020 527 528extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */ 529#endif 530 531char *ahc_name(struct ahc_softc *ahc); 532 533struct ahc_softc *ahc_alloc(int unit, u_int32_t io_base, 534 vm_offset_t maddr, ahc_chip chip, 535 ahc_feature features, ahc_flag flags, 536 struct scb_data *scb_data); 537int ahc_reset(struct ahc_softc *ahc); 538void ahc_free(struct ahc_softc *); 539int ahc_probe_scbs(struct ahc_softc *); 540int ahc_init(struct ahc_softc *); 541int ahc_attach(struct ahc_softc *); 542void ahc_intr(void *arg); 543 544#define ahc_inb(ahc, port) \ 545 bus_space_read_1((ahc)->tag, (ahc)->bsh, port) 546 547#define ahc_outb(ahc, port, value) \ 548 bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value) 549 550#define ahc_outsb(ahc, port, valp, count) \ 551 bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count) 552 553#endif /* _AIC7XXX_H_ */ 554