aic7xxx.h revision 115332
194380Sdfr/* 2119331Speter * Core definitions and data structures shareable across OS platforms. 3119331Speter * 4119331Speter * Copyright (c) 1994-2001 Justin T. Gibbs. 5119331Speter * Copyright (c) 2000-2001 Adaptec Inc. 6119331Speter * All rights reserved. 794380Sdfr * 8119331Speter * Redistribution and use in source and binary forms, with or without 9119331Speter * modification, are permitted provided that the following conditions 10119331Speter * are met: 11219559Savg * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#76 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.h 115332 2003-05-26 21:20:47Z gibbs $ 43 */ 44 45#ifndef _AIC7XXX_H_ 46#define _AIC7XXX_H_ 47 48/* Register Definitions */ 49#include "aic7xxx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahc_platform_data; 53struct scb_platform_data; 54struct seeprom_descriptor; 55 56/****************************** Useful Macros *********************************/ 57#ifndef MAX 58#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 59#endif 60 61#ifndef MIN 62#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 63#endif 64 65#ifndef TRUE 66#define TRUE 1 67#endif 68#ifndef FALSE 69#define FALSE 0 70#endif 71 72#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 73 74#define ALL_CHANNELS '\0' 75#define ALL_TARGETS_MASK 0xFFFF 76#define INITIATOR_WILDCARD (~0) 77 78#define SCSIID_TARGET(ahc, scsiid) \ 79 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \ 80 >> TID_SHIFT) 81#define SCSIID_OUR_ID(scsiid) \ 82 ((scsiid) & OID) 83#define SCSIID_CHANNEL(ahc, scsiid) \ 84 ((((ahc)->features & AHC_TWIN) != 0) \ 85 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \ 86 : 'A') 87#define SCB_IS_SCSIBUS_B(ahc, scb) \ 88 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B') 89#define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91#define SCB_GET_TARGET(ahc, scb) \ 92 SCSIID_TARGET((ahc), (scb)->hscb->scsiid) 93#define SCB_GET_CHANNEL(ahc, scb) \ 94 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) 95#define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun) 97#define SCB_GET_TARGET_OFFSET(ahc, scb) \ 98 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0)) 99#define SCB_GET_TARGET_MASK(ahc, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb))) 101#ifdef AHC_DEBUG 102#define SCB_IS_SILENT(scb) \ 103 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \ 104 && (((scb)->flags & SCB_SILENT) != 0)) 105#else 106#define SCB_IS_SILENT(scb) \ 107 (((scb)->flags & SCB_SILENT) != 0) 108#endif 109#define TCL_TARGET_OFFSET(tcl) \ 110 ((((tcl) >> 4) & TID) >> 4) 111#define TCL_LUN(tcl) \ 112 (tcl & (AHC_NUM_LUNS - 1)) 113#define BUILD_TCL(scsiid, lun) \ 114 ((lun) | (((scsiid) & TID) << 4)) 115 116#ifndef AHC_TARGET_MODE 117#undef AHC_TMODE_ENABLE 118#define AHC_TMODE_ENABLE 0 119#endif 120 121/**************************** Driver Constants ********************************/ 122/* 123 * The maximum number of supported targets. 124 */ 125#define AHC_NUM_TARGETS 16 126 127/* 128 * The maximum number of supported luns. 129 * The identify message only supports 64 luns in SPI3. 130 * You can have 2^64 luns when information unit transfers are enabled, 131 * but it is doubtful this driver will ever support IUTs. 132 */ 133#define AHC_NUM_LUNS 64 134 135/* 136 * The maximum transfer per S/G segment. 137 */ 138#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 139 140/* 141 * The maximum amount of SCB storage in hardware on a controller. 142 * This value represents an upper bound. Controllers vary in the number 143 * they actually support. 144 */ 145#define AHC_SCB_MAX 255 146 147/* 148 * The maximum number of concurrent transactions supported per driver instance. 149 * Sequencer Control Blocks (SCBs) store per-transaction information. Although 150 * the space for SCBs on the host adapter varies by model, the driver will 151 * page the SCBs between host and controller memory as needed. We are limited 152 * to 253 because: 153 * 1) The 8bit nature of the RISC engine holds us to an 8bit value. 154 * 2) We reserve one value, 255, to represent the invalid element. 155 * 3) Our input queue scheme requires one SCB to always be reserved 156 * in advance of queuing any SCBs. This takes us down to 254. 157 * 4) To handle our output queue correctly on machines that only 158 * support 32bit stores, we must clear the array 4 bytes at a 159 * time. To avoid colliding with a DMA write from the sequencer, 160 * we must be sure that 4 slots are empty when we write to clear 161 * the queue. This reduces us to 253 SCBs: 1 that just completed 162 * and the known three additional empty slots in the queue that 163 * precede it. 164 */ 165#define AHC_MAX_QUEUE 253 166 167/* 168 * The maximum amount of SCB storage we allocate in host memory. This 169 * number should reflect the 1 additional SCB we require to handle our 170 * qinfifo mechanism. 171 */ 172#define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1) 173 174/* 175 * Ring Buffer of incoming target commands. 176 * We allocate 256 to simplify the logic in the sequencer 177 * by using the natural wrap point of an 8bit counter. 178 */ 179#define AHC_TMODE_CMDS 256 180 181/* Reset line assertion time in us */ 182#define AHC_BUSRESET_DELAY 25 183 184/******************* Chip Characteristics/Operating Settings *****************/ 185/* 186 * Chip Type 187 * The chip order is from least sophisticated to most sophisticated. 188 */ 189typedef enum { 190 AHC_NONE = 0x0000, 191 AHC_CHIPID_MASK = 0x00FF, 192 AHC_AIC7770 = 0x0001, 193 AHC_AIC7850 = 0x0002, 194 AHC_AIC7855 = 0x0003, 195 AHC_AIC7859 = 0x0004, 196 AHC_AIC7860 = 0x0005, 197 AHC_AIC7870 = 0x0006, 198 AHC_AIC7880 = 0x0007, 199 AHC_AIC7895 = 0x0008, 200 AHC_AIC7895C = 0x0009, 201 AHC_AIC7890 = 0x000a, 202 AHC_AIC7896 = 0x000b, 203 AHC_AIC7892 = 0x000c, 204 AHC_AIC7899 = 0x000d, 205 AHC_VL = 0x0100, /* Bus type VL */ 206 AHC_EISA = 0x0200, /* Bus type EISA */ 207 AHC_PCI = 0x0400, /* Bus type PCI */ 208 AHC_BUS_MASK = 0x0F00 209} ahc_chip; 210 211/* 212 * Features available in each chip type. 213 */ 214typedef enum { 215 AHC_FENONE = 0x00000, 216 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */ 217 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */ 218 AHC_WIDE = 0x00004, /* Wide Channel */ 219 AHC_TWIN = 0x00008, /* Twin Channel */ 220 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */ 221 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */ 222 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */ 223 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */ 224 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */ 225 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */ 226 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */ 227 AHC_DT = 0x00800, /* Double Transition transfers */ 228 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */ 229 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */ 230 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */ 231 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/ 232 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */ 233 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */ 234 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */ 235 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */ 236 AHC_AIC7770_FE = AHC_FENONE, 237 /* 238 * The real 7850 does not support Ultra modes, but there are 239 * several cards that use the generic 7850 PCI ID even though 240 * they are using an Ultra capable chip (7859/7860). We start 241 * out with the AHC_ULTRA feature set and then check the DEVSTATUS 242 * register to determine if the capability is really present. 243 */ 244 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA, 245 AHC_AIC7860_FE = AHC_AIC7850_FE, 246 AHC_AIC7870_FE = AHC_TARGETMODE, 247 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA, 248 /* 249 * Although we have space for both the initiator and 250 * target roles on ULTRA2 chips, we currently disable 251 * the initiator role to allow multi-scsi-id target mode 252 * configurations. We can only respond on the same SCSI 253 * ID as our initiator role if we allow initiator operation. 254 * At some point, we should add a configuration knob to 255 * allow both roles to be loaded. 256 */ 257 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2 258 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID 259 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS 260 |AHC_TARGETMODE, 261 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE, 262 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE 263 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS, 264 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID, 265 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC, 266 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC 267} ahc_feature; 268 269/* 270 * Bugs in the silicon that we work around in software. 271 */ 272typedef enum { 273 AHC_BUGNONE = 0x00, 274 /* 275 * On all chips prior to the U2 product line, 276 * the WIDEODD S/G segment feature does not 277 * work during scsi->HostBus transfers. 278 */ 279 AHC_TMODE_WIDEODD_BUG = 0x01, 280 /* 281 * On the aic7890/91 Rev 0 chips, the autoflush 282 * feature does not work. A manual flush of 283 * the DMA FIFO is required. 284 */ 285 AHC_AUTOFLUSH_BUG = 0x02, 286 /* 287 * On many chips, cacheline streaming does not work. 288 */ 289 AHC_CACHETHEN_BUG = 0x04, 290 /* 291 * On the aic7896/97 chips, cacheline 292 * streaming must be enabled. 293 */ 294 AHC_CACHETHEN_DIS_BUG = 0x08, 295 /* 296 * PCI 2.1 Retry failure on non-empty data fifo. 297 */ 298 AHC_PCI_2_1_RETRY_BUG = 0x10, 299 /* 300 * Controller does not handle cacheline residuals 301 * properly on S/G segments if PCI MWI instructions 302 * are allowed. 303 */ 304 AHC_PCI_MWI_BUG = 0x20, 305 /* 306 * An SCB upload using the SCB channel's 307 * auto array entry copy feature may 308 * corrupt data. This appears to only 309 * occur on 66MHz systems. 310 */ 311 AHC_SCBCHAN_UPLOAD_BUG = 0x40 312} ahc_bug; 313 314/* 315 * Configuration specific settings. 316 * The driver determines these settings by probing the 317 * chip/controller's configuration. 318 */ 319typedef enum { 320 AHC_FNONE = 0x000, 321 AHC_PRIMARY_CHANNEL = 0x003, /* 322 * The channel that should 323 * be probed first. 324 */ 325 AHC_USEDEFAULTS = 0x004, /* 326 * For cards without an seeprom 327 * or a BIOS to initialize the chip's 328 * SRAM, we use the default target 329 * settings. 330 */ 331 AHC_SEQUENCER_DEBUG = 0x008, 332 AHC_SHARED_SRAM = 0x010, 333 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */ 334 AHC_RESET_BUS_A = 0x040, 335 AHC_RESET_BUS_B = 0x080, 336 AHC_EXTENDED_TRANS_A = 0x100, 337 AHC_EXTENDED_TRANS_B = 0x200, 338 AHC_TERM_ENB_A = 0x400, 339 AHC_TERM_ENB_B = 0x800, 340 AHC_INITIATORROLE = 0x1000, /* 341 * Allow initiator operations on 342 * this controller. 343 */ 344 AHC_TARGETROLE = 0x2000, /* 345 * Allow target operations on this 346 * controller. 347 */ 348 AHC_NEWEEPROM_FMT = 0x4000, 349 AHC_RESOURCE_SHORTAGE = 0x8000, 350 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */ 351 AHC_INT50_SPEEDFLEX = 0x20000, /* 352 * Internal 50pin connector 353 * sits behind an aic3860 354 */ 355 AHC_SCB_BTT = 0x40000, /* 356 * The busy targets table is 357 * stored in SCB space rather 358 * than SRAM. 359 */ 360 AHC_BIOS_ENABLED = 0x80000, 361 AHC_ALL_INTERRUPTS = 0x100000, 362 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */ 363 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */ 364 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */ 365 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */ 366 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */ 367 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */ 368 AHC_DISABLE_PCI_PERR = 0x10000000, 369 AHC_HAS_TERM_LOGIC = 0x20000000 370} ahc_flag; 371 372/************************* Hardware SCB Definition ***************************/ 373 374/* 375 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 376 * consists of a "hardware SCB" mirroring the fields available on the card 377 * and additional information the kernel stores for each transaction. 378 * 379 * To minimize space utilization, a portion of the hardware scb stores 380 * different data during different portions of a SCSI transaction. 381 * As initialized by the host driver for the initiator role, this area 382 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 383 * the cdb has been presented to the target, this area serves to store 384 * residual transfer information and the SCSI status byte. 385 * For the target role, the contents of this area do not change, but 386 * still serve a different purpose than for the initiator role. See 387 * struct target_data for details. 388 */ 389 390/* 391 * Status information embedded in the shared poriton of 392 * an SCB after passing the cdb to the target. The kernel 393 * driver will only read this data for transactions that 394 * complete abnormally (non-zero status byte). 395 */ 396struct status_pkt { 397 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 398 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 399 uint8_t scsi_status; /* Standard SCSI status byte */ 400}; 401 402/* 403 * Target mode version of the shared data SCB segment. 404 */ 405struct target_data { 406 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 407 uint32_t residual_sg_ptr; /* The next S/G for this transfer */ 408 uint8_t scsi_status; /* SCSI status to give to initiator */ 409 uint8_t target_phases; /* Bitmap of phases to execute */ 410 uint8_t data_phase; /* Data-In or Data-Out */ 411 uint8_t initiator_tag; /* Initiator's transaction tag */ 412}; 413 414struct hardware_scb { 415/*0*/ union { 416 /* 417 * If the cdb is 12 bytes or less, we embed it directly 418 * in the SCB. For longer cdbs, we embed the address 419 * of the cdb payload as seen by the chip and a DMA 420 * is used to pull it in. 421 */ 422 uint8_t cdb[12]; 423 uint32_t cdb_ptr; 424 struct status_pkt status; 425 struct target_data tdata; 426 } shared_data; 427/* 428 * A word about residuals. 429 * The scb is presented to the sequencer with the dataptr and datacnt 430 * fields initialized to the contents of the first S/G element to 431 * transfer. The sgptr field is initialized to the bus address for 432 * the S/G element that follows the first in the in core S/G array 433 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 434 * S/G entry for this transfer (single S/G element transfer with the 435 * first elements address and length preloaded in the dataptr/datacnt 436 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 437 * The SG_FULL_RESID flag ensures that the residual will be correctly 438 * noted even if no data transfers occur. Once the data phase is entered, 439 * the residual sgptr and datacnt are loaded from the sgptr and the 440 * datacnt fields. After each S/G element's dataptr and length are 441 * loaded into the hardware, the residual sgptr is advanced. After 442 * each S/G element is expired, its datacnt field is checked to see 443 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 444 * residual sg ptr and the transfer is considered complete. If the 445 * sequencer determines that there is a residual in the tranfer, it 446 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into 447 * host memory. To sumarize: 448 * 449 * Sequencer: 450 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 451 * or residual_sgptr does not have SG_LIST_NULL set. 452 * 453 * o We are transfering the last segment if residual_datacnt has 454 * the SG_LAST_SEG flag set. 455 * 456 * Host: 457 * o A residual has occurred if a completed scb has the 458 * SG_RESID_VALID flag set. 459 * 460 * o residual_sgptr and sgptr refer to the "next" sg entry 461 * and so may point beyond the last valid sg entry for the 462 * transfer. 463 */ 464/*12*/ uint32_t dataptr; 465/*16*/ uint32_t datacnt; /* 466 * Byte 3 (numbered from 0) of 467 * the datacnt is really the 468 * 4th byte in that data address. 469 */ 470/*20*/ uint32_t sgptr; 471#define SG_PTR_MASK 0xFFFFFFF8 472/*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */ 473/*25*/ uint8_t scsiid; /* what to load in the SCSIID register */ 474/*26*/ uint8_t lun; 475/*27*/ uint8_t tag; /* 476 * Index into our kernel SCB array. 477 * Also used as the tag for tagged I/O 478 */ 479/*28*/ uint8_t cdb_len; 480/*29*/ uint8_t scsirate; /* Value for SCSIRATE register */ 481/*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */ 482/*31*/ uint8_t next; /* 483 * Used for threading SCBs in the 484 * "Waiting for Selection" and 485 * "Disconnected SCB" lists down 486 * in the sequencer. 487 */ 488/*32*/ uint8_t cdb32[32]; /* 489 * CDB storage for cdbs of size 490 * 13->32. We store them here 491 * because hardware scbs are 492 * allocated from DMA safe 493 * memory so we are guaranteed 494 * the controller can access 495 * this data. 496 */ 497}; 498 499/************************ Kernel SCB Definitions ******************************/ 500/* 501 * Some fields of the SCB are OS dependent. Here we collect the 502 * definitions for elements that all OS platforms need to include 503 * in there SCB definition. 504 */ 505 506/* 507 * Definition of a scatter/gather element as transfered to the controller. 508 * The aic7xxx chips only support a 24bit length. We use the top byte of 509 * the length to store additional address bits and a flag to indicate 510 * that a given segment terminates the transfer. This gives us an 511 * addressable range of 512GB on machines with 64bit PCI or with chips 512 * that can support dual address cycles on 32bit PCI busses. 513 */ 514struct ahc_dma_seg { 515 uint32_t addr; 516 uint32_t len; 517#define AHC_DMA_LAST_SEG 0x80000000 518#define AHC_SG_HIGH_ADDR_MASK 0x7F000000 519#define AHC_SG_LEN_MASK 0x00FFFFFF 520}; 521 522struct sg_map_node { 523 bus_dmamap_t sg_dmamap; 524 bus_addr_t sg_physaddr; 525 struct ahc_dma_seg* sg_vaddr; 526 SLIST_ENTRY(sg_map_node) links; 527}; 528 529/* 530 * The current state of this SCB. 531 */ 532typedef enum { 533 SCB_FREE = 0x0000, 534 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 535 * Another device was active 536 * during the first timeout for 537 * this SCB so we gave ourselves 538 * an additional timeout period 539 * in case it was hogging the 540 * bus. 541 */ 542 SCB_DEVICE_RESET = 0x0004, 543 SCB_SENSE = 0x0008, 544 SCB_CDB32_PTR = 0x0010, 545 SCB_RECOVERY_SCB = 0x0020, 546 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 547 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 548 SCB_ABORT = 0x0100, 549 SCB_UNTAGGEDQ = 0x0200, 550 SCB_ACTIVE = 0x0400, 551 SCB_TARGET_IMMEDIATE = 0x0800, 552 SCB_TRANSMISSION_ERROR = 0x1000,/* 553 * We detected a parity or CRC 554 * error that has effected the 555 * payload of the command. This 556 * flag is checked when normal 557 * status is returned to catch 558 * the case of a target not 559 * responding to our attempt 560 * to report the error. 561 */ 562 SCB_TARGET_SCB = 0x2000, 563 SCB_SILENT = 0x4000 /* 564 * Be quiet about transmission type 565 * errors. They are expected and we 566 * don't want to upset the user. This 567 * flag is typically used during DV. 568 */ 569} scb_flag; 570 571struct scb { 572 struct hardware_scb *hscb; 573 union { 574 SLIST_ENTRY(scb) sle; 575 TAILQ_ENTRY(scb) tqe; 576 } links; 577 LIST_ENTRY(scb) pending_links; 578 ahc_io_ctx_t io_ctx; 579 struct ahc_softc *ahc_softc; 580 scb_flag flags; 581#ifndef __linux__ 582 bus_dmamap_t dmamap; 583#endif 584 struct scb_platform_data *platform_data; 585 struct sg_map_node *sg_map; 586 struct ahc_dma_seg *sg_list; 587 bus_addr_t sg_list_phys; 588 u_int sg_count;/* How full ahc_dma_seg is */ 589}; 590 591struct scb_data { 592 SLIST_HEAD(, scb) free_scbs; /* 593 * Pool of SCBs ready to be assigned 594 * commands to execute. 595 */ 596 struct scb *scbindex[256]; /* 597 * Mapping from tag to SCB. 598 * As tag identifiers are an 599 * 8bit value, we provide space 600 * for all possible tag values. 601 * Any lookups to entries at or 602 * above AHC_SCB_MAX_ALLOC will 603 * always fail. 604 */ 605 struct hardware_scb *hscbs; /* Array of hardware SCBs */ 606 struct scb *scbarray; /* Array of kernel SCBs */ 607 struct scsi_sense_data *sense; /* Per SCB sense data */ 608 609 /* 610 * "Bus" addresses of our data structures. 611 */ 612 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 613 bus_dmamap_t hscb_dmamap; 614 bus_addr_t hscb_busaddr; 615 bus_dma_tag_t sense_dmat; 616 bus_dmamap_t sense_dmamap; 617 bus_addr_t sense_busaddr; 618 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 619 SLIST_HEAD(, sg_map_node) sg_maps; 620 uint8_t numscbs; 621 uint8_t maxhscbs; /* Number of SCBs on the card */ 622 uint8_t init_level; /* 623 * How far we've initialized 624 * this structure. 625 */ 626}; 627 628/************************ Target Mode Definitions *****************************/ 629 630/* 631 * Connection desciptor for select-in requests in target mode. 632 */ 633struct target_cmd { 634 uint8_t scsiid; /* Our ID and the initiator's ID */ 635 uint8_t identify; /* Identify message */ 636 uint8_t bytes[22]; /* 637 * Bytes contains any additional message 638 * bytes terminated by 0xFF. The remainder 639 * is the cdb to execute. 640 */ 641 uint8_t cmd_valid; /* 642 * When a command is complete, the firmware 643 * will set cmd_valid to all bits set. 644 * After the host has seen the command, 645 * the bits are cleared. This allows us 646 * to just peek at host memory to determine 647 * if more work is complete. cmd_valid is on 648 * an 8 byte boundary to simplify setting 649 * it on aic7880 hardware which only has 650 * limited direct access to the DMA FIFO. 651 */ 652 uint8_t pad[7]; 653}; 654 655/* 656 * Number of events we can buffer up if we run out 657 * of immediate notify ccbs. 658 */ 659#define AHC_TMODE_EVENT_BUFFER_SIZE 8 660struct ahc_tmode_event { 661 uint8_t initiator_id; 662 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 663#define EVENT_TYPE_BUS_RESET 0xFF 664 uint8_t event_arg; 665}; 666 667/* 668 * Per enabled lun target mode state. 669 * As this state is directly influenced by the host OS'es target mode 670 * environment, we let the OS module define it. Forward declare the 671 * structure here so we can store arrays of them, etc. in OS neutral 672 * data structures. 673 */ 674#ifdef AHC_TARGET_MODE 675struct ahc_tmode_lstate { 676 struct cam_path *path; 677 struct ccb_hdr_slist accept_tios; 678 struct ccb_hdr_slist immed_notifies; 679 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE]; 680 uint8_t event_r_idx; 681 uint8_t event_w_idx; 682}; 683#else 684struct ahc_tmode_lstate; 685#endif 686 687/******************** Transfer Negotiation Datastructures *********************/ 688#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */ 689#define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 690#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */ 691#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */ 692 693#define AHC_WIDTH_UNKNOWN 0xFF 694#define AHC_PERIOD_UNKNOWN 0xFF 695#define AHC_OFFSET_UNKNOWN 0xFF 696#define AHC_PPR_OPTS_UNKNOWN 0xFF 697 698/* 699 * Transfer Negotiation Information. 700 */ 701struct ahc_transinfo { 702 uint8_t protocol_version; /* SCSI Revision level */ 703 uint8_t transport_version; /* SPI Revision level */ 704 uint8_t width; /* Bus width */ 705 uint8_t period; /* Sync rate factor */ 706 uint8_t offset; /* Sync offset */ 707 uint8_t ppr_options; /* Parallel Protocol Request options */ 708}; 709 710/* 711 * Per-initiator current, goal and user transfer negotiation information. */ 712struct ahc_initiator_tinfo { 713 uint8_t scsirate; /* Computed value for SCSIRATE reg */ 714 struct ahc_transinfo curr; 715 struct ahc_transinfo goal; 716 struct ahc_transinfo user; 717}; 718 719/* 720 * Per enabled target ID state. 721 * Pointers to lun target state as well as sync/wide negotiation information 722 * for each initiator<->target mapping. For the initiator role we pretend 723 * that we are the target and the targets are the initiators since the 724 * negotiation is the same regardless of role. 725 */ 726struct ahc_tmode_tstate { 727 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS]; 728 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS]; 729 730 /* 731 * Per initiator state bitmasks. 732 */ 733 uint16_t auto_negotiate;/* Auto Negotiation Required */ 734 uint16_t ultraenb; /* Using ultra sync rate */ 735 uint16_t discenable; /* Disconnection allowed */ 736 uint16_t tagenable; /* Tagged Queuing allowed */ 737}; 738 739/* 740 * Data structure for our table of allowed synchronous transfer rates. 741 */ 742struct ahc_syncrate { 743 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */ 744 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */ 745#define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */ 746#define ST_SXFR 0x010 /* Rate Single Transition Only */ 747#define DT_SXFR 0x040 /* Rate Double Transition Only */ 748 uint8_t period; /* Period to send to SCSI target */ 749 char *rate; 750}; 751 752/* Safe and valid period for async negotiations. */ 753#define AHC_ASYNC_XFER_PERIOD 0x45 754#define AHC_ULTRA2_XFER_PERIOD 0x0a 755 756/* 757 * Indexes into our table of syncronous transfer rates. 758 */ 759#define AHC_SYNCRATE_DT 0 760#define AHC_SYNCRATE_ULTRA2 1 761#define AHC_SYNCRATE_ULTRA 3 762#define AHC_SYNCRATE_FAST 6 763#define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT 764#define AHC_SYNCRATE_MIN 13 765 766/***************************** Lookup Tables **********************************/ 767/* 768 * Phase -> name and message out response 769 * to parity errors in each phase table. 770 */ 771struct ahc_phase_table_entry { 772 uint8_t phase; 773 uint8_t mesg_out; /* Message response to parity errors */ 774 char *phasemsg; 775}; 776 777/************************** Serial EEPROM Format ******************************/ 778 779struct seeprom_config { 780/* 781 * Per SCSI ID Configuration Flags 782 */ 783 uint16_t device_flags[16]; /* words 0-15 */ 784#define CFXFER 0x0007 /* synchronous transfer rate */ 785#define CFSYNCH 0x0008 /* enable synchronous transfer */ 786#define CFDISC 0x0010 /* enable disconnection */ 787#define CFWIDEB 0x0020 /* wide bus device */ 788#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/ 789#define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */ 790#define CFSTART 0x0100 /* send start unit SCSI command */ 791#define CFINCBIOS 0x0200 /* include in BIOS scan */ 792#define CFRNFOUND 0x0400 /* report even if not found */ 793#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 794#define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */ 795#define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */ 796 797/* 798 * BIOS Control Bits 799 */ 800 uint16_t bios_control; /* word 16 */ 801#define CFSUPREM 0x0001 /* support all removeable drives */ 802#define CFSUPREMB 0x0002 /* support removeable boot drives */ 803#define CFBIOSEN 0x0004 /* BIOS enabled */ 804#define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */ 805#define CFSM2DRV 0x0010 /* support more than two drives */ 806#define CFSTPWLEVEL 0x0010 /* Termination level control */ 807#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */ 808#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 809#define CFTERM_MENU 0x0040 /* BIOS displays termination menu */ 810#define CFEXTEND 0x0080 /* extended translation enabled */ 811#define CFSCAMEN 0x0100 /* SCAM enable */ 812#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 813#define CFMSG_VERBOSE 0x0000 814#define CFMSG_SILENT 0x0200 815#define CFMSG_DIAG 0x0400 816#define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */ 817/* UNUSED 0xff00 */ 818 819/* 820 * Host Adapter Control Bits 821 */ 822 uint16_t adapter_control; /* word 17 */ 823#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 824#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */ 825#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */ 826#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */ 827#define CFSTERM 0x0004 /* SCSI low byte termination */ 828#define CFWSTERM 0x0008 /* SCSI high byte termination */ 829#define CFSPARITY 0x0010 /* SCSI parity */ 830#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */ 831#define CFMULTILUN 0x0020 832#define CFRESETB 0x0040 /* reset SCSI bus at boot */ 833#define CFCLUSTERENB 0x0080 /* Cluster Enable */ 834#define CFBOOTCHAN 0x0300 /* probe this channel first */ 835#define CFBOOTCHANSHIFT 8 836#define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/ 837#define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */ 838#define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */ 839#define CFENABLEDV 0x4000 /* Perform Domain Validation*/ 840 841/* 842 * Bus Release Time, Host Adapter ID 843 */ 844 uint16_t brtime_id; /* word 18 */ 845#define CFSCSIID 0x000f /* host adapter SCSI ID */ 846/* UNUSED 0x00f0 */ 847#define CFBRTIME 0xff00 /* bus release time */ 848 849/* 850 * Maximum targets 851 */ 852 uint16_t max_targets; /* word 19 */ 853#define CFMAXTARG 0x00ff /* maximum targets */ 854#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 855#define CFBOOTID 0xf000 /* Target to boot from */ 856 uint16_t res_1[10]; /* words 20-29 */ 857 uint16_t signature; /* Signature == 0x250 */ 858#define CFSIGNATURE 0x250 859#define CFSIGNATURE2 0x300 860 uint16_t checksum; /* word 31 */ 861}; 862 863/**************************** Message Buffer *********************************/ 864typedef enum { 865 MSG_TYPE_NONE = 0x00, 866 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 867 MSG_TYPE_INITIATOR_MSGIN = 0x02, 868 MSG_TYPE_TARGET_MSGOUT = 0x03, 869 MSG_TYPE_TARGET_MSGIN = 0x04 870} ahc_msg_type; 871 872typedef enum { 873 MSGLOOP_IN_PROG, 874 MSGLOOP_MSGCOMPLETE, 875 MSGLOOP_TERMINATED 876} msg_loop_stat; 877 878/*********************** Software Configuration Structure *********************/ 879TAILQ_HEAD(scb_tailq, scb); 880 881struct ahc_aic7770_softc { 882 /* 883 * Saved register state used for chip_init(). 884 */ 885 uint8_t busspd; 886 uint8_t bustime; 887}; 888 889struct ahc_pci_softc { 890 /* 891 * Saved register state used for chip_init(). 892 */ 893 uint32_t devconfig; 894 uint16_t targcrccnt; 895 uint8_t command; 896 uint8_t csize_lattime; 897 uint8_t optionmode; 898 uint8_t crccontrol1; 899 uint8_t dscommand0; 900 uint8_t dspcistatus; 901 uint8_t scbbaddr; 902 uint8_t dff_thrsh; 903}; 904 905union ahc_bus_softc { 906 struct ahc_aic7770_softc aic7770_softc; 907 struct ahc_pci_softc pci_softc; 908}; 909 910typedef void (*ahc_bus_intr_t)(struct ahc_softc *); 911typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *); 912typedef int (*ahc_bus_suspend_t)(struct ahc_softc *); 913typedef int (*ahc_bus_resume_t)(struct ahc_softc *); 914typedef void ahc_callback_t (void *); 915 916struct ahc_softc { 917 bus_space_tag_t tag; 918 bus_space_handle_t bsh; 919#ifndef __linux__ 920 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 921#endif 922 struct scb_data *scb_data; 923 924 struct scb *next_queued_scb; 925 926 /* 927 * SCBs that have been sent to the controller 928 */ 929 LIST_HEAD(, scb) pending_scbs; 930 931 /* 932 * Counting lock for deferring the release of additional 933 * untagged transactions from the untagged_queues. When 934 * the lock is decremented to 0, all queues in the 935 * untagged_queues array are run. 936 */ 937 u_int untagged_queue_lock; 938 939 /* 940 * Per-target queue of untagged-transactions. The 941 * transaction at the head of the queue is the 942 * currently pending untagged transaction for the 943 * target. The driver only allows a single untagged 944 * transaction per target. 945 */ 946 struct scb_tailq untagged_queues[AHC_NUM_TARGETS]; 947 948 /* 949 * Bus attachment specific data. 950 */ 951 union ahc_bus_softc bus_softc; 952 953 /* 954 * Platform specific data. 955 */ 956 struct ahc_platform_data *platform_data; 957 958 /* 959 * Platform specific device information. 960 */ 961 ahc_dev_softc_t dev_softc; 962 963 /* 964 * Bus specific device information. 965 */ 966 ahc_bus_intr_t bus_intr; 967 968 /* 969 * Bus specific initialization required 970 * after a chip reset. 971 */ 972 ahc_bus_chip_init_t bus_chip_init; 973 974 /* 975 * Bus specific suspend routine. 976 */ 977 ahc_bus_suspend_t bus_suspend; 978 979 /* 980 * Bus specific resume routine. 981 */ 982 ahc_bus_resume_t bus_resume; 983 984 /* 985 * Target mode related state kept on a per enabled lun basis. 986 * Targets that are not enabled will have null entries. 987 * As an initiator, we keep one target entry for our initiator 988 * ID to store our sync/wide transfer settings. 989 */ 990 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS]; 991 992 /* 993 * The black hole device responsible for handling requests for 994 * disabled luns on enabled targets. 995 */ 996 struct ahc_tmode_lstate *black_hole; 997 998 /* 999 * Device instance currently on the bus awaiting a continue TIO 1000 * for a command that was not given the disconnect priveledge. 1001 */ 1002 struct ahc_tmode_lstate *pending_device; 1003 1004 /* 1005 * Card characteristics 1006 */ 1007 ahc_chip chip; 1008 ahc_feature features; 1009 ahc_bug bugs; 1010 ahc_flag flags; 1011 struct seeprom_config *seep_config; 1012 1013 /* Values to store in the SEQCTL register for pause and unpause */ 1014 uint8_t unpause; 1015 uint8_t pause; 1016 1017 /* Command Queues */ 1018 uint8_t qoutfifonext; 1019 uint8_t qinfifonext; 1020 uint8_t *qoutfifo; 1021 uint8_t *qinfifo; 1022 1023 /* Critical Section Data */ 1024 struct cs *critical_sections; 1025 u_int num_critical_sections; 1026 1027 /* Links for chaining softcs */ 1028 TAILQ_ENTRY(ahc_softc) links; 1029 1030 /* Channel Names ('A', 'B', etc.) */ 1031 char channel; 1032 char channel_b; 1033 1034 /* Initiator Bus ID */ 1035 uint8_t our_id; 1036 uint8_t our_id_b; 1037 1038 /* 1039 * PCI error detection. 1040 */ 1041 int unsolicited_ints; 1042 1043 /* 1044 * Target incoming command FIFO. 1045 */ 1046 struct target_cmd *targetcmds; 1047 uint8_t tqinfifonext; 1048 1049 /* 1050 * Cached copy of the sequencer control register. 1051 */ 1052 uint8_t seqctl; 1053 1054 /* 1055 * Incoming and outgoing message handling. 1056 */ 1057 uint8_t send_msg_perror; 1058 ahc_msg_type msg_type; 1059 uint8_t msgout_buf[12];/* Message we are sending */ 1060 uint8_t msgin_buf[12];/* Message we are receiving */ 1061 u_int msgout_len; /* Length of message to send */ 1062 u_int msgout_index; /* Current index in msgout */ 1063 u_int msgin_index; /* Current index in msgin */ 1064 1065 /* 1066 * Mapping information for data structures shared 1067 * between the sequencer and kernel. 1068 */ 1069 bus_dma_tag_t parent_dmat; 1070 bus_dma_tag_t shared_data_dmat; 1071 bus_dmamap_t shared_data_dmamap; 1072 bus_addr_t shared_data_busaddr; 1073 1074 /* 1075 * Bus address of the one byte buffer used to 1076 * work-around a DMA bug for chips <= aic7880 1077 * in target mode. 1078 */ 1079 bus_addr_t dma_bug_buf; 1080 1081 /* Number of enabled target mode device on this card */ 1082 u_int enabled_luns; 1083 1084 /* Initialization level of this data structure */ 1085 u_int init_level; 1086 1087 /* PCI cacheline size. */ 1088 u_int pci_cachesize; 1089 1090 /* 1091 * Count of parity errors we have seen as a target. 1092 * We auto-disable parity error checking after seeing 1093 * AHC_PCI_TARGET_PERR_THRESH number of errors. 1094 */ 1095 u_int pci_target_perr_count; 1096#define AHC_PCI_TARGET_PERR_THRESH 10 1097 1098 /* Maximum number of sequencer instructions supported. */ 1099 u_int instruction_ram_size; 1100 1101 /* Per-Unit descriptive information */ 1102 const char *description; 1103 char *name; 1104 int unit; 1105 1106 /* Selection Timer settings */ 1107 int seltime; 1108 int seltime_b; 1109 1110 uint16_t user_discenable;/* Disconnection allowed */ 1111 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1112}; 1113 1114TAILQ_HEAD(ahc_softc_tailq, ahc_softc); 1115extern struct ahc_softc_tailq ahc_tailq; 1116 1117/************************ Active Device Information ***************************/ 1118typedef enum { 1119 ROLE_UNKNOWN, 1120 ROLE_INITIATOR, 1121 ROLE_TARGET 1122} role_t; 1123 1124struct ahc_devinfo { 1125 int our_scsiid; 1126 int target_offset; 1127 uint16_t target_mask; 1128 u_int target; 1129 u_int lun; 1130 char channel; 1131 role_t role; /* 1132 * Only guaranteed to be correct if not 1133 * in the busfree state. 1134 */ 1135}; 1136 1137/****************************** PCI Structures ********************************/ 1138typedef int (ahc_device_setup_t)(struct ahc_softc *); 1139 1140struct ahc_pci_identity { 1141 uint64_t full_id; 1142 uint64_t id_mask; 1143 char *name; 1144 ahc_device_setup_t *setup; 1145}; 1146extern struct ahc_pci_identity ahc_pci_ident_table []; 1147extern const u_int ahc_num_pci_devs; 1148 1149/***************************** VL/EISA Declarations ***************************/ 1150struct aic7770_identity { 1151 uint32_t full_id; 1152 uint32_t id_mask; 1153 char *name; 1154 ahc_device_setup_t *setup; 1155}; 1156extern struct aic7770_identity aic7770_ident_table []; 1157extern const int ahc_num_aic7770_devs; 1158 1159#define AHC_EISA_SLOT_OFFSET 0xc00 1160#define AHC_EISA_IOSIZE 0x100 1161 1162/*************************** Function Declarations ****************************/ 1163/******************************************************************************/ 1164u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 1165void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 1166void ahc_busy_tcl(struct ahc_softc *ahc, 1167 u_int tcl, u_int busyid); 1168 1169/***************************** PCI Front End *********************************/ 1170struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t); 1171int ahc_pci_config(struct ahc_softc *, 1172 struct ahc_pci_identity *); 1173int ahc_pci_test_register_access(struct ahc_softc *); 1174 1175/*************************** EISA/VL Front End ********************************/ 1176struct aic7770_identity *aic7770_find_device(uint32_t); 1177int aic7770_config(struct ahc_softc *ahc, 1178 struct aic7770_identity *, 1179 u_int port); 1180 1181/************************** SCB and SCB queue management **********************/ 1182int ahc_probe_scbs(struct ahc_softc *); 1183void ahc_run_untagged_queues(struct ahc_softc *ahc); 1184void ahc_run_untagged_queue(struct ahc_softc *ahc, 1185 struct scb_tailq *queue); 1186void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, 1187 struct scb *scb); 1188int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, 1189 int target, char channel, int lun, 1190 u_int tag, role_t role); 1191 1192/****************************** Initialization ********************************/ 1193struct ahc_softc *ahc_alloc(void *platform_arg, char *name); 1194int ahc_softc_init(struct ahc_softc *); 1195void ahc_controller_info(struct ahc_softc *ahc, char *buf); 1196int ahc_chip_init(struct ahc_softc *ahc); 1197int ahc_init(struct ahc_softc *ahc); 1198void ahc_intr_enable(struct ahc_softc *ahc, int enable); 1199void ahc_pause_and_flushwork(struct ahc_softc *ahc); 1200int ahc_suspend(struct ahc_softc *ahc); 1201int ahc_resume(struct ahc_softc *ahc); 1202void ahc_softc_insert(struct ahc_softc *); 1203struct ahc_softc *ahc_find_softc(struct ahc_softc *ahc); 1204void ahc_set_unit(struct ahc_softc *, int); 1205void ahc_set_name(struct ahc_softc *, char *); 1206void ahc_alloc_scbs(struct ahc_softc *ahc); 1207void ahc_free(struct ahc_softc *ahc); 1208int ahc_reset(struct ahc_softc *ahc); 1209void ahc_shutdown(void *arg); 1210 1211/*************************** Interrupt Services *******************************/ 1212void ahc_clear_intstat(struct ahc_softc *ahc); 1213void ahc_run_qoutfifo(struct ahc_softc *ahc); 1214#ifdef AHC_TARGET_MODE 1215void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 1216#endif 1217void ahc_handle_brkadrint(struct ahc_softc *ahc); 1218void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 1219void ahc_handle_scsiint(struct ahc_softc *ahc, 1220 u_int intstat); 1221void ahc_clear_critical_section(struct ahc_softc *ahc); 1222 1223/***************************** Error Recovery *********************************/ 1224typedef enum { 1225 SEARCH_COMPLETE, 1226 SEARCH_COUNT, 1227 SEARCH_REMOVE 1228} ahc_search_action; 1229int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 1230 char channel, int lun, u_int tag, 1231 role_t role, uint32_t status, 1232 ahc_search_action action); 1233int ahc_search_untagged_queues(struct ahc_softc *ahc, 1234 ahc_io_ctx_t ctx, 1235 int target, char channel, 1236 int lun, uint32_t status, 1237 ahc_search_action action); 1238int ahc_search_disc_list(struct ahc_softc *ahc, int target, 1239 char channel, int lun, u_int tag, 1240 int stop_on_first, int remove, 1241 int save_state); 1242void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 1243int ahc_reset_channel(struct ahc_softc *ahc, char channel, 1244 int initiate_reset); 1245int ahc_abort_scbs(struct ahc_softc *ahc, int target, 1246 char channel, int lun, u_int tag, 1247 role_t role, uint32_t status); 1248void ahc_restart(struct ahc_softc *ahc); 1249void ahc_calc_residual(struct ahc_softc *ahc, 1250 struct scb *scb); 1251/*************************** Utility Functions ********************************/ 1252struct ahc_phase_table_entry* 1253 ahc_lookup_phase_entry(int phase); 1254void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 1255 u_int our_id, u_int target, 1256 u_int lun, char channel, 1257 role_t role); 1258/************************** Transfer Negotiation ******************************/ 1259struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1260 u_int *ppr_options, u_int maxsync); 1261u_int ahc_find_period(struct ahc_softc *ahc, 1262 u_int scsirate, u_int maxsync); 1263void ahc_validate_offset(struct ahc_softc *ahc, 1264 struct ahc_initiator_tinfo *tinfo, 1265 struct ahc_syncrate *syncrate, 1266 u_int *offset, int wide, 1267 role_t role); 1268void ahc_validate_width(struct ahc_softc *ahc, 1269 struct ahc_initiator_tinfo *tinfo, 1270 u_int *bus_width, 1271 role_t role); 1272/* 1273 * Negotiation types. These are used to qualify if we should renegotiate 1274 * even if our goal and current transport parameters are identical. 1275 */ 1276typedef enum { 1277 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1278 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1279 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1280} ahc_neg_type; 1281int ahc_update_neg_request(struct ahc_softc*, 1282 struct ahc_devinfo*, 1283 struct ahc_tmode_tstate*, 1284 struct ahc_initiator_tinfo*, 1285 ahc_neg_type); 1286void ahc_set_width(struct ahc_softc *ahc, 1287 struct ahc_devinfo *devinfo, 1288 u_int width, u_int type, int paused); 1289void ahc_set_syncrate(struct ahc_softc *ahc, 1290 struct ahc_devinfo *devinfo, 1291 struct ahc_syncrate *syncrate, 1292 u_int period, u_int offset, 1293 u_int ppr_options, 1294 u_int type, int paused); 1295typedef enum { 1296 AHC_QUEUE_NONE, 1297 AHC_QUEUE_BASIC, 1298 AHC_QUEUE_TAGGED 1299} ahc_queue_alg; 1300 1301void ahc_set_tags(struct ahc_softc *ahc, 1302 struct ahc_devinfo *devinfo, 1303 ahc_queue_alg alg); 1304 1305/**************************** Target Mode *************************************/ 1306#ifdef AHC_TARGET_MODE 1307void ahc_send_lstate_events(struct ahc_softc *, 1308 struct ahc_tmode_lstate *); 1309void ahc_handle_en_lun(struct ahc_softc *ahc, 1310 struct cam_sim *sim, union ccb *ccb); 1311cam_status ahc_find_tmode_devs(struct ahc_softc *ahc, 1312 struct cam_sim *sim, union ccb *ccb, 1313 struct ahc_tmode_tstate **tstate, 1314 struct ahc_tmode_lstate **lstate, 1315 int notfound_failure); 1316#ifndef AHC_TMODE_ENABLE 1317#define AHC_TMODE_ENABLE 0 1318#endif 1319#endif 1320/******************************* Debug ***************************************/ 1321#ifdef AHC_DEBUG 1322extern uint32_t ahc_debug; 1323#define AHC_SHOW_MISC 0x0001 1324#define AHC_SHOW_SENSE 0x0002 1325#define AHC_DUMP_SEEPROM 0x0004 1326#define AHC_SHOW_TERMCTL 0x0008 1327#define AHC_SHOW_MEMORY 0x0010 1328#define AHC_SHOW_MESSAGES 0x0020 1329#define AHC_SHOW_DV 0x0040 1330#define AHC_SHOW_SELTO 0x0080 1331#define AHC_SHOW_QFULL 0x0200 1332#define AHC_SHOW_QUEUE 0x0400 1333#define AHC_SHOW_TQIN 0x0800 1334#define AHC_SHOW_MASKED_ERRORS 0x1000 1335#define AHC_DEBUG_SEQUENCER 0x2000 1336#endif 1337void ahc_print_scb(struct scb *scb); 1338void ahc_print_devinfo(struct ahc_softc *ahc, 1339 struct ahc_devinfo *dev); 1340void ahc_dump_card_state(struct ahc_softc *ahc); 1341int ahc_print_register(ahc_reg_parse_entry_t *table, 1342 u_int num_entries, 1343 const char *name, 1344 u_int address, 1345 u_int value, 1346 u_int *cur_column, 1347 u_int wrap_point); 1348/******************************* SEEPROM *************************************/ 1349int ahc_acquire_seeprom(struct ahc_softc *ahc, 1350 struct seeprom_descriptor *sd); 1351void ahc_release_seeprom(struct seeprom_descriptor *sd); 1352#endif /* _AIC7XXX_H_ */ 1353