aic79xx_pci.c revision 123579
1/* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#84 $ 42 */ 43 44#ifdef __linux__ 45#include "aic79xx_osm.h" 46#include "aic79xx_inline.h" 47#else 48#include <sys/cdefs.h> 49__FBSDID("$FreeBSD: head/sys/dev/aic7xxx/aic79xx_pci.c 123579 2003-12-17 00:02:10Z gibbs $"); 50#include <dev/aic7xxx/aic79xx_osm.h> 51#include <dev/aic7xxx/aic79xx_inline.h> 52#endif 53 54static __inline uint64_t 55ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56{ 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65} 66 67#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68#define ID_ALL_IROC_MASK 0xFFFFFF7FFFFFFFFFull 69#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 70#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71#define ID_9005_GENERIC_IROC_MASK 0xFFF0FF7F00000000ull 72 73#define ID_AIC7901 0x800F9005FFFF9005ull 74#define ID_AHA_29320A 0x8000900500609005ull 75#define ID_AHA_29320ALP 0x8017900500449005ull 76 77#define ID_AIC7901A 0x801E9005FFFF9005ull 78#define ID_AHA_29320LP 0x8014900500449005ull 79 80#define ID_AIC7902 0x801F9005FFFF9005ull 81#define ID_AIC7902_B 0x801D9005FFFF9005ull 82#define ID_AHA_39320 0x8010900500409005ull 83#define ID_AHA_29320 0x8012900500429005ull 84#define ID_AHA_29320B 0x8013900500439005ull 85#define ID_AHA_39320_B 0x8015900500409005ull 86#define ID_AHA_39320A 0x8016900500409005ull 87#define ID_AHA_39320D 0x8011900500419005ull 88#define ID_AHA_39320D_B 0x801C900500419005ull 89#define ID_AHA_39320D_HP 0x8011900500AC0E11ull 90#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 91#define ID_AIC7902_PCI_REV_A4 0x3 92#define ID_AIC7902_PCI_REV_B0 0x10 93#define SUBID_HP 0x0E11 94 95#define DEVID_9005_TYPE(id) ((id) & 0xF) 96#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 97#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 98#define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 99#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 100 101#define DEVID_9005_MFUNC(id) ((id) & 0x10) 102 103#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 104 105#define SUBID_9005_TYPE(id) ((id) & 0xF) 106#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 107#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 108 109#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 110 111#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 112 113#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 114#define SUBID_9005_SEEPTYPE_NONE 0x0 115#define SUBID_9005_SEEPTYPE_4K 0x1 116 117static ahd_device_setup_t ahd_aic7901_setup; 118static ahd_device_setup_t ahd_aic7901A_setup; 119static ahd_device_setup_t ahd_aic7902_setup; 120static ahd_device_setup_t ahd_aic790X_setup; 121 122struct ahd_pci_identity ahd_pci_ident_table [] = 123{ 124 /* aic7901 based controllers */ 125 { 126 ID_AHA_29320A, 127 ID_ALL_MASK, 128 "Adaptec 29320A Ultra320 SCSI adapter", 129 ahd_aic7901_setup 130 }, 131 { 132 ID_AHA_29320ALP, 133 ID_ALL_MASK, 134 "Adaptec 29320ALP Ultra320 SCSI adapter", 135 ahd_aic7901_setup 136 }, 137 /* aic7901A based controllers */ 138 { 139 ID_AHA_29320LP, 140 ID_ALL_MASK, 141 "Adaptec 29320LP Ultra320 SCSI adapter", 142 ahd_aic7901A_setup 143 }, 144 /* aic7902 based controllers */ 145 { 146 ID_AHA_29320, 147 ID_ALL_MASK, 148 "Adaptec 29320 Ultra320 SCSI adapter", 149 ahd_aic7902_setup 150 }, 151 { 152 ID_AHA_29320B, 153 ID_ALL_MASK, 154 "Adaptec 29320B Ultra320 SCSI adapter", 155 ahd_aic7902_setup 156 }, 157 { 158 ID_AHA_39320, 159 ID_ALL_MASK, 160 "Adaptec 39320 Ultra320 SCSI adapter", 161 ahd_aic7902_setup 162 }, 163 { 164 ID_AHA_39320_B, 165 ID_ALL_MASK, 166 "Adaptec 39320 Ultra320 SCSI adapter", 167 ahd_aic7902_setup 168 }, 169 { 170 ID_AHA_39320A, 171 ID_ALL_MASK, 172 "Adaptec 39320A Ultra320 SCSI adapter", 173 ahd_aic7902_setup 174 }, 175 { 176 ID_AHA_39320D, 177 ID_ALL_MASK, 178 "Adaptec 39320D Ultra320 SCSI adapter", 179 ahd_aic7902_setup 180 }, 181 { 182 ID_AHA_39320D_HP, 183 ID_ALL_MASK, 184 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 185 ahd_aic7902_setup 186 }, 187 { 188 ID_AHA_39320D_B, 189 ID_ALL_MASK, 190 "Adaptec 39320D Ultra320 SCSI adapter", 191 ahd_aic7902_setup 192 }, 193 { 194 ID_AHA_39320D_B_HP, 195 ID_ALL_MASK, 196 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 197 ahd_aic7902_setup 198 }, 199 /* Generic chip probes for devices we don't know 'exactly' */ 200 { 201 ID_AIC7901 & ID_DEV_VENDOR_MASK, 202 ID_DEV_VENDOR_MASK, 203 "Adaptec AIC7901 Ultra320 SCSI adapter", 204 ahd_aic7901_setup 205 }, 206 { 207 ID_AIC7901A & ID_DEV_VENDOR_MASK, 208 ID_DEV_VENDOR_MASK, 209 "Adaptec AIC7901A Ultra320 SCSI adapter", 210 ahd_aic7901A_setup 211 }, 212 { 213 ID_AIC7902 & ID_9005_GENERIC_MASK, 214 ID_9005_GENERIC_MASK, 215 "Adaptec AIC7902 Ultra320 SCSI adapter", 216 ahd_aic7902_setup 217 } 218}; 219 220const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 221 222#define DEVCONFIG 0x40 223#define PCIXINITPAT 0x0000E000ul 224#define PCIXINIT_PCI33_66 0x0000E000ul 225#define PCIXINIT_PCIX50_66 0x0000C000ul 226#define PCIXINIT_PCIX66_100 0x0000A000ul 227#define PCIXINIT_PCIX100_133 0x00008000ul 228#define PCI_BUS_MODES_INDEX(devconfig) \ 229 (((devconfig) & PCIXINITPAT) >> 13) 230static const char *pci_bus_modes[] = 231{ 232 "PCI bus mode unknown", 233 "PCI bus mode unknown", 234 "PCI bus mode unknown", 235 "PCI bus mode unknown", 236 "PCI-X 101-133Mhz", 237 "PCI-X 67-100Mhz", 238 "PCI-X 50-66Mhz", 239 "PCI 33 or 66Mhz" 240}; 241 242#define TESTMODE 0x00000800ul 243#define IRDY_RST 0x00000200ul 244#define FRAME_RST 0x00000100ul 245#define PCI64BIT 0x00000080ul 246#define MRDCEN 0x00000040ul 247#define ENDIANSEL 0x00000020ul 248#define MIXQWENDIANEN 0x00000008ul 249#define DACEN 0x00000004ul 250#define STPWLEVEL 0x00000002ul 251#define QWENDIANSEL 0x00000001ul 252 253#define DEVCONFIG1 0x44 254#define PREQDIS 0x01 255 256#define CSIZE_LATTIME 0x0c 257#define CACHESIZE 0x000000fful 258#define LATTIME 0x0000ff00ul 259 260static int ahd_check_extport(struct ahd_softc *ahd); 261static void ahd_configure_termination(struct ahd_softc *ahd, 262 u_int adapter_control); 263static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 264 265struct ahd_pci_identity * 266ahd_find_pci_device(aic_dev_softc_t pci) 267{ 268 uint64_t full_id; 269 uint16_t device; 270 uint16_t vendor; 271 uint16_t subdevice; 272 uint16_t subvendor; 273 struct ahd_pci_identity *entry; 274 u_int i; 275 276 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 277 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 278 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 279 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 280 full_id = ahd_compose_id(device, 281 vendor, 282 subdevice, 283 subvendor); 284 285 for (i = 0; i < ahd_num_pci_devs; i++) { 286 entry = &ahd_pci_ident_table[i]; 287 if (entry->full_id == (full_id & entry->id_mask)) { 288 /* Honor exclusion entries. */ 289 if (entry->name == NULL) 290 return (NULL); 291 return (entry); 292 } 293 } 294 return (NULL); 295} 296 297int 298ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 299{ 300 struct scb_data *shared_scb_data; 301 u_long l; 302 u_int command; 303 uint32_t devconfig; 304 uint16_t subvendor; 305 int error; 306 307 shared_scb_data = NULL; 308 ahd->description = entry->name; 309 /* 310 * Record if this is an HP board. 311 */ 312 subvendor = aic_pci_read_config(ahd->dev_softc, 313 PCIR_SUBVEND_0, /*bytes*/2); 314 if (subvendor == SUBID_HP) 315 ahd->flags |= AHD_HP_BOARD; 316 317 error = entry->setup(ahd); 318 if (error != 0) 319 return (error); 320 321 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 322 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 323 ahd->chip |= AHD_PCI; 324 /* Disable PCIX workarounds when running in PCI mode. */ 325 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 326 } else { 327 ahd->chip |= AHD_PCIX; 328 } 329 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 330 331 aic_power_state_change(ahd, AIC_POWER_STATE_D0); 332 333 error = ahd_pci_map_registers(ahd); 334 if (error != 0) 335 return (error); 336 337 /* 338 * If we need to support high memory, enable dual 339 * address cycles. This bit must be set to enable 340 * high address bit generation even if we are on a 341 * 64bit bus (PCI64BIT set in devconfig). 342 */ 343 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 344 uint32_t devconfig; 345 346 if (bootverbose) 347 printf("%s: Enabling 39Bit Addressing\n", 348 ahd_name(ahd)); 349 devconfig = aic_pci_read_config(ahd->dev_softc, 350 DEVCONFIG, /*bytes*/4); 351 devconfig |= DACEN; 352 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 353 devconfig, /*bytes*/4); 354 } 355 356 /* Ensure busmastering is enabled */ 357 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 358 command |= PCIM_CMD_BUSMASTEREN; 359 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 360 361 error = ahd_softc_init(ahd); 362 if (error != 0) 363 return (error); 364 365 ahd->bus_intr = ahd_pci_intr; 366 367 error = ahd_reset(ahd, /*reinit*/FALSE); 368 if (error != 0) 369 return (ENXIO); 370 371 ahd->pci_cachesize = 372 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 373 /*bytes*/1) & CACHESIZE; 374 ahd->pci_cachesize *= 4; 375 376 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 377 /* See if we have a SEEPROM and perform auto-term */ 378 error = ahd_check_extport(ahd); 379 if (error != 0) 380 return (error); 381 382 /* Core initialization */ 383 error = ahd_init(ahd); 384 if (error != 0) 385 return (error); 386 387 /* 388 * Allow interrupts now that we are completely setup. 389 */ 390 error = ahd_pci_map_int(ahd); 391 if (error != 0) 392 return (error); 393 394 ahd_list_lock(&l); 395 /* 396 * Link this softc in with all other ahd instances. 397 */ 398 ahd_softc_insert(ahd); 399 ahd_list_unlock(&l); 400 return (0); 401} 402 403/* 404 * Perform some simple tests that should catch situations where 405 * our registers are invalidly mapped. 406 */ 407int 408ahd_pci_test_register_access(struct ahd_softc *ahd) 409{ 410 uint32_t cmd; 411 u_int targpcistat; 412 u_int pci_status1; 413 int error; 414 uint8_t hcntrl; 415 416 error = EIO; 417 418 /* 419 * Enable PCI error interrupt status, but suppress NMIs 420 * generated by SERR raised due to target aborts. 421 */ 422 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 423 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 424 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 425 426 /* 427 * First a simple test to see if any 428 * registers can be read. Reading 429 * HCNTRL has no side effects and has 430 * at least one bit that is guaranteed to 431 * be zero so it is a good register to 432 * use for this test. 433 */ 434 hcntrl = ahd_inb(ahd, HCNTRL); 435 if (hcntrl == 0xFF) 436 goto fail; 437 438 /* 439 * Next create a situation where write combining 440 * or read prefetching could be initiated by the 441 * CPU or host bridge. Our device does not support 442 * either, so look for data corruption and/or flaged 443 * PCI errors. First pause without causing another 444 * chip reset. 445 */ 446 hcntrl &= ~CHIPRST; 447 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 448 while (ahd_is_paused(ahd) == 0) 449 ; 450 451 /* Clear any PCI errors that occurred before our driver attached. */ 452 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 453 targpcistat = ahd_inb(ahd, TARGPCISTAT); 454 ahd_outb(ahd, TARGPCISTAT, targpcistat); 455 pci_status1 = aic_pci_read_config(ahd->dev_softc, 456 PCIR_STATUS + 1, /*bytes*/1); 457 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 458 pci_status1, /*bytes*/1); 459 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 460 ahd_outb(ahd, CLRINT, CLRPCIINT); 461 462 ahd_outb(ahd, SEQCTL0, PERRORDIS); 463 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 464 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 465 goto fail; 466 467 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 468 u_int targpcistat; 469 470 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 471 targpcistat = ahd_inb(ahd, TARGPCISTAT); 472 if ((targpcistat & STA) != 0) 473 goto fail; 474 } 475 476 error = 0; 477 478fail: 479 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 480 481 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 482 targpcistat = ahd_inb(ahd, TARGPCISTAT); 483 484 /* Silently clear any latched errors. */ 485 ahd_outb(ahd, TARGPCISTAT, targpcistat); 486 pci_status1 = aic_pci_read_config(ahd->dev_softc, 487 PCIR_STATUS + 1, /*bytes*/1); 488 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 489 pci_status1, /*bytes*/1); 490 ahd_outb(ahd, CLRINT, CLRPCIINT); 491 } 492 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 493 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 494 return (error); 495} 496 497/* 498 * Check the external port logic for a serial eeprom 499 * and termination/cable detection contrls. 500 */ 501static int 502ahd_check_extport(struct ahd_softc *ahd) 503{ 504 struct vpd_config vpd; 505 struct seeprom_config *sc; 506 u_int adapter_control; 507 int have_seeprom; 508 int error; 509 510 sc = ahd->seep_config; 511 have_seeprom = ahd_acquire_seeprom(ahd); 512 if (have_seeprom) { 513 u_int start_addr; 514 515 /* 516 * Fetch VPD for this function and parse it. 517 */ 518 if (bootverbose) 519 printf("%s: Reading VPD from SEEPROM...", 520 ahd_name(ahd)); 521 522 /* Address is always in units of 16bit words */ 523 start_addr = ((2 * sizeof(*sc)) 524 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 525 526 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 527 start_addr, sizeof(vpd)/2, 528 /*bytestream*/TRUE); 529 if (error == 0) 530 error = ahd_parse_vpddata(ahd, &vpd); 531 if (bootverbose) 532 printf("%s: VPD parsing %s\n", 533 ahd_name(ahd), 534 error == 0 ? "successful" : "failed"); 535 536 if (bootverbose) 537 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 538 539 /* Address is always in units of 16bit words */ 540 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 541 542 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 543 start_addr, sizeof(*sc)/2, 544 /*bytestream*/FALSE); 545 546 if (error != 0) { 547 printf("Unable to read SEEPROM\n"); 548 have_seeprom = 0; 549 } else { 550 have_seeprom = ahd_verify_cksum(sc); 551 552 if (bootverbose) { 553 if (have_seeprom == 0) 554 printf ("checksum error\n"); 555 else 556 printf ("done.\n"); 557 } 558 } 559 ahd_release_seeprom(ahd); 560 } 561 562 if (!have_seeprom) { 563 u_int nvram_scb; 564 565 /* 566 * Pull scratch ram settings and treat them as 567 * if they are the contents of an seeprom if 568 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 569 * in SCB 0xFF. We manually compose the data as 16bit 570 * values to avoid endian issues. 571 */ 572 ahd_set_scbptr(ahd, 0xFF); 573 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 574 if (nvram_scb != 0xFF 575 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 576 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 577 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 578 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 579 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 580 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 581 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 582 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 583 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 584 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 585 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 586 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 587 uint16_t *sc_data; 588 int i; 589 590 ahd_set_scbptr(ahd, nvram_scb); 591 sc_data = (uint16_t *)sc; 592 for (i = 0; i < 64; i += 2) 593 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 594 have_seeprom = ahd_verify_cksum(sc); 595 if (have_seeprom) 596 ahd->flags |= AHD_SCB_CONFIG_USED; 597 } 598 } 599 600#if AHD_DEBUG 601 if (have_seeprom != 0 602 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 603 uint16_t *sc_data; 604 int i; 605 606 printf("%s: Seeprom Contents:", ahd_name(ahd)); 607 sc_data = (uint16_t *)sc; 608 for (i = 0; i < (sizeof(*sc)); i += 2) 609 printf("\n\t0x%.4x", sc_data[i]); 610 printf("\n"); 611 } 612#endif 613 614 if (!have_seeprom) { 615 if (bootverbose) 616 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 617 ahd->flags |= AHD_USEDEFAULTS; 618 error = ahd_default_config(ahd); 619 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 620 free(ahd->seep_config, M_DEVBUF); 621 ahd->seep_config = NULL; 622 } else { 623 error = ahd_parse_cfgdata(ahd, sc); 624 adapter_control = sc->adapter_control; 625 } 626 if (error != 0) 627 return (error); 628 629 ahd_configure_termination(ahd, adapter_control); 630 631 return (0); 632} 633 634static void 635ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 636{ 637 int error; 638 u_int sxfrctl1; 639 uint8_t termctl; 640 uint32_t devconfig; 641 642 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 643 devconfig &= ~STPWLEVEL; 644 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 645 devconfig |= STPWLEVEL; 646 if (bootverbose) 647 printf("%s: STPWLEVEL is %s\n", 648 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 649 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 650 651 /* Make sure current sensing is off. */ 652 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 653 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 654 } 655 656 /* 657 * Read to sense. Write to set. 658 */ 659 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 660 if ((adapter_control & CFAUTOTERM) == 0) { 661 if (bootverbose) 662 printf("%s: Manual Primary Termination\n", 663 ahd_name(ahd)); 664 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 665 if ((adapter_control & CFSTERM) != 0) 666 termctl |= FLX_TERMCTL_ENPRILOW; 667 if ((adapter_control & CFWSTERM) != 0) 668 termctl |= FLX_TERMCTL_ENPRIHIGH; 669 } else if (error != 0) { 670 printf("%s: Primary Auto-Term Sensing failed! " 671 "Using Defaults.\n", ahd_name(ahd)); 672 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 673 } 674 675 if ((adapter_control & CFSEAUTOTERM) == 0) { 676 if (bootverbose) 677 printf("%s: Manual Secondary Termination\n", 678 ahd_name(ahd)); 679 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 680 if ((adapter_control & CFSELOWTERM) != 0) 681 termctl |= FLX_TERMCTL_ENSECLOW; 682 if ((adapter_control & CFSEHIGHTERM) != 0) 683 termctl |= FLX_TERMCTL_ENSECHIGH; 684 } else if (error != 0) { 685 printf("%s: Secondary Auto-Term Sensing failed! " 686 "Using Defaults.\n", ahd_name(ahd)); 687 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 688 } 689 690 /* 691 * Now set the termination based on what we found. 692 */ 693 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 694 ahd->flags &= ~AHD_TERM_ENB_A; 695 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 696 ahd->flags |= AHD_TERM_ENB_A; 697 sxfrctl1 |= STPWEN; 698 } 699 /* Must set the latch once in order to be effective. */ 700 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 701 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 702 703 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 704 if (error != 0) { 705 printf("%s: Unable to set termination settings!\n", 706 ahd_name(ahd)); 707 } else if (bootverbose) { 708 printf("%s: Primary High byte termination %sabled\n", 709 ahd_name(ahd), 710 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 711 712 printf("%s: Primary Low byte termination %sabled\n", 713 ahd_name(ahd), 714 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 715 716 printf("%s: Secondary High byte termination %sabled\n", 717 ahd_name(ahd), 718 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 719 720 printf("%s: Secondary Low byte termination %sabled\n", 721 ahd_name(ahd), 722 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 723 } 724 return; 725} 726 727#define DPE 0x80 728#define SSE 0x40 729#define RMA 0x20 730#define RTA 0x10 731#define STA 0x08 732#define DPR 0x01 733 734static const char *split_status_source[] = 735{ 736 "DFF0", 737 "DFF1", 738 "OVLY", 739 "CMC", 740}; 741 742static const char *pci_status_source[] = 743{ 744 "DFF0", 745 "DFF1", 746 "SG", 747 "CMC", 748 "OVLY", 749 "NONE", 750 "MSI", 751 "TARG" 752}; 753 754static const char *split_status_strings[] = 755{ 756 "%s: Received split response in %s.\n", 757 "%s: Received split completion error message in %s\n", 758 "%s: Receive overrun in %s\n", 759 "%s: Count not complete in %s\n", 760 "%s: Split completion data bucket in %s\n", 761 "%s: Split completion address error in %s\n", 762 "%s: Split completion byte count error in %s\n", 763 "%s: Signaled Target-abort to early terminate a split in %s\n" 764}; 765 766static const char *pci_status_strings[] = 767{ 768 "%s: Data Parity Error has been reported via PERR# in %s\n", 769 "%s: Target initial wait state error in %s\n", 770 "%s: Split completion read data parity error in %s\n", 771 "%s: Split completion address attribute parity error in %s\n", 772 "%s: Received a Target Abort in %s\n", 773 "%s: Received a Master Abort in %s\n", 774 "%s: Signal System Error Detected in %s\n", 775 "%s: Address or Write Phase Parity Error Detected in %s.\n" 776}; 777 778void 779ahd_pci_intr(struct ahd_softc *ahd) 780{ 781 uint8_t pci_status[8]; 782 ahd_mode_state saved_modes; 783 u_int pci_status1; 784 u_int intstat; 785 u_int i; 786 u_int reg; 787 788 intstat = ahd_inb(ahd, INTSTAT); 789 790 if ((intstat & SPLTINT) != 0) 791 ahd_pci_split_intr(ahd, intstat); 792 793 if ((intstat & PCIINT) == 0) 794 return; 795 796 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 797 saved_modes = ahd_save_modes(ahd); 798 ahd_dump_card_state(ahd); 799 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 800 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 801 802 if (i == 5) 803 continue; 804 pci_status[i] = ahd_inb(ahd, reg); 805 /* Clear latched errors. So our interrupt deasserts. */ 806 ahd_outb(ahd, reg, pci_status[i]); 807 } 808 809 for (i = 0; i < 8; i++) { 810 u_int bit; 811 812 if (i == 5) 813 continue; 814 815 for (bit = 0; bit < 8; bit++) { 816 817 if ((pci_status[i] & (0x1 << bit)) != 0) { 818 static const char *s; 819 820 s = pci_status_strings[bit]; 821 if (i == 7/*TARG*/ && bit == 3) 822 s = "%s: Signaled Target Abort\n"; 823 printf(s, ahd_name(ahd), pci_status_source[i]); 824 } 825 } 826 } 827 pci_status1 = aic_pci_read_config(ahd->dev_softc, 828 PCIR_STATUS + 1, /*bytes*/1); 829 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 830 pci_status1, /*bytes*/1); 831 ahd_restore_modes(ahd, saved_modes); 832 ahd_outb(ahd, CLRINT, CLRPCIINT); 833 ahd_unpause(ahd); 834} 835 836static void 837ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 838{ 839 uint8_t split_status[4]; 840 uint8_t split_status1[4]; 841 uint8_t sg_split_status[2]; 842 uint8_t sg_split_status1[2]; 843 ahd_mode_state saved_modes; 844 u_int i; 845 uint16_t pcix_status; 846 847 /* 848 * Check for splits in all modes. Modes 0 and 1 849 * additionally have SG engine splits to look at. 850 */ 851 pcix_status = aic_pci_read_config(ahd->dev_softc, PCIXR_STATUS, 852 /*bytes*/2); 853 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 854 ahd_name(ahd), pcix_status); 855 saved_modes = ahd_save_modes(ahd); 856 for (i = 0; i < 4; i++) { 857 ahd_set_modes(ahd, i, i); 858 859 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 860 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 861 /* Clear latched errors. So our interrupt deasserts. */ 862 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 863 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 864 if (i > 1) 865 continue; 866 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 867 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 868 /* Clear latched errors. So our interrupt deasserts. */ 869 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 870 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 871 } 872 873 for (i = 0; i < 4; i++) { 874 u_int bit; 875 876 for (bit = 0; bit < 8; bit++) { 877 878 if ((split_status[i] & (0x1 << bit)) != 0) { 879 static const char *s; 880 881 s = split_status_strings[bit]; 882 printf(s, ahd_name(ahd), 883 split_status_source[i]); 884 } 885 886 if (i > 1) 887 continue; 888 889 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 890 static const char *s; 891 892 s = split_status_strings[bit]; 893 printf(s, ahd_name(ahd), "SG"); 894 } 895 } 896 } 897 /* 898 * Clear PCI-X status bits. 899 */ 900 aic_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 901 pcix_status, /*bytes*/2); 902 ahd_outb(ahd, CLRINT, CLRSPLTINT); 903 ahd_restore_modes(ahd, saved_modes); 904} 905 906static int 907ahd_aic7901_setup(struct ahd_softc *ahd) 908{ 909 910 ahd->chip = AHD_AIC7901; 911 ahd->features = AHD_AIC7901_FE; 912 return (ahd_aic790X_setup(ahd)); 913} 914 915static int 916ahd_aic7901A_setup(struct ahd_softc *ahd) 917{ 918 919 ahd->chip = AHD_AIC7901A; 920 ahd->features = AHD_AIC7901A_FE; 921 return (ahd_aic790X_setup(ahd)); 922} 923 924static int 925ahd_aic7902_setup(struct ahd_softc *ahd) 926{ 927 ahd->chip = AHD_AIC7902; 928 ahd->features = AHD_AIC7902_FE; 929 return (ahd_aic790X_setup(ahd)); 930} 931 932static int 933ahd_aic790X_setup(struct ahd_softc *ahd) 934{ 935 aic_dev_softc_t pci; 936 u_int rev; 937 938 pci = ahd->dev_softc; 939 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 940 if (rev < ID_AIC7902_PCI_REV_A4) { 941 printf("%s: Unable to attach to unsupported chip revision %d\n", 942 ahd_name(ahd), rev); 943 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 944 return (ENXIO); 945 } 946 ahd->channel = aic_get_pci_function(pci) + 'A'; 947 if (rev < ID_AIC7902_PCI_REV_B0) { 948 /* 949 * Enable A series workarounds. 950 */ 951 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 952 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 953 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 954 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 955 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 956 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 957 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 958 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 959 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 960 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 961 | AHD_FAINT_LED_BUG; 962 963 /* 964 * IO Cell paramter setup. 965 */ 966 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 967 968 if ((ahd->flags & AHD_HP_BOARD) == 0) 969 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 970 } else { 971 u_int devconfig1; 972 973 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 974 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 975 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 976 977 /* 978 * Some issues have been resolved in the 7901B. 979 */ 980 if ((ahd->features & AHD_MULTI_FUNC) != 0) 981 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 982 983 /* 984 * IO Cell paramter setup. 985 */ 986 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 987 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 988 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 989 990 /* 991 * Set the PREQDIS bit for H2B which disables some workaround 992 * that doesn't work on regular PCI busses. 993 * XXX - Find out exactly what this does from the hardware 994 * folks! 995 */ 996 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 997 aic_pci_write_config(pci, DEVCONFIG1, 998 devconfig1|PREQDIS, /*bytes*/1); 999 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1000 } 1001 1002 return (0); 1003} 1004