aic79xx_pci.c revision 104023
1/* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#44 $ 42 * 43 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx_pci.c 104023 2002-09-26 22:54:00Z gibbs $ 44 */ 45 46#ifdef __linux__ 47#include "aic79xx_osm.h" 48#include "aic79xx_inline.h" 49#else 50#include <dev/aic7xxx/aic79xx_osm.h> 51#include <dev/aic7xxx/aic79xx_inline.h> 52#endif 53 54static __inline uint64_t 55ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56{ 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65} 66 67#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 69#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 70 71#define ID_AIC7901 0x800F9005FFFF9005ull 72#define ID_AIC7901_IROC 0x80089005FFFF9005ull 73#define ID_AIC7901A 0x801E9005FFFF9005ull 74#define ID_AHA_29320A 0x8000900500609005ull 75 76#define ID_AIC7902 0x801F9005FFFF9005ull 77#define ID_AIC7902_IROC 0x80189005FFFF9005ull 78#define ID_AHA_39320 0x8010900500409005ull 79#define ID_AHA_39320D 0x8011900500419005ull 80#define ID_AHA_39320D_CPQ 0x8011900500AC0E11ull 81#define ID_AHA_29320 0x8012900500429005ull 82#define ID_AHA_29320B 0x8013900500439005ull 83#define ID_AHA_29320LP 0x8014900500449005ull 84#define ID_AIC7902_PCI_REV_A4 0x3 85#define ID_AIC7902_PCI_REV_B0 0x10 86#define SUBID_CPQ 0x0E11 87 88#define DEVID_9005_TYPE(id) ((id) & 0xF) 89#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 90#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 91#define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 92#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 93 94#define DEVID_9005_MFUNC(id) ((id) & 0x10) 95 96#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 97 98#define SUBID_9005_TYPE(id) ((id) & 0xF) 99#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 100#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 101 102#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 103 104#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 105 106#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 107#define SUBID_9005_SEEPTYPE_NONE 0x0 108#define SUBID_9005_SEEPTYPE_4K 0x1 109 110static ahd_device_setup_t ahd_aic7901_setup; 111static ahd_device_setup_t ahd_aic7902_setup; 112static ahd_device_setup_t ahd_aic7901A_setup; 113 114struct ahd_pci_identity ahd_pci_ident_table [] = 115{ 116 /* aic7901 based controllers */ 117 { 118 ID_AHA_29320A, 119 ID_ALL_MASK, 120 "Adaptec 29320A Ultra320 SCSI adapter", 121 ahd_aic7901_setup 122 }, 123 /* aic7902 based controllers */ 124 { 125 ID_AHA_39320, 126 ID_ALL_MASK, 127 "Adaptec 39320 Ultra320 SCSI adapter", 128 ahd_aic7902_setup 129 }, 130 { 131 ID_AHA_39320D, 132 ID_ALL_MASK, 133 "Adaptec 39320D Ultra320 SCSI adapter", 134 ahd_aic7902_setup 135 }, 136 { 137 ID_AHA_39320D_CPQ, 138 ID_ALL_MASK, 139 "Adaptec (Compaq OEM) 39320D Ultra320 SCSI adapter", 140 ahd_aic7902_setup 141 }, 142 { 143 ID_AHA_29320, 144 ID_ALL_MASK, 145 "Adaptec 29320 Ultra320 SCSI adapter", 146 ahd_aic7902_setup 147 }, 148 { 149 ID_AHA_29320B, 150 ID_ALL_MASK, 151 "Adaptec 29320B Ultra320 SCSI adapter", 152 ahd_aic7902_setup 153 }, 154 { 155 ID_AHA_29320LP, 156 ID_ALL_MASK, 157 "Adaptec 29320LP Ultra320 SCSI adapter", 158 ahd_aic7902_setup 159 }, 160 { 161 ID_AIC7901A & ID_9005_GENERIC_MASK, 162 ID_9005_GENERIC_MASK, 163 "Adaptec 7901A Ultra320 SCSI adapter", 164 ahd_aic7901A_setup 165 }, 166 /* Generic chip probes for devices we don't know 'exactly' */ 167 { 168 ID_AIC7901 & ID_9005_GENERIC_MASK, 169 ID_9005_GENERIC_MASK, 170 "Adaptec aic7901 Ultra320 SCSI adapter", 171 ahd_aic7901_setup 172 }, 173 { 174 ID_AIC7902 & ID_9005_GENERIC_MASK, 175 ID_9005_GENERIC_MASK, 176 "Adaptec aic7902 Ultra320 SCSI adapter", 177 ahd_aic7902_setup 178 } 179}; 180 181const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 182 183#define DEVCONFIG 0x40 184#define PCIXINITPAT 0x0000E000ul 185#define PCIXINIT_PCI33_66 0x0000E000ul 186#define PCIXINIT_PCIX50_66 0x0000C000ul 187#define PCIXINIT_PCIX66_100 0x0000A000ul 188#define PCIXINIT_PCIX100_133 0x00008000ul 189#define PCI_BUS_MODES_INDEX(devconfig) \ 190 (((devconfig) & PCIXINITPAT) >> 13) 191static const char *pci_bus_modes[] = 192{ 193 "PCI bus mode unknown", 194 "PCI bus mode unknown", 195 "PCI bus mode unknown", 196 "PCI bus mode unknown", 197 "PCI-X 101-133Mhz", 198 "PCI-X 67-100Mhz", 199 "PCI-X 50-66Mhz", 200 "PCI 33 or 66Mhz" 201}; 202 203#define TESTMODE 0x00000800ul 204#define IRDY_RST 0x00000200ul 205#define FRAME_RST 0x00000100ul 206#define PCI64BIT 0x00000080ul 207#define MRDCEN 0x00000040ul 208#define ENDIANSEL 0x00000020ul 209#define MIXQWENDIANEN 0x00000008ul 210#define DACEN 0x00000004ul 211#define STPWLEVEL 0x00000002ul 212#define QWENDIANSEL 0x00000001ul 213 214#define DEVCONFIG1 0x44 215#define PREQDIS 0x01 216 217#define CSIZE_LATTIME 0x0c 218#define CACHESIZE 0x000000fful 219#define LATTIME 0x0000ff00ul 220 221static int ahd_check_extport(struct ahd_softc *ahd); 222static void ahd_configure_termination(struct ahd_softc *ahd, 223 u_int adapter_control); 224static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 225 226struct ahd_pci_identity * 227ahd_find_pci_device(ahd_dev_softc_t pci) 228{ 229 uint64_t full_id; 230 uint16_t device; 231 uint16_t vendor; 232 uint16_t subdevice; 233 uint16_t subvendor; 234 struct ahd_pci_identity *entry; 235 u_int i; 236 237 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 238 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 239 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 240 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 241 full_id = ahd_compose_id(device, 242 vendor, 243 subdevice, 244 subvendor); 245 246 for (i = 0; i < ahd_num_pci_devs; i++) { 247 entry = &ahd_pci_ident_table[i]; 248 if (entry->full_id == (full_id & entry->id_mask)) { 249 /* Honor exclusion entries. */ 250 if (entry->name == NULL) 251 return (NULL); 252 return (entry); 253 } 254 } 255 return (NULL); 256} 257 258int 259ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 260{ 261 struct scb_data *shared_scb_data; 262 u_long l; 263 u_int command; 264 uint32_t devconfig; 265 uint16_t subvendor; 266 int error; 267 268 shared_scb_data = NULL; 269 error = entry->setup(ahd); 270 if (error != 0) 271 return (error); 272 273 ahd->description = entry->name; 274 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 275 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 276 ahd->chip |= AHD_PCI; 277 /* Disable PCIX workarounds when running in PCI mode. */ 278 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 279 } else { 280 ahd->chip |= AHD_PCIX; 281 } 282 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 283 284 /* 285 * Record if this is a Compaq board. 286 */ 287 subvendor = ahd_pci_read_config(ahd->dev_softc, 288 PCIR_SUBVEND_0, /*bytes*/2); 289 if (subvendor == SUBID_CPQ) 290 ahd->flags |= AHD_CPQ_BOARD; 291 292 ahd_power_state_change(ahd, AHD_POWER_STATE_D0); 293 294 error = ahd_pci_map_registers(ahd); 295 if (error != 0) 296 return (error); 297 298 /* 299 * If we need to support high memory, enable dual 300 * address cycles. This bit must be set to enable 301 * high address bit generation even if we are on a 302 * 64bit bus (PCI64BIT set in devconfig). 303 */ 304 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 305 uint32_t devconfig; 306 307 if (bootverbose) 308 printf("%s: Enabling 39Bit Addressing\n", 309 ahd_name(ahd)); 310 devconfig = ahd_pci_read_config(ahd->dev_softc, 311 DEVCONFIG, /*bytes*/4); 312 devconfig |= DACEN; 313 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, 314 devconfig, /*bytes*/4); 315 } 316 317 /* Ensure busmastering is enabled */ 318 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1); 319 command |= PCIM_CMD_BUSMASTEREN; 320 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 321 322 error = ahd_softc_init(ahd); 323 if (error != 0) 324 return (error); 325 326 ahd->bus_intr = ahd_pci_intr; 327 328 error = ahd_reset(ahd); 329 if (error != 0) 330 return (ENXIO); 331 332 ahd->pci_cachesize = 333 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 334 /*bytes*/1) & CACHESIZE; 335 ahd->pci_cachesize *= 4; 336 337 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 338 /* See if we have a SEEPROM and perform auto-term */ 339 error = ahd_check_extport(ahd); 340 if (error != 0) 341 return (error); 342 343 /* Core initialization */ 344 error = ahd_init(ahd); 345 if (error != 0) 346 return (error); 347 348 /* 349 * Allow interrupts now that we are completely setup. 350 */ 351 error = ahd_pci_map_int(ahd); 352 if (error != 0) 353 return (error); 354 355 ahd_list_lock(&l); 356 /* 357 * Link this softc in with all other ahd instances. 358 */ 359 ahd_softc_insert(ahd); 360 ahd_list_unlock(&l); 361 return (0); 362} 363 364/* 365 * Check the external port logic for a serial eeprom 366 * and termination/cable detection contrls. 367 */ 368static int 369ahd_check_extport(struct ahd_softc *ahd) 370{ 371 struct seeprom_config *sc; 372 u_int adapter_control; 373 int have_seeprom; 374 int error; 375 376 sc = ahd->seep_config; 377 have_seeprom = ahd_acquire_seeprom(ahd); 378 if (have_seeprom) { 379 u_int start_addr; 380 381 if (bootverbose) 382 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 383 384 /* Address is always in units of 16bit words */ 385 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 386 387 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 388 start_addr, sizeof(*sc)/2); 389 390 if (error != 0) { 391 printf("Unable to read SEEPROM\n"); 392 have_seeprom = 0; 393 } else { 394 have_seeprom = ahd_verify_cksum(sc); 395 396 if (bootverbose) { 397 if (have_seeprom == 0) 398 printf ("checksum error\n"); 399 else 400 printf ("done.\n"); 401 } 402 } 403 ahd_release_seeprom(ahd); 404 } 405 406 if (!have_seeprom) { 407 u_int nvram_scb; 408 409 /* 410 * Pull scratch ram settings and treat them as 411 * if they are the contents of an seeprom if 412 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 413 * in SCB 0xFF. We manually compose the data as 16bit 414 * values to avoid endian issues. 415 */ 416 ahd_set_scbptr(ahd, 0xFF); 417 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 418 if (nvram_scb != 0xFF 419 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 420 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 421 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 422 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 423 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 424 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 425 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 426 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 427 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 428 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 429 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 430 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 431 uint16_t *sc_data; 432 int i; 433 434 ahd_set_scbptr(ahd, nvram_scb); 435 sc_data = (uint16_t *)sc; 436 for (i = 0; i < 64; i += 2) 437 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 438 have_seeprom = ahd_verify_cksum(sc); 439 if (have_seeprom) 440 ahd->flags |= AHD_SCB_CONFIG_USED; 441 } 442 } 443 444#if AHD_DEBUG 445 if (have_seeprom != 0 446 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 447 uint8_t *sc_data; 448 int i; 449 450 printf("%s: Seeprom Contents:", ahd_name(ahd)); 451 sc_data = (uint8_t *)sc; 452 for (i = 0; i < (sizeof(*sc)); i += 2) 453 printf("\n\t0x%.4x", 454 sc_data[i] | (sc_data[i+1] << 8)); 455 printf("\n"); 456 } 457#endif 458 459 if (!have_seeprom) { 460 if (bootverbose) 461 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 462 ahd->flags |= AHD_USEDEFAULTS; 463 error = ahd_default_config(ahd); 464 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 465 free(ahd->seep_config, M_DEVBUF); 466 ahd->seep_config = NULL; 467 } else { 468 error = ahd_parse_cfgdata(ahd, sc); 469 adapter_control = sc->adapter_control; 470 } 471 if (error != 0) 472 return (error); 473 474 ahd_configure_termination(ahd, adapter_control); 475 476 return (0); 477} 478 479static void 480ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 481{ 482 int error; 483 u_int sxfrctl1; 484 uint8_t termctl; 485 uint32_t devconfig; 486 487 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 488 devconfig &= ~STPWLEVEL; 489 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 490 devconfig |= STPWLEVEL; 491 if (bootverbose) 492 printf("%s: STPWLEVEL is %s\n", 493 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 494 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 495 496 /* Make sure current sensing is off. */ 497 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 498 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 499 } 500 501 /* 502 * Read to sense. Write to set. 503 */ 504 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 505 if ((adapter_control & CFAUTOTERM) == 0) { 506 if (bootverbose) 507 printf("%s: Manual Primary Termination\n", 508 ahd_name(ahd)); 509 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 510 if ((adapter_control & CFSTERM) != 0) 511 termctl |= FLX_TERMCTL_ENPRILOW; 512 if ((adapter_control & CFWSTERM) != 0) 513 termctl |= FLX_TERMCTL_ENPRIHIGH; 514 } else if (error != 0) { 515 printf("%s: Primary Auto-Term Sensing failed! " 516 "Using Defaults.\n", ahd_name(ahd)); 517 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 518 } 519 520 if ((adapter_control & CFSEAUTOTERM) == 0) { 521 if (bootverbose) 522 printf("%s: Manual Secondary Termination\n", 523 ahd_name(ahd)); 524 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 525 if ((adapter_control & CFSELOWTERM) != 0) 526 termctl |= FLX_TERMCTL_ENSECLOW; 527 if ((adapter_control & CFSEHIGHTERM) != 0) 528 termctl |= FLX_TERMCTL_ENSECHIGH; 529 } else if (error != 0) { 530 printf("%s: Secondary Auto-Term Sensing failed! " 531 "Using Defaults.\n", ahd_name(ahd)); 532 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 533 } 534 535 /* 536 * Now set the termination based on what we found. 537 */ 538 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 539 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 540 ahd->flags |= AHD_TERM_ENB_A; 541 sxfrctl1 |= STPWEN; 542 } 543 /* Must set the latch once in order to be effective. */ 544 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 545 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 546 547 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 548 if (error != 0) { 549 printf("%s: Unable to set termination settings!\n", 550 ahd_name(ahd)); 551 } else if (bootverbose) { 552 printf("%s: Primary High byte termination %sabled\n", 553 ahd_name(ahd), 554 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 555 556 printf("%s: Primary Low byte termination %sabled\n", 557 ahd_name(ahd), 558 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 559 560 printf("%s: Secondary High byte termination %sabled\n", 561 ahd_name(ahd), 562 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 563 564 printf("%s: Secondary Low byte termination %sabled\n", 565 ahd_name(ahd), 566 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 567 } 568 return; 569} 570 571#define DPE 0x80 572#define SSE 0x40 573#define RMA 0x20 574#define RTA 0x10 575#define STA 0x08 576#define DPR 0x01 577 578static const char *split_status_source[] = 579{ 580 "DFF0", 581 "DFF1", 582 "OVLY", 583 "CMC", 584}; 585 586static const char *pci_status_source[] = 587{ 588 "DFF0", 589 "DFF1", 590 "SG", 591 "CMC", 592 "OVLY", 593 "NONE", 594 "MSI", 595 "TARG" 596}; 597 598static const char *split_status_strings[] = 599{ 600 "%s: Received split response in %s.\n" 601 "%s: Received split completion error message in %s\n", 602 "%s: Receive overrun in %s\n", 603 "%s: Count not complete in %s\n", 604 "%s: Split completion data bucket in %s\n", 605 "%s: Split completion address error in %s\n", 606 "%s: Split completion byte count error in %s\n", 607 "%s: Signaled Target-abort to early terminate a split in %s\n", 608}; 609 610static const char *pci_status_strings[] = 611{ 612 "%s: Data Parity Error has been reported via PERR# in %s\n", 613 "%s: Target initial wait state error in %s\n", 614 "%s: Split completion read data parity error in %s\n", 615 "%s: Split completion address attribute parity error in %s\n", 616 "%s: Received a Target Abort in %s\n", 617 "%s: Received a Master Abort in %s\n", 618 "%s: Signal System Error Detected in %s\n", 619 "%s: Address or Write Phase Parity Error Detected in %s.\n" 620}; 621 622void 623ahd_pci_intr(struct ahd_softc *ahd) 624{ 625 uint8_t pci_status[8]; 626 ahd_mode_state saved_modes; 627 u_int pci_status1; 628 u_int intstat; 629 u_int i; 630 u_int reg; 631 632 intstat = ahd_inb(ahd, INTSTAT); 633 634 if ((intstat & SPLTINT) != 0) 635 ahd_pci_split_intr(ahd, intstat); 636 637 if ((intstat & PCIINT) == 0) 638 return; 639 640 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 641 saved_modes = ahd_save_modes(ahd); 642 ahd_dump_card_state(ahd); 643 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 644 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 645 646 if (i == 5) 647 continue; 648 pci_status[i] = ahd_inb(ahd, reg); 649 /* Clear latched errors. So our interupt deasserts. */ 650 ahd_outb(ahd, reg, pci_status[i]); 651 } 652 653 for (i = 0; i < 8; i++) { 654 u_int bit; 655 656 if (i == 5) 657 continue; 658 659 for (bit = 0; bit < 8; bit++) { 660 661 if ((pci_status[i] & (0x1 << bit)) != 0) { 662 static const char *s; 663 664 s = pci_status_strings[bit]; 665 if (i == 7/*TARG*/ && bit == 3) 666 s = "%s: Signal Target Abort\n"; 667 printf(s, ahd_name(ahd), pci_status_source[i]); 668 } 669 } 670 } 671 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 672 PCIR_STATUS + 1, /*bytes*/1); 673 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 674 pci_status1, /*bytes*/1); 675 ahd_restore_modes(ahd, saved_modes); 676 ahd_unpause(ahd); 677} 678 679static void 680ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 681{ 682 uint8_t split_status[4]; 683 uint8_t split_status1[4]; 684 uint8_t sg_split_status[2]; 685 uint8_t sg_split_status1[2]; 686 ahd_mode_state saved_modes; 687 u_int i; 688 uint16_t pcix_status; 689 690 /* 691 * Check for splits in all modes. Modes 0 and 1 692 * additionally have SG engine splits to look at. 693 */ 694 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS, 695 /*bytes*/2); 696 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 697 ahd_name(ahd), pcix_status); 698 saved_modes = ahd_save_modes(ahd); 699 for (i = 0; i < 4; i++) { 700 ahd_set_modes(ahd, i, i); 701 702 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 703 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 704 /* Clear latched errors. So our interupt deasserts. */ 705 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 706 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 707 if (i != 0) 708 continue; 709 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 710 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 711 /* Clear latched errors. So our interupt deasserts. */ 712 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 713 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 714 } 715 716 for (i = 0; i < 4; i++) { 717 u_int bit; 718 719 for (bit = 0; bit < 8; bit++) { 720 721 if ((split_status[i] & (0x1 << bit)) != 0) { 722 static const char *s; 723 724 s = split_status_strings[bit]; 725 printf(s, ahd_name(ahd), 726 split_status_source[i]); 727 } 728 729 if (i != 0) 730 continue; 731 732 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 733 static const char *s; 734 735 s = split_status_strings[bit]; 736 printf(s, ahd_name(ahd), "SG"); 737 } 738 } 739 } 740 /* 741 * Clear PCI-X status bits. 742 */ 743 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 744 pcix_status, /*bytes*/2); 745 ahd_restore_modes(ahd, saved_modes); 746} 747 748static int 749ahd_aic7901_setup(struct ahd_softc *ahd) 750{ 751 ahd_dev_softc_t pci; 752 753 pci = ahd->dev_softc; 754 ahd->channel = 'A'; 755 ahd->chip = AHD_AIC7901; 756 ahd->features = AHD_AIC7901_FE; 757 return (0); 758} 759 760static int 761ahd_aic7902_setup(struct ahd_softc *ahd) 762{ 763 ahd_dev_softc_t pci; 764 u_int rev; 765 u_int devconfig1; 766 767 pci = ahd->dev_softc; 768 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 769 if (rev < ID_AIC7902_PCI_REV_A4) { 770 printf("%s: Unable to attach to unsupported chip revision %d\n", 771 ahd_name(ahd), rev); 772 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/1); 773 return (ENXIO); 774 } 775 if (rev < ID_AIC7902_PCI_REV_B0) { 776 /* 777 * Pending request assertion does not work on the A if we have 778 * DMA requests outstanding on both channels. See H2A3 Razors 779 * #327 and #365. 780 */ 781 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 782 ahd_pci_write_config(pci, DEVCONFIG1, 783 devconfig1|PREQDIS, /*bytes*/1); 784 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 785 /* 786 * Enable A series workarounds. 787 */ 788 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 789 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 790 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 791 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 792 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 793 | AHD_PCIX_CHIPRST_BUG|AHD_PKTIZED_STATUS_BUG 794 | AHD_PKT_LUN_BUG|AHD_MDFF_WSCBPTR_BUG 795 | AHD_REG_SLOW_SETTLE_BUG|AHD_SET_MODE_BUG 796 | AHD_BUSFREEREV_BUG; 797 } 798 799 ahd->channel = ahd_get_pci_function(pci) + 'A'; 800 ahd->chip = AHD_AIC7902; 801 ahd->features = AHD_AIC7902_FE; 802 return (0); 803} 804 805static int 806ahd_aic7901A_setup(struct ahd_softc *ahd) 807{ 808 int error; 809 810 error = ahd_aic7902_setup(ahd); 811 if (error != 0) 812 return (error); 813 ahd->chip = AHD_AIC7901A; 814 return (0); 815} 816 817