1139749Simp/*- 297883Sgibbs * Product specific probe and attach routines for: 397883Sgibbs * aic7901 and aic7902 SCSI controllers 497883Sgibbs * 597883Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 6102686Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 797883Sgibbs * All rights reserved. 897883Sgibbs * 997883Sgibbs * Redistribution and use in source and binary forms, with or without 1097883Sgibbs * modification, are permitted provided that the following conditions 1197883Sgibbs * are met: 1297883Sgibbs * 1. Redistributions of source code must retain the above copyright 1397883Sgibbs * notice, this list of conditions, and the following disclaimer, 1497883Sgibbs * without modification. 1597883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1697883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1797883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1897883Sgibbs * including a substantially similar Disclaimer requirement for further 1997883Sgibbs * binary redistribution. 2097883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2197883Sgibbs * of any contributors may be used to endorse or promote products derived 2297883Sgibbs * from this software without specific prior written permission. 2397883Sgibbs * 2497883Sgibbs * Alternatively, this software may be distributed under the terms of the 2597883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2697883Sgibbs * Software Foundation. 2797883Sgibbs * 2897883Sgibbs * NO WARRANTY 2997883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3097883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3197883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3297883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3397883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3497883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3597883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3697883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3797883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3897883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3997883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 4097883Sgibbs * 41129134Sgibbs * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 4297883Sgibbs */ 4397883Sgibbs 4497883Sgibbs#ifdef __linux__ 4597883Sgibbs#include "aic79xx_osm.h" 4697883Sgibbs#include "aic79xx_inline.h" 4797883Sgibbs#else 48123579Sgibbs#include <sys/cdefs.h> 49123579Sgibbs__FBSDID("$FreeBSD$"); 5097883Sgibbs#include <dev/aic7xxx/aic79xx_osm.h> 5197883Sgibbs#include <dev/aic7xxx/aic79xx_inline.h> 5297883Sgibbs#endif 5397883Sgibbs 5497883Sgibbsstatic __inline uint64_t 5597883Sgibbsahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 5697883Sgibbs{ 5797883Sgibbs uint64_t id; 5897883Sgibbs 5997883Sgibbs id = subvendor 6097883Sgibbs | (subdevice << 16) 6197883Sgibbs | ((uint64_t)vendor << 32) 6297883Sgibbs | ((uint64_t)device << 48); 6397883Sgibbs 6497883Sgibbs return (id); 6597883Sgibbs} 6697883Sgibbs 6797883Sgibbs#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68125448Sgibbs#define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 6997883Sgibbs#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 7097883Sgibbs#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71125448Sgibbs#define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 7297883Sgibbs 7397883Sgibbs#define ID_AIC7901 0x800F9005FFFF9005ull 74115330Sgibbs#define ID_AHA_29320A 0x8000900500609005ull 75115330Sgibbs#define ID_AHA_29320ALP 0x8017900500449005ull 76115330Sgibbs 77102686Sgibbs#define ID_AIC7901A 0x801E9005FFFF9005ull 78107440Sscottl#define ID_AHA_29320LP 0x8014900500449005ull 7997883Sgibbs 8097883Sgibbs#define ID_AIC7902 0x801F9005FFFF9005ull 81107440Sscottl#define ID_AIC7902_B 0x801D9005FFFF9005ull 8297883Sgibbs#define ID_AHA_39320 0x8010900500409005ull 83123579Sgibbs#define ID_AHA_29320 0x8012900500429005ull 84123579Sgibbs#define ID_AHA_29320B 0x8013900500439005ull 85115330Sgibbs#define ID_AHA_39320_B 0x8015900500409005ull 86129134Sgibbs#define ID_AHA_39320_B_DELL 0x8015900501681028ull 87111653Sgibbs#define ID_AHA_39320A 0x8016900500409005ull 8897883Sgibbs#define ID_AHA_39320D 0x8011900500419005ull 89107440Sscottl#define ID_AHA_39320D_B 0x801C900500419005ull 90107440Sscottl#define ID_AHA_39320D_HP 0x8011900500AC0E11ull 91107440Sscottl#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 92198684Sbrueffer#define ID_AHA_39320LPE 0x8017900500459005ull 9397883Sgibbs#define ID_AIC7902_PCI_REV_A4 0x3 94102686Sgibbs#define ID_AIC7902_PCI_REV_B0 0x10 95107440Sscottl#define SUBID_HP 0x0E11 96284022Sachim#define DEVICE8081 0x8081 97284022Sachim#define DEVICE8088 0x8088 98284022Sachim#define DEVICE8089 0x8089 99284022Sachim#define ADAPTECVENDORID 0x9005 100284022Sachim#define SUBVENDOR9005 0x9005 10197883Sgibbs 102125448Sgibbs#define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 103125448Sgibbs 10497883Sgibbs#define DEVID_9005_TYPE(id) ((id) & 0xF) 10597883Sgibbs#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 10697883Sgibbs#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 10797883Sgibbs#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 10897883Sgibbs 10997883Sgibbs#define DEVID_9005_MFUNC(id) ((id) & 0x10) 11097883Sgibbs 11197883Sgibbs#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 11297883Sgibbs 11397883Sgibbs#define SUBID_9005_TYPE(id) ((id) & 0xF) 11497883Sgibbs#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 11597883Sgibbs#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 11697883Sgibbs 11797883Sgibbs#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 11897883Sgibbs 11997883Sgibbs#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 12097883Sgibbs 12197883Sgibbs#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 12297883Sgibbs#define SUBID_9005_SEEPTYPE_NONE 0x0 12397883Sgibbs#define SUBID_9005_SEEPTYPE_4K 0x1 12497883Sgibbs 125115330Sgibbsstatic ahd_device_setup_t ahd_aic7901_setup; 126107440Sscottlstatic ahd_device_setup_t ahd_aic7901A_setup; 12797883Sgibbsstatic ahd_device_setup_t ahd_aic7902_setup; 128116933Sgibbsstatic ahd_device_setup_t ahd_aic790X_setup; 12997883Sgibbs 13097883Sgibbsstruct ahd_pci_identity ahd_pci_ident_table [] = 13197883Sgibbs{ 132115330Sgibbs /* aic7901 based controllers */ 133115330Sgibbs { 134115330Sgibbs ID_AHA_29320A, 135115330Sgibbs ID_ALL_MASK, 136115330Sgibbs "Adaptec 29320A Ultra320 SCSI adapter", 137115330Sgibbs ahd_aic7901_setup 138115330Sgibbs }, 139115330Sgibbs { 140115330Sgibbs ID_AHA_29320ALP, 141115330Sgibbs ID_ALL_MASK, 142115330Sgibbs "Adaptec 29320ALP Ultra320 SCSI adapter", 143115330Sgibbs ahd_aic7901_setup 144115330Sgibbs }, 145107440Sscottl /* aic7901A based controllers */ 14697883Sgibbs { 147123579Sgibbs ID_AHA_29320LP, 148123579Sgibbs ID_ALL_MASK, 149123579Sgibbs "Adaptec 29320LP Ultra320 SCSI adapter", 150123579Sgibbs ahd_aic7901A_setup 151123579Sgibbs }, 152123579Sgibbs /* aic7902 based controllers */ 153123579Sgibbs { 154115330Sgibbs ID_AHA_29320, 155107440Sscottl ID_ALL_MASK, 156115330Sgibbs "Adaptec 29320 Ultra320 SCSI adapter", 157123579Sgibbs ahd_aic7902_setup 158107440Sscottl }, 159107440Sscottl { 160115330Sgibbs ID_AHA_29320B, 16197883Sgibbs ID_ALL_MASK, 162115330Sgibbs "Adaptec 29320B Ultra320 SCSI adapter", 163123579Sgibbs ahd_aic7902_setup 16497883Sgibbs }, 165115330Sgibbs { 16697883Sgibbs ID_AHA_39320, 16797883Sgibbs ID_ALL_MASK, 16897883Sgibbs "Adaptec 39320 Ultra320 SCSI adapter", 16997883Sgibbs ahd_aic7902_setup 17097883Sgibbs }, 17197883Sgibbs { 172115330Sgibbs ID_AHA_39320_B, 173115330Sgibbs ID_ALL_MASK, 174115330Sgibbs "Adaptec 39320 Ultra320 SCSI adapter", 175115330Sgibbs ahd_aic7902_setup 176115330Sgibbs }, 177115330Sgibbs { 178129134Sgibbs ID_AHA_39320_B_DELL, 179129134Sgibbs ID_ALL_MASK, 180129134Sgibbs "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 181129134Sgibbs ahd_aic7902_setup 182129134Sgibbs }, 183129134Sgibbs { 184111653Sgibbs ID_AHA_39320A, 185111653Sgibbs ID_ALL_MASK, 186111653Sgibbs "Adaptec 39320A Ultra320 SCSI adapter", 187111653Sgibbs ahd_aic7902_setup 188111653Sgibbs }, 189111653Sgibbs { 19097883Sgibbs ID_AHA_39320D, 19197883Sgibbs ID_ALL_MASK, 19297883Sgibbs "Adaptec 39320D Ultra320 SCSI adapter", 19397883Sgibbs ahd_aic7902_setup 19497883Sgibbs }, 19597883Sgibbs { 196107440Sscottl ID_AHA_39320D_HP, 19797883Sgibbs ID_ALL_MASK, 198107440Sscottl "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 19997883Sgibbs ahd_aic7902_setup 20097883Sgibbs }, 201102686Sgibbs { 202107440Sscottl ID_AHA_39320D_B, 203102686Sgibbs ID_ALL_MASK, 204107440Sscottl "Adaptec 39320D Ultra320 SCSI adapter", 205102686Sgibbs ahd_aic7902_setup 206102686Sgibbs }, 207102686Sgibbs { 208107440Sscottl ID_AHA_39320D_B_HP, 209102686Sgibbs ID_ALL_MASK, 210107440Sscottl "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 211102686Sgibbs ahd_aic7902_setup 212102686Sgibbs }, 213198684Sbrueffer { 214198684Sbrueffer ID_AHA_39320LPE, 215198684Sbrueffer ID_ALL_MASK, 216198684Sbrueffer "Adaptec 39320LPE Ultra320 SCSI adapter", 217198684Sbrueffer ahd_aic7902_setup 218198684Sbrueffer }, 21997883Sgibbs /* Generic chip probes for devices we don't know 'exactly' */ 22097883Sgibbs { 221125448Sgibbs ID_AIC7901 & ID_9005_GENERIC_MASK, 222129134Sgibbs ID_9005_GENERIC_MASK, 223115330Sgibbs "Adaptec AIC7901 Ultra320 SCSI adapter", 224115330Sgibbs ahd_aic7901_setup 225115330Sgibbs }, 226115330Sgibbs { 227107623Sscottl ID_AIC7901A & ID_DEV_VENDOR_MASK, 228107623Sscottl ID_DEV_VENDOR_MASK, 229107440Sscottl "Adaptec AIC7901A Ultra320 SCSI adapter", 230107440Sscottl ahd_aic7901A_setup 23197883Sgibbs }, 23297883Sgibbs { 23397883Sgibbs ID_AIC7902 & ID_9005_GENERIC_MASK, 23497883Sgibbs ID_9005_GENERIC_MASK, 235107440Sscottl "Adaptec AIC7902 Ultra320 SCSI adapter", 23697883Sgibbs ahd_aic7902_setup 23797883Sgibbs } 23897883Sgibbs}; 23997883Sgibbs 24097883Sgibbsconst u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 24197883Sgibbs 24297883Sgibbs#define DEVCONFIG 0x40 24397883Sgibbs#define PCIXINITPAT 0x0000E000ul 24497883Sgibbs#define PCIXINIT_PCI33_66 0x0000E000ul 24597883Sgibbs#define PCIXINIT_PCIX50_66 0x0000C000ul 24697883Sgibbs#define PCIXINIT_PCIX66_100 0x0000A000ul 24797883Sgibbs#define PCIXINIT_PCIX100_133 0x00008000ul 24897883Sgibbs#define PCI_BUS_MODES_INDEX(devconfig) \ 24997883Sgibbs (((devconfig) & PCIXINITPAT) >> 13) 25097883Sgibbsstatic const char *pci_bus_modes[] = 25197883Sgibbs{ 25297883Sgibbs "PCI bus mode unknown", 25397883Sgibbs "PCI bus mode unknown", 25497883Sgibbs "PCI bus mode unknown", 25597883Sgibbs "PCI bus mode unknown", 256202161Sgavin "PCI-X 101-133MHz", 257202161Sgavin "PCI-X 67-100MHz", 258202161Sgavin "PCI-X 50-66MHz", 259202161Sgavin "PCI 33 or 66MHz" 26097883Sgibbs}; 26197883Sgibbs 26297883Sgibbs#define TESTMODE 0x00000800ul 26397883Sgibbs#define IRDY_RST 0x00000200ul 26497883Sgibbs#define FRAME_RST 0x00000100ul 26597883Sgibbs#define PCI64BIT 0x00000080ul 26697883Sgibbs#define MRDCEN 0x00000040ul 26797883Sgibbs#define ENDIANSEL 0x00000020ul 26897883Sgibbs#define MIXQWENDIANEN 0x00000008ul 26997883Sgibbs#define DACEN 0x00000004ul 27097883Sgibbs#define STPWLEVEL 0x00000002ul 27197883Sgibbs#define QWENDIANSEL 0x00000001ul 27297883Sgibbs 27397883Sgibbs#define DEVCONFIG1 0x44 27497883Sgibbs#define PREQDIS 0x01 27597883Sgibbs 27697883Sgibbs#define CSIZE_LATTIME 0x0c 27797883Sgibbs#define CACHESIZE 0x000000fful 27897883Sgibbs#define LATTIME 0x0000ff00ul 27997883Sgibbs 28097883Sgibbsstatic int ahd_check_extport(struct ahd_softc *ahd); 28197883Sgibbsstatic void ahd_configure_termination(struct ahd_softc *ahd, 28297883Sgibbs u_int adapter_control); 28397883Sgibbsstatic void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 28497883Sgibbs 28597883Sgibbsstruct ahd_pci_identity * 286123579Sgibbsahd_find_pci_device(aic_dev_softc_t pci) 28797883Sgibbs{ 28897883Sgibbs uint64_t full_id; 28997883Sgibbs uint16_t device; 29097883Sgibbs uint16_t vendor; 29197883Sgibbs uint16_t subdevice; 29297883Sgibbs uint16_t subvendor; 29397883Sgibbs struct ahd_pci_identity *entry; 29497883Sgibbs u_int i; 29597883Sgibbs 296123579Sgibbs vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 297123579Sgibbs device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 298123579Sgibbs subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 299123579Sgibbs subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 300284022Sachim 301284022Sachim if ((vendor == ADAPTECVENDORID) && (subvendor == SUBVENDOR9005)) { 302284022Sachim if ((device == DEVICE8081) || (device == DEVICE8088) || 303284022Sachim (device == DEVICE8089)) { 304284022Sachim printf("Controller device ID conflict with PMC Adaptec HBA\n"); 305284022Sachim return (NULL); 306284022Sachim } 307284022Sachim } 308284022Sachim 30997883Sgibbs full_id = ahd_compose_id(device, 31097883Sgibbs vendor, 31197883Sgibbs subdevice, 31297883Sgibbs subvendor); 31397883Sgibbs 314125448Sgibbs /* 315125448Sgibbs * If we are configured to attach to HostRAID 316125448Sgibbs * controllers, mask out the IROC/HostRAID bit 317125448Sgibbs * in the 318125448Sgibbs */ 319125448Sgibbs if (ahd_attach_to_HostRAID_controllers) 320125448Sgibbs full_id &= ID_ALL_IROC_MASK; 321125448Sgibbs 32297883Sgibbs for (i = 0; i < ahd_num_pci_devs; i++) { 32397883Sgibbs entry = &ahd_pci_ident_table[i]; 32497883Sgibbs if (entry->full_id == (full_id & entry->id_mask)) { 32597883Sgibbs /* Honor exclusion entries. */ 32697883Sgibbs if (entry->name == NULL) 32797883Sgibbs return (NULL); 32897883Sgibbs return (entry); 32997883Sgibbs } 33097883Sgibbs } 33197883Sgibbs return (NULL); 33297883Sgibbs} 33397883Sgibbs 33497883Sgibbsint 33597883Sgibbsahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 33697883Sgibbs{ 33797883Sgibbs u_int command; 33897883Sgibbs uint32_t devconfig; 339125448Sgibbs uint16_t device; 34097883Sgibbs uint16_t subvendor; 34197883Sgibbs int error; 34297883Sgibbs 343107440Sscottl ahd->description = entry->name; 344107440Sscottl /* 345125448Sgibbs * Record if this is a HostRAID board. 346125448Sgibbs */ 347125448Sgibbs device = aic_pci_read_config(ahd->dev_softc, 348125448Sgibbs PCIR_DEVICE, /*bytes*/2); 349125448Sgibbs if (DEVID_9005_HOSTRAID(device)) 350125448Sgibbs ahd->flags |= AHD_HOSTRAID_BOARD; 351125448Sgibbs 352125448Sgibbs /* 353107440Sscottl * Record if this is an HP board. 354107440Sscottl */ 355123579Sgibbs subvendor = aic_pci_read_config(ahd->dev_softc, 356107440Sscottl PCIR_SUBVEND_0, /*bytes*/2); 357107440Sscottl if (subvendor == SUBID_HP) 358107440Sscottl ahd->flags |= AHD_HP_BOARD; 359107440Sscottl 36097883Sgibbs error = entry->setup(ahd); 36197883Sgibbs if (error != 0) 36297883Sgibbs return (error); 363166109Sjhb 364166109Sjhb /* 365166109Sjhb * Find the PCI-X cap pointer. If we don't find it, 366166109Sjhb * pcix_ptr will be 0. 367166109Sjhb */ 368219902Sjhb pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 369123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 37097883Sgibbs if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 37197883Sgibbs ahd->chip |= AHD_PCI; 37297883Sgibbs /* Disable PCIX workarounds when running in PCI mode. */ 37397883Sgibbs ahd->bugs &= ~AHD_PCIX_BUG_MASK; 37497883Sgibbs } else { 37597883Sgibbs ahd->chip |= AHD_PCIX; 376166109Sjhb if (ahd->pcix_ptr == 0) 377166109Sjhb return (ENXIO); 37897883Sgibbs } 37997883Sgibbs ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 38097883Sgibbs 381123579Sgibbs aic_power_state_change(ahd, AIC_POWER_STATE_D0); 38297883Sgibbs 38397883Sgibbs error = ahd_pci_map_registers(ahd); 38497883Sgibbs if (error != 0) 38597883Sgibbs return (error); 38697883Sgibbs 38797883Sgibbs /* 38897883Sgibbs * If we need to support high memory, enable dual 38997883Sgibbs * address cycles. This bit must be set to enable 39097883Sgibbs * high address bit generation even if we are on a 39197883Sgibbs * 64bit bus (PCI64BIT set in devconfig). 39297883Sgibbs */ 39397883Sgibbs if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 39497883Sgibbs uint32_t devconfig; 39597883Sgibbs 39697883Sgibbs if (bootverbose) 39797883Sgibbs printf("%s: Enabling 39Bit Addressing\n", 39897883Sgibbs ahd_name(ahd)); 399123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, 40097883Sgibbs DEVCONFIG, /*bytes*/4); 40197883Sgibbs devconfig |= DACEN; 402123579Sgibbs aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 40397883Sgibbs devconfig, /*bytes*/4); 40497883Sgibbs } 40597883Sgibbs 40697883Sgibbs /* Ensure busmastering is enabled */ 407123579Sgibbs command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 40897883Sgibbs command |= PCIM_CMD_BUSMASTEREN; 409123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 41097883Sgibbs 41197883Sgibbs error = ahd_softc_init(ahd); 41297883Sgibbs if (error != 0) 41397883Sgibbs return (error); 41497883Sgibbs 41597883Sgibbs ahd->bus_intr = ahd_pci_intr; 41697883Sgibbs 417115917Sgibbs error = ahd_reset(ahd, /*reinit*/FALSE); 41897883Sgibbs if (error != 0) 41997883Sgibbs return (ENXIO); 42097883Sgibbs 42197883Sgibbs ahd->pci_cachesize = 422123579Sgibbs aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 42397883Sgibbs /*bytes*/1) & CACHESIZE; 42497883Sgibbs ahd->pci_cachesize *= 4; 42597883Sgibbs 42697883Sgibbs ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 42797883Sgibbs /* See if we have a SEEPROM and perform auto-term */ 42897883Sgibbs error = ahd_check_extport(ahd); 42997883Sgibbs if (error != 0) 43097883Sgibbs return (error); 43197883Sgibbs 43297883Sgibbs /* Core initialization */ 43397883Sgibbs error = ahd_init(ahd); 43497883Sgibbs if (error != 0) 43597883Sgibbs return (error); 43697883Sgibbs 43797883Sgibbs /* 43897883Sgibbs * Allow interrupts now that we are completely setup. 43997883Sgibbs */ 44097883Sgibbs error = ahd_pci_map_int(ahd); 44197883Sgibbs if (error != 0) 44297883Sgibbs return (error); 44397883Sgibbs 444168807Sscottl ahd_lock(ahd); 44597883Sgibbs /* 44697883Sgibbs * Link this softc in with all other ahd instances. 44797883Sgibbs */ 44897883Sgibbs ahd_softc_insert(ahd); 449168807Sscottl ahd_unlock(ahd); 45097883Sgibbs return (0); 45197883Sgibbs} 45297883Sgibbs 45397883Sgibbs/* 454107440Sscottl * Perform some simple tests that should catch situations where 455107440Sscottl * our registers are invalidly mapped. 456107440Sscottl */ 457107440Sscottlint 458107440Sscottlahd_pci_test_register_access(struct ahd_softc *ahd) 459107440Sscottl{ 460115919Sgibbs uint32_t cmd; 461115919Sgibbs u_int targpcistat; 462115919Sgibbs u_int pci_status1; 463115919Sgibbs int error; 464115919Sgibbs uint8_t hcntrl; 465107440Sscottl 466107623Sscottl error = EIO; 467107623Sscottl 468109588Sgibbs /* 469109588Sgibbs * Enable PCI error interrupt status, but suppress NMIs 470109588Sgibbs * generated by SERR raised due to target aborts. 471109588Sgibbs */ 472123579Sgibbs cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 473123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 474109588Sgibbs cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 475107623Sscottl 476107440Sscottl /* 477107440Sscottl * First a simple test to see if any 478107440Sscottl * registers can be read. Reading 479107440Sscottl * HCNTRL has no side effects and has 480107440Sscottl * at least one bit that is guaranteed to 481107440Sscottl * be zero so it is a good register to 482107440Sscottl * use for this test. 483107440Sscottl */ 484109588Sgibbs hcntrl = ahd_inb(ahd, HCNTRL); 485109588Sgibbs if (hcntrl == 0xFF) 486107623Sscottl goto fail; 487107440Sscottl 488107440Sscottl /* 489107440Sscottl * Next create a situation where write combining 490107440Sscottl * or read prefetching could be initiated by the 491107440Sscottl * CPU or host bridge. Our device does not support 492299375Spfg * either, so look for data corruption and/or flagged 493120445Sscottl * PCI errors. First pause without causing another 494120445Sscottl * chip reset. 495107440Sscottl */ 496120445Sscottl hcntrl &= ~CHIPRST; 497109588Sgibbs ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 498109588Sgibbs while (ahd_is_paused(ahd) == 0) 499109588Sgibbs ; 500115919Sgibbs 501115919Sgibbs /* Clear any PCI errors that occurred before our driver attached. */ 502115919Sgibbs ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 503115919Sgibbs targpcistat = ahd_inb(ahd, TARGPCISTAT); 504115919Sgibbs ahd_outb(ahd, TARGPCISTAT, targpcistat); 505123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 506115919Sgibbs PCIR_STATUS + 1, /*bytes*/1); 507123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 508115919Sgibbs pci_status1, /*bytes*/1); 509115919Sgibbs ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 510115919Sgibbs ahd_outb(ahd, CLRINT, CLRPCIINT); 511115919Sgibbs 512109588Sgibbs ahd_outb(ahd, SEQCTL0, PERRORDIS); 513107623Sscottl ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 514107623Sscottl if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 515107623Sscottl goto fail; 516107440Sscottl 517107623Sscottl if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 518107623Sscottl u_int targpcistat; 519107440Sscottl 520107623Sscottl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 521107623Sscottl targpcistat = ahd_inb(ahd, TARGPCISTAT); 522107623Sscottl if ((targpcistat & STA) != 0) 523107623Sscottl goto fail; 524107623Sscottl } 525107623Sscottl 526107623Sscottl error = 0; 527107623Sscottl 528107623Sscottlfail: 529107440Sscottl if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 530107440Sscottl 531107440Sscottl ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 532107440Sscottl targpcistat = ahd_inb(ahd, TARGPCISTAT); 533107440Sscottl 534107440Sscottl /* Silently clear any latched errors. */ 535107440Sscottl ahd_outb(ahd, TARGPCISTAT, targpcistat); 536123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 537107440Sscottl PCIR_STATUS + 1, /*bytes*/1); 538123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 539107440Sscottl pci_status1, /*bytes*/1); 540107623Sscottl ahd_outb(ahd, CLRINT, CLRPCIINT); 541107440Sscottl } 542109588Sgibbs ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 543123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 544107623Sscottl return (error); 545107440Sscottl} 546107440Sscottl 547107440Sscottl/* 54897883Sgibbs * Check the external port logic for a serial eeprom 54997883Sgibbs * and termination/cable detection contrls. 55097883Sgibbs */ 55197883Sgibbsstatic int 55297883Sgibbsahd_check_extport(struct ahd_softc *ahd) 55397883Sgibbs{ 554114623Sgibbs struct vpd_config vpd; 55597883Sgibbs struct seeprom_config *sc; 55697883Sgibbs u_int adapter_control; 55797883Sgibbs int have_seeprom; 55897883Sgibbs int error; 55997883Sgibbs 56097883Sgibbs sc = ahd->seep_config; 56197883Sgibbs have_seeprom = ahd_acquire_seeprom(ahd); 56297883Sgibbs if (have_seeprom) { 56397883Sgibbs u_int start_addr; 56497883Sgibbs 565114623Sgibbs /* 566114623Sgibbs * Fetch VPD for this function and parse it. 567114623Sgibbs */ 56897883Sgibbs if (bootverbose) 569114623Sgibbs printf("%s: Reading VPD from SEEPROM...", 570114623Sgibbs ahd_name(ahd)); 571114623Sgibbs 572114623Sgibbs /* Address is always in units of 16bit words */ 573114623Sgibbs start_addr = ((2 * sizeof(*sc)) 574114623Sgibbs + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 575114623Sgibbs 576114623Sgibbs error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 577114623Sgibbs start_addr, sizeof(vpd)/2, 578114623Sgibbs /*bytestream*/TRUE); 579114623Sgibbs if (error == 0) 580114623Sgibbs error = ahd_parse_vpddata(ahd, &vpd); 581114623Sgibbs if (bootverbose) 582114623Sgibbs printf("%s: VPD parsing %s\n", 583114623Sgibbs ahd_name(ahd), 584114623Sgibbs error == 0 ? "successful" : "failed"); 585114623Sgibbs 586114623Sgibbs if (bootverbose) 58797883Sgibbs printf("%s: Reading SEEPROM...", ahd_name(ahd)); 58897883Sgibbs 58997883Sgibbs /* Address is always in units of 16bit words */ 59097883Sgibbs start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 59197883Sgibbs 59297883Sgibbs error = ahd_read_seeprom(ahd, (uint16_t *)sc, 593114623Sgibbs start_addr, sizeof(*sc)/2, 594114623Sgibbs /*bytestream*/FALSE); 59597883Sgibbs 59697883Sgibbs if (error != 0) { 59797883Sgibbs printf("Unable to read SEEPROM\n"); 59897883Sgibbs have_seeprom = 0; 59997883Sgibbs } else { 60097883Sgibbs have_seeprom = ahd_verify_cksum(sc); 60197883Sgibbs 60297883Sgibbs if (bootverbose) { 60397883Sgibbs if (have_seeprom == 0) 60497883Sgibbs printf ("checksum error\n"); 60597883Sgibbs else 60697883Sgibbs printf ("done.\n"); 60797883Sgibbs } 60897883Sgibbs } 60997883Sgibbs ahd_release_seeprom(ahd); 61097883Sgibbs } 61197883Sgibbs 61297883Sgibbs if (!have_seeprom) { 61397883Sgibbs u_int nvram_scb; 61497883Sgibbs 61597883Sgibbs /* 61697883Sgibbs * Pull scratch ram settings and treat them as 61797883Sgibbs * if they are the contents of an seeprom if 61897883Sgibbs * the 'ADPT', 'BIOS', or 'ASPI' signature is found 61997883Sgibbs * in SCB 0xFF. We manually compose the data as 16bit 62097883Sgibbs * values to avoid endian issues. 62197883Sgibbs */ 62297883Sgibbs ahd_set_scbptr(ahd, 0xFF); 62397883Sgibbs nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 62497883Sgibbs if (nvram_scb != 0xFF 62597883Sgibbs && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 62697883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 62797883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 62897883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 62997883Sgibbs || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 63097883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 63197883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 63297883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 63397883Sgibbs || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 63497883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 63597883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 63697883Sgibbs && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 63797883Sgibbs uint16_t *sc_data; 63897883Sgibbs int i; 63997883Sgibbs 64097883Sgibbs ahd_set_scbptr(ahd, nvram_scb); 64197883Sgibbs sc_data = (uint16_t *)sc; 64297883Sgibbs for (i = 0; i < 64; i += 2) 64397883Sgibbs *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 64497883Sgibbs have_seeprom = ahd_verify_cksum(sc); 64597883Sgibbs if (have_seeprom) 64697883Sgibbs ahd->flags |= AHD_SCB_CONFIG_USED; 64797883Sgibbs } 64897883Sgibbs } 64997883Sgibbs 650153072Sru#ifdef AHD_DEBUG 65197883Sgibbs if (have_seeprom != 0 65297883Sgibbs && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 653114623Sgibbs uint16_t *sc_data; 654114623Sgibbs int i; 65597883Sgibbs 65697883Sgibbs printf("%s: Seeprom Contents:", ahd_name(ahd)); 657114623Sgibbs sc_data = (uint16_t *)sc; 65897883Sgibbs for (i = 0; i < (sizeof(*sc)); i += 2) 659114623Sgibbs printf("\n\t0x%.4x", sc_data[i]); 66097883Sgibbs printf("\n"); 66197883Sgibbs } 66297883Sgibbs#endif 66397883Sgibbs 66497883Sgibbs if (!have_seeprom) { 66597883Sgibbs if (bootverbose) 66697883Sgibbs printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 66797883Sgibbs ahd->flags |= AHD_USEDEFAULTS; 66897883Sgibbs error = ahd_default_config(ahd); 66997883Sgibbs adapter_control = CFAUTOTERM|CFSEAUTOTERM; 67097883Sgibbs free(ahd->seep_config, M_DEVBUF); 67197883Sgibbs ahd->seep_config = NULL; 67297883Sgibbs } else { 67397883Sgibbs error = ahd_parse_cfgdata(ahd, sc); 67497883Sgibbs adapter_control = sc->adapter_control; 67597883Sgibbs } 67697883Sgibbs if (error != 0) 67797883Sgibbs return (error); 67897883Sgibbs 67997883Sgibbs ahd_configure_termination(ahd, adapter_control); 68097883Sgibbs 68197883Sgibbs return (0); 68297883Sgibbs} 68397883Sgibbs 68497883Sgibbsstatic void 68597883Sgibbsahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 68697883Sgibbs{ 68797883Sgibbs int error; 68897883Sgibbs u_int sxfrctl1; 68997883Sgibbs uint8_t termctl; 69097883Sgibbs uint32_t devconfig; 69197883Sgibbs 692123579Sgibbs devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 69397883Sgibbs devconfig &= ~STPWLEVEL; 694102686Sgibbs if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 69597883Sgibbs devconfig |= STPWLEVEL; 696102686Sgibbs if (bootverbose) 697102686Sgibbs printf("%s: STPWLEVEL is %s\n", 698102686Sgibbs ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 699123579Sgibbs aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 70097883Sgibbs 70197883Sgibbs /* Make sure current sensing is off. */ 70297883Sgibbs if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 70397883Sgibbs (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 70497883Sgibbs } 70597883Sgibbs 70697883Sgibbs /* 70797883Sgibbs * Read to sense. Write to set. 70897883Sgibbs */ 70997883Sgibbs error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 71097883Sgibbs if ((adapter_control & CFAUTOTERM) == 0) { 71197883Sgibbs if (bootverbose) 71297883Sgibbs printf("%s: Manual Primary Termination\n", 71397883Sgibbs ahd_name(ahd)); 71497883Sgibbs termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 71597883Sgibbs if ((adapter_control & CFSTERM) != 0) 71697883Sgibbs termctl |= FLX_TERMCTL_ENPRILOW; 71797883Sgibbs if ((adapter_control & CFWSTERM) != 0) 71897883Sgibbs termctl |= FLX_TERMCTL_ENPRIHIGH; 71997883Sgibbs } else if (error != 0) { 72097883Sgibbs printf("%s: Primary Auto-Term Sensing failed! " 72197883Sgibbs "Using Defaults.\n", ahd_name(ahd)); 72297883Sgibbs termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 72397883Sgibbs } 72497883Sgibbs 72597883Sgibbs if ((adapter_control & CFSEAUTOTERM) == 0) { 72697883Sgibbs if (bootverbose) 72797883Sgibbs printf("%s: Manual Secondary Termination\n", 72897883Sgibbs ahd_name(ahd)); 72997883Sgibbs termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 73097883Sgibbs if ((adapter_control & CFSELOWTERM) != 0) 73197883Sgibbs termctl |= FLX_TERMCTL_ENSECLOW; 73297883Sgibbs if ((adapter_control & CFSEHIGHTERM) != 0) 73397883Sgibbs termctl |= FLX_TERMCTL_ENSECHIGH; 73497883Sgibbs } else if (error != 0) { 73597883Sgibbs printf("%s: Secondary Auto-Term Sensing failed! " 73697883Sgibbs "Using Defaults.\n", ahd_name(ahd)); 73797883Sgibbs termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 73897883Sgibbs } 73997883Sgibbs 74097883Sgibbs /* 74197883Sgibbs * Now set the termination based on what we found. 74297883Sgibbs */ 74397883Sgibbs sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 744123579Sgibbs ahd->flags &= ~AHD_TERM_ENB_A; 74597883Sgibbs if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 74697883Sgibbs ahd->flags |= AHD_TERM_ENB_A; 74797883Sgibbs sxfrctl1 |= STPWEN; 74897883Sgibbs } 74997883Sgibbs /* Must set the latch once in order to be effective. */ 75097883Sgibbs ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 75197883Sgibbs ahd_outb(ahd, SXFRCTL1, sxfrctl1); 75297883Sgibbs 75397883Sgibbs error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 75497883Sgibbs if (error != 0) { 75597883Sgibbs printf("%s: Unable to set termination settings!\n", 75697883Sgibbs ahd_name(ahd)); 75797883Sgibbs } else if (bootverbose) { 75897883Sgibbs printf("%s: Primary High byte termination %sabled\n", 75997883Sgibbs ahd_name(ahd), 76097883Sgibbs (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 76197883Sgibbs 76297883Sgibbs printf("%s: Primary Low byte termination %sabled\n", 76397883Sgibbs ahd_name(ahd), 76497883Sgibbs (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 76597883Sgibbs 76697883Sgibbs printf("%s: Secondary High byte termination %sabled\n", 76797883Sgibbs ahd_name(ahd), 76897883Sgibbs (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 76997883Sgibbs 77097883Sgibbs printf("%s: Secondary Low byte termination %sabled\n", 77197883Sgibbs ahd_name(ahd), 77297883Sgibbs (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 77397883Sgibbs } 77497883Sgibbs return; 77597883Sgibbs} 77697883Sgibbs 77797883Sgibbs#define DPE 0x80 77897883Sgibbs#define SSE 0x40 77997883Sgibbs#define RMA 0x20 78097883Sgibbs#define RTA 0x10 78197883Sgibbs#define STA 0x08 78297883Sgibbs#define DPR 0x01 78397883Sgibbs 78497883Sgibbsstatic const char *split_status_source[] = 78597883Sgibbs{ 78697883Sgibbs "DFF0", 78797883Sgibbs "DFF1", 78897883Sgibbs "OVLY", 78997883Sgibbs "CMC", 79097883Sgibbs}; 79197883Sgibbs 79297883Sgibbsstatic const char *pci_status_source[] = 79397883Sgibbs{ 79497883Sgibbs "DFF0", 79597883Sgibbs "DFF1", 79697883Sgibbs "SG", 79797883Sgibbs "CMC", 79897883Sgibbs "OVLY", 79997883Sgibbs "NONE", 80097883Sgibbs "MSI", 80197883Sgibbs "TARG" 80297883Sgibbs}; 80397883Sgibbs 80497883Sgibbsstatic const char *split_status_strings[] = 80597883Sgibbs{ 806111653Sgibbs "%s: Received split response in %s.\n", 80797883Sgibbs "%s: Received split completion error message in %s\n", 80897883Sgibbs "%s: Receive overrun in %s\n", 80997883Sgibbs "%s: Count not complete in %s\n", 81097883Sgibbs "%s: Split completion data bucket in %s\n", 81197883Sgibbs "%s: Split completion address error in %s\n", 81297883Sgibbs "%s: Split completion byte count error in %s\n", 813111653Sgibbs "%s: Signaled Target-abort to early terminate a split in %s\n" 81497883Sgibbs}; 81597883Sgibbs 81697883Sgibbsstatic const char *pci_status_strings[] = 81797883Sgibbs{ 81897883Sgibbs "%s: Data Parity Error has been reported via PERR# in %s\n", 81997883Sgibbs "%s: Target initial wait state error in %s\n", 82097883Sgibbs "%s: Split completion read data parity error in %s\n", 82197883Sgibbs "%s: Split completion address attribute parity error in %s\n", 82297883Sgibbs "%s: Received a Target Abort in %s\n", 82397883Sgibbs "%s: Received a Master Abort in %s\n", 82497883Sgibbs "%s: Signal System Error Detected in %s\n", 82597883Sgibbs "%s: Address or Write Phase Parity Error Detected in %s.\n" 82697883Sgibbs}; 82797883Sgibbs 82897883Sgibbsvoid 82997883Sgibbsahd_pci_intr(struct ahd_softc *ahd) 83097883Sgibbs{ 83197883Sgibbs uint8_t pci_status[8]; 83297883Sgibbs ahd_mode_state saved_modes; 83397883Sgibbs u_int pci_status1; 83497883Sgibbs u_int intstat; 83597883Sgibbs u_int i; 83697883Sgibbs u_int reg; 83797883Sgibbs 83897883Sgibbs intstat = ahd_inb(ahd, INTSTAT); 83997883Sgibbs 84097883Sgibbs if ((intstat & SPLTINT) != 0) 84197883Sgibbs ahd_pci_split_intr(ahd, intstat); 84297883Sgibbs 84397883Sgibbs if ((intstat & PCIINT) == 0) 84497883Sgibbs return; 84597883Sgibbs 84697883Sgibbs printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 84797883Sgibbs saved_modes = ahd_save_modes(ahd); 84897883Sgibbs ahd_dump_card_state(ahd); 84997883Sgibbs ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 85097883Sgibbs for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 85197883Sgibbs 85297883Sgibbs if (i == 5) 85397883Sgibbs continue; 85497883Sgibbs pci_status[i] = ahd_inb(ahd, reg); 855111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 85697883Sgibbs ahd_outb(ahd, reg, pci_status[i]); 85797883Sgibbs } 85897883Sgibbs 85997883Sgibbs for (i = 0; i < 8; i++) { 86097883Sgibbs u_int bit; 86197883Sgibbs 86297883Sgibbs if (i == 5) 86397883Sgibbs continue; 86497883Sgibbs 86597883Sgibbs for (bit = 0; bit < 8; bit++) { 86697883Sgibbs 86797883Sgibbs if ((pci_status[i] & (0x1 << bit)) != 0) { 86897883Sgibbs static const char *s; 86997883Sgibbs 87097883Sgibbs s = pci_status_strings[bit]; 87197883Sgibbs if (i == 7/*TARG*/ && bit == 3) 872107623Sscottl s = "%s: Signaled Target Abort\n"; 87397883Sgibbs printf(s, ahd_name(ahd), pci_status_source[i]); 87497883Sgibbs } 87597883Sgibbs } 87697883Sgibbs } 877123579Sgibbs pci_status1 = aic_pci_read_config(ahd->dev_softc, 87897883Sgibbs PCIR_STATUS + 1, /*bytes*/1); 879123579Sgibbs aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 88097883Sgibbs pci_status1, /*bytes*/1); 88197883Sgibbs ahd_restore_modes(ahd, saved_modes); 882107623Sscottl ahd_outb(ahd, CLRINT, CLRPCIINT); 88397883Sgibbs ahd_unpause(ahd); 88497883Sgibbs} 88597883Sgibbs 88697883Sgibbsstatic void 88797883Sgibbsahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 88897883Sgibbs{ 88997883Sgibbs uint8_t split_status[4]; 89097883Sgibbs uint8_t split_status1[4]; 89197883Sgibbs uint8_t sg_split_status[2]; 89297883Sgibbs uint8_t sg_split_status1[2]; 89397883Sgibbs ahd_mode_state saved_modes; 89497883Sgibbs u_int i; 895166109Sjhb uint32_t pcix_status; 89697883Sgibbs 89797883Sgibbs /* 89897883Sgibbs * Check for splits in all modes. Modes 0 and 1 89997883Sgibbs * additionally have SG engine splits to look at. 90097883Sgibbs */ 901166109Sjhb pcix_status = aic_pci_read_config(ahd->dev_softc, 902166109Sjhb ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 90397883Sgibbs printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 904166109Sjhb ahd_name(ahd), pcix_status >> 16); 90597883Sgibbs saved_modes = ahd_save_modes(ahd); 90697883Sgibbs for (i = 0; i < 4; i++) { 90797883Sgibbs ahd_set_modes(ahd, i, i); 90897883Sgibbs 90997883Sgibbs split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 91097883Sgibbs split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 911111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 91297883Sgibbs ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 91397883Sgibbs ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 914114623Sgibbs if (i > 1) 91597883Sgibbs continue; 91697883Sgibbs sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 91797883Sgibbs sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 918111653Sgibbs /* Clear latched errors. So our interrupt deasserts. */ 91997883Sgibbs ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 92097883Sgibbs ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 92197883Sgibbs } 92297883Sgibbs 92397883Sgibbs for (i = 0; i < 4; i++) { 92497883Sgibbs u_int bit; 92597883Sgibbs 92697883Sgibbs for (bit = 0; bit < 8; bit++) { 92797883Sgibbs 92897883Sgibbs if ((split_status[i] & (0x1 << bit)) != 0) { 92997883Sgibbs static const char *s; 93097883Sgibbs 93197883Sgibbs s = split_status_strings[bit]; 93297883Sgibbs printf(s, ahd_name(ahd), 93397883Sgibbs split_status_source[i]); 93497883Sgibbs } 93597883Sgibbs 936114623Sgibbs if (i > 1) 93797883Sgibbs continue; 93897883Sgibbs 93997883Sgibbs if ((sg_split_status[i] & (0x1 << bit)) != 0) { 94097883Sgibbs static const char *s; 94197883Sgibbs 94297883Sgibbs s = split_status_strings[bit]; 94397883Sgibbs printf(s, ahd_name(ahd), "SG"); 94497883Sgibbs } 94597883Sgibbs } 94697883Sgibbs } 94797883Sgibbs /* 94897883Sgibbs * Clear PCI-X status bits. 94997883Sgibbs */ 950166109Sjhb aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 951166109Sjhb pcix_status, /*bytes*/4); 952107623Sscottl ahd_outb(ahd, CLRINT, CLRSPLTINT); 95397883Sgibbs ahd_restore_modes(ahd, saved_modes); 95497883Sgibbs} 95597883Sgibbs 95697883Sgibbsstatic int 957115330Sgibbsahd_aic7901_setup(struct ahd_softc *ahd) 958115330Sgibbs{ 959115330Sgibbs 960115330Sgibbs ahd->chip = AHD_AIC7901; 961116933Sgibbs ahd->features = AHD_AIC7901_FE; 962116933Sgibbs return (ahd_aic790X_setup(ahd)); 963115330Sgibbs} 964115330Sgibbs 965115330Sgibbsstatic int 966107440Sscottlahd_aic7901A_setup(struct ahd_softc *ahd) 96797883Sgibbs{ 968107440Sscottl 969107440Sscottl ahd->chip = AHD_AIC7901A; 970116933Sgibbs ahd->features = AHD_AIC7901A_FE; 971116933Sgibbs return (ahd_aic790X_setup(ahd)); 97297883Sgibbs} 97397883Sgibbs 97497883Sgibbsstatic int 97597883Sgibbsahd_aic7902_setup(struct ahd_softc *ahd) 97697883Sgibbs{ 977116933Sgibbs ahd->chip = AHD_AIC7902; 978116933Sgibbs ahd->features = AHD_AIC7902_FE; 979116933Sgibbs return (ahd_aic790X_setup(ahd)); 980116933Sgibbs} 981116933Sgibbs 982116933Sgibbsstatic int 983116933Sgibbsahd_aic790X_setup(struct ahd_softc *ahd) 984116933Sgibbs{ 985123579Sgibbs aic_dev_softc_t pci; 98697883Sgibbs u_int rev; 98797883Sgibbs 98897883Sgibbs pci = ahd->dev_softc; 989123579Sgibbs rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 990102686Sgibbs if (rev < ID_AIC7902_PCI_REV_A4) { 99197883Sgibbs printf("%s: Unable to attach to unsupported chip revision %d\n", 99297883Sgibbs ahd_name(ahd), rev); 993123579Sgibbs aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 99497883Sgibbs return (ENXIO); 99597883Sgibbs } 996123579Sgibbs ahd->channel = aic_get_pci_function(pci) + 'A'; 99797883Sgibbs if (rev < ID_AIC7902_PCI_REV_B0) { 99897883Sgibbs /* 99997883Sgibbs * Enable A series workarounds. 100097883Sgibbs */ 100197883Sgibbs ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 100297883Sgibbs | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 100397883Sgibbs | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 100497883Sgibbs | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 100597883Sgibbs | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1006111954Sgibbs | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1007111954Sgibbs | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1008111954Sgibbs | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1009111954Sgibbs | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1010114623Sgibbs | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1011114623Sgibbs | AHD_FAINT_LED_BUG; 101297883Sgibbs 1013107440Sscottl /* 1014299375Spfg * IO Cell parameter setup. 1015107440Sscottl */ 1016107440Sscottl AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1017102686Sgibbs 1018107440Sscottl if ((ahd->flags & AHD_HP_BOARD) == 0) 1019107440Sscottl AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1020107440Sscottl } else { 1021107440Sscottl u_int devconfig1; 1022102686Sgibbs 1023107440Sscottl ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1024134156Sgibbs | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1025141979Sgibbs ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1026107440Sscottl 1027107440Sscottl /* 1028116933Sgibbs * Some issues have been resolved in the 7901B. 1029116933Sgibbs */ 1030116933Sgibbs if ((ahd->features & AHD_MULTI_FUNC) != 0) 1031141979Sgibbs ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1032141979Sgibbs | AHD_BUSFREEREV_BUG; 1033116933Sgibbs 1034116933Sgibbs /* 1035299375Spfg * IO Cell parameter setup. 1036107440Sscottl */ 1037107440Sscottl AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1038107440Sscottl AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1039107440Sscottl AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1040107440Sscottl 1041107440Sscottl /* 1042107440Sscottl * Set the PREQDIS bit for H2B which disables some workaround 1043107440Sscottl * that doesn't work on regular PCI busses. 1044107440Sscottl * XXX - Find out exactly what this does from the hardware 1045107440Sscottl * folks! 1046107440Sscottl */ 1047123579Sgibbs devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1048123579Sgibbs aic_pci_write_config(pci, DEVCONFIG1, 1049107440Sscottl devconfig1|PREQDIS, /*bytes*/1); 1050123579Sgibbs devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1051107440Sscottl } 1052107440Sscottl 1053102686Sgibbs return (0); 1054102686Sgibbs} 1055