aic79xx.reg revision 104023
197883Sgibbs/* 297883Sgibbs * Aic79xx register and scratch ram definitions. 397883Sgibbs * 497883Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 5102681Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 697883Sgibbs * All rights reserved. 797883Sgibbs * 897883Sgibbs * Redistribution and use in source and binary forms, with or without 997883Sgibbs * modification, are permitted provided that the following conditions 1097883Sgibbs * are met: 1197883Sgibbs * 1. Redistributions of source code must retain the above copyright 1297883Sgibbs * notice, this list of conditions, and the following disclaimer, 1397883Sgibbs * without modification. 1497883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1597883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1697883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1797883Sgibbs * including a substantially similar Disclaimer requirement for further 1897883Sgibbs * binary redistribution. 1997883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2097883Sgibbs * of any contributors may be used to endorse or promote products derived 2197883Sgibbs * from this software without specific prior written permission. 2297883Sgibbs * 2397883Sgibbs * Alternatively, this software may be distributed under the terms of the 2497883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2597883Sgibbs * Software Foundation. 2697883Sgibbs * 2797883Sgibbs * NO WARRANTY 2897883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2997883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3097883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3197883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3297883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3397883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3497883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3597883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3697883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3797883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3897883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3997883Sgibbs * 4097883Sgibbs * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 104023 2002-09-26 22:54:00Z gibbs $ 4197883Sgibbs */ 42104023SgibbsVERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#45 $" 4397883Sgibbs 4497883Sgibbs/* 4597883Sgibbs * This file is processed by the aic7xxx_asm utility for use in assembling 4697883Sgibbs * firmware for the aic79xx family of SCSI host adapters as well as to generate 4797883Sgibbs * a C header file for use in the kernel portion of the Aic79xx driver. 4897883Sgibbs */ 4997883Sgibbs 5097883Sgibbs/* Register window Modes */ 5197883Sgibbs#define M_DFF0 0 5297883Sgibbs#define M_DFF1 1 5397883Sgibbs#define M_CCHAN 2 5497883Sgibbs#define M_SCSI 3 5597883Sgibbs#define M_CFG 4 5697883Sgibbs#define M_DST_SHIFT 4 5797883Sgibbs 5897883Sgibbs#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59104023Sgibbs#define SET_MODE(src, dst) \ 60104023Sgibbs SET_SRC_MODE src; \ 61104023Sgibbs SET_DST_MODE dst; \ 62104023Sgibbs if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63104023Sgibbs mvi MK_MODE(src, dst) call set_mode_work_around; \ 64104023Sgibbs } else { \ 65104023Sgibbs mvi MODE_PTR, MK_MODE(src, dst); \ 66104023Sgibbs } 6797883Sgibbs 68104023Sgibbs#define TOGGLE_DFF_MODE \ 69104023Sgibbs if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70104023Sgibbs call toggle_dff_mode_work_around; \ 71104023Sgibbs } else { \ 72104023Sgibbs xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \ 73104023Sgibbs } 74104023Sgibbs 75104023Sgibbs 7697883Sgibbs/* 7797883Sgibbs * Mode Pointer 7897883Sgibbs * Controls which of the 5, 512byte, address spaces should be used 7997883Sgibbs * as the source and destination of any register accesses in our 8097883Sgibbs * register window. 8197883Sgibbs */ 8297883Sgibbsregister MODE_PTR { 8397883Sgibbs address 0x000 8497883Sgibbs access_mode RW 85102681Sgibbs field DST_MODE 0x70 86102681Sgibbs field SRC_MODE 0x07 8797883Sgibbs mode_pointer 8897883Sgibbs} 8997883Sgibbs 9097883Sgibbsconst SRC_MODE_SHIFT 0 9197883Sgibbsconst DST_MODE_SHIFT 4 9297883Sgibbs 9397883Sgibbs/* 9497883Sgibbs * Host Interrupt Status 9597883Sgibbs */ 9697883Sgibbsregister INTSTAT { 9797883Sgibbs address 0x001 9897883Sgibbs access_mode RW 99102681Sgibbs field HWERRINT 0x80 100102681Sgibbs field BRKADRINT 0x40 101102681Sgibbs field SWTMINT 0x20 102102681Sgibbs field PCIINT 0x10 103102681Sgibbs field SCSIINT 0x08 104102681Sgibbs field SEQINT 0x04 105102681Sgibbs field CMDCMPLT 0x02 106102681Sgibbs field SPLTINT 0x01 10797883Sgibbs mask INT_PEND 0xFF 10897883Sgibbs} 10997883Sgibbs 11097883Sgibbs/* 11197883Sgibbs * Sequencer Interrupt Code 11297883Sgibbs */ 11397883Sgibbsregister SEQINTCODE { 11497883Sgibbs address 0x002 11597883Sgibbs access_mode RW 116102681Sgibbs field { 117102681Sgibbs BAD_PHASE 1, /* unknown scsi bus phase */ 118102681Sgibbs SEND_REJECT, /* sending a message reject */ 119102681Sgibbs PROTO_VIOLATION, /* Protocol Violation */ 120102681Sgibbs NO_MATCH, /* no cmd match for reconnect */ 121102681Sgibbs IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 122102681Sgibbs PDATA_REINIT, /* 12397883Sgibbs * Returned to data phase 12497883Sgibbs * that requires data 12597883Sgibbs * transfer pointers to be 12697883Sgibbs * recalculated from the 12797883Sgibbs * transfer residual. 12897883Sgibbs */ 129102681Sgibbs HOST_MSG_LOOP, /* 13097883Sgibbs * The bus is ready for the 13197883Sgibbs * host to perform another 13297883Sgibbs * message transaction. This 13397883Sgibbs * mechanism is used for things 13497883Sgibbs * like sync/wide negotiation 13597883Sgibbs * that require a kernel based 13697883Sgibbs * message state engine. 13797883Sgibbs */ 138102681Sgibbs BAD_STATUS, /* Bad status from target */ 139102681Sgibbs DATA_OVERRUN, /* 14097883Sgibbs * Target attempted to write 14197883Sgibbs * beyond the bounds of its 14297883Sgibbs * command. 14397883Sgibbs */ 144102681Sgibbs MKMSG_FAILED, /* 14597883Sgibbs * Target completed command 14697883Sgibbs * without honoring our ATN 14797883Sgibbs * request to issue a message. 14897883Sgibbs */ 149102681Sgibbs MISSED_BUSFREE, /* 15097883Sgibbs * The sequencer never saw 15197883Sgibbs * the bus go free after 15297883Sgibbs * either a command complete 15397883Sgibbs * or disconnect message. 15497883Sgibbs */ 155102681Sgibbs DUMP_CARD_STATE, 156102681Sgibbs ILLEGAL_PHASE, 157102681Sgibbs INVALID_SEQINT, 158102681Sgibbs CFG4ISTAT_INTR, 159102681Sgibbs STATUS_OVERRUN, 160102681Sgibbs CFG4OVERRUN, 161102681Sgibbs ENTERING_NONPACK 162102681Sgibbs } 16397883Sgibbs} 16497883Sgibbs 16597883Sgibbs/* 16697883Sgibbs * Clear Host Interrupt 16797883Sgibbs */ 16897883Sgibbsregister CLRINT { 16997883Sgibbs address 0x003 17097883Sgibbs access_mode WO 171102681Sgibbs field CLRHWERRINT 0x80 /* Rev B or greater */ 172102681Sgibbs field CLRBRKADRINT 0x40 173102681Sgibbs field CLRSWTMINT 0x20 174102681Sgibbs field CLRSCSIINT 0x08 175102681Sgibbs field CLRSEQINT 0x04 176102681Sgibbs field CLRCMDINT 0x02 177102681Sgibbs field CLRSPLTINT 0x01 17897883Sgibbs} 17997883Sgibbs 18097883Sgibbs/* 18197883Sgibbs * Error Register 18297883Sgibbs */ 18397883Sgibbsregister ERROR { 18497883Sgibbs address 0x004 18597883Sgibbs access_mode RO 186102681Sgibbs field CIOPARERR 0x80 187102681Sgibbs field CIOACCESFAIL 0x40 /* Rev B or greater */ 188102681Sgibbs field MPARERR 0x20 189102681Sgibbs field DPARERR 0x10 190102681Sgibbs field SQPARERR 0x08 191102681Sgibbs field ILLOPCODE 0x04 192102681Sgibbs field DSCTMOUT 0x02 19397883Sgibbs} 19497883Sgibbs 19597883Sgibbs/* 19697883Sgibbs * Clear Error 19797883Sgibbs */ 19897883Sgibbsregister CLRERR { 19997883Sgibbs address 0x004 20097883Sgibbs access_mode WO 201102681Sgibbs field CLRCIOPARERR 0x80 202102681Sgibbs field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 203102681Sgibbs field CLRMPARERR 0x20 204102681Sgibbs field CLRDPARERR 0x10 205102681Sgibbs field CLRSQPARERR 0x08 206102681Sgibbs field CLRILLOPCODE 0x04 207102681Sgibbs field CLRDSCTMOUT 0x02 20897883Sgibbs} 20997883Sgibbs 21097883Sgibbs/* 21197883Sgibbs * Host Control Register 21297883Sgibbs * Overall host control of the device. 21397883Sgibbs */ 21497883Sgibbsregister HCNTRL { 21597883Sgibbs address 0x005 21697883Sgibbs access_mode RW 217102681Sgibbs field SEQ_RESET 0x80 /* Rev B or greater */ 218102681Sgibbs field POWRDN 0x40 219102681Sgibbs field SWINT 0x10 220102681Sgibbs field SWTIMER_START_B 0x08 /* Rev B or greater */ 221102681Sgibbs field PAUSE 0x04 222102681Sgibbs field INTEN 0x02 223102681Sgibbs field CHIPRST 0x01 224102681Sgibbs field CHIPRSTACK 0x01 22597883Sgibbs} 22697883Sgibbs 22797883Sgibbs/* 22897883Sgibbs * Host New SCB Queue Offset 22997883Sgibbs */ 23097883Sgibbsregister HNSCB_QOFF { 23197883Sgibbs address 0x006 23297883Sgibbs access_mode RW 23397883Sgibbs size 2 23497883Sgibbs} 23597883Sgibbs 23697883Sgibbs/* 23797883Sgibbs * Host Empty SCB Queue Offset 23897883Sgibbs */ 23997883Sgibbsregister HESCB_QOFF { 24097883Sgibbs address 0x008 24197883Sgibbs access_mode RW 24297883Sgibbs} 24397883Sgibbs 24497883Sgibbs/* 24597883Sgibbs * Host Mailbox 24697883Sgibbs */ 24797883Sgibbsregister HS_MAILBOX { 24897883Sgibbs address 0x0B 24997883Sgibbs access_mode RW 25097883Sgibbs mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 25197883Sgibbs} 25297883Sgibbs 25397883Sgibbs/* 25497883Sgibbs * Sequencer Interupt Status 25597883Sgibbs */ 25697883Sgibbsregister SEQINTSTAT { 25797883Sgibbs address 0x0C 25897883Sgibbs access_mode RO 259102681Sgibbs field SEQ_SWTMRTO 0x10 260102681Sgibbs field SEQ_SEQINT 0x08 261102681Sgibbs field SEQ_SCSIINT 0x04 262102681Sgibbs field SEQ_PCIINT 0x02 263102681Sgibbs field SEQ_SPLTINT 0x01 26497883Sgibbs} 26597883Sgibbs 26697883Sgibbs/* 26797883Sgibbs * Clear SEQ Interrupt 26897883Sgibbs */ 26997883Sgibbsregister CLRSEQINTSTAT { 27097883Sgibbs address 0x0C0 27197883Sgibbs access_mode WO 272102681Sgibbs field CLRSEQ_SWTMRTO 0x10 273102681Sgibbs field CLRSEQ_SEQINT 0x08 274102681Sgibbs field CLRSEQ_SCSIINT 0x04 275102681Sgibbs field CLRSEQ_PCIINT 0x02 276102681Sgibbs field CLRSEQ_SPLTINT 0x01 27797883Sgibbs} 27897883Sgibbs 27997883Sgibbs/* 28097883Sgibbs * Software Timer 28197883Sgibbs */ 28297883Sgibbsregister SWTIMER { 28397883Sgibbs address 0x0E0 28497883Sgibbs access_mode RW 28597883Sgibbs size 2 28697883Sgibbs} 28797883Sgibbs 28897883Sgibbs/* 28997883Sgibbs * SEQ New SCB Queue Offset 29097883Sgibbs */ 29197883Sgibbsregister SNSCB_QOFF { 29297883Sgibbs address 0x010 29397883Sgibbs access_mode RW 29497883Sgibbs size 2 29597883Sgibbs modes M_CCHAN 29697883Sgibbs} 29797883Sgibbs 29897883Sgibbs/* 29997883Sgibbs * SEQ Empty SCB Queue Offset 30097883Sgibbs */ 30197883Sgibbsregister SESCB_QOFF { 30297883Sgibbs address 0x012 30397883Sgibbs access_mode RW 30497883Sgibbs modes M_CCHAN 30597883Sgibbs} 30697883Sgibbs 30797883Sgibbs/* 30897883Sgibbs * SEQ Done SCB Queue Offset 30997883Sgibbs */ 31097883Sgibbsregister SDSCB_QOFF { 31197883Sgibbs address 0x014 31297883Sgibbs access_mode RW 31397883Sgibbs modes M_CCHAN 31497883Sgibbs size 2 31597883Sgibbs} 31697883Sgibbs 31797883Sgibbs/* 31897883Sgibbs * Queue Offset Control & Status 31997883Sgibbs */ 32097883Sgibbsregister QOFF_CTLSTA { 32197883Sgibbs address 0x016 32297883Sgibbs access_mode RW 32397883Sgibbs modes M_CCHAN 324102681Sgibbs field EMPTY_SCB_AVAIL 0x80 325102681Sgibbs field NEW_SCB_AVAIL 0x40 326102681Sgibbs field SDSCB_ROLLOVR 0x20 327102681Sgibbs field HS_MAILBOX_ACT 0x10 328102681Sgibbs field SCB_QSIZE 0x0F { 329102681Sgibbs SCB_QSIZE_4, 330102681Sgibbs SCB_QSIZE_8, 331102681Sgibbs SCB_QSIZE_16, 332102681Sgibbs SCB_QSIZE_32, 333102681Sgibbs SCB_QSIZE_64, 334102681Sgibbs SCB_QSIZE_128, 335102681Sgibbs SCB_QSIZE_256, 336102681Sgibbs SCB_QSIZE_512, 337102681Sgibbs SCB_QSIZE_1024, 338102681Sgibbs SCB_QSIZE_2048, 339102681Sgibbs SCB_QSIZE_4096, 340102681Sgibbs SCB_QSIZE_8192, 341102681Sgibbs SCB_QSIZE_16384 342102681Sgibbs } 34397883Sgibbs} 34497883Sgibbs 34597883Sgibbs/* 34697883Sgibbs * Interrupt Control 34797883Sgibbs */ 34897883Sgibbsregister INTCTL { 34997883Sgibbs address 0x018 35097883Sgibbs access_mode RW 351102681Sgibbs field SWTMINTMASK 0x80 352102681Sgibbs field SWTMINTEN 0x40 353102681Sgibbs field SWTIMER_START 0x20 354102681Sgibbs field AUTOCLRCMDINT 0x10 355102681Sgibbs field PCIINTEN 0x08 356102681Sgibbs field SCSIINTEN 0x04 357102681Sgibbs field SEQINTEN 0x02 358102681Sgibbs field SPLTINTEN 0x01 35997883Sgibbs} 36097883Sgibbs 36197883Sgibbs/* 36297883Sgibbs * Data FIFO Control 36397883Sgibbs */ 36497883Sgibbsregister DFCNTRL { 36597883Sgibbs address 0x019 36697883Sgibbs access_mode RW 36797883Sgibbs modes M_DFF0, M_DFF1 368102681Sgibbs field PRELOADEN 0x80 369102681Sgibbs field SCSIEN 0x20 370102681Sgibbs field SCSIENACK 0x20 371102681Sgibbs field HDMAEN 0x08 372102681Sgibbs field HDMAENACK 0x08 373102681Sgibbs field DIRECTION 0x04 374102681Sgibbs field DIRECTIONACK 0x04 375102681Sgibbs field FIFOFLUSH 0x02 376102681Sgibbs field FIFOFLUSHACK 0x02 377102681Sgibbs field DIRECTIONEN 0x01 37897883Sgibbs} 37997883Sgibbs 38097883Sgibbs/* 38197883Sgibbs * Device Space Command 0 38297883Sgibbs */ 38397883Sgibbsregister DSCOMMAND0 { 38497883Sgibbs address 0x019 38597883Sgibbs access_mode RW 38697883Sgibbs modes M_CFG 387102681Sgibbs field CACHETHEN 0x80 /* Cache Threshold enable */ 388102681Sgibbs field DPARCKEN 0x40 /* Data Parity Check Enable */ 389102681Sgibbs field MPARCKEN 0x20 /* Memory Parity Check Enable */ 390102681Sgibbs field EXTREQLCK 0x10 /* External Request Lock */ 391102681Sgibbs field DISABLE_TWATE 0x02 /* Rev B or greater */ 392102681Sgibbs field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 39397883Sgibbs} 39497883Sgibbs 39597883Sgibbs/* 39697883Sgibbs * Data FIFO Status 39797883Sgibbs */ 39897883Sgibbsregister DFSTATUS { 39997883Sgibbs address 0x01A 40097883Sgibbs access_mode RO 40197883Sgibbs modes M_DFF0, M_DFF1 402102681Sgibbs field PRELOAD_AVAIL 0x80 403102681Sgibbs field PKT_PRELOAD_AVAIL 0x40 404102681Sgibbs field MREQPEND 0x10 405102681Sgibbs field HDONE 0x08 406102681Sgibbs field DFTHRESH 0x04 407102681Sgibbs field FIFOFULL 0x02 408102681Sgibbs field FIFOEMP 0x01 40997883Sgibbs} 41097883Sgibbs 41197883Sgibbs/* 41297883Sgibbs * S/G Cache Pointer 41397883Sgibbs */ 41497883Sgibbsregister SG_CACHE_PRE { 41597883Sgibbs address 0x01B 41697883Sgibbs access_mode WO 41797883Sgibbs modes M_DFF0, M_DFF1 418102681Sgibbs field SG_ADDR_MASK 0xf8 419102681Sgibbs field ODD_SEG 0x04 420102681Sgibbs field LAST_SEG 0x02 42197883Sgibbs} 42297883Sgibbs 42397883Sgibbsregister SG_CACHE_SHADOW { 42497883Sgibbs address 0x01B 42597883Sgibbs access_mode RO 42697883Sgibbs modes M_DFF0, M_DFF1 427102681Sgibbs field SG_ADDR_MASK 0xf8 428102681Sgibbs field ODD_SEG 0x04 429102681Sgibbs field LAST_SEG 0x02 430102681Sgibbs field LAST_SEG_DONE 0x01 43197883Sgibbs} 43297883Sgibbs 43397883Sgibbs/* 43497883Sgibbs * Arbiter Control 43597883Sgibbs */ 43697883Sgibbsregister ARBCTL { 43797883Sgibbs address 0x01B 43897883Sgibbs access_mode RW 43997883Sgibbs modes M_CFG 440102681Sgibbs field RESET_HARB 0x80 441102681Sgibbs field RETRY_SWEN 0x08 442102681Sgibbs field USE_TIME 0x07 44397883Sgibbs} 44497883Sgibbs 44597883Sgibbs/* 44697883Sgibbs * Data Channel Host Address 44797883Sgibbs */ 44897883Sgibbsregister HADDR { 44997883Sgibbs address 0x070 45097883Sgibbs access_mode RW 45197883Sgibbs size 8 45297883Sgibbs modes M_DFF0, M_DFF1 45397883Sgibbs} 45497883Sgibbs 45597883Sgibbs/* 45697883Sgibbs * Host Overlay DMA Address 45797883Sgibbs */ 45897883Sgibbsregister HODMAADR { 45997883Sgibbs address 0x070 46097883Sgibbs access_mode RW 46197883Sgibbs size 8 46297883Sgibbs modes M_SCSI 46397883Sgibbs} 46497883Sgibbs 46597883Sgibbs/* 46697883Sgibbs * Data Channel Host Count 46797883Sgibbs */ 46897883Sgibbsregister HCNT { 46997883Sgibbs address 0x078 47097883Sgibbs access_mode RW 47197883Sgibbs size 3 47297883Sgibbs modes M_DFF0, M_DFF1 47397883Sgibbs} 47497883Sgibbs 47597883Sgibbs/* 47697883Sgibbs * Host Overlay DMA Count 47797883Sgibbs */ 47897883Sgibbsregister HODMACNT { 47997883Sgibbs address 0x078 48097883Sgibbs access_mode RW 48197883Sgibbs size 2 48297883Sgibbs modes M_SCSI 48397883Sgibbs} 48497883Sgibbs 48597883Sgibbs/* 48697883Sgibbs * Host Overlay DMA Enable 48797883Sgibbs */ 48897883Sgibbsregister HODMAEN { 48997883Sgibbs address 0x07A 49097883Sgibbs access_mode RW 49197883Sgibbs modes M_SCSI 49297883Sgibbs} 49397883Sgibbs 49497883Sgibbs/* 49597883Sgibbs * Scatter/Gather Host Address 49697883Sgibbs */ 49797883Sgibbsregister SGHADDR { 49897883Sgibbs address 0x07C 49997883Sgibbs access_mode RW 50097883Sgibbs size 8 50197883Sgibbs modes M_DFF0, M_DFF1 50297883Sgibbs} 50397883Sgibbs 50497883Sgibbs/* 50597883Sgibbs * SCB Host Address 50697883Sgibbs */ 50797883Sgibbsregister SCBHADDR { 50897883Sgibbs address 0x07C 50997883Sgibbs access_mode RW 51097883Sgibbs size 8 51197883Sgibbs modes M_CCHAN 51297883Sgibbs} 51397883Sgibbs 51497883Sgibbs/* 51597883Sgibbs * Scatter/Gather Host Count 51697883Sgibbs */ 51797883Sgibbsregister SGHCNT { 51897883Sgibbs address 0x084 51997883Sgibbs access_mode RW 52097883Sgibbs modes M_DFF0, M_DFF1 52197883Sgibbs} 52297883Sgibbs 52397883Sgibbs/* 52497883Sgibbs * SCB Host Count 52597883Sgibbs */ 52697883Sgibbsregister SCBHCNT { 52797883Sgibbs address 0x084 52897883Sgibbs access_mode RW 52997883Sgibbs modes M_CCHAN 53097883Sgibbs} 53197883Sgibbs 53297883Sgibbs/* 53397883Sgibbs * Data FIFO Threshold 53497883Sgibbs */ 53597883Sgibbsregister DFF_THRSH { 53697883Sgibbs address 0x088 53797883Sgibbs access_mode RW 53897883Sgibbs modes M_CFG 539102681Sgibbs field WR_DFTHRSH 0x70 { 540102681Sgibbs WR_DFTHRSH_MIN, 541102681Sgibbs WR_DFTHRSH_25, 542102681Sgibbs WR_DFTHRSH_50, 543102681Sgibbs WR_DFTHRSH_63, 544102681Sgibbs WR_DFTHRSH_75, 545102681Sgibbs WR_DFTHRSH_85, 546102681Sgibbs WR_DFTHRSH_90, 547102681Sgibbs WR_DFTHRSH_MAX 548102681Sgibbs } 549102681Sgibbs field RD_DFTHRSH 0x07 { 550102681Sgibbs RD_DFTHRSH_MIN, 551102681Sgibbs RD_DFTHRSH_25, 552102681Sgibbs RD_DFTHRSH_50, 553102681Sgibbs RD_DFTHRSH_63, 554102681Sgibbs RD_DFTHRSH_75, 555102681Sgibbs RD_DFTHRSH_85, 556102681Sgibbs RD_DFTHRSH_90, 557102681Sgibbs RD_DFTHRSH_MAX 558102681Sgibbs } 55997883Sgibbs} 56097883Sgibbs 56197883Sgibbs/* 56297883Sgibbs * ROM Address 56397883Sgibbs */ 56497883Sgibbsregister ROMADDR { 56597883Sgibbs address 0x08A 56697883Sgibbs access_mode RW 56797883Sgibbs size 3 56897883Sgibbs} 56997883Sgibbs 57097883Sgibbs/* 57197883Sgibbs * ROM Control 57297883Sgibbs */ 57397883Sgibbsregister ROMCNTRL { 57497883Sgibbs address 0x08D 57597883Sgibbs access_mode RW 576102681Sgibbs field ROMOP 0xE0 577102681Sgibbs field ROMSPD 0x18 578102681Sgibbs field REPEAT 0x02 579102681Sgibbs field RDY 0x01 58097883Sgibbs} 58197883Sgibbs 58297883Sgibbs/* 58397883Sgibbs * ROM Data 58497883Sgibbs */ 58597883Sgibbsregister ROMDATA { 58697883Sgibbs address 0x08E 58797883Sgibbs access_mode RW 58897883Sgibbs} 58997883Sgibbs 59097883Sgibbs/* 59197883Sgibbs * Data Channel Receive Message 0 59297883Sgibbs */ 59397883Sgibbsregister DCHRXMSG0 { 59497883Sgibbs address 0x090 59597883Sgibbs access_mode RO 59697883Sgibbs modes M_DFF0, M_DFF1 597102681Sgibbs field CDNUM 0xF8 598102681Sgibbs field CFNUM 0x07 59997883Sgibbs} 60097883Sgibbs 60197883Sgibbs/* 60297883Sgibbs * CMC Recieve Message 0 60397883Sgibbs */ 60497883Sgibbsregister CMCRXMSG0 { 60597883Sgibbs address 0x090 60697883Sgibbs access_mode RO 60797883Sgibbs modes M_CCHAN 608102681Sgibbs field CDNUM 0xF8 609102681Sgibbs field CFNUM 0x07 61097883Sgibbs} 61197883Sgibbs 61297883Sgibbs/* 61397883Sgibbs * Overlay Recieve Message 0 61497883Sgibbs */ 61597883Sgibbsregister OVLYRXMSG0 { 61697883Sgibbs address 0x090 61797883Sgibbs access_mode RO 61897883Sgibbs modes M_SCSI 619102681Sgibbs field CDNUM 0xF8 620102681Sgibbs field CFNUM 0x07 62197883Sgibbs} 62297883Sgibbs 62397883Sgibbs/* 62497883Sgibbs * Relaxed Order Enable 62597883Sgibbs */ 62697883Sgibbsregister ROENABLE { 62797883Sgibbs address 0x090 62897883Sgibbs access_mode RW 62997883Sgibbs modes M_CFG 630102681Sgibbs field MSIROEN 0x20 631102681Sgibbs field OVLYROEN 0x10 632102681Sgibbs field CMCROEN 0x08 633102681Sgibbs field SGROEN 0x04 634102681Sgibbs field DCH1ROEN 0x02 635102681Sgibbs field DCH0ROEN 0x01 63697883Sgibbs} 63797883Sgibbs 63897883Sgibbs/* 63997883Sgibbs * Data Channel Receive Message 1 64097883Sgibbs */ 64197883Sgibbsregister DCHRXMSG1 { 64297883Sgibbs address 0x091 64397883Sgibbs access_mode RO 64497883Sgibbs modes M_DFF0, M_DFF1 645102681Sgibbs field CBNUM 0xFF 64697883Sgibbs} 64797883Sgibbs 64897883Sgibbs/* 64997883Sgibbs * CMC Recieve Message 1 65097883Sgibbs */ 65197883Sgibbsregister CMCRXMSG1 { 65297883Sgibbs address 0x091 65397883Sgibbs access_mode RO 65497883Sgibbs modes M_CCHAN 655102681Sgibbs field CBNUM 0xFF 65697883Sgibbs} 65797883Sgibbs 65897883Sgibbs/* 65997883Sgibbs * Overlay Recieve Message 1 66097883Sgibbs */ 66197883Sgibbsregister OVLYRXMSG1 { 66297883Sgibbs address 0x091 66397883Sgibbs access_mode RO 66497883Sgibbs modes M_SCSI 665102681Sgibbs field CBNUM 0xFF 66697883Sgibbs} 66797883Sgibbs 66897883Sgibbs/* 66997883Sgibbs * No Snoop Enable 67097883Sgibbs */ 67197883Sgibbsregister NSENABLE { 67297883Sgibbs address 0x091 67397883Sgibbs access_mode RW 67497883Sgibbs modes M_CFG 675102681Sgibbs field MSINSEN 0x20 676102681Sgibbs field OVLYNSEN 0x10 677102681Sgibbs field CMCNSEN 0x08 678102681Sgibbs field SGNSEN 0x04 679102681Sgibbs field DCH1NSEN 0x02 680102681Sgibbs field DCH0NSEN 0x01 68197883Sgibbs} 68297883Sgibbs 68397883Sgibbs/* 68497883Sgibbs * Data Channel Receive Message 2 68597883Sgibbs */ 68697883Sgibbsregister DCHRXMSG2 { 68797883Sgibbs address 0x092 68897883Sgibbs access_mode RO 68997883Sgibbs modes M_DFF0, M_DFF1 690102681Sgibbs field MINDEX 0xFF 69197883Sgibbs} 69297883Sgibbs 69397883Sgibbs/* 69497883Sgibbs * CMC Recieve Message 2 69597883Sgibbs */ 69697883Sgibbsregister CMCRXMSG2 { 69797883Sgibbs address 0x092 69897883Sgibbs access_mode RO 69997883Sgibbs modes M_CCHAN 700102681Sgibbs field MINDEX 0xFF 70197883Sgibbs} 70297883Sgibbs 70397883Sgibbs/* 70497883Sgibbs * Overlay Recieve Message 2 70597883Sgibbs */ 70697883Sgibbsregister OVLYRXMSG2 { 70797883Sgibbs address 0x092 70897883Sgibbs access_mode RO 70997883Sgibbs modes M_SCSI 710102681Sgibbs field MINDEX 0xFF 71197883Sgibbs} 71297883Sgibbs 71397883Sgibbs/* 71497883Sgibbs * Outstanding Split Transactions 71597883Sgibbs */ 71697883Sgibbsregister OST { 71797883Sgibbs address 0x092 71897883Sgibbs access_mode RW 71997883Sgibbs modes M_CFG 72097883Sgibbs} 72197883Sgibbs 72297883Sgibbs/* 72397883Sgibbs * Data Channel Receive Message 3 72497883Sgibbs */ 72597883Sgibbsregister DCHRXMSG3 { 72697883Sgibbs address 0x093 72797883Sgibbs access_mode RO 72897883Sgibbs modes M_DFF0, M_DFF1 729102681Sgibbs field MCLASS 0x0F 73097883Sgibbs} 73197883Sgibbs 73297883Sgibbs/* 73397883Sgibbs * CMC Recieve Message 3 73497883Sgibbs */ 73597883Sgibbsregister CMCRXMSG3 { 73697883Sgibbs address 0x093 73797883Sgibbs access_mode RO 73897883Sgibbs modes M_CCHAN 739102681Sgibbs field MCLASS 0x0F 74097883Sgibbs} 74197883Sgibbs 74297883Sgibbs/* 74397883Sgibbs * Overlay Recieve Message 3 74497883Sgibbs */ 74597883Sgibbsregister OVLYRXMSG3 { 74697883Sgibbs address 0x093 74797883Sgibbs access_mode RO 74897883Sgibbs modes M_SCSI 749102681Sgibbs field MCLASS 0x0F 75097883Sgibbs} 75197883Sgibbs 75297883Sgibbs/* 75397883Sgibbs * PCI-X Control 75497883Sgibbs */ 75597883Sgibbsregister PCIXCTL { 75697883Sgibbs address 0x093 75797883Sgibbs access_mode RW 75897883Sgibbs modes M_CFG 759102681Sgibbs field SERRPULSE 0x80 760102681Sgibbs field UNEXPSCIEN 0x20 761102681Sgibbs field SPLTSMADIS 0x10 762102681Sgibbs field SPLTSTADIS 0x08 763102681Sgibbs field SRSPDPEEN 0x04 764102681Sgibbs field TSCSERREN 0x02 765102681Sgibbs field CMPABCDIS 0x01 76697883Sgibbs} 76797883Sgibbs 76897883Sgibbs/* 76997883Sgibbs * CMC Sequencer Byte Count 77097883Sgibbs */ 77197883Sgibbsregister CMCSEQBCNT { 77297883Sgibbs address 0x094 77397883Sgibbs access_mode RO 77497883Sgibbs modes M_CCHAN 77597883Sgibbs} 77697883Sgibbs 77797883Sgibbs/* 77897883Sgibbs * Overlay Sequencer Byte Count 77997883Sgibbs */ 78097883Sgibbsregister OVLYSEQBCNT { 78197883Sgibbs address 0x094 78297883Sgibbs access_mode RO 78397883Sgibbs modes M_SCSI 78497883Sgibbs} 78597883Sgibbs 78697883Sgibbs/* 78797883Sgibbs * Data Channel Sequencer Byte Count 78897883Sgibbs */ 78997883Sgibbsregister DCHSEQBCNT { 79097883Sgibbs address 0x094 79197883Sgibbs access_mode RO 79297883Sgibbs size 2 79397883Sgibbs modes M_DFF0, M_DFF1 79497883Sgibbs} 79597883Sgibbs 79697883Sgibbs/* 79797883Sgibbs * Data Channel Split Status 0 79897883Sgibbs */ 79997883Sgibbsregister DCHSPLTSTAT0 { 80097883Sgibbs address 0x096 80197883Sgibbs access_mode RW 80297883Sgibbs modes M_DFF0, M_DFF1 803102681Sgibbs field STAETERM 0x80 804102681Sgibbs field SCBCERR 0x40 805102681Sgibbs field SCADERR 0x20 806102681Sgibbs field SCDATBUCKET 0x10 807102681Sgibbs field CNTNOTCMPLT 0x08 808102681Sgibbs field RXOVRUN 0x04 809102681Sgibbs field RXSCEMSG 0x02 810102681Sgibbs field RXSPLTRSP 0x01 81197883Sgibbs} 81297883Sgibbs 81397883Sgibbs/* 81497883Sgibbs * CMC Split Status 0 81597883Sgibbs */ 81697883Sgibbsregister CMCSPLTSTAT0 { 81797883Sgibbs address 0x096 81897883Sgibbs access_mode RW 81997883Sgibbs modes M_CCHAN 820102681Sgibbs field STAETERM 0x80 821102681Sgibbs field SCBCERR 0x40 822102681Sgibbs field SCADERR 0x20 823102681Sgibbs field SCDATBUCKET 0x10 824102681Sgibbs field CNTNOTCMPLT 0x08 825102681Sgibbs field RXOVRUN 0x04 826102681Sgibbs field RXSCEMSG 0x02 827102681Sgibbs field RXSPLTRSP 0x01 82897883Sgibbs} 82997883Sgibbs 83097883Sgibbs/* 83197883Sgibbs * Overlay Split Status 0 83297883Sgibbs */ 83397883Sgibbsregister OVLYSPLTSTAT0 { 83497883Sgibbs address 0x096 83597883Sgibbs access_mode RW 83697883Sgibbs modes M_SCSI 837102681Sgibbs field STAETERM 0x80 838102681Sgibbs field SCBCERR 0x40 839102681Sgibbs field SCADERR 0x20 840102681Sgibbs field SCDATBUCKET 0x10 841102681Sgibbs field CNTNOTCMPLT 0x08 842102681Sgibbs field RXOVRUN 0x04 843102681Sgibbs field RXSCEMSG 0x02 844102681Sgibbs field RXSPLTRSP 0x01 84597883Sgibbs} 84697883Sgibbs 84797883Sgibbs/* 84897883Sgibbs * Data Channel Split Status 1 84997883Sgibbs */ 85097883Sgibbsregister DCHSPLTSTAT1 { 85197883Sgibbs address 0x097 85297883Sgibbs access_mode RW 85397883Sgibbs modes M_DFF0, M_DFF1 854102681Sgibbs field RXDATABUCKET 0x01 85597883Sgibbs} 85697883Sgibbs 85797883Sgibbs/* 85897883Sgibbs * CMC Split Status 1 85997883Sgibbs */ 86097883Sgibbsregister CMCSPLTSTAT1 { 86197883Sgibbs address 0x097 86297883Sgibbs access_mode RW 86397883Sgibbs modes M_CCHAN 864102681Sgibbs field RXDATABUCKET 0x01 86597883Sgibbs} 86697883Sgibbs 86797883Sgibbs/* 86897883Sgibbs * Overlay Split Status 1 86997883Sgibbs */ 87097883Sgibbsregister OVLYSPLTSTAT1 { 87197883Sgibbs address 0x097 87297883Sgibbs access_mode RW 87397883Sgibbs modes M_SCSI 874102681Sgibbs field RXDATABUCKET 0x01 87597883Sgibbs} 87697883Sgibbs 87797883Sgibbs/* 87897883Sgibbs * S/G Receive Message 0 87997883Sgibbs */ 88097883Sgibbsregister SGRXMSG0 { 88197883Sgibbs address 0x098 88297883Sgibbs access_mode RO 88397883Sgibbs modes M_DFF0, M_DFF1 884102681Sgibbs field CDNUM 0xF8 885102681Sgibbs field CFNUM 0x07 88697883Sgibbs} 88797883Sgibbs 88897883Sgibbs/* 88997883Sgibbs * S/G Receive Message 1 89097883Sgibbs */ 89197883Sgibbsregister SGRXMSG1 { 89297883Sgibbs address 0x099 89397883Sgibbs access_mode RO 89497883Sgibbs modes M_DFF0, M_DFF1 895102681Sgibbs field CBNUM 0xFF 89697883Sgibbs} 89797883Sgibbs 89897883Sgibbs/* 89997883Sgibbs * S/G Receive Message 2 90097883Sgibbs */ 90197883Sgibbsregister SGRXMSG2 { 90297883Sgibbs address 0x09A 90397883Sgibbs access_mode RO 90497883Sgibbs modes M_DFF0, M_DFF1 905102681Sgibbs field MINDEX 0xFF 90697883Sgibbs} 90797883Sgibbs 90897883Sgibbs/* 90997883Sgibbs * S/G Receive Message 3 91097883Sgibbs */ 91197883Sgibbsregister SGRXMSG3 { 91297883Sgibbs address 0x09B 91397883Sgibbs access_mode RO 91497883Sgibbs modes M_DFF0, M_DFF1 915102681Sgibbs field MCLASS 0x0F 91697883Sgibbs} 91797883Sgibbs 91897883Sgibbs/* 91997883Sgibbs * Slave Split Out Address 0 92097883Sgibbs */ 92197883Sgibbsregister SLVSPLTOUTADR0 { 92297883Sgibbs address 0x098 92397883Sgibbs access_mode RO 92497883Sgibbs modes M_SCSI 925102681Sgibbs field LOWER_ADDR 0x7F 92697883Sgibbs} 92797883Sgibbs 92897883Sgibbs/* 92997883Sgibbs * Slave Split Out Address 1 93097883Sgibbs */ 93197883Sgibbsregister SLVSPLTOUTADR1 { 93297883Sgibbs address 0x099 93397883Sgibbs access_mode RO 93497883Sgibbs modes M_SCSI 935102681Sgibbs field REQ_DNUM 0xF8 936102681Sgibbs field REQ_FNUM 0x07 93797883Sgibbs} 93897883Sgibbs 93997883Sgibbs/* 94097883Sgibbs * Slave Split Out Address 2 94197883Sgibbs */ 94297883Sgibbsregister SLVSPLTOUTADR2 { 94397883Sgibbs address 0x09A 94497883Sgibbs access_mode RO 94597883Sgibbs modes M_SCSI 946102681Sgibbs field REQ_BNUM 0xFF 94797883Sgibbs} 94897883Sgibbs 94997883Sgibbs/* 95097883Sgibbs * Slave Split Out Address 3 95197883Sgibbs */ 95297883Sgibbsregister SLVSPLTOUTADR3 { 95397883Sgibbs address 0x09B 95497883Sgibbs access_mode RO 95597883Sgibbs modes M_SCSI 956102681Sgibbs field RLXORD 020 957102681Sgibbs field TAG_NUM 0x1F 95897883Sgibbs} 95997883Sgibbs 96097883Sgibbs/* 96197883Sgibbs * SG Sequencer Byte Count 96297883Sgibbs */ 96397883Sgibbsregister SGSEQBCNT { 96497883Sgibbs address 0x09C 96597883Sgibbs access_mode RO 96697883Sgibbs modes M_DFF0, M_DFF1 96797883Sgibbs} 96897883Sgibbs 96997883Sgibbs/* 97097883Sgibbs * Slave Split Out Attribute 0 97197883Sgibbs */ 97297883Sgibbsregister SLVSPLTOUTATTR0 { 97397883Sgibbs address 0x09C 97497883Sgibbs access_mode RO 97597883Sgibbs modes M_SCSI 976102681Sgibbs field LOWER_BCNT 0xFF 97797883Sgibbs} 97897883Sgibbs 97997883Sgibbs/* 98097883Sgibbs * Slave Split Out Attribute 1 98197883Sgibbs */ 98297883Sgibbsregister SLVSPLTOUTATTR1 { 98397883Sgibbs address 0x09D 98497883Sgibbs access_mode RO 98597883Sgibbs modes M_SCSI 986102681Sgibbs field CMPLT_DNUM 0xF8 987102681Sgibbs field CMPLT_FNUM 0x07 98897883Sgibbs} 98997883Sgibbs 99097883Sgibbs/* 99197883Sgibbs * Slave Split Out Attribute 2 99297883Sgibbs */ 99397883Sgibbsregister SLVSPLTOUTATTR2 { 99497883Sgibbs address 0x09E 99597883Sgibbs access_mode RO 99697883Sgibbs size 2 99797883Sgibbs modes M_SCSI 998102681Sgibbs field CMPLT_BNUM 0xFF 99997883Sgibbs} 100097883Sgibbs/* 100197883Sgibbs * S/G Split Status 0 100297883Sgibbs */ 100397883Sgibbsregister SGSPLTSTAT0 { 100497883Sgibbs address 0x09E 100597883Sgibbs access_mode RW 100697883Sgibbs modes M_DFF0, M_DFF1 1007102681Sgibbs field STAETERM 0x80 1008102681Sgibbs field SCBCERR 0x40 1009102681Sgibbs field SCADERR 0x20 1010102681Sgibbs field SCDATBUCKET 0x10 1011102681Sgibbs field CNTNOTCMPLT 0x08 1012102681Sgibbs field RXOVRUN 0x04 1013102681Sgibbs field RXSCEMSG 0x02 1014102681Sgibbs field RXSPLTRSP 0x01 101597883Sgibbs} 101697883Sgibbs 101797883Sgibbs/* 101897883Sgibbs * S/G Split Status 1 101997883Sgibbs */ 102097883Sgibbsregister SGSPLTSTAT1 { 102197883Sgibbs address 0x09F 102297883Sgibbs access_mode RW 102397883Sgibbs modes M_DFF0, M_DFF1 1024102681Sgibbs field RXDATABUCKET 0x01 102597883Sgibbs} 102697883Sgibbs 102797883Sgibbs/* 102897883Sgibbs * Special Function 102997883Sgibbs */ 103097883Sgibbsregister SFUNCT { 103197883Sgibbs address 0x09f 103297883Sgibbs access_mode RW 103397883Sgibbs modes M_CFG 1034102681Sgibbs field TEST_GROUP 0xF0 1035102681Sgibbs field TEST_NUM 0x0F 103697883Sgibbs} 103797883Sgibbs 103897883Sgibbs/* 103997883Sgibbs * Data FIFO 0 PCI Status 104097883Sgibbs */ 104197883Sgibbsregister DF0PCISTAT { 104297883Sgibbs address 0x0A0 104397883Sgibbs access_mode RW 104497883Sgibbs modes M_CFG 1045102681Sgibbs field DPE 0x80 1046102681Sgibbs field SSE 0x40 1047102681Sgibbs field RMA 0x20 1048102681Sgibbs field RTA 0x10 1049102681Sgibbs field SCAAPERR 0x08 1050102681Sgibbs field RDPERR 0x04 1051102681Sgibbs field TWATERR 0x02 1052102681Sgibbs field DPR 0x01 105397883Sgibbs} 105497883Sgibbs 105597883Sgibbs/* 105697883Sgibbs * Data FIFO 1 PCI Status 105797883Sgibbs */ 105897883Sgibbsregister DF1PCISTAT { 105997883Sgibbs address 0x0A1 106097883Sgibbs access_mode RW 106197883Sgibbs modes M_CFG 1062102681Sgibbs field DPE 0x80 1063102681Sgibbs field SSE 0x40 1064102681Sgibbs field RMA 0x20 1065102681Sgibbs field RTA 0x10 1066102681Sgibbs field SCAAPERR 0x08 1067102681Sgibbs field RDPERR 0x04 1068102681Sgibbs field TWATERR 0x02 1069102681Sgibbs field DPR 0x01 107097883Sgibbs} 107197883Sgibbs 107297883Sgibbs/* 107397883Sgibbs * S/G PCI Status 107497883Sgibbs */ 107597883Sgibbsregister SGPCISTAT { 107697883Sgibbs address 0x0A2 107797883Sgibbs access_mode RW 107897883Sgibbs modes M_CFG 1079102681Sgibbs field DPE 0x80 1080102681Sgibbs field SSE 0x40 1081102681Sgibbs field RMA 0x20 1082102681Sgibbs field RTA 0x10 1083102681Sgibbs field SCAAPERR 0x08 1084102681Sgibbs field RDPERR 0x04 1085102681Sgibbs field DPR 0x01 108697883Sgibbs} 108797883Sgibbs 108897883Sgibbs/* 108997883Sgibbs * CMC PCI Status 109097883Sgibbs */ 109197883Sgibbsregister CMCPCISTAT { 109297883Sgibbs address 0x0A3 109397883Sgibbs access_mode RW 109497883Sgibbs modes M_CFG 1095102681Sgibbs field DPE 0x80 1096102681Sgibbs field SSE 0x40 1097102681Sgibbs field RMA 0x20 1098102681Sgibbs field RTA 0x10 1099102681Sgibbs field SCAAPERR 0x08 1100102681Sgibbs field RDPERR 0x04 1101102681Sgibbs field TWATERR 0x02 1102102681Sgibbs field DPR 0x01 110397883Sgibbs} 110497883Sgibbs 110597883Sgibbs/* 110697883Sgibbs * Overlay PCI Status 110797883Sgibbs */ 110897883Sgibbsregister OVLYPCISTAT { 110997883Sgibbs address 0x0A4 111097883Sgibbs access_mode RW 111197883Sgibbs modes M_CFG 1112102681Sgibbs field DPE 0x80 1113102681Sgibbs field SSE 0x40 1114102681Sgibbs field RMA 0x20 1115102681Sgibbs field RTA 0x10 1116102681Sgibbs field SCAAPERR 0x08 1117102681Sgibbs field RDPERR 0x04 1118102681Sgibbs field DPR 0x01 111997883Sgibbs} 112097883Sgibbs 112197883Sgibbs/* 112297883Sgibbs * PCI Status for MSI Master DMA Transfer 112397883Sgibbs */ 112497883Sgibbsregister MSIPCISTAT { 112597883Sgibbs address 0x0A6 112697883Sgibbs access_mode RW 112797883Sgibbs modes M_CFG 1128102681Sgibbs field SSE 0x40 1129102681Sgibbs field RMA 0x20 1130102681Sgibbs field RTA 0x10 1131102681Sgibbs field CLRPENDMSI 0x08 1132102681Sgibbs field TWATERR 0x02 1133102681Sgibbs field DPR 0x01 113497883Sgibbs} 113597883Sgibbs 113697883Sgibbs/* 113797883Sgibbs * PCI Status for Target 113897883Sgibbs */ 113997883Sgibbsregister TARGPCISTAT { 114097883Sgibbs address 0x0A6 114197883Sgibbs access_mode RW 114297883Sgibbs modes M_CFG 1143102681Sgibbs field DPE 0x80 1144102681Sgibbs field SSE 0x40 1145102681Sgibbs field STA 0x08 1146102681Sgibbs field TWATERR 0x02 114797883Sgibbs} 114897883Sgibbs 114997883Sgibbs/* 115097883Sgibbs * LQ Packet In 115197883Sgibbs * The last LQ Packet recieved 115297883Sgibbs */ 115397883Sgibbsregister LQIN { 115497883Sgibbs address 0x020 115597883Sgibbs access_mode RW 115697883Sgibbs size 20 115797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 115897883Sgibbs} 115997883Sgibbs 116097883Sgibbs/* 116197883Sgibbs * SCB Type Pointer 116297883Sgibbs * SCB offset for Target Mode SCB type information 116397883Sgibbs */ 116497883Sgibbsregister TYPEPTR { 116597883Sgibbs address 0x020 116697883Sgibbs access_mode RW 116797883Sgibbs modes M_CFG 116897883Sgibbs} 116997883Sgibbs 117097883Sgibbs/* 117197883Sgibbs * Queue Tag Pointer 117297883Sgibbs * SCB offset to the Two Byte tag identifier used for target mode. 117397883Sgibbs */ 117497883Sgibbsregister TAGPTR { 117597883Sgibbs address 0x021 117697883Sgibbs access_mode RW 117797883Sgibbs modes M_CFG 117897883Sgibbs} 117997883Sgibbs 118097883Sgibbs/* 118197883Sgibbs * Logical Unit Number Pointer 118297883Sgibbs * SCB offset to the LSB (little endian) of the lun field. 118397883Sgibbs */ 118497883Sgibbsregister LUNPTR { 118597883Sgibbs address 0x022 118697883Sgibbs access_mode RW 118797883Sgibbs modes M_CFG 118897883Sgibbs} 118997883Sgibbs 119097883Sgibbs/* 119197883Sgibbs * Data Length Pointer 119297883Sgibbs * SCB offset for the 4 byte data length field in target mode. 119397883Sgibbs */ 119497883Sgibbsregister DATALENPTR { 119597883Sgibbs address 0x023 119697883Sgibbs access_mode RW 119797883Sgibbs modes M_CFG 119897883Sgibbs} 119997883Sgibbs 120097883Sgibbs/* 120197883Sgibbs * Status Length Pointer 120297883Sgibbs * SCB offset to the two byte status field in target SCBs. 120397883Sgibbs */ 120497883Sgibbsregister STATLENPTR { 120597883Sgibbs address 0x024 120697883Sgibbs access_mode RW 120797883Sgibbs modes M_CFG 120897883Sgibbs} 120997883Sgibbs 121097883Sgibbs/* 121197883Sgibbs * Command Length Pointer 121297883Sgibbs * Scb offset for the CDB length field in initiator SCBs. 121397883Sgibbs */ 121497883Sgibbsregister CMDLENPTR { 121597883Sgibbs address 0x025 121697883Sgibbs access_mode RW 121797883Sgibbs modes M_CFG 121897883Sgibbs} 121997883Sgibbs 122097883Sgibbs/* 122197883Sgibbs * Task Attribute Pointer 122297883Sgibbs * Scb offset for the byte field specifying the attribute byte 122397883Sgibbs * to be used in command packets. 122497883Sgibbs */ 122597883Sgibbsregister ATTRPTR { 122697883Sgibbs address 0x026 122797883Sgibbs access_mode RW 122897883Sgibbs modes M_CFG 122997883Sgibbs} 123097883Sgibbs 123197883Sgibbs/* 123297883Sgibbs * Task Management Flags Pointer 123397883Sgibbs * Scb offset for the byte field specifying the attribute flags 123497883Sgibbs * byte to be used in command packets. 123597883Sgibbs */ 123697883Sgibbsregister FLAGPTR { 123797883Sgibbs address 0x027 123897883Sgibbs access_mode RW 123997883Sgibbs modes M_CFG 124097883Sgibbs} 124197883Sgibbs 124297883Sgibbs/* 124397883Sgibbs * Command Pointer 124497883Sgibbs * Scb offset for the first byte in the CDB for initiator SCBs. 124597883Sgibbs */ 124697883Sgibbsregister CMDPTR { 124797883Sgibbs address 0x028 124897883Sgibbs access_mode RW 124997883Sgibbs modes M_CFG 125097883Sgibbs} 125197883Sgibbs 125297883Sgibbs/* 125397883Sgibbs * Queue Next Pointer 125497883Sgibbs * Scb offset for the 2 byte "next scb link". 125597883Sgibbs */ 125697883Sgibbsregister QNEXTPTR { 125797883Sgibbs address 0x029 125897883Sgibbs access_mode RW 125997883Sgibbs modes M_CFG 126097883Sgibbs} 126197883Sgibbs 126297883Sgibbs/* 126397883Sgibbs * SCSI ID Pointer 126497883Sgibbs * Scb offset to the value to place in the SCSIID register 126597883Sgibbs * during target mode connections. 126697883Sgibbs */ 126797883Sgibbsregister IDPTR { 126897883Sgibbs address 0x02A 126997883Sgibbs access_mode RW 127097883Sgibbs modes M_CFG 127197883Sgibbs} 127297883Sgibbs 127397883Sgibbs/* 127497883Sgibbs * Command Aborted Byte Pointer 127597883Sgibbs * Offset to the SCB flags field that includes the 127697883Sgibbs * "SCB aborted" status bit. 127797883Sgibbs */ 127897883Sgibbsregister ABRTBYTEPTR { 127997883Sgibbs address 0x02B 128097883Sgibbs access_mode RW 128197883Sgibbs modes M_CFG 128297883Sgibbs} 128397883Sgibbs 128497883Sgibbs/* 128597883Sgibbs * Command Aborted Bit Pointer 128697883Sgibbs * Bit offset in the SCB flags field for "SCB aborted" status. 128797883Sgibbs */ 128897883Sgibbsregister ABRTBITPTR { 128997883Sgibbs address 0x02C 129097883Sgibbs access_mode RW 129197883Sgibbs modes M_CFG 129297883Sgibbs} 129397883Sgibbs 129497883Sgibbs/* 1295102681Sgibbs * Rev B or greater. 1296102681Sgibbs */ 1297102681Sgibbsregister MAXCMDBYTES { 1298102681Sgibbs address 0x02D 1299102681Sgibbs access_mode RW 1300102681Sgibbs modes M_CFG 1301102681Sgibbs} 1302102681Sgibbs 1303102681Sgibbs/* 1304102681Sgibbs * Rev B or greater. 1305102681Sgibbs */ 1306102681Sgibbsregister MAXCMD2RCV { 1307102681Sgibbs address 0x02E 1308102681Sgibbs access_mode RW 1309102681Sgibbs modes M_CFG 1310102681Sgibbs} 1311102681Sgibbs 1312102681Sgibbs/* 1313102681Sgibbs * Rev B or greater. 1314102681Sgibbs */ 1315102681Sgibbsregister SHORTTHRESH { 1316102681Sgibbs address 0x02F 1317102681Sgibbs access_mode RW 1318102681Sgibbs modes M_CFG 1319102681Sgibbs} 1320102681Sgibbs 1321102681Sgibbs/* 132297883Sgibbs * Logical Unit Number Length 132397883Sgibbs * The length, in bytes, of the SCB lun field. 132497883Sgibbs */ 132597883Sgibbsregister LUNLEN { 132697883Sgibbs address 0x030 132797883Sgibbs access_mode RW 132897883Sgibbs modes M_CFG 132997883Sgibbs} 133097883Sgibbs 133197883Sgibbs/* 133297883Sgibbs * CDB Limit 133397883Sgibbs * The size, in bytes, of the embedded CDB field in initator SCBs. 133497883Sgibbs */ 133597883Sgibbsregister CDBLIMIT { 133697883Sgibbs address 0x031 133797883Sgibbs access_mode RW 133897883Sgibbs modes M_CFG 133997883Sgibbs} 134097883Sgibbs 134197883Sgibbs/* 134297883Sgibbs * Maximum Commands 134397883Sgibbs * The maximum number of commands to issue during a 134497883Sgibbs * single packetized connection. 134597883Sgibbs */ 134697883Sgibbsregister MAXCMD { 134797883Sgibbs address 0x032 134897883Sgibbs access_mode RW 134997883Sgibbs modes M_CFG 135097883Sgibbs} 135197883Sgibbs 135297883Sgibbs/* 135397883Sgibbs * Maximum Command Counter 135497883Sgibbs * The number of commands already sent during this connection 135597883Sgibbs */ 135697883Sgibbsregister MAXCMDCNT { 135797883Sgibbs address 0x033 135897883Sgibbs access_mode RW 135997883Sgibbs modes M_CFG 136097883Sgibbs} 136197883Sgibbs 136297883Sgibbs/* 136397883Sgibbs * LQ Packet Reserved Bytes 136497883Sgibbs * The bytes to be sent in the currently reserved fileds 136597883Sgibbs * of all LQ packets. 136697883Sgibbs */ 136797883Sgibbsregister LQRSVD01 { 136897883Sgibbs address 0x034 136997883Sgibbs access_mode RW 137097883Sgibbs modes M_SCSI 137197883Sgibbs} 137297883Sgibbsregister LQRSVD16 { 137397883Sgibbs address 0x035 137497883Sgibbs access_mode RW 137597883Sgibbs modes M_SCSI 137697883Sgibbs} 137797883Sgibbsregister LQRSVD17 { 137897883Sgibbs address 0x036 137997883Sgibbs access_mode RW 138097883Sgibbs modes M_SCSI 138197883Sgibbs} 138297883Sgibbs 138397883Sgibbs/* 138497883Sgibbs * Command Reserved 0 138597883Sgibbs * The byte to be sent for the reserved byte 0 of 138697883Sgibbs * outgoing command packets. 138797883Sgibbs */ 138897883Sgibbsregister CMDRSVD0 { 138997883Sgibbs address 0x037 139097883Sgibbs access_mode RW 139197883Sgibbs modes M_CFG 139297883Sgibbs} 139397883Sgibbs 139497883Sgibbs/* 139597883Sgibbs * LQ Manager Control 0 139697883Sgibbs */ 139797883Sgibbsregister LQCTL0 { 139897883Sgibbs address 0x038 139997883Sgibbs access_mode RW 140097883Sgibbs modes M_CFG 1401102681Sgibbs field LQITARGCLT 0xC0 1402102681Sgibbs field LQIINITGCLT 0x30 1403102681Sgibbs field LQ0TARGCLT 0x0C 1404102681Sgibbs field LQ0INITGCLT 0x03 140597883Sgibbs} 140697883Sgibbs 140797883Sgibbs/* 140897883Sgibbs * LQ Manager Control 1 140997883Sgibbs */ 141097883Sgibbsregister LQCTL1 { 141197883Sgibbs address 0x038 141297883Sgibbs access_mode RW 141397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1414102681Sgibbs field PCI2PCI 0x04 1415102681Sgibbs field SINGLECMD 0x02 1416102681Sgibbs field ABORTPENDING 0x01 141797883Sgibbs} 141897883Sgibbs 141997883Sgibbs/* 142097883Sgibbs * LQ Manager Control 2 142197883Sgibbs */ 142297883Sgibbsregister LQCTL2 { 142397883Sgibbs address 0x039 142497883Sgibbs access_mode RW 142597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1426102681Sgibbs field LQIRETRY 0x80 1427102681Sgibbs field LQICONTINUE 0x40 1428102681Sgibbs field LQITOIDLE 0x20 1429102681Sgibbs field LQIPAUSE 0x10 1430102681Sgibbs field LQORETRY 0x08 1431102681Sgibbs field LQOCONTINUE 0x04 1432102681Sgibbs field LQOTOIDLE 0x02 1433102681Sgibbs field LQOPAUSE 0x01 143497883Sgibbs} 143597883Sgibbs 143697883Sgibbs/* 143797883Sgibbs * SCSI RAM BIST0 143897883Sgibbs */ 143997883Sgibbsregister SCSBIST0 { 144097883Sgibbs address 0x039 144197883Sgibbs access_mode RW 144297883Sgibbs modes M_CFG 1443102681Sgibbs field GSBISTERR 0x40 1444102681Sgibbs field GSBISTDONE 0x20 1445102681Sgibbs field GSBISTRUN 0x10 1446102681Sgibbs field OSBISTERR 0x04 1447102681Sgibbs field OSBISTDONE 0x02 1448102681Sgibbs field OSBISTRUN 0x01 144997883Sgibbs} 145097883Sgibbs 145197883Sgibbs/* 145297883Sgibbs * SCSI Sequence Control0 145397883Sgibbs */ 145497883Sgibbsregister SCSISEQ0 { 145597883Sgibbs address 0x03A 145697883Sgibbs access_mode RW 145797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1458102681Sgibbs field TEMODEO 0x80 1459102681Sgibbs field ENSELO 0x40 1460102681Sgibbs field ENARBO 0x20 1461102681Sgibbs field FORCEBUSFREE 0x10 1462102681Sgibbs field SCSIRSTO 0x01 146397883Sgibbs} 146497883Sgibbs 146597883Sgibbs/* 146697883Sgibbs * SCSI RAM BIST 1 146797883Sgibbs */ 146897883Sgibbsregister SCSBIST1 { 146997883Sgibbs address 0x03A 147097883Sgibbs access_mode RW 147197883Sgibbs modes M_CFG 1472102681Sgibbs field NTBISTERR 0x04 1473102681Sgibbs field NTBISTDONE 0x02 1474102681Sgibbs field NTBISTRUN 0x01 147597883Sgibbs} 147697883Sgibbs 147797883Sgibbs/* 147897883Sgibbs * SCSI Sequence Control 1 147997883Sgibbs */ 148097883Sgibbsregister SCSISEQ1 { 148197883Sgibbs address 0x03B 148297883Sgibbs access_mode RW 148397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1484102681Sgibbs field MANUALCTL 0x40 1485102681Sgibbs field ENSELI 0x20 1486102681Sgibbs field ENRSELI 0x10 1487102681Sgibbs field MANUALP 0x0C 1488102681Sgibbs field ENAUTOATNP 0x02 1489102681Sgibbs field ALTSTIM 0x01 149097883Sgibbs} 149197883Sgibbs 149297883Sgibbs/* 149397883Sgibbs * SCSI Transfer Control 0 149497883Sgibbs */ 149597883Sgibbsregister SXFRCTL0 { 149697883Sgibbs address 0x03C 149797883Sgibbs access_mode RW 149897883Sgibbs modes M_SCSI 1499102681Sgibbs field DFON 0x80 1500102681Sgibbs field DFPEXP 0x40 1501102681Sgibbs field BIOSCANCELEN 0x10 1502102681Sgibbs field SPIOEN 0x08 150397883Sgibbs} 150497883Sgibbs 150597883Sgibbs/* 150697883Sgibbs * SCSI Transfer Control 1 150797883Sgibbs */ 150897883Sgibbsregister SXFRCTL1 { 150997883Sgibbs address 0x03D 151097883Sgibbs access_mode RW 151197883Sgibbs modes M_SCSI 1512102681Sgibbs field BITBUCKET 0x80 1513102681Sgibbs field ENSACHK 0x40 1514102681Sgibbs field ENSPCHK 0x20 1515102681Sgibbs field STIMESEL 0x18 1516102681Sgibbs field ENSTIMER 0x04 1517102681Sgibbs field ACTNEGEN 0x02 1518102681Sgibbs field STPWEN 0x01 151997883Sgibbs} 152097883Sgibbs 152197883Sgibbs/* 152297883Sgibbs * SCSI Transfer Control 2 152397883Sgibbs */ 152497883Sgibbsregister SXFRCTL2 { 152597883Sgibbs address 0x03E 152697883Sgibbs access_mode RW 152797883Sgibbs modes M_SCSI 1528102681Sgibbs field AUTORSTDIS 0x10 1529102681Sgibbs field CMDDMAEN 0x08 1530102681Sgibbs field ASU 0x07 153197883Sgibbs} 153297883Sgibbs 153397883Sgibbs/* 153497883Sgibbs * SCSI Bus Initiator IDs 153597883Sgibbs * Bitmask of observed initiators on the bus. 153697883Sgibbs */ 153797883Sgibbsregister BUSINITID { 153897883Sgibbs address 0x03C 153997883Sgibbs access_mode RW 154097883Sgibbs modes M_CFG 154197883Sgibbs size 2 154297883Sgibbs} 154397883Sgibbs 154497883Sgibbs/* 154597883Sgibbs * Data Length Counters 154697883Sgibbs * Packet byte counter. 154797883Sgibbs */ 154897883Sgibbsregister DLCOUNT { 154997883Sgibbs address 0x03C 155097883Sgibbs access_mode RW 155197883Sgibbs modes M_DFF0, M_DFF1 155297883Sgibbs size 3 155397883Sgibbs} 155497883Sgibbs 155597883Sgibbs/* 155697883Sgibbs * Data FIFO Status 155797883Sgibbs */ 155897883Sgibbsregister DFFSTAT { 155997883Sgibbs address 0x03F 156097883Sgibbs access_mode RW 156197883Sgibbs modes M_SCSI 1562102681Sgibbs field FIFO1FREE 0x20 1563102681Sgibbs field FIFO0FREE 0x10 1564102681Sgibbs field CURRFIFO 0x01 156597883Sgibbs} 156697883Sgibbs 156797883Sgibbs/* 156897883Sgibbs * SCSI Bus Target IDs 156997883Sgibbs * Bitmask of observed targets on the bus. 157097883Sgibbs */ 157197883Sgibbsregister BUSTARGID { 157297883Sgibbs address 0x03E 157397883Sgibbs access_mode RW 157497883Sgibbs modes M_CFG 157597883Sgibbs size 2 157697883Sgibbs} 157797883Sgibbs 157897883Sgibbs/* 157997883Sgibbs * SCSI Control Signal Out 158097883Sgibbs */ 158197883Sgibbsregister SCSISIGO { 158297883Sgibbs address 0x040 158397883Sgibbs access_mode RW 158497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1585102681Sgibbs field CDO 0x80 1586102681Sgibbs field IOO 0x40 1587102681Sgibbs field MSGO 0x20 1588102681Sgibbs field ATNO 0x10 1589102681Sgibbs field SELO 0x08 1590102681Sgibbs field BSYO 0x04 1591102681Sgibbs field REQO 0x02 1592102681Sgibbs field ACKO 0x01 159397883Sgibbs/* 159497883Sgibbs * Possible phases to write into SCSISIG0 159597883Sgibbs */ 1596102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1597102681Sgibbs P_DATAOUT 0x0, 1598102681Sgibbs P_DATAIN IOO, 1599102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1600102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1601102681Sgibbs P_COMMAND CDO, 1602102681Sgibbs P_MESGOUT CDO|MSGO, 1603102681Sgibbs P_STATUS CDO|IOO, 1604102681Sgibbs P_MESGIN CDO|IOO|MSGO 1605102681Sgibbs } 160697883Sgibbs} 160797883Sgibbs 160897883Sgibbsregister SCSISIGI { 160997883Sgibbs address 0x041 161097883Sgibbs access_mode RO 161197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1612102681Sgibbs field CDI 0x80 1613102681Sgibbs field IOI 0x40 1614102681Sgibbs field MSGI 0x20 1615102681Sgibbs field ATNI 0x10 1616102681Sgibbs field SELI 0x08 1617102681Sgibbs field BSYI 0x04 1618102681Sgibbs field REQI 0x02 1619102681Sgibbs field ACKI 0x01 162097883Sgibbs/* 162197883Sgibbs * Possible phases in SCSISIGI 162297883Sgibbs */ 1623102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1624102681Sgibbs P_DATAOUT 0x0, 1625102681Sgibbs P_DATAIN IOO, 1626102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1627102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1628102681Sgibbs P_COMMAND CDO, 1629102681Sgibbs P_MESGOUT CDO|MSGO, 1630102681Sgibbs P_STATUS CDO|IOO, 1631102681Sgibbs P_MESGIN CDO|IOO|MSGO 1632102681Sgibbs } 163397883Sgibbs} 163497883Sgibbs 163597883Sgibbs/* 163697883Sgibbs * Multiple Target IDs 163797883Sgibbs * Bitmask of ids to respond as a target. 163897883Sgibbs */ 163997883Sgibbsregister MULTARGID { 164097883Sgibbs address 0x040 164197883Sgibbs access_mode RW 164297883Sgibbs modes M_CFG 164397883Sgibbs size 2 164497883Sgibbs} 164597883Sgibbs 164697883Sgibbs/* 164797883Sgibbs * SCSI Phase 164897883Sgibbs */ 164997883Sgibbsregister SCSIPHASE { 165097883Sgibbs address 0x042 165197883Sgibbs access_mode RO 165297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1653102681Sgibbs field STATUS_PHASE 0x20 1654102681Sgibbs field COMMAND_PHASE 0x10 1655102681Sgibbs field MSG_IN_PHASE 0x08 1656102681Sgibbs field MSG_OUT_PHASE 0x04 1657102681Sgibbs field DATA_PHASE_MASK 0x03 { 1658102681Sgibbs DATA_OUT_PHASE 0x01, 1659102681Sgibbs DATA_IN_PHASE 0x02 1660102681Sgibbs } 166197883Sgibbs} 166297883Sgibbs 166397883Sgibbs/* 166497883Sgibbs * SCSI Data 0 Image 166597883Sgibbs */ 166697883Sgibbsregister SCSIDAT0_IMG { 166797883Sgibbs address 0x043 166897883Sgibbs access_mode RW 166997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 167097883Sgibbs} 167197883Sgibbs 167297883Sgibbs/* 167397883Sgibbs * SCSI Latched Data 167497883Sgibbs */ 167597883Sgibbsregister SCSIDAT { 167697883Sgibbs address 0x044 167797883Sgibbs access_mode RW 167897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 167997883Sgibbs size 2 168097883Sgibbs} 168197883Sgibbs 168297883Sgibbs/* 168397883Sgibbs * SCSI Data Bus 168497883Sgibbs */ 168597883Sgibbsregister SCSIBUS { 168697883Sgibbs address 0x046 168797883Sgibbs access_mode RW 168897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 168997883Sgibbs size 2 169097883Sgibbs} 169197883Sgibbs 169297883Sgibbs/* 169397883Sgibbs * Target ID In 169497883Sgibbs */ 169597883Sgibbsregister TARGIDIN { 169697883Sgibbs address 0x048 169797883Sgibbs access_mode RO 169897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1699102681Sgibbs field CLKOUT 0x80 1700102681Sgibbs field TARGID 0x0F 170197883Sgibbs} 170297883Sgibbs 170397883Sgibbs/* 170497883Sgibbs * Selection/Reselection ID 170597883Sgibbs * Upper four bits are the device id. The ONEBIT is set when the re/selecting 170697883Sgibbs * device did not set its own ID. 170797883Sgibbs */ 170897883Sgibbsregister SELID { 170997883Sgibbs address 0x049 171097883Sgibbs access_mode RW 171197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1712102681Sgibbs field SELID_MASK 0xf0 1713102681Sgibbs field ONEBIT 0x08 171497883Sgibbs} 171597883Sgibbs 171697883Sgibbs/* 171797883Sgibbs * SCSI Block Control 171897883Sgibbs * Controls Bus type and channel selection. SELWIDE allows for the 171997883Sgibbs * coexistence of 8bit and 16bit devices on a wide bus. 172097883Sgibbs */ 172197883Sgibbsregister SBLKCTL { 172297883Sgibbs address 0x04A 172397883Sgibbs access_mode RW 172497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1725102681Sgibbs field DIAGLEDEN 0x80 1726102681Sgibbs field DIAGLEDON 0x40 1727102681Sgibbs field ENAB40 0x08 /* LVD transceiver active */ 1728102681Sgibbs field ENAB20 0x04 /* SE/HVD transceiver active */ 1729102681Sgibbs field SELWIDE 0x02 173097883Sgibbs} 173197883Sgibbs 173297883Sgibbs/* 173397883Sgibbs * Option Mode 173497883Sgibbs */ 173597883Sgibbsregister OPTIONMODE { 173697883Sgibbs address 0x04A 173797883Sgibbs access_mode RW 173897883Sgibbs modes M_CFG 1739102681Sgibbs field BIOSCANCTL 0x80 1740102681Sgibbs field AUTOACKEN 0x40 1741102681Sgibbs field BIASCANCTL 0x20 1742102681Sgibbs field BUSFREEREV 0x10 1743102681Sgibbs field ENDGFORMCHK 0x04 1744102681Sgibbs field AUTO_MSGOUT_DE 0x02 174597883Sgibbs mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 174697883Sgibbs} 174797883Sgibbs 174897883Sgibbs/* 174997883Sgibbs * SCSI Status 0 175097883Sgibbs */ 175197883Sgibbsregister SSTAT0 { 175297883Sgibbs address 0x04B 175397883Sgibbs access_mode RO 175497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1755102681Sgibbs field TARGET 0x80 /* Board acting as target */ 1756102681Sgibbs field SELDO 0x40 /* Selection Done */ 1757102681Sgibbs field SELDI 0x20 /* Board has been selected */ 1758102681Sgibbs field SELINGO 0x10 /* Selection In Progress */ 1759102681Sgibbs field IOERR 0x08 /* LVD Tranceiver mode changed */ 1760102681Sgibbs field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1761102681Sgibbs field SPIORDY 0x02 /* SCSI PIO Ready */ 1762102681Sgibbs field ARBDO 0x01 /* Arbitration Done Out */ 176397883Sgibbs} 176497883Sgibbs 176597883Sgibbs/* 176697883Sgibbs * Clear SCSI Interrupt 0 176797883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 176897883Sgibbs */ 176997883Sgibbsregister CLRSINT0 { 177097883Sgibbs address 0x04B 177197883Sgibbs access_mode WO 177297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1773102681Sgibbs field CLRSELDO 0x40 1774102681Sgibbs field CLRSELDI 0x20 1775102681Sgibbs field CLRSELINGO 0x10 1776102681Sgibbs field CLRIOERR 0x08 1777102681Sgibbs field CLROVERRUN 0x04 1778102681Sgibbs field CLRSPIORDY 0x02 1779102681Sgibbs field CLRARBDO 0x01 178097883Sgibbs} 178197883Sgibbs 178297883Sgibbs/* 178397883Sgibbs * SCSI Interrupt Mode 0 178497883Sgibbs * Setting any bit will enable the corresponding function 178597883Sgibbs * in SIMODE0 to interrupt via the IRQ pin. 178697883Sgibbs */ 178797883Sgibbsregister SIMODE0 { 178897883Sgibbs address 0x04B 178997883Sgibbs access_mode RW 179097883Sgibbs modes M_CFG 1791102681Sgibbs field ENSELDO 0x40 1792102681Sgibbs field ENSELDI 0x20 1793102681Sgibbs field ENSELINGO 0x10 1794102681Sgibbs field ENIOERR 0x08 1795102681Sgibbs field ENOVERRUN 0x04 1796102681Sgibbs field ENSPIORDY 0x02 1797102681Sgibbs field ENARBDO 0x01 179897883Sgibbs} 179997883Sgibbs 180097883Sgibbs/* 180197883Sgibbs * SCSI Status 1 180297883Sgibbs */ 180397883Sgibbsregister SSTAT1 { 180497883Sgibbs address 0x04C 180597883Sgibbs access_mode RO 180697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1807102681Sgibbs field SELTO 0x80 1808102681Sgibbs field ATNTARG 0x40 1809102681Sgibbs field SCSIRSTI 0x20 1810102681Sgibbs field PHASEMIS 0x10 1811102681Sgibbs field BUSFREE 0x08 1812102681Sgibbs field SCSIPERR 0x04 1813102681Sgibbs field STRB2FAST 0x02 1814102681Sgibbs field REQINIT 0x01 181597883Sgibbs} 181697883Sgibbs 181797883Sgibbs/* 181897883Sgibbs * Clear SCSI Interrupt 1 181997883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 182097883Sgibbs */ 182197883Sgibbsregister CLRSINT1 { 1822104023Sgibbs address 0x04C 182397883Sgibbs access_mode WO 182497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1825102681Sgibbs field CLRSELTIMEO 0x80 1826102681Sgibbs field CLRATNO 0x40 1827102681Sgibbs field CLRSCSIRSTI 0x20 1828102681Sgibbs field CLRBUSFREE 0x08 1829102681Sgibbs field CLRSCSIPERR 0x04 1830102681Sgibbs field CLRSTRB2FAST 0x02 1831102681Sgibbs field CLRREQINIT 0x01 183297883Sgibbs} 183397883Sgibbs 183497883Sgibbs/* 183597883Sgibbs * SCSI Status 2 183697883Sgibbs */ 183797883Sgibbsregister SSTAT2 { 183897883Sgibbs address 0x04d 183997883Sgibbs access_mode RO 184097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1841102681Sgibbs field BUSFREETIME 0xc0 { 1842102681Sgibbs BUSFREE_LQO 0x40, 1843102681Sgibbs BUSFREE_DFF0 0x80, 1844102681Sgibbs BUSFREE_DFF1 0xC0 1845102681Sgibbs } 1846102681Sgibbs field NONPACKREQ 0x20 1847102681Sgibbs field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1848102681Sgibbs field BSYX 0x08 /* Busy Expander */ 1849102681Sgibbs field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1850102681Sgibbs field SDONE 0x02 /* Modes 0 and 1 only */ 1851102681Sgibbs field DMADONE 0x01 /* Modes 0 and 1 only */ 185297883Sgibbs} 185397883Sgibbs 185497883Sgibbs/* 185597883Sgibbs * Clear SCSI Interrupt 2 185697883Sgibbs */ 185797883Sgibbsregister CLRSINT2 { 185897883Sgibbs address 0x04D 185997883Sgibbs access_mode WO 186097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1861102681Sgibbs field CLRNONPACKREQ 0x20 1862102681Sgibbs field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1863102681Sgibbs field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1864102681Sgibbs field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 186597883Sgibbs} 186697883Sgibbs 186797883Sgibbs/* 186897883Sgibbs * SCSI Interrupt Mode 2 186997883Sgibbs */ 187097883Sgibbsregister SIMODE2 { 187197883Sgibbs address 0x04D 187297883Sgibbs access_mode RW 187397883Sgibbs modes M_CFG 1874102681Sgibbs field ENWIDE_RES 0x04 1875102681Sgibbs field ENSDONE 0x02 1876102681Sgibbs field ENDMADONE 0x01 187797883Sgibbs} 187897883Sgibbs 187997883Sgibbs/* 188097883Sgibbs * Physical Error Diagnosis 188197883Sgibbs */ 188297883Sgibbsregister PERRDIAG { 188397883Sgibbs address 0x04E 188497883Sgibbs access_mode RO 188597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1886102681Sgibbs field HIZERO 0x80 1887102681Sgibbs field HIPERR 0x40 1888102681Sgibbs field PREVPHASE 0x20 1889102681Sgibbs field PARITYERR 0x10 1890102681Sgibbs field AIPERR 0x08 1891102681Sgibbs field CRCERR 0x04 1892102681Sgibbs field DGFORMERR 0x02 1893102681Sgibbs field DTERR 0x01 189497883Sgibbs} 189597883Sgibbs 189697883Sgibbs/* 189797883Sgibbs * LQI Manager Current State 189897883Sgibbs */ 189997883Sgibbsregister LQISTATE { 190097883Sgibbs address 0x04E 190197883Sgibbs access_mode RO 190297883Sgibbs modes M_CFG 190397883Sgibbs} 190497883Sgibbs 190597883Sgibbs/* 190697883Sgibbs * SCSI Offset Count 190797883Sgibbs */ 190897883Sgibbsregister SOFFCNT { 190997883Sgibbs address 0x04F 191097883Sgibbs access_mode RO 191197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 191297883Sgibbs} 191397883Sgibbs 191497883Sgibbs/* 191597883Sgibbs * LQO Manager Current State 191697883Sgibbs */ 191797883Sgibbsregister LQOSTATE { 191897883Sgibbs address 0x04F 191997883Sgibbs access_mode RO 192097883Sgibbs modes M_CFG 192197883Sgibbs} 192297883Sgibbs 192397883Sgibbs/* 192497883Sgibbs * LQI Manager Status 192597883Sgibbs */ 192697883Sgibbsregister LQISTAT0 { 192797883Sgibbs address 0x050 192897883Sgibbs access_mode RO 192997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1930102681Sgibbs field LQIATNQAS 0x20 1931102681Sgibbs field LQICRCT1 0x10 1932102681Sgibbs field LQICRCT2 0x08 1933102681Sgibbs field LQIBADLQT 0x04 1934102681Sgibbs field LQIATNLQ 0x02 1935102681Sgibbs field LQIATNCMD 0x01 193697883Sgibbs} 193797883Sgibbs 193897883Sgibbs/* 193997883Sgibbs * Clear LQI Interrupts 0 194097883Sgibbs */ 1941102681Sgibbsregister CLRLQIINT0 { 194297883Sgibbs address 0x050 194397883Sgibbs access_mode WO 194497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1945102681Sgibbs field CLRLQIATNQAS 0x20 1946102681Sgibbs field CLRLQICRCT1 0x10 1947102681Sgibbs field CLRLQICRCT2 0x08 1948102681Sgibbs field CLRLQIBADLQT 0x04 1949102681Sgibbs field CLRLQIATNLQ 0x02 1950102681Sgibbs field CLRLQIATNCMD 0x01 195197883Sgibbs} 195297883Sgibbs 195397883Sgibbs/* 195497883Sgibbs * LQI Manager Interrupt Mode 0 195597883Sgibbs */ 195697883Sgibbsregister LQIMODE0 { 195797883Sgibbs address 0x050 195897883Sgibbs access_mode RW 195997883Sgibbs modes M_CFG 1960102681Sgibbs field ENLQIATNQASK 0x20 1961102681Sgibbs field ENLQICRCT1 0x10 1962102681Sgibbs field ENLQICRCT2 0x08 1963102681Sgibbs field ENLQIBADLQT 0x04 1964102681Sgibbs field ENLQIATNLQ 0x02 1965102681Sgibbs field ENLQIATNCMD 0x01 196697883Sgibbs} 196797883Sgibbs 196897883Sgibbs/* 196997883Sgibbs * LQI Manager Status 1 197097883Sgibbs */ 197197883Sgibbsregister LQISTAT1 { 197297883Sgibbs address 0x051 197397883Sgibbs access_mode RO 197497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1975102681Sgibbs field LQIPHASE_LQ 0x80 1976102681Sgibbs field LQIPHASE_NLQ 0x40 1977102681Sgibbs field LQIABORT 0x20 1978102681Sgibbs field LQICRCI_LQ 0x10 1979102681Sgibbs field LQICRCI_NLQ 0x08 1980102681Sgibbs field LQIBADLQI 0x04 1981102681Sgibbs field LQIOVERI_LQ 0x02 1982102681Sgibbs field LQIOVERI_NLQ 0x01 198397883Sgibbs} 198497883Sgibbs 198597883Sgibbs/* 198697883Sgibbs * Clear LQI Manager Interrupts1 198797883Sgibbs */ 198897883Sgibbsregister CLRLQIINT1 { 198997883Sgibbs address 0x051 199097883Sgibbs access_mode WO 199197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1992102681Sgibbs field CLRLQIPHASE_LQ 0x80 1993102681Sgibbs field CLRLQIPHASE_NLQ 0x40 1994102681Sgibbs field CLRLIQABORT 0x20 1995102681Sgibbs field CLRLQICRCI_LQ 0x10 1996102681Sgibbs field CLRLQICRCI_NLQ 0x08 1997102681Sgibbs field CLRLQIBADLQI 0x04 1998102681Sgibbs field CLRLQIOVERI_LQ 0x02 1999102681Sgibbs field CLRLQIOVERI_NLQ 0x01 200097883Sgibbs} 200197883Sgibbs 200297883Sgibbs/* 200397883Sgibbs * LQI Manager Interrupt Mode 1 200497883Sgibbs */ 200597883Sgibbsregister LQIMODE1 { 200697883Sgibbs address 0x051 200797883Sgibbs access_mode RW 200897883Sgibbs modes M_CFG 2009102681Sgibbs field ENLQIPHASE_LQ 0x80 2010102681Sgibbs field ENLQIPHASE_NLQ 0x40 2011102681Sgibbs field ENLIQABORT 0x20 2012102681Sgibbs field ENLQICRCI_LQ 0x10 2013102681Sgibbs field ENLQICRCI_NLQ 0x08 2014102681Sgibbs field ENLQIBADLQI 0x04 2015102681Sgibbs field ENLQIOVERI_LQ 0x02 2016102681Sgibbs field ENLQIOVERI_NLQ 0x01 201797883Sgibbs} 201897883Sgibbs 201997883Sgibbs/* 202097883Sgibbs * LQI Manager Status 2 202197883Sgibbs */ 202297883Sgibbsregister LQISTAT2 { 202397883Sgibbs address 0x052 202497883Sgibbs access_mode RO 202597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2026102681Sgibbs field PACKETIZED 0x80 2027102681Sgibbs field LQIPHASE_OUTPKT 0x40 2028102681Sgibbs field LQIWORKONLQ 0x20 2029102681Sgibbs field LQIWAITFIFO 0x10 2030102681Sgibbs field LQISTOPPKT 0x08 2031102681Sgibbs field LQISTOPLQ 0x04 2032102681Sgibbs field LQISTOPCMD 0x02 2033102681Sgibbs field LQIGSAVAIL 0x01 203497883Sgibbs} 203597883Sgibbs 203697883Sgibbs/* 203797883Sgibbs * SCSI Status 3 203897883Sgibbs */ 203997883Sgibbsregister SSTAT3 { 204097883Sgibbs address 0x053 204197883Sgibbs access_mode RO 204297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2043102681Sgibbs field NTRAMPERR 0x02 2044102681Sgibbs field OSRAMPERR 0x01 204597883Sgibbs} 204697883Sgibbs 204797883Sgibbs/* 204897883Sgibbs * Clear SCSI Status 3 204997883Sgibbs */ 205097883Sgibbsregister CLRSINT3 { 205197883Sgibbs address 0x053 205297883Sgibbs access_mode WO 205397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2054102681Sgibbs field CLRNTRAMPERR 0x02 2055102681Sgibbs field CLROSRAMPERR 0x01 205697883Sgibbs} 205797883Sgibbs 205897883Sgibbs/* 205997883Sgibbs * SCSI Interrupt Mode 3 206097883Sgibbs */ 206197883Sgibbsregister SIMODE3 { 206297883Sgibbs address 0x053 206397883Sgibbs access_mode RW 206497883Sgibbs modes M_CFG 2065102681Sgibbs field ENNTRAMPERR 0x02 2066102681Sgibbs field ENOSRAMPERR 0x01 206797883Sgibbs} 206897883Sgibbs 206997883Sgibbs/* 207097883Sgibbs * LQO Manager Status 0 207197883Sgibbs */ 207297883Sgibbsregister LQOSTAT0 { 207397883Sgibbs address 0x054 207497883Sgibbs access_mode RO 207597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2076102681Sgibbs field LQOTARGSCBPERR 0x10 2077102681Sgibbs field LQOSTOPT2 0x08 2078102681Sgibbs field LQOATNLQ 0x04 2079102681Sgibbs field LQOATNPKT 0x02 2080102681Sgibbs field LQOTCRC 0x01 208197883Sgibbs} 208297883Sgibbs 208397883Sgibbs/* 208497883Sgibbs * Clear LQO Manager interrupt 0 208597883Sgibbs */ 208697883Sgibbsregister CLRLQOINT0 { 208797883Sgibbs address 0x054 208897883Sgibbs access_mode WO 208997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2090102681Sgibbs field CLRLQOTARGSCBPERR 0x10 2091102681Sgibbs field CLRLQOSTOPT2 0x08 2092102681Sgibbs field CLRLQOATNLQ 0x04 2093102681Sgibbs field CLRLQOATNPKT 0x02 2094102681Sgibbs field CLRLQOTCRC 0x01 209597883Sgibbs} 209697883Sgibbs 209797883Sgibbs/* 209897883Sgibbs * LQO Manager Interrupt Mode 0 209997883Sgibbs */ 210097883Sgibbsregister LQOMODE0 { 210197883Sgibbs address 0x054 210297883Sgibbs access_mode RW 210397883Sgibbs modes M_CFG 2104102681Sgibbs field ENLQOTARGSCBPERR 0x10 2105102681Sgibbs field ENLQOSTOPT2 0x08 2106102681Sgibbs field ENLQOATNLQ 0x04 2107102681Sgibbs field ENLQOATNPKT 0x02 2108102681Sgibbs field ENLQOTCRC 0x01 210997883Sgibbs} 211097883Sgibbs 211197883Sgibbs/* 211297883Sgibbs * LQO Manager Status 1 211397883Sgibbs */ 211497883Sgibbsregister LQOSTAT1 { 211597883Sgibbs address 0x055 211697883Sgibbs access_mode RO 211797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2118102681Sgibbs field LQOINITSCBPERR 0x10 2119102681Sgibbs field LQOSTOPI2 0x08 2120102681Sgibbs field LQOBADQAS 0x04 2121102681Sgibbs field LQOBUSFREE 0x02 2122102681Sgibbs field LQOPHACHGINPKT 0x01 212397883Sgibbs} 212497883Sgibbs 212597883Sgibbs/* 212697883Sgibbs * Clear LOQ Interrupt 1 212797883Sgibbs */ 212897883Sgibbsregister CLRLQOINT1 { 212997883Sgibbs address 0x055 213097883Sgibbs access_mode WO 213197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2132102681Sgibbs field CLRLQOINITSCBPERR 0x10 2133102681Sgibbs field CLRLQOSTOPI2 0x08 2134102681Sgibbs field CLRLQOBADQAS 0x04 2135102681Sgibbs field CLRLQOBUSFREE 0x02 2136102681Sgibbs field CLRLQOPHACHGINPKT 0x01 213797883Sgibbs} 213897883Sgibbs 213997883Sgibbs/* 214097883Sgibbs * LQO Manager Interrupt Mode 1 214197883Sgibbs */ 214297883Sgibbsregister LQOMODE1 { 214397883Sgibbs address 0x055 214497883Sgibbs access_mode RW 214597883Sgibbs modes M_CFG 2146102681Sgibbs field ENLQOINITSCBPERR 0x10 2147102681Sgibbs field ENLQOSTOPI2 0x08 2148102681Sgibbs field ENLQOBADQAS 0x04 2149102681Sgibbs field ENLQOBUSFREE 0x02 2150102681Sgibbs field ENLQOPHACHGINPKT 0x01 215197883Sgibbs} 215297883Sgibbs 215397883Sgibbs/* 215497883Sgibbs * LQO Manager Status 2 215597883Sgibbs */ 215697883Sgibbsregister LQOSTAT2 { 215797883Sgibbs address 0x056 215897883Sgibbs access_mode RO 215997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2160102681Sgibbs field LQOPKT 0xE0 2161102681Sgibbs field LQOWAITFIFO 0x10 2162102681Sgibbs field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2163102681Sgibbs field LQOSTOP0 0x01 /* Stopped after sending all packets */ 216497883Sgibbs} 216597883Sgibbs 216697883Sgibbs/* 216797883Sgibbs * Output Synchronizer Space Count 216897883Sgibbs */ 216997883Sgibbsregister OS_SPACE_CNT { 217097883Sgibbs address 0x056 217197883Sgibbs access_mode RO 217297883Sgibbs modes M_CFG 217397883Sgibbs} 217497883Sgibbs 217597883Sgibbs/* 217697883Sgibbs * SCSI Interrupt Mode 1 217797883Sgibbs * Setting any bit will enable the corresponding function 217897883Sgibbs * in SIMODE1 to interrupt via the IRQ pin. 217997883Sgibbs */ 218097883Sgibbsregister SIMODE1 { 218197883Sgibbs address 0x057 218297883Sgibbs access_mode RW 218397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2184102681Sgibbs field ENSELTIMO 0x80 2185102681Sgibbs field ENATNTARG 0x40 2186102681Sgibbs field ENSCSIRST 0x20 2187102681Sgibbs field ENPHASEMIS 0x10 2188102681Sgibbs field ENBUSFREE 0x08 2189102681Sgibbs field ENSCSIPERR 0x04 2190102681Sgibbs field ENSTRB2FAST 0x02 2191102681Sgibbs field ENREQINIT 0x01 219297883Sgibbs} 219397883Sgibbs 219497883Sgibbs/* 219597883Sgibbs * Good Status FIFO 219697883Sgibbs */ 219797883Sgibbsregister GSFIFO { 219897883Sgibbs address 0x058 219997883Sgibbs access_mode RO 220097883Sgibbs size 2 220197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 220297883Sgibbs} 220397883Sgibbs 220497883Sgibbs/* 220597883Sgibbs * Data FIFO SCSI Transfer Control 220697883Sgibbs */ 220797883Sgibbsregister DFFSXFRCTL { 220897883Sgibbs address 0x05A 220997883Sgibbs access_mode RW 221097883Sgibbs modes M_DFF0, M_DFF1 2211102681Sgibbs field CLRSHCNT 0x04 2212102681Sgibbs field CLRCHN 0x02 2213102681Sgibbs field RSTCHN 0x01 221497883Sgibbs} 221597883Sgibbs 221697883Sgibbs/* 221797883Sgibbs * Next SCSI Control Block 221897883Sgibbs */ 221997883Sgibbsregister NEXTSCB { 222097883Sgibbs address 0x05A 222197883Sgibbs access_mode RW 222297883Sgibbs size 2 222397883Sgibbs modes M_SCSI 222497883Sgibbs} 222597883Sgibbs 222697883Sgibbs/* 222797883Sgibbs * SEQ Interrupts 222897883Sgibbs */ 222997883Sgibbsregister SEQINTSRC { 223097883Sgibbs address 0x05B 223197883Sgibbs access_mode RO 223297883Sgibbs modes M_DFF0, M_DFF1 2233102681Sgibbs field CTXTDONE 0x40 2234102681Sgibbs field SAVEPTRS 0x20 2235102681Sgibbs field CFG4DATA 0x10 2236102681Sgibbs field CFG4ISTAT 0x08 2237102681Sgibbs field CFG4TSTAT 0x04 2238102681Sgibbs field CFG4ICMD 0x02 2239102681Sgibbs field CFG4TCMD 0x01 224097883Sgibbs} 224197883Sgibbs 224297883Sgibbs/* 224397883Sgibbs * Clear Arp Interrupts 224497883Sgibbs */ 224597883Sgibbsregister CLRSEQINTSRC { 224697883Sgibbs address 0x05B 224797883Sgibbs access_mode WO 224897883Sgibbs modes M_DFF0, M_DFF1 2249102681Sgibbs field CLRCTXTDONE 0x40 2250102681Sgibbs field CLRSAVEPTRS 0x20 2251102681Sgibbs field CLRCFG4DATA 0x10 2252102681Sgibbs field CLRCFG4ISTAT 0x08 2253102681Sgibbs field CLRCFG4TSTAT 0x04 2254102681Sgibbs field CLRCFG4ICMD 0x02 2255102681Sgibbs field CLRCFG4TCMD 0x01 225697883Sgibbs} 225797883Sgibbs 225897883Sgibbs/* 225997883Sgibbs * SEQ Interrupt Enabled (Shared) 226097883Sgibbs */ 226197883Sgibbsregister SEQIMODE { 226297883Sgibbs address 0x05C 226397883Sgibbs access_mode RW 226497883Sgibbs modes M_DFF0, M_DFF1 2265102681Sgibbs field ENCTXTDONE 0x40 2266102681Sgibbs field ENSAVEPTRS 0x20 2267102681Sgibbs field ENCFG4DATA 0x10 2268102681Sgibbs field ENCFG4ISTAT 0x08 2269102681Sgibbs field ENCFG4TSTAT 0x04 2270102681Sgibbs field ENCFG4ICMD 0x02 2271102681Sgibbs field ENCFG4TCMD 0x01 227297883Sgibbs} 227397883Sgibbs 227497883Sgibbs/* 227597883Sgibbs * Current SCSI Control Block 227697883Sgibbs */ 227797883Sgibbsregister CURRSCB { 227897883Sgibbs address 0x05C 227997883Sgibbs access_mode RW 228097883Sgibbs size 2 228197883Sgibbs modes M_SCSI 228297883Sgibbs} 228397883Sgibbs 228497883Sgibbs/* 228597883Sgibbs * Data FIFO Status 228697883Sgibbs */ 228797883Sgibbsregister MDFFSTAT { 228897883Sgibbs address 0x05D 228997883Sgibbs access_mode RO 229097883Sgibbs modes M_DFF0, M_DFF1 2291102681Sgibbs field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2292102681Sgibbs field SHCNTMINUS1 0x20 /* Rev B or higher */ 2293102681Sgibbs field LASTSDONE 0x10 2294102681Sgibbs field SHVALID 0x08 2295102681Sgibbs field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2296102681Sgibbs field DATAINFIFO 0x02 2297102681Sgibbs field FIFOFREE 0x01 229897883Sgibbs} 229997883Sgibbs 230097883Sgibbs/* 230197883Sgibbs * CRC Control 230297883Sgibbs */ 230397883Sgibbsregister CRCCONTROL { 230497883Sgibbs address 0x05d 230597883Sgibbs access_mode RW 230697883Sgibbs modes M_CFG 2307102681Sgibbs field CRCVALCHKEN 0x40 230897883Sgibbs} 230997883Sgibbs 231097883Sgibbs/* 231197883Sgibbs * SCSI Test Control 231297883Sgibbs */ 231397883Sgibbsregister SCSITEST { 231497883Sgibbs address 0x05E 231597883Sgibbs access_mode RW 231697883Sgibbs modes M_CFG 2317102681Sgibbs field CNTRTEST 0x08 2318102681Sgibbs field SEL_TXPLL_DEBUG 0x04 231997883Sgibbs} 232097883Sgibbs 232197883Sgibbs/* 232297883Sgibbs * Data FIFO Queue Tag 232397883Sgibbs */ 232497883Sgibbsregister DFFTAG { 232597883Sgibbs address 0x05E 232697883Sgibbs access_mode RW 232797883Sgibbs size 2 232897883Sgibbs modes M_DFF0, M_DFF1 232997883Sgibbs} 233097883Sgibbs 233197883Sgibbs/* 233297883Sgibbs * Last SCSI Control Block 233397883Sgibbs */ 233497883Sgibbsregister LASTSCB { 233597883Sgibbs address 0x05E 233697883Sgibbs access_mode RW 233797883Sgibbs size 2 233897883Sgibbs modes M_SCSI 233997883Sgibbs} 234097883Sgibbs 234197883Sgibbs/* 234297883Sgibbs * SCSI I/O Cell Power-down Control 234397883Sgibbs */ 234497883Sgibbsregister IOPDNCTL { 234597883Sgibbs address 0x05F 234697883Sgibbs access_mode RW 234797883Sgibbs modes M_CFG 2348102681Sgibbs field DISABLE_OE 0x80 2349102681Sgibbs field PDN_IDIST 0x04 2350102681Sgibbs field PDN_DIFFSENSE 0x01 235197883Sgibbs} 235297883Sgibbs 235397883Sgibbs/* 235497883Sgibbs * Shaddow Host Address. 235597883Sgibbs */ 235697883Sgibbsregister SHADDR { 235797883Sgibbs address 0x060 235897883Sgibbs access_mode RO 235997883Sgibbs size 8 236097883Sgibbs modes M_DFF0, M_DFF1 236197883Sgibbs} 236297883Sgibbs 236397883Sgibbs/* 236497883Sgibbs * Data Group CRC Interval. 236597883Sgibbs */ 236697883Sgibbsregister DGRPCRCI { 236797883Sgibbs address 0x060 236897883Sgibbs access_mode RW 236997883Sgibbs size 2 237097883Sgibbs modes M_CFG 237197883Sgibbs} 237297883Sgibbs 237397883Sgibbs/* 237497883Sgibbs * Data Transfer Negotiation Address 237597883Sgibbs */ 237697883Sgibbsregister NEGOADDR { 237797883Sgibbs address 0x060 237897883Sgibbs access_mode RW 237997883Sgibbs modes M_SCSI 238097883Sgibbs} 238197883Sgibbs 238297883Sgibbs/* 238397883Sgibbs * Data Transfer Negotiation Data - Period Byte 238497883Sgibbs */ 238597883Sgibbsregister NEGPERIOD { 238697883Sgibbs address 0x061 238797883Sgibbs access_mode RW 238897883Sgibbs modes M_SCSI 238997883Sgibbs} 239097883Sgibbs 239197883Sgibbs/* 239297883Sgibbs * Packetized CRC Interval 239397883Sgibbs */ 239497883Sgibbsregister PACKCRCI { 239597883Sgibbs address 0x062 239697883Sgibbs access_mode RW 239797883Sgibbs size 2 239897883Sgibbs modes M_CFG 239997883Sgibbs} 240097883Sgibbs 240197883Sgibbs/* 240297883Sgibbs * Data Transfer Negotiation Data - Offset Byte 240397883Sgibbs */ 240497883Sgibbsregister NEGOFFSET { 240597883Sgibbs address 0x062 240697883Sgibbs access_mode RW 240797883Sgibbs modes M_SCSI 240897883Sgibbs} 240997883Sgibbs 241097883Sgibbs/* 241197883Sgibbs * Data Transfer Negotiation Data - PPR Options 241297883Sgibbs */ 241397883Sgibbsregister NEGPPROPTS { 241497883Sgibbs address 0x063 241597883Sgibbs access_mode RW 241697883Sgibbs modes M_SCSI 2417102681Sgibbs field PPROPT_PACE 0x08 2418102681Sgibbs field PPROPT_QAS 0x04 2419102681Sgibbs field PPROPT_DT 0x02 2420102681Sgibbs field PPROPT_IUT 0x01 242197883Sgibbs} 242297883Sgibbs 242397883Sgibbs/* 242497883Sgibbs * Data Transfer Negotiation Data - Connection Options 242597883Sgibbs */ 242697883Sgibbsregister NEGCONOPTS { 242797883Sgibbs address 0x064 242897883Sgibbs access_mode RW 242997883Sgibbs modes M_SCSI 2430102681Sgibbs field ENAIP 0x08 2431102681Sgibbs field ENAUTOATNI 0x04 2432102681Sgibbs field ENAUTOATNO 0x02 2433102681Sgibbs field WIDEXFER 0x01 243497883Sgibbs} 243597883Sgibbs 243697883Sgibbs/* 243797883Sgibbs * Negotiation Table Annex Column Index. 243897883Sgibbs */ 243997883Sgibbsregister ANNEXCOL { 244097883Sgibbs address 0x065 244197883Sgibbs access_mode RW 244297883Sgibbs modes M_SCSI 244397883Sgibbs} 244497883Sgibbs 2445102681Sgibbsregister SCSCHKN { 2446102681Sgibbs address 0x066 2447102681Sgibbs access_mode RW 2448102681Sgibbs modes M_CFG 2449102681Sgibbs field STSELSKIDDIS 0x40 2450102681Sgibbs field CURFIFODEF 0x20 2451102681Sgibbs field WIDERESEN 0x10 2452102681Sgibbs field SDONEMSKDIS 0x08 2453102681Sgibbs field DFFACTCLR 0x04 2454102681Sgibbs field SHVALIDSTDIS 0x02 2455102681Sgibbs field LSTSGCLRDIS 0x01 2456102681Sgibbs} 2457102681Sgibbs 245897883Sgibbsconst AHD_ANNEXCOL_PRECOMP 4 245997883Sgibbsconst AHD_PRECOMP_MASK 0x07 246097883Sgibbsconst AHD_PRECOMP_CUTBACK_17 0x04 246197883Sgibbsconst AHD_PRECOMP_CUTBACK_29 0x06 246297883Sgibbsconst AHD_PRECOMP_CUTBACK_37 0x07 246397883Sgibbsconst AHD_PRECOMP_FASTSLEW 0x40 246497883Sgibbsconst AHD_NUM_ANNEXCOLS 4 246597883Sgibbs 246697883Sgibbs/* 246797883Sgibbs * Negotiation Table Annex Data Port. 246897883Sgibbs */ 246997883Sgibbsregister ANNEXDAT { 247097883Sgibbs address 0x066 247197883Sgibbs access_mode RW 247297883Sgibbs modes M_SCSI 247397883Sgibbs} 247497883Sgibbs 247597883Sgibbs/* 247697883Sgibbs * Initiator's Own Id. 247797883Sgibbs * The SCSI ID to use for Selection Out and seen during a reselection.. 247897883Sgibbs */ 247997883Sgibbsregister IOWNID { 248097883Sgibbs address 0x067 248197883Sgibbs access_mode RW 248297883Sgibbs modes M_SCSI 248397883Sgibbs} 248497883Sgibbs 248597883Sgibbs/* 248697883Sgibbs * 960MHz Phase-Locked Loop Control 0 248797883Sgibbs */ 248897883Sgibbsregister PLL960CTL0 { 248997883Sgibbs address 0x068 249097883Sgibbs access_mode RW 249197883Sgibbs modes M_CFG 2492102681Sgibbs field PLL_VCOSEL 0x80 2493102681Sgibbs field PLL_PWDN 0x40 2494102681Sgibbs field PLL_NS 0x30 2495102681Sgibbs field PLL_ENLUD 0x08 2496102681Sgibbs field PLL_ENLPF 0x04 2497102681Sgibbs field PLL_DLPF 0x02 2498102681Sgibbs field PLL_ENFBM 0x01 249997883Sgibbs} 250097883Sgibbs 250197883Sgibbs/* 250297883Sgibbs * Target Own Id 250397883Sgibbs */ 250497883Sgibbsregister TOWNID { 250597883Sgibbs address 0x069 250697883Sgibbs access_mode RW 250797883Sgibbs modes M_SCSI 250897883Sgibbs} 250997883Sgibbs 251097883Sgibbs/* 251197883Sgibbs * 960MHz Phase-Locked Loop Control 1 251297883Sgibbs */ 251397883Sgibbsregister PLL960CTL1 { 251497883Sgibbs address 0x069 251597883Sgibbs access_mode RW 251697883Sgibbs modes M_CFG 2517102681Sgibbs field PLL_CNTEN 0x80 2518102681Sgibbs field PLL_CNTCLR 0x40 2519102681Sgibbs field PLL_RST 0x01 252097883Sgibbs} 252197883Sgibbs 252297883Sgibbs/* 252397883Sgibbs * Expander Signature 252497883Sgibbs */ 252597883Sgibbsregister XSIG { 252697883Sgibbs address 0x06A 252797883Sgibbs access_mode RW 252897883Sgibbs modes M_SCSI 252997883Sgibbs} 253097883Sgibbs 253197883Sgibbs/* 253297883Sgibbs * Shadow Byte Count 253397883Sgibbs */ 253497883Sgibbsregister SHCNT { 253597883Sgibbs address 0x068 253697883Sgibbs access_mode RW 253797883Sgibbs size 3 253897883Sgibbs modes M_DFF0, M_DFF1 253997883Sgibbs} 254097883Sgibbs 254197883Sgibbs/* 254297883Sgibbs * Selection Out ID 254397883Sgibbs */ 254497883Sgibbsregister SELOID { 254597883Sgibbs address 0x06B 254697883Sgibbs access_mode RW 254797883Sgibbs modes M_SCSI 254897883Sgibbs} 254997883Sgibbs 255097883Sgibbs/* 255197883Sgibbs * 960-MHz Phase-Locked Loop Test Count 255297883Sgibbs */ 255397883Sgibbsregister PLL960CNT0 { 255497883Sgibbs address 0x06A 255597883Sgibbs access_mode RO 255697883Sgibbs size 2 255797883Sgibbs modes M_CFG 255897883Sgibbs} 255997883Sgibbs 256097883Sgibbs/* 256197883Sgibbs * 400-MHz Phase-Locked Loop Control 0 256297883Sgibbs */ 256397883Sgibbsregister PLL400CTL0 { 256497883Sgibbs address 0x06C 256597883Sgibbs access_mode RW 256697883Sgibbs modes M_CFG 2567102681Sgibbs field PLL_VCOSEL 0x80 2568102681Sgibbs field PLL_PWDN 0x40 2569102681Sgibbs field PLL_NS 0x30 2570102681Sgibbs field PLL_ENLUD 0x08 2571102681Sgibbs field PLL_ENLPF 0x04 2572102681Sgibbs field PLL_DLPF 0x02 2573102681Sgibbs field PLL_ENFBM 0x01 257497883Sgibbs} 257597883Sgibbs 257697883Sgibbs/* 257797883Sgibbs * Arbitration Fairness 257897883Sgibbs */ 257997883Sgibbsregister FAIRNESS { 258097883Sgibbs address 0x06C 258197883Sgibbs access_mode RW 258297883Sgibbs size 2 258397883Sgibbs modes M_SCSI 258497883Sgibbs} 258597883Sgibbs 258697883Sgibbs/* 258797883Sgibbs * 400-MHz Phase-Locked Loop Control 1 258897883Sgibbs */ 258997883Sgibbsregister PLL400CTL1 { 259097883Sgibbs address 0x06D 259197883Sgibbs access_mode RW 259297883Sgibbs modes M_CFG 2593102681Sgibbs field PLL_CNTEN 0x80 2594102681Sgibbs field PLL_CNTCLR 0x40 2595102681Sgibbs field PLL_RST 0x01 259697883Sgibbs} 259797883Sgibbs 259897883Sgibbs/* 259997883Sgibbs * Arbitration Unfairness 260097883Sgibbs */ 260197883Sgibbsregister UNFAIRNESS { 260297883Sgibbs address 0x06E 260397883Sgibbs access_mode RW 260497883Sgibbs size 2 260597883Sgibbs modes M_SCSI 260697883Sgibbs} 260797883Sgibbs 260897883Sgibbs/* 260997883Sgibbs * 400-MHz Phase-Locked Loop Test Count 261097883Sgibbs */ 261197883Sgibbsregister PLL400CNT0 { 261297883Sgibbs address 0x06E 261397883Sgibbs access_mode RO 261497883Sgibbs size 2 261597883Sgibbs modes M_CFG 261697883Sgibbs} 261797883Sgibbs 261897883Sgibbs/* 261997883Sgibbs * SCB Page Pointer 262097883Sgibbs */ 262197883Sgibbsregister SCBPTR { 262297883Sgibbs address 0x0A8 262397883Sgibbs access_mode RW 262497883Sgibbs size 2 262597883Sgibbs modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 262697883Sgibbs} 262797883Sgibbs 262897883Sgibbs/* 262997883Sgibbs * CMC SCB Array Count 263097883Sgibbs * Number of bytes to transfer between CMC SCB memory and SCBRAM. 263197883Sgibbs * Transfers must be 8byte aligned and sized. 263297883Sgibbs */ 263397883Sgibbsregister CCSCBACNT { 263497883Sgibbs address 0x0AB 263597883Sgibbs access_mode RW 263697883Sgibbs modes M_CCHAN 263797883Sgibbs} 263897883Sgibbs 263997883Sgibbs/* 264097883Sgibbs * SCB Autopointer 264197883Sgibbs * SCB-Next Address Snooping logic. When an SCB is transferred to 264297883Sgibbs * the card, the next SCB address to be used by the CMC array can 264397883Sgibbs * be autoloaded from that transfer. 264497883Sgibbs */ 264597883Sgibbsregister SCBAUTOPTR { 264697883Sgibbs address 0x0AB 264797883Sgibbs access_mode RW 264897883Sgibbs modes M_CFG 2649102681Sgibbs field AUSCBPTR_EN 0x80 2650102681Sgibbs field SCBPTR_ADDR 0x38 2651102681Sgibbs field SCBPTR_OFF 0x07 265297883Sgibbs} 265397883Sgibbs 265497883Sgibbs/* 265597883Sgibbs * CMC SG Ram Address Pointer 265697883Sgibbs */ 265797883Sgibbsregister CCSGADDR { 265897883Sgibbs address 0x0AC 265997883Sgibbs access_mode RW 266097883Sgibbs modes M_DFF0, M_DFF1 266197883Sgibbs} 266297883Sgibbs 266397883Sgibbs/* 266497883Sgibbs * CMC SCB RAM Address Pointer 266597883Sgibbs */ 266697883Sgibbsregister CCSCBADDR { 266797883Sgibbs address 0x0AC 266897883Sgibbs access_mode RW 266997883Sgibbs modes M_CCHAN 267097883Sgibbs} 267197883Sgibbs 267297883Sgibbs/* 267397883Sgibbs * CMC SCB Ram Back-up Address Pointer 267497883Sgibbs * Indicates the true stop location of transfers halted prior 267597883Sgibbs * to SCBHCNT going to 0. 267697883Sgibbs */ 267797883Sgibbsregister CCSCBADR_BK { 267897883Sgibbs address 0x0AC 267997883Sgibbs access_mode RO 268097883Sgibbs modes M_CFG 268197883Sgibbs} 268297883Sgibbs 268397883Sgibbs/* 268497883Sgibbs * CMC SG Control 268597883Sgibbs */ 268697883Sgibbsregister CCSGCTL { 268797883Sgibbs address 0x0AD 268897883Sgibbs access_mode RW 268997883Sgibbs modes M_DFF0, M_DFF1 2690102681Sgibbs field CCSGDONE 0x80 2691102681Sgibbs field SG_CACHE_AVAIL 0x10 2692102681Sgibbs field CCSGEN 0x08 2693102681Sgibbs field SG_FETCH_REQ 0x02 2694102681Sgibbs field CCSGRESET 0x01 269597883Sgibbs} 269697883Sgibbs 269797883Sgibbs/* 269897883Sgibbs * CMD SCB Control 269997883Sgibbs */ 270097883Sgibbsregister CCSCBCTL { 270197883Sgibbs address 0x0AD 270297883Sgibbs access_mode RW 270397883Sgibbs modes M_CCHAN 2704102681Sgibbs field CCSCBDONE 0x80 2705102681Sgibbs field ARRDONE 0x40 2706102681Sgibbs field CCARREN 0x10 2707102681Sgibbs field CCSCBEN 0x08 2708102681Sgibbs field CCSCBDIR 0x04 2709102681Sgibbs field CCSCBRESET 0x01 271097883Sgibbs} 271197883Sgibbs 271297883Sgibbs/* 271397883Sgibbs * CMC Ram BIST 271497883Sgibbs */ 271597883Sgibbsregister CMC_RAMBIST { 271697883Sgibbs address 0x0AD 271797883Sgibbs access_mode RW 271897883Sgibbs modes M_CFG 2719102681Sgibbs field SG_ELEMENT_SIZE 0x80 2720102681Sgibbs field SCBRAMBIST_FAIL 0x40 2721102681Sgibbs field SG_BIST_FAIL 0x20 2722102681Sgibbs field SG_BIST_EN 0x10 2723102681Sgibbs field CMC_BUFFER_BIST_FAIL 0x02 2724102681Sgibbs field CMC_BUFFER_BIST_EN 0x01 272597883Sgibbs} 272697883Sgibbs 272797883Sgibbs/* 272897883Sgibbs * CMC SG RAM Data Port 272997883Sgibbs */ 273097883Sgibbsregister CCSGRAM { 273197883Sgibbs address 0x0B0 273297883Sgibbs access_mode RW 273397883Sgibbs modes M_DFF0, M_DFF1 273497883Sgibbs} 273597883Sgibbs 273697883Sgibbs/* 273797883Sgibbs * CMC SCB RAM Data Port 273897883Sgibbs */ 273997883Sgibbsregister CCSCBRAM { 274097883Sgibbs address 0x0B0 274197883Sgibbs access_mode RW 274297883Sgibbs modes M_CCHAN 274397883Sgibbs} 274497883Sgibbs 274597883Sgibbs/* 274697883Sgibbs * Flex DMA Address. 274797883Sgibbs */ 274897883Sgibbsregister FLEXADR { 274997883Sgibbs address 0x0B0 275097883Sgibbs access_mode RW 275197883Sgibbs size 3 275297883Sgibbs modes M_SCSI 275397883Sgibbs} 275497883Sgibbs 275597883Sgibbs/* 275697883Sgibbs * Flex DMA Byte Count 275797883Sgibbs */ 275897883Sgibbsregister FLEXCNT { 275997883Sgibbs address 0x0B3 276097883Sgibbs access_mode RW 276197883Sgibbs size 2 276297883Sgibbs modes M_SCSI 276397883Sgibbs} 276497883Sgibbs 276597883Sgibbs/* 276697883Sgibbs * Flex DMA Status 276797883Sgibbs */ 276897883Sgibbsregister FLEXDMASTAT { 276997883Sgibbs address 0x0B5 277097883Sgibbs access_mode RW 277197883Sgibbs modes M_SCSI 2772102681Sgibbs field FLEXDMAERR 0x02 2773102681Sgibbs field FLEXDMADONE 0x01 277497883Sgibbs} 277597883Sgibbs 277697883Sgibbs/* 277797883Sgibbs * Flex DMA Data Port 277897883Sgibbs */ 277997883Sgibbsregister FLEXDATA { 278097883Sgibbs address 0x0B6 278197883Sgibbs access_mode RW 278297883Sgibbs modes M_SCSI 278397883Sgibbs} 278497883Sgibbs 278597883Sgibbs/* 278697883Sgibbs * Board Data 278797883Sgibbs */ 278897883Sgibbsregister BRDDAT { 278997883Sgibbs address 0x0B8 279097883Sgibbs access_mode RW 279197883Sgibbs modes M_SCSI 279297883Sgibbs} 279397883Sgibbs 279497883Sgibbs/* 279597883Sgibbs * Board Control 279697883Sgibbs */ 279797883Sgibbsregister BRDCTL { 279897883Sgibbs address 0x0B9 279997883Sgibbs access_mode RW 280097883Sgibbs modes M_SCSI 2801102681Sgibbs field FLXARBACK 0x80 2802102681Sgibbs field FLXARBREQ 0x40 2803102681Sgibbs field BRDADDR 0x38 2804102681Sgibbs field BRDEN 0x04 2805102681Sgibbs field BRDRW 0x02 2806102681Sgibbs field BRDSTB 0x01 280797883Sgibbs} 280897883Sgibbs 280997883Sgibbs/* 281097883Sgibbs * Serial EEPROM Address 281197883Sgibbs */ 281297883Sgibbsregister SEEADR { 281397883Sgibbs address 0x0BA 281497883Sgibbs access_mode RW 281597883Sgibbs modes M_SCSI 281697883Sgibbs} 281797883Sgibbs 281897883Sgibbs/* 281997883Sgibbs * Serial EEPROM Data 282097883Sgibbs */ 282197883Sgibbsregister SEEDAT { 282297883Sgibbs address 0x0BC 282397883Sgibbs access_mode RW 282497883Sgibbs size 2 282597883Sgibbs modes M_SCSI 282697883Sgibbs} 282797883Sgibbs 282897883Sgibbs/* 282997883Sgibbs * Serial EEPROM Status 283097883Sgibbs */ 283197883Sgibbsregister SEESTAT { 283297883Sgibbs address 0x0BE 283397883Sgibbs access_mode RO 283497883Sgibbs modes M_SCSI 2835102681Sgibbs field INIT_DONE 0x80 2836102681Sgibbs field SEEOPCODE 0x70 2837102681Sgibbs field LDALTID_L 0x08 2838102681Sgibbs field SEEARBACK 0x04 2839102681Sgibbs field SEEBUSY 0x02 2840102681Sgibbs field SEESTART 0x01 284197883Sgibbs} 284297883Sgibbs 284397883Sgibbs/* 284497883Sgibbs * Serial EEPROM Control 284597883Sgibbs */ 284697883Sgibbsregister SEECTL { 284797883Sgibbs address 0x0BE 284897883Sgibbs access_mode RW 284997883Sgibbs modes M_SCSI 2850102681Sgibbs field SEEOPCODE 0x70 { 2851102681Sgibbs SEEOP_ERASE 0x70, 2852102681Sgibbs SEEOP_READ 0x60, 2853102681Sgibbs SEEOP_WRITE 0x50, 285497883Sgibbs /* 285597883Sgibbs * The following four commands use special 285697883Sgibbs * addresses for differentiation. 285797883Sgibbs */ 2858102681Sgibbs SEEOP_ERAL 0x40 2859102681Sgibbs } 286097883Sgibbs mask SEEOP_EWEN 0x40 286197883Sgibbs mask SEEOP_WALL 0x40 286297883Sgibbs mask SEEOP_EWDS 0x40 2863102681Sgibbs field SEERST 0x02 2864102681Sgibbs field SEESTART 0x01 286597883Sgibbs} 286697883Sgibbs 286797883Sgibbsconst SEEOP_ERAL_ADDR 0x80 286897883Sgibbsconst SEEOP_EWEN_ADDR 0xC0 286997883Sgibbsconst SEEOP_WRAL_ADDR 0x40 287097883Sgibbsconst SEEOP_EWDS_ADDR 0x00 287197883Sgibbs 287297883Sgibbs/* 287397883Sgibbs * SCB Counter 287497883Sgibbs */ 287597883Sgibbsregister SCBCNT { 287697883Sgibbs address 0x0BF 287797883Sgibbs access_mode RW 287897883Sgibbs modes M_SCSI 287997883Sgibbs} 288097883Sgibbs 288197883Sgibbs/* 288297883Sgibbs * Data FIFO Write Address 288397883Sgibbs * Pointer to the next QWD location to be written to the data FIFO. 288497883Sgibbs */ 288597883Sgibbsregister DFWADDR { 288697883Sgibbs address 0x0C0 288797883Sgibbs access_mode RW 288897883Sgibbs size 2 288997883Sgibbs modes M_DFF0, M_DFF1 289097883Sgibbs} 289197883Sgibbs 289297883Sgibbs/* 289397883Sgibbs * DSP Filter Control 289497883Sgibbs */ 289597883Sgibbsregister DSPFLTRCTL { 289697883Sgibbs address 0x0C0 289797883Sgibbs access_mode RW 289897883Sgibbs modes M_CFG 2899102681Sgibbs field FLTRDISABLE 0x20 2900102681Sgibbs field EDGESENSE 0x10 2901102681Sgibbs field DSPFCNTSEL 0x0F 290297883Sgibbs} 290397883Sgibbs 290497883Sgibbs/* 290597883Sgibbs * DSP Data Channel Control 290697883Sgibbs */ 290797883Sgibbsregister DSPDATACTL { 290897883Sgibbs address 0x0C1 290997883Sgibbs access_mode RW 291097883Sgibbs modes M_CFG 2911102681Sgibbs field BYPASSENAB 0x80 2912102681Sgibbs field DESQDIS 0x10 2913102681Sgibbs field RCVROFFSTDIS 0x04 2914102681Sgibbs field XMITOFFSTDIS 0x02 291597883Sgibbs} 291697883Sgibbs 291797883Sgibbs/* 291897883Sgibbs * Data FIFO Read Address 291997883Sgibbs * Pointer to the next QWD location to be read from the data FIFO. 292097883Sgibbs */ 292197883Sgibbsregister DFRADDR { 292297883Sgibbs address 0x0C2 292397883Sgibbs access_mode RW 292497883Sgibbs size 2 292597883Sgibbs modes M_DFF0, M_DFF1 292697883Sgibbs} 292797883Sgibbs 292897883Sgibbs/* 292997883Sgibbs * DSP REQ Control 293097883Sgibbs */ 293197883Sgibbsregister DSPREQCTL { 293297883Sgibbs address 0x0C2 293397883Sgibbs access_mode RW 293497883Sgibbs modes M_CFG 2935102681Sgibbs field MANREQCTL 0xC0 2936102681Sgibbs field MANREQDLY 0x3F 293797883Sgibbs} 293897883Sgibbs 293997883Sgibbs/* 294097883Sgibbs * DSP ACK Control 294197883Sgibbs */ 294297883Sgibbsregister DSPACKCTL { 294397883Sgibbs address 0x0C3 294497883Sgibbs access_mode RW 294597883Sgibbs modes M_CFG 2946102681Sgibbs field MANACKCTL 0xC0 2947102681Sgibbs field MANACKDLY 0x3F 294897883Sgibbs} 294997883Sgibbs 295097883Sgibbs/* 295197883Sgibbs * Data FIFO Data 295297883Sgibbs * Read/Write byte port into the data FIFO. The read and write 295397883Sgibbs * FIFO pointers increment with each read and write respectively 295497883Sgibbs * to this port. 295597883Sgibbs */ 295697883Sgibbsregister DFDAT { 295797883Sgibbs address 0x0C4 295897883Sgibbs access_mode RW 295997883Sgibbs modes M_DFF0, M_DFF1 296097883Sgibbs} 296197883Sgibbs 296297883Sgibbs/* 296397883Sgibbs * DSP Channel Select 296497883Sgibbs */ 296597883Sgibbsregister DSPSELECT { 296697883Sgibbs address 0x0C4 296797883Sgibbs access_mode RW 296897883Sgibbs modes M_CFG 2969102681Sgibbs field AUTOINCEN 0x80 2970102681Sgibbs field DSPSEL 0x1F 297197883Sgibbs} 297297883Sgibbs 297397883Sgibbsconst NUMDSPS 0x14 297497883Sgibbs 297597883Sgibbs/* 297697883Sgibbs * Write Bias Control 297797883Sgibbs */ 297897883Sgibbsregister WRTBIASCTL { 297997883Sgibbs address 0x0C5 298097883Sgibbs access_mode WO 298197883Sgibbs modes M_CFG 2982102681Sgibbs field AUTOXBCDIS 0x80 2983102681Sgibbs field XMITMANVAL 0x3F 298497883Sgibbs} 298597883Sgibbs 298697883Sgibbsconst WRTBIASCTL_CPQ_DEFAULT 0x97 298797883Sgibbs 298897883Sgibbs/* 298997883Sgibbs * Receiver Bias Control 299097883Sgibbs */ 299197883Sgibbsregister RCVRBIOSCTL { 299297883Sgibbs address 0x0C6 299397883Sgibbs access_mode WO 299497883Sgibbs modes M_CFG 2995102681Sgibbs field AUTORBCDIS 0x80 2996102681Sgibbs field RCVRMANVAL 0x3F 299797883Sgibbs} 299897883Sgibbs 299997883Sgibbs/* 300097883Sgibbs * Write Bias Calculator 300197883Sgibbs */ 300297883Sgibbsregister WRTBIASCALC { 300397883Sgibbs address 0x0C7 300497883Sgibbs access_mode RO 300597883Sgibbs modes M_CFG 300697883Sgibbs} 300797883Sgibbs 300897883Sgibbs/* 300997883Sgibbs * Data FIFO Pointers 301097883Sgibbs * Contains the byte offset from DFWADDR and DWRADDR to the current 301197883Sgibbs * FIFO write/read locations. 301297883Sgibbs */ 301397883Sgibbsregister DFPTRS { 301497883Sgibbs address 0x0C8 301597883Sgibbs access_mode RW 301697883Sgibbs modes M_DFF0, M_DFF1 301797883Sgibbs} 301897883Sgibbs 301997883Sgibbs/* 302097883Sgibbs * Receiver Bias Calculator 302197883Sgibbs */ 302297883Sgibbsregister RCVRBIASCALC { 302397883Sgibbs address 0x0C8 302497883Sgibbs access_mode RO 302597883Sgibbs modes M_CFG 302697883Sgibbs} 302797883Sgibbs 302897883Sgibbs/* 302997883Sgibbs * Data FIFO Debug Control 303097883Sgibbs */ 303197883Sgibbsregister DFDBCTL { 303297883Sgibbs address 0x0C8 303397883Sgibbs access_mode RW 303497883Sgibbs modes M_DFF0, M_DFF1 3035102681Sgibbs field DFF_CIO_WR_RDY 0x20 3036102681Sgibbs field DFF_CIO_RD_RDY 0x10 3037102681Sgibbs field DFF_DIR_ERR 0x08 3038102681Sgibbs field DFF_RAMBIST_FAIL 0x04 3039102681Sgibbs field DFF_RAMBIST_DONE 0x02 3040102681Sgibbs field DFF_RAMBIST_EN 0x01 304197883Sgibbs} 304297883Sgibbs 304397883Sgibbs/* 304497883Sgibbs * Data FIFO Backup Read Pointer 304597883Sgibbs * Contains the data FIFO address to be restored if the last 304697883Sgibbs * data accessed from the data FIFO was not transferred successfully. 304797883Sgibbs */ 304897883Sgibbsregister DFBKPTR { 304997883Sgibbs address 0x0C9 305097883Sgibbs access_mode RW 305197883Sgibbs size 2 305297883Sgibbs modes M_DFF0, M_DFF1 305397883Sgibbs} 305497883Sgibbs 305597883Sgibbs/* 305697883Sgibbs * Skew Calculator 305797883Sgibbs */ 305897883Sgibbsregister SKEWCALC { 305997883Sgibbs address 0x0C9 306097883Sgibbs access_mode RO 306197883Sgibbs modes M_CFG 306297883Sgibbs} 306397883Sgibbs 306497883Sgibbs/* 306597883Sgibbs * Data FIFO Space Count 306697883Sgibbs * Number of FIFO locations that are free. 306797883Sgibbs */ 306897883Sgibbsregister DFSCNT { 306997883Sgibbs address 0x0CC 307097883Sgibbs access_mode RO 307197883Sgibbs size 2 307297883Sgibbs modes M_DFF0, M_DFF1 307397883Sgibbs} 307497883Sgibbs 307597883Sgibbs/* 307697883Sgibbs * Data FIFO Byte Count 307797883Sgibbs * Number of filled FIFO locations. 307897883Sgibbs */ 307997883Sgibbsregister DFBCNT { 308097883Sgibbs address 0x0CE 308197883Sgibbs access_mode RO 308297883Sgibbs size 2 308397883Sgibbs modes M_DFF0, M_DFF1 308497883Sgibbs} 308597883Sgibbs 308697883Sgibbs/* 308797883Sgibbs * Sequencer Program Overlay Address. 308897883Sgibbs * Low address must be written prior to high address. 308997883Sgibbs */ 309097883Sgibbsregister OVLYADDR { 309197883Sgibbs address 0x0D4 309297883Sgibbs modes M_SCSI 309397883Sgibbs size 2 309497883Sgibbs access_mode RW 309597883Sgibbs} 309697883Sgibbs 309797883Sgibbs/* 309897883Sgibbs * Sequencer Control 0 309997883Sgibbs * Error detection mode, speed configuration, 310097883Sgibbs * single step, breakpoints and program load. 310197883Sgibbs */ 310297883Sgibbsregister SEQCTL0 { 310397883Sgibbs address 0x0D6 310497883Sgibbs access_mode RW 3105102681Sgibbs field PERRORDIS 0x80 3106102681Sgibbs field PAUSEDIS 0x40 3107102681Sgibbs field FAILDIS 0x20 3108102681Sgibbs field FASTMODE 0x10 3109102681Sgibbs field BRKADRINTEN 0x08 3110102681Sgibbs field STEP 0x04 3111102681Sgibbs field SEQRESET 0x02 3112102681Sgibbs field LOADRAM 0x01 311397883Sgibbs} 311497883Sgibbs 311597883Sgibbs/* 311697883Sgibbs * Sequencer Control 1 311797883Sgibbs * Instruction RAM Diagnostics 311897883Sgibbs */ 311997883Sgibbsregister SEQCTL1 { 312097883Sgibbs address 0x0D7 312197883Sgibbs access_mode RW 3122102681Sgibbs field OVRLAY_DATA_CHK 0x08 3123102681Sgibbs field RAMBIST_DONE 0x04 3124102681Sgibbs field RAMBIST_FAIL 0x02 3125102681Sgibbs field RAMBIST_EN 0x01 312697883Sgibbs} 312797883Sgibbs 312897883Sgibbs/* 312997883Sgibbs * Sequencer Flags 313097883Sgibbs * Zero and Carry state of the ALU. 313197883Sgibbs */ 313297883Sgibbsregister FLAGS { 313397883Sgibbs address 0x0D8 313497883Sgibbs access_mode RO 3135102681Sgibbs field ZERO 0x02 3136102681Sgibbs field CARRY 0x01 313797883Sgibbs} 313897883Sgibbs 313997883Sgibbs/* 314097883Sgibbs * Sequencer Interrupt Control 314197883Sgibbs */ 314297883Sgibbsregister SEQINTCTL { 314397883Sgibbs address 0x0D9 314497883Sgibbs access_mode RW 3145102681Sgibbs field INTVEC1DSL 0x80 3146102681Sgibbs field INT1_CONTEXT 0x20 3147102681Sgibbs field SCS_SEQ_INT1M1 0x10 3148102681Sgibbs field SCS_SEQ_INT1M0 0x08 3149102681Sgibbs field INTMASK 0x06 3150102681Sgibbs field IRET 0x01 315197883Sgibbs} 315297883Sgibbs 315397883Sgibbs/* 315497883Sgibbs * Sequencer RAM Data Port 315597883Sgibbs * Single byte window into the Sequencer Instruction Ram area starting 315697883Sgibbs * at the address specified by OVLYADDR. To write a full instruction word, 315797883Sgibbs * simply write four bytes in succession. OVLYADDR will increment after the 315897883Sgibbs * most significant instrution byte (the byte with the parity bit) is written. 315997883Sgibbs */ 316097883Sgibbsregister SEQRAM { 316197883Sgibbs address 0x0DA 316297883Sgibbs access_mode RW 316397883Sgibbs} 316497883Sgibbs 316597883Sgibbs/* 316697883Sgibbs * Sequencer Program Counter 316797883Sgibbs * Low byte must be written prior to high byte. 316897883Sgibbs */ 316997883Sgibbsregister PRGMCNT { 317097883Sgibbs address 0x0DE 317197883Sgibbs access_mode RW 317297883Sgibbs size 2 317397883Sgibbs} 317497883Sgibbs 317597883Sgibbs/* 317697883Sgibbs * Accumulator 317797883Sgibbs */ 317897883Sgibbsregister ACCUM { 317997883Sgibbs address 0x0E0 318097883Sgibbs access_mode RW 318197883Sgibbs accumulator 318297883Sgibbs} 318397883Sgibbs 318497883Sgibbs/* 318597883Sgibbs * Source Index Register 318697883Sgibbs * Incrementing index for reads of SINDIR and the destination (low byte only) 318797883Sgibbs * for any immediate operands passed in jmp, jc, jnc, call instructions. 318897883Sgibbs * Example: 318997883Sgibbs * mvi 0xFF call some_routine; 319097883Sgibbs * 319197883Sgibbs * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 319297883Sgibbs */ 319397883Sgibbsregister SINDEX { 319497883Sgibbs address 0x0E2 319597883Sgibbs access_mode RW 319697883Sgibbs size 2 319797883Sgibbs sindex 319897883Sgibbs} 319997883Sgibbs 320097883Sgibbs/* 320197883Sgibbs * Destination Index Register 320297883Sgibbs * Incrementing index for writes to DINDIR. Can be used as a scratch register. 320397883Sgibbs */ 320497883Sgibbsregister DINDEX { 320597883Sgibbs address 0x0E4 320697883Sgibbs access_mode RW 320797883Sgibbs size 2 320897883Sgibbs} 320997883Sgibbs 321097883Sgibbs/* 321197883Sgibbs * Break Address 321297883Sgibbs * Sequencer instruction breakpoint address address. 321397883Sgibbs */ 321497883Sgibbsregister BRKADDR0 { 321597883Sgibbs address 0x0E6 321697883Sgibbs access_mode RW 321797883Sgibbs} 321897883Sgibbs 321997883Sgibbsregister BRKADDR1 { 322097883Sgibbs address 0x0E6 322197883Sgibbs access_mode RW 3222102681Sgibbs field BRKDIS 0x80 /* Disable Breakpoint */ 322397883Sgibbs} 322497883Sgibbs 322597883Sgibbs/* 322697883Sgibbs * All Ones 322797883Sgibbs * All reads to this register return the value 0xFF. 322897883Sgibbs */ 322997883Sgibbsregister ALLONES { 323097883Sgibbs address 0x0E8 323197883Sgibbs access_mode RO 323297883Sgibbs allones 323397883Sgibbs} 323497883Sgibbs 323597883Sgibbs/* 323697883Sgibbs * All Zeros 323797883Sgibbs * All reads to this register return the value 0. 323897883Sgibbs */ 323997883Sgibbsregister ALLZEROS { 324097883Sgibbs address 0x0EA 324197883Sgibbs access_mode RO 324297883Sgibbs allzeros 324397883Sgibbs} 324497883Sgibbs 324597883Sgibbs/* 324697883Sgibbs * No Destination 324797883Sgibbs * Writes to this register have no effect. 324897883Sgibbs */ 324997883Sgibbsregister NONE { 325097883Sgibbs address 0x0EA 325197883Sgibbs access_mode WO 325297883Sgibbs none 325397883Sgibbs} 325497883Sgibbs 325597883Sgibbs/* 325697883Sgibbs * Source Index Indirect 325797883Sgibbs * Reading this register is equivalent to reading (register_base + SINDEX) and 325897883Sgibbs * incrementing SINDEX by 1. 325997883Sgibbs */ 326097883Sgibbsregister SINDIR { 326197883Sgibbs address 0x0EC 326297883Sgibbs access_mode RO 326397883Sgibbs} 326497883Sgibbs 326597883Sgibbs/* 326697883Sgibbs * Destination Index Indirect 326797883Sgibbs * Writing this register is equivalent to writing to (register_base + DINDEX) 326897883Sgibbs * and incrementing DINDEX by 1. 326997883Sgibbs */ 327097883Sgibbsregister DINDIR { 327197883Sgibbs address 0x0ED 327297883Sgibbs access_mode WO 327397883Sgibbs} 327497883Sgibbs 327597883Sgibbs/* 327697883Sgibbs * Function One 327797883Sgibbs * 2's complement to bit value conversion. Write the 2's complement value 327897883Sgibbs * (0-7 only) to the top nibble and retrieve the bit indexed by that value 327997883Sgibbs * on the next read of this register. 328097883Sgibbs * Example: 328197883Sgibbs * Write 0x60 328297883Sgibbs * Read 0x40 328397883Sgibbs */ 328497883Sgibbsregister FUNCTION1 { 328597883Sgibbs address 0x0F0 328697883Sgibbs access_mode RW 328797883Sgibbs} 328897883Sgibbs 328997883Sgibbs/* 329097883Sgibbs * Stack 329197883Sgibbs * Window into the stack. Each stack location is 10 bits wide reported 329297883Sgibbs * low byte followed by high byte. There are 8 stack locations. 329397883Sgibbs */ 329497883Sgibbsregister STACK { 329597883Sgibbs address 0x0F2 329697883Sgibbs access_mode RW 329797883Sgibbs} 329897883Sgibbs 329997883Sgibbs/* 330097883Sgibbs * Interrupt Vector 1 Address 330197883Sgibbs * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 330297883Sgibbs */ 330397883Sgibbsregister INTVEC1_ADDR { 330497883Sgibbs address 0x0F4 330597883Sgibbs access_mode RW 330697883Sgibbs size 2 330797883Sgibbs modes M_CFG 330897883Sgibbs} 330997883Sgibbs 331097883Sgibbs/* 331197883Sgibbs * Current Address 331297883Sgibbs * Address of the SEQRAM instruction currently executing instruction. 331397883Sgibbs */ 331497883Sgibbsregister CURADDR { 331597883Sgibbs address 0x0F4 331697883Sgibbs access_mode RW 331797883Sgibbs size 2 331897883Sgibbs modes M_SCSI 331997883Sgibbs} 332097883Sgibbs 332197883Sgibbs/* 332297883Sgibbs * Interrupt Vector 2 Address 332397883Sgibbs * Interrupt branch address for HST_SEQ_INT2 interrupts. 332497883Sgibbs */ 332597883Sgibbsregister INTVEC2_ADDR { 332697883Sgibbs address 0x0F6 332797883Sgibbs access_mode RW 332897883Sgibbs size 2 332997883Sgibbs modes M_CFG 333097883Sgibbs} 333197883Sgibbs 333297883Sgibbs/* 333397883Sgibbs * Last Address 333497883Sgibbs * Address of the SEQRAM instruction executed prior to the current instruction. 333597883Sgibbs */ 333697883Sgibbsregister LASTADDR { 333797883Sgibbs address 0x0F6 333897883Sgibbs access_mode RW 333997883Sgibbs size 2 334097883Sgibbs modes M_SCSI 334197883Sgibbs} 334297883Sgibbs 334397883Sgibbsregister AHD_PCI_CONFIG_BASE { 334497883Sgibbs address 0x100 334597883Sgibbs access_mode RW 334697883Sgibbs size 256 334797883Sgibbs modes M_CFG 334897883Sgibbs} 334997883Sgibbs 335097883Sgibbs/* ---------------------- Scratch RAM Offsets ------------------------- */ 335197883Sgibbsscratch_ram { 335297883Sgibbs /* Mode Specific */ 335397883Sgibbs address 0x0A0 335497883Sgibbs size 8 335597883Sgibbs modes 0, 1, 2, 3 335697883Sgibbs REG0 { 335797883Sgibbs size 2 335897883Sgibbs } 335997883Sgibbs REG1 { 336097883Sgibbs size 2 336197883Sgibbs } 3362104023Sgibbs REG_ISR { 336397883Sgibbs size 2 336497883Sgibbs } 336597883Sgibbs SG_STATE { 336697883Sgibbs size 1 3367102681Sgibbs field SEGS_AVAIL 0x01 3368102681Sgibbs field LOADING_NEEDED 0x02 3369102681Sgibbs field FETCH_INPROG 0x04 337097883Sgibbs } 337197883Sgibbs /* 337297883Sgibbs * Track whether the transfer byte count for 337397883Sgibbs * the current data phase is odd. 337497883Sgibbs */ 337597883Sgibbs DATA_COUNT_ODD { 337697883Sgibbs size 1 337797883Sgibbs } 337897883Sgibbs} 337997883Sgibbs 338097883Sgibbsscratch_ram { 338197883Sgibbs /* Mode Specific */ 338297883Sgibbs address 0x0F8 338397883Sgibbs size 8 338497883Sgibbs modes 0, 1, 2, 3 338597883Sgibbs LONGJMP_ADDR { 338697883Sgibbs size 2 338797883Sgibbs } 338897883Sgibbs LONGJMP_SCB { 338997883Sgibbs size 2 339097883Sgibbs } 339197883Sgibbs ACCUM_SAVE { 339297883Sgibbs size 1 339397883Sgibbs } 339497883Sgibbs} 339597883Sgibbs 339697883Sgibbs 339797883Sgibbsscratch_ram { 339897883Sgibbs address 0x100 339997883Sgibbs size 128 340097883Sgibbs modes 0, 1, 2, 3 340197883Sgibbs /* 340297883Sgibbs * Per "other-id" execution queues. We use an array of 340397883Sgibbs * tail pointers into lists of SCBs sorted by "other-id". 340497883Sgibbs * The execution head pointer threads the head SCBs for 340597883Sgibbs * each list. 340697883Sgibbs */ 340797883Sgibbs WAITING_SCB_TAILS { 340897883Sgibbs size 32 340997883Sgibbs } 341097883Sgibbs WAITING_TID_HEAD { 341197883Sgibbs size 2 341297883Sgibbs } 341397883Sgibbs WAITING_TID_TAIL { 341497883Sgibbs size 2 341597883Sgibbs } 341697883Sgibbs /* 341797883Sgibbs * SCBID of the next SCB in the new SCB queue. 341897883Sgibbs */ 341997883Sgibbs NEXT_QUEUED_SCB_ADDR { 342097883Sgibbs size 4 342197883Sgibbs } 342297883Sgibbs /* 342397883Sgibbs * head of list of SCBs that have 342497883Sgibbs * completed but have not been 342597883Sgibbs * put into the qoutfifo. 342697883Sgibbs */ 342797883Sgibbs COMPLETE_SCB_HEAD { 342897883Sgibbs size 2 342997883Sgibbs } 343097883Sgibbs /* 343197883Sgibbs * The list of completed SCBs in 343297883Sgibbs * the active DMA. 343397883Sgibbs */ 343497883Sgibbs COMPLETE_SCB_DMAINPROG_HEAD { 343597883Sgibbs size 2 343697883Sgibbs } 343797883Sgibbs /* 343897883Sgibbs * head of list of SCBs that have 343997883Sgibbs * completed but need to be uploaded 344097883Sgibbs * to the host prior to being completed. 344197883Sgibbs */ 344297883Sgibbs COMPLETE_DMA_SCB_HEAD { 344397883Sgibbs size 2 344497883Sgibbs } 344597883Sgibbs /* Counting semaphore to prevent new select-outs */ 344697883Sgibbs QFREEZE_COUNT { 344797883Sgibbs size 2 344897883Sgibbs } 344997883Sgibbs /* 345097883Sgibbs * Mode to restore on idle_loop exit. 345197883Sgibbs */ 345297883Sgibbs SAVED_MODE { 345397883Sgibbs size 1 345497883Sgibbs } 345597883Sgibbs /* 345697883Sgibbs * Single byte buffer used to designate the type or message 345797883Sgibbs * to send to a target. 345897883Sgibbs */ 345997883Sgibbs MSG_OUT { 346097883Sgibbs size 1 346197883Sgibbs } 346297883Sgibbs /* Parameters for DMA Logic */ 346397883Sgibbs DMAPARAMS { 346497883Sgibbs size 1 3465102681Sgibbs field PRELOADEN 0x80 3466102681Sgibbs field WIDEODD 0x40 3467102681Sgibbs field SCSIEN 0x20 3468102681Sgibbs field SDMAEN 0x10 3469102681Sgibbs field SDMAENACK 0x10 3470102681Sgibbs field HDMAEN 0x08 3471102681Sgibbs field HDMAENACK 0x08 3472102681Sgibbs field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3473102681Sgibbs field FIFOFLUSH 0x02 3474102681Sgibbs field FIFORESET 0x01 347597883Sgibbs } 347697883Sgibbs SEQ_FLAGS { 347797883Sgibbs size 1 3478102681Sgibbs field NOT_IDENTIFIED 0x80 3479104023Sgibbs field NO_CDB_SENT 0x40 3480102681Sgibbs field TARGET_CMD_IS_TAGGED 0x40 3481102681Sgibbs field DPHASE 0x20 348297883Sgibbs /* Target flags */ 3483102681Sgibbs field TARG_CMD_PENDING 0x10 3484102681Sgibbs field CMDPHASE_PENDING 0x08 3485102681Sgibbs field DPHASE_PENDING 0x04 3486102681Sgibbs field SPHASE_PENDING 0x02 3487102681Sgibbs field NO_DISCONNECT 0x01 348897883Sgibbs } 348997883Sgibbs /* 349097883Sgibbs * Temporary storage for the 349197883Sgibbs * target/channel/lun of a 349297883Sgibbs * reconnecting target 349397883Sgibbs */ 349497883Sgibbs SAVED_SCSIID { 349597883Sgibbs size 1 349697883Sgibbs } 349797883Sgibbs SAVED_LUN { 349897883Sgibbs size 1 349997883Sgibbs } 350097883Sgibbs /* 350197883Sgibbs * The last bus phase as seen by the sequencer. 350297883Sgibbs */ 350397883Sgibbs LASTPHASE { 350497883Sgibbs size 1 3505102681Sgibbs field CDI 0x80 3506102681Sgibbs field IOI 0x40 3507102681Sgibbs field MSGI 0x20 3508104023Sgibbs field P_BUSFREE 0x01 3509102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 3510102681Sgibbs P_DATAOUT 0x0, 3511102681Sgibbs P_DATAIN IOO, 3512102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 3513102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 3514102681Sgibbs P_COMMAND CDO, 3515102681Sgibbs P_MESGOUT CDO|MSGO, 3516102681Sgibbs P_STATUS CDO|IOO, 3517104023Sgibbs P_MESGIN CDO|IOO|MSGO 3518102681Sgibbs } 351997883Sgibbs } 352097883Sgibbs /* 352197883Sgibbs * Base address of our shared data with the kernel driver in host 352297883Sgibbs * memory. This includes the qoutfifo and target mode 352397883Sgibbs * incoming command queue. 352497883Sgibbs */ 352597883Sgibbs SHARED_DATA_ADDR { 352697883Sgibbs size 4 352797883Sgibbs } 352897883Sgibbs /* 352997883Sgibbs * Pointer to location in host memory for next 353097883Sgibbs * position in the qoutfifo. 353197883Sgibbs */ 353297883Sgibbs QOUTFIFO_NEXT_ADDR { 353397883Sgibbs size 4 353497883Sgibbs } 353597883Sgibbs /* 3536102681Sgibbs * Value to "or" into the SCBPTR[1] value to 3537102681Sgibbs * indicate that an entry in the QINFIFO is valid. 3538102681Sgibbs */ 3539102681Sgibbs QOUTFIFO_ENTRY_VALID_TAG { 3540102681Sgibbs size 1 3541102681Sgibbs } 3542102681Sgibbs /* 354397883Sgibbs * Kernel and sequencer offsets into the queue of 354497883Sgibbs * incoming target mode command descriptors. The 354597883Sgibbs * queue is full when the KERNEL_TQINPOS == TQINPOS. 354697883Sgibbs */ 354797883Sgibbs KERNEL_TQINPOS { 354897883Sgibbs size 1 354997883Sgibbs } 355097883Sgibbs TQINPOS { 355197883Sgibbs size 1 355297883Sgibbs } 355397883Sgibbs ARG_1 { 355497883Sgibbs size 1 355597883Sgibbs mask SEND_MSG 0x80 355697883Sgibbs mask SEND_SENSE 0x40 355797883Sgibbs mask SEND_REJ 0x20 355897883Sgibbs mask MSGOUT_PHASEMIS 0x10 355997883Sgibbs mask EXIT_MSG_LOOP 0x08 356097883Sgibbs mask CONT_MSG_LOOP_WRITE 0x04 356197883Sgibbs mask CONT_MSG_LOOP_READ 0x03 356297883Sgibbs mask CONT_MSG_LOOP_TARG 0x02 356397883Sgibbs alias RETURN_1 356497883Sgibbs } 356597883Sgibbs ARG_2 { 356697883Sgibbs size 1 356797883Sgibbs alias RETURN_2 356897883Sgibbs } 356997883Sgibbs 357097883Sgibbs /* 357197883Sgibbs * Snapshot of MSG_OUT taken after each message is sent. 357297883Sgibbs */ 357397883Sgibbs LAST_MSG { 357497883Sgibbs size 1 357597883Sgibbs } 357697883Sgibbs 357797883Sgibbs /* 357897883Sgibbs * Sequences the kernel driver has okayed for us. This allows 357997883Sgibbs * the driver to do things like prevent initiator or target 358097883Sgibbs * operations. 358197883Sgibbs */ 358297883Sgibbs SCSISEQ_TEMPLATE { 358397883Sgibbs size 1 3584102681Sgibbs field MANUALCTL 0x40 3585102681Sgibbs field ENSELI 0x20 3586102681Sgibbs field ENRSELI 0x10 3587102681Sgibbs field MANUALP 0x0C 3588102681Sgibbs field ENAUTOATNP 0x02 3589102681Sgibbs field ALTSTIM 0x01 359097883Sgibbs } 359197883Sgibbs 359297883Sgibbs /* 359397883Sgibbs * The initiator specified tag for this target mode transaction. 359497883Sgibbs */ 359597883Sgibbs INITIATOR_TAG { 359697883Sgibbs size 1 359797883Sgibbs } 359897883Sgibbs 359997883Sgibbs SEQ_FLAGS2 { 360097883Sgibbs size 1 3601102681Sgibbs field TARGET_MSG_PENDING 0x02 3602102681Sgibbs field SELECTOUT_QFROZEN 0x04 360397883Sgibbs } 3604104023Sgibbs 3605104023Sgibbs ALLOCFIFO_SCBPTR { 3606104023Sgibbs size 2 3607104023Sgibbs } 3608104023Sgibbs 360997883Sgibbs /* 361097883Sgibbs * Target-mode CDB type to CDB length table used 361197883Sgibbs * in non-packetized operation. 361297883Sgibbs */ 361397883Sgibbs CMDSIZE_TABLE { 361497883Sgibbs size 8 361597883Sgibbs } 361697883Sgibbs} 361797883Sgibbs 361897883Sgibbs/************************* Hardware SCB Definition ****************************/ 361997883Sgibbsscb { 362097883Sgibbs address 0x180 362197883Sgibbs size 64 362297883Sgibbs modes 0, 1, 2, 3 362397883Sgibbs SCB_RESIDUAL_DATACNT { 362497883Sgibbs size 4 362597883Sgibbs alias SCB_CDB_STORE 362697883Sgibbs } 362797883Sgibbs SCB_RESIDUAL_SGPTR { 362897883Sgibbs size 4 362997883Sgibbs alias SCB_CDB_PTR 3630102681Sgibbs field SG_ADDR_MASK 0xf8 /* In the last byte */ 3631102681Sgibbs field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3632102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 363397883Sgibbs } 363497883Sgibbs SCB_SCSI_STATUS { 363597883Sgibbs size 1 363697883Sgibbs } 363797883Sgibbs SCB_TARGET_PHASES { 363897883Sgibbs size 1 363997883Sgibbs } 364097883Sgibbs SCB_TARGET_DATA_DIR { 364197883Sgibbs size 1 364297883Sgibbs } 364397883Sgibbs SCB_TARGET_ITAG { 364497883Sgibbs size 1 364597883Sgibbs } 364697883Sgibbs SCB_SENSE_BUSADDR { 364797883Sgibbs /* 364897883Sgibbs * Only valid if CDB length is less than 13 bytes or 364997883Sgibbs * we are using a CDB pointer. Otherwise contains 365097883Sgibbs * the last 4 bytes of embedded cdb information. 365197883Sgibbs */ 365297883Sgibbs size 4 365397883Sgibbs alias SCB_NEXT_COMPLETE 365497883Sgibbs } 3655104023Sgibbs SCB_TAG { 3656104023Sgibbs size 2 3657104023Sgibbs } 365897883Sgibbs SCB_CDB_LEN { 365997883Sgibbs size 1 3660102681Sgibbs field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 366197883Sgibbs } 366297883Sgibbs SCB_TASK_MANAGEMENT { 366397883Sgibbs size 1 366497883Sgibbs } 366597883Sgibbs SCB_NEXT { 366697883Sgibbs alias SCB_NEXT_SCB_BUSADDR 366797883Sgibbs size 2 366897883Sgibbs } 366997883Sgibbs SCB_NEXT2 { 367097883Sgibbs size 2 367197883Sgibbs } 367297883Sgibbs SCB_DATAPTR { 367397883Sgibbs size 8 367497883Sgibbs } 367597883Sgibbs SCB_DATACNT { 367697883Sgibbs /* 367797883Sgibbs * The last byte is really the high address bits for 367897883Sgibbs * the data address. 367997883Sgibbs */ 368097883Sgibbs size 4 3681102681Sgibbs field SG_LAST_SEG 0x80 /* In the fourth byte */ 3682102681Sgibbs field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 368397883Sgibbs } 368497883Sgibbs SCB_SGPTR { 368597883Sgibbs size 4 3686102681Sgibbs field SG_STATUS_VALID 0x04 /* In the first byte */ 3687102681Sgibbs field SG_FULL_RESID 0x02 /* In the first byte */ 3688102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 368997883Sgibbs } 369097883Sgibbs SCB_CONTROL { 369197883Sgibbs size 1 3692102681Sgibbs field TARGET_SCB 0x80 3693102681Sgibbs field DISCENB 0x40 3694102681Sgibbs field TAG_ENB 0x20 3695102681Sgibbs field MK_MESSAGE 0x10 3696102681Sgibbs field STATUS_RCVD 0x08 3697102681Sgibbs field DISCONNECTED 0x04 3698102681Sgibbs field SCB_TAG_TYPE 0x03 369997883Sgibbs } 370097883Sgibbs SCB_SCSIID { 370197883Sgibbs size 1 3702102681Sgibbs field TID 0xF0 3703102681Sgibbs field OID 0x0F 370497883Sgibbs } 370597883Sgibbs SCB_LUN { 370697883Sgibbs size 1 3707102681Sgibbs field LID 0xff 370897883Sgibbs } 370997883Sgibbs SCB_TASK_ATTRIBUTE { 371097883Sgibbs size 1 371197883Sgibbs } 371297883Sgibbs SCB_BUSADDR { 371397883Sgibbs size 4 371497883Sgibbs } 3715102681Sgibbs SCB_SPARE { 3716102681Sgibbs size 8 3717102681Sgibbs alias SCB_PKT_LUN 3718102681Sgibbs } 371997883Sgibbs SCB_DISCONNECTED_LISTS { 3720102681Sgibbs size 8 372197883Sgibbs } 372297883Sgibbs} 372397883Sgibbs 372497883Sgibbs/*********************************** Constants ********************************/ 372597883Sgibbsconst SEQ_STACK_SIZE 8 372697883Sgibbsconst MK_MESSAGE_BIT_OFFSET 4 372797883Sgibbsconst TID_SHIFT 4 372897883Sgibbsconst TARGET_CMD_CMPLT 0xfe 372997883Sgibbsconst INVALID_ADDR 0x80 373097883Sgibbs#define SCB_LIST_NULL 0xff 3731102681Sgibbs#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 373297883Sgibbs 373397883Sgibbsconst CCSGADDR_MAX 0x80 373497883Sgibbsconst CCSCBADDR_MAX 0x80 373597883Sgibbsconst CCSGRAM_MAXSEGS 16 373697883Sgibbs 373797883Sgibbs/* Selection Timeout Timer Constants */ 373897883Sgibbsconst STIMESEL_SHIFT 3 373997883Sgibbsconst STIMESEL_MIN 0x18 374097883Sgibbsconst STIMESEL_BUG_ADJ 0x8 374197883Sgibbs 374297883Sgibbs/* WDTR Message values */ 374397883Sgibbsconst BUS_8_BIT 0x00 374497883Sgibbsconst BUS_16_BIT 0x01 374597883Sgibbsconst BUS_32_BIT 0x02 374697883Sgibbs 374797883Sgibbs/* Offset maximums */ 374897883Sgibbsconst MAX_OFFSET 0xfe 374997883Sgibbsconst MAX_OFFSET_PACED 0x7f 375097883Sgibbsconst HOST_MSG 0xff 375197883Sgibbs 375297883Sgibbs/* 375397883Sgibbs * The size of our sense buffers. 375497883Sgibbs * Sense buffer mapping can be handled in either of two ways. 375597883Sgibbs * The first is to allocate a dmamap for each transaction. 375697883Sgibbs * Depending on the architecture, dmamaps can be costly. The 375797883Sgibbs * alternative is to statically map the buffers in much the same 375897883Sgibbs * way we handle our scatter gather lists. The driver implements 375997883Sgibbs * the later. 376097883Sgibbs */ 376197883Sgibbsconst AHD_SENSE_BUFSIZE 256 376297883Sgibbs 376397883Sgibbs/* Target mode command processing constants */ 376497883Sgibbsconst CMD_GROUP_CODE_SHIFT 0x05 376597883Sgibbs 376697883Sgibbsconst STATUS_BUSY 0x08 376797883Sgibbsconst STATUS_QUEUE_FULL 0x28 376897883Sgibbsconst STATUS_PKT_SENSE 0xFF 376997883Sgibbsconst TARGET_DATA_IN 1 377097883Sgibbs 3771102681Sgibbsconst SCB_TRANSFER_SIZE_FULL_LUN 56 3772102681Sgibbsconst SCB_TRANSFER_SIZE_1BYTE_LUN 48 377397883Sgibbs/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 377497883Sgibbsconst PKT_OVERRUN_BUFSIZE 512 377597883Sgibbs 377697883Sgibbs/* 377797883Sgibbs * Downloaded (kernel inserted) constants 377897883Sgibbs */ 377997883Sgibbsconst SG_PREFETCH_CNT download 378097883Sgibbsconst SG_PREFETCH_CNT_LIMIT download 378197883Sgibbsconst SG_PREFETCH_ALIGN_MASK download 378297883Sgibbsconst SG_PREFETCH_ADDR_MASK download 378397883Sgibbsconst SG_SIZEOF download 378497883Sgibbsconst PKT_OVERRUN_BUFOFFSET download 3785102681Sgibbsconst SCB_TRANSFER_SIZE download 378697883Sgibbs 378797883Sgibbs/* 378897883Sgibbs * BIOS SCB offsets 378997883Sgibbs */ 379097883Sgibbsconst NVRAM_SCB_OFFSET 0x2C 3791