aic79xx.reg revision 102681
197883Sgibbs/* 297883Sgibbs * Aic79xx register and scratch ram definitions. 397883Sgibbs * 497883Sgibbs * Copyright (c) 1994-2001 Justin T. Gibbs. 5102681Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 697883Sgibbs * All rights reserved. 797883Sgibbs * 897883Sgibbs * Redistribution and use in source and binary forms, with or without 997883Sgibbs * modification, are permitted provided that the following conditions 1097883Sgibbs * are met: 1197883Sgibbs * 1. Redistributions of source code must retain the above copyright 1297883Sgibbs * notice, this list of conditions, and the following disclaimer, 1397883Sgibbs * without modification. 1497883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1597883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1697883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1797883Sgibbs * including a substantially similar Disclaimer requirement for further 1897883Sgibbs * binary redistribution. 1997883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2097883Sgibbs * of any contributors may be used to endorse or promote products derived 2197883Sgibbs * from this software without specific prior written permission. 2297883Sgibbs * 2397883Sgibbs * Alternatively, this software may be distributed under the terms of the 2497883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2597883Sgibbs * Software Foundation. 2697883Sgibbs * 2797883Sgibbs * NO WARRANTY 2897883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2997883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3097883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3197883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3297883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3397883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3497883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3597883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3697883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3797883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3897883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3997883Sgibbs * 4097883Sgibbs * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.reg 102681 2002-08-31 06:49:11Z gibbs $ 4197883Sgibbs */ 42102681SgibbsVERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#39 $" 4397883Sgibbs 4497883Sgibbs/* 4597883Sgibbs * This file is processed by the aic7xxx_asm utility for use in assembling 4697883Sgibbs * firmware for the aic79xx family of SCSI host adapters as well as to generate 4797883Sgibbs * a C header file for use in the kernel portion of the Aic79xx driver. 4897883Sgibbs */ 4997883Sgibbs 5097883Sgibbs/* Register window Modes */ 5197883Sgibbs#define M_DFF0 0 5297883Sgibbs#define M_DFF1 1 5397883Sgibbs#define M_CCHAN 2 5497883Sgibbs#define M_SCSI 3 5597883Sgibbs#define M_CFG 4 5697883Sgibbs#define M_DST_SHIFT 4 5797883Sgibbs 5897883Sgibbs#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 5997883Sgibbs#define SET_MODE(src, dst) \ 6097883Sgibbs SET_SRC_MODE src; \ 6197883Sgibbs SET_DST_MODE dst; \ 6297883Sgibbs mvi MK_MODE(src, dst) call set_mode_work_around 6397883Sgibbs 6497883Sgibbs/* 6597883Sgibbs * Mode Pointer 6697883Sgibbs * Controls which of the 5, 512byte, address spaces should be used 6797883Sgibbs * as the source and destination of any register accesses in our 6897883Sgibbs * register window. 6997883Sgibbs */ 7097883Sgibbsregister MODE_PTR { 7197883Sgibbs address 0x000 7297883Sgibbs access_mode RW 73102681Sgibbs field DST_MODE 0x70 74102681Sgibbs field SRC_MODE 0x07 7597883Sgibbs mode_pointer 7697883Sgibbs} 7797883Sgibbs 7897883Sgibbsconst SRC_MODE_SHIFT 0 7997883Sgibbsconst DST_MODE_SHIFT 4 8097883Sgibbs 8197883Sgibbs/* 8297883Sgibbs * Host Interrupt Status 8397883Sgibbs */ 8497883Sgibbsregister INTSTAT { 8597883Sgibbs address 0x001 8697883Sgibbs access_mode RW 87102681Sgibbs field HWERRINT 0x80 88102681Sgibbs field BRKADRINT 0x40 89102681Sgibbs field SWTMINT 0x20 90102681Sgibbs field PCIINT 0x10 91102681Sgibbs field SCSIINT 0x08 92102681Sgibbs field SEQINT 0x04 93102681Sgibbs field CMDCMPLT 0x02 94102681Sgibbs field SPLTINT 0x01 9597883Sgibbs mask INT_PEND 0xFF 9697883Sgibbs} 9797883Sgibbs 9897883Sgibbs/* 9997883Sgibbs * Sequencer Interrupt Code 10097883Sgibbs */ 10197883Sgibbsregister SEQINTCODE { 10297883Sgibbs address 0x002 10397883Sgibbs access_mode RW 104102681Sgibbs field { 105102681Sgibbs BAD_PHASE 1, /* unknown scsi bus phase */ 106102681Sgibbs SEND_REJECT, /* sending a message reject */ 107102681Sgibbs PROTO_VIOLATION, /* Protocol Violation */ 108102681Sgibbs NO_MATCH, /* no cmd match for reconnect */ 109102681Sgibbs IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 110102681Sgibbs PDATA_REINIT, /* 11197883Sgibbs * Returned to data phase 11297883Sgibbs * that requires data 11397883Sgibbs * transfer pointers to be 11497883Sgibbs * recalculated from the 11597883Sgibbs * transfer residual. 11697883Sgibbs */ 117102681Sgibbs HOST_MSG_LOOP, /* 11897883Sgibbs * The bus is ready for the 11997883Sgibbs * host to perform another 12097883Sgibbs * message transaction. This 12197883Sgibbs * mechanism is used for things 12297883Sgibbs * like sync/wide negotiation 12397883Sgibbs * that require a kernel based 12497883Sgibbs * message state engine. 12597883Sgibbs */ 126102681Sgibbs BAD_STATUS, /* Bad status from target */ 127102681Sgibbs DATA_OVERRUN, /* 12897883Sgibbs * Target attempted to write 12997883Sgibbs * beyond the bounds of its 13097883Sgibbs * command. 13197883Sgibbs */ 132102681Sgibbs MKMSG_FAILED, /* 13397883Sgibbs * Target completed command 13497883Sgibbs * without honoring our ATN 13597883Sgibbs * request to issue a message. 13697883Sgibbs */ 137102681Sgibbs MISSED_BUSFREE, /* 13897883Sgibbs * The sequencer never saw 13997883Sgibbs * the bus go free after 14097883Sgibbs * either a command complete 14197883Sgibbs * or disconnect message. 14297883Sgibbs */ 143102681Sgibbs DUMP_CARD_STATE, 144102681Sgibbs ILLEGAL_PHASE, 145102681Sgibbs INVALID_SEQINT, 146102681Sgibbs CFG4ISTAT_INTR, 147102681Sgibbs STATUS_OVERRUN, 148102681Sgibbs CFG4OVERRUN, 149102681Sgibbs ENTERING_NONPACK 150102681Sgibbs } 15197883Sgibbs} 15297883Sgibbs 15397883Sgibbs/* 15497883Sgibbs * Clear Host Interrupt 15597883Sgibbs */ 15697883Sgibbsregister CLRINT { 15797883Sgibbs address 0x003 15897883Sgibbs access_mode WO 159102681Sgibbs field CLRHWERRINT 0x80 /* Rev B or greater */ 160102681Sgibbs field CLRBRKADRINT 0x40 161102681Sgibbs field CLRSWTMINT 0x20 162102681Sgibbs field CLRSCSIINT 0x08 163102681Sgibbs field CLRSEQINT 0x04 164102681Sgibbs field CLRCMDINT 0x02 165102681Sgibbs field CLRSPLTINT 0x01 16697883Sgibbs} 16797883Sgibbs 16897883Sgibbs/* 16997883Sgibbs * Error Register 17097883Sgibbs */ 17197883Sgibbsregister ERROR { 17297883Sgibbs address 0x004 17397883Sgibbs access_mode RO 174102681Sgibbs field CIOPARERR 0x80 175102681Sgibbs field CIOACCESFAIL 0x40 /* Rev B or greater */ 176102681Sgibbs field MPARERR 0x20 177102681Sgibbs field DPARERR 0x10 178102681Sgibbs field SQPARERR 0x08 179102681Sgibbs field ILLOPCODE 0x04 180102681Sgibbs field DSCTMOUT 0x02 18197883Sgibbs} 18297883Sgibbs 18397883Sgibbs/* 18497883Sgibbs * Clear Error 18597883Sgibbs */ 18697883Sgibbsregister CLRERR { 18797883Sgibbs address 0x004 18897883Sgibbs access_mode WO 189102681Sgibbs field CLRCIOPARERR 0x80 190102681Sgibbs field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 191102681Sgibbs field CLRMPARERR 0x20 192102681Sgibbs field CLRDPARERR 0x10 193102681Sgibbs field CLRSQPARERR 0x08 194102681Sgibbs field CLRILLOPCODE 0x04 195102681Sgibbs field CLRDSCTMOUT 0x02 19697883Sgibbs} 19797883Sgibbs 19897883Sgibbs/* 19997883Sgibbs * Host Control Register 20097883Sgibbs * Overall host control of the device. 20197883Sgibbs */ 20297883Sgibbsregister HCNTRL { 20397883Sgibbs address 0x005 20497883Sgibbs access_mode RW 205102681Sgibbs field SEQ_RESET 0x80 /* Rev B or greater */ 206102681Sgibbs field POWRDN 0x40 207102681Sgibbs field SWINT 0x10 208102681Sgibbs field SWTIMER_START_B 0x08 /* Rev B or greater */ 209102681Sgibbs field PAUSE 0x04 210102681Sgibbs field INTEN 0x02 211102681Sgibbs field CHIPRST 0x01 212102681Sgibbs field CHIPRSTACK 0x01 21397883Sgibbs} 21497883Sgibbs 21597883Sgibbs/* 21697883Sgibbs * Host New SCB Queue Offset 21797883Sgibbs */ 21897883Sgibbsregister HNSCB_QOFF { 21997883Sgibbs address 0x006 22097883Sgibbs access_mode RW 22197883Sgibbs size 2 22297883Sgibbs} 22397883Sgibbs 22497883Sgibbs/* 22597883Sgibbs * Host Empty SCB Queue Offset 22697883Sgibbs */ 22797883Sgibbsregister HESCB_QOFF { 22897883Sgibbs address 0x008 22997883Sgibbs access_mode RW 23097883Sgibbs} 23197883Sgibbs 23297883Sgibbs/* 23397883Sgibbs * Host Mailbox 23497883Sgibbs */ 23597883Sgibbsregister HS_MAILBOX { 23697883Sgibbs address 0x0B 23797883Sgibbs access_mode RW 23897883Sgibbs mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 23997883Sgibbs} 24097883Sgibbs 24197883Sgibbs/* 24297883Sgibbs * Sequencer Interupt Status 24397883Sgibbs */ 24497883Sgibbsregister SEQINTSTAT { 24597883Sgibbs address 0x0C 24697883Sgibbs access_mode RO 247102681Sgibbs field SEQ_SWTMRTO 0x10 248102681Sgibbs field SEQ_SEQINT 0x08 249102681Sgibbs field SEQ_SCSIINT 0x04 250102681Sgibbs field SEQ_PCIINT 0x02 251102681Sgibbs field SEQ_SPLTINT 0x01 25297883Sgibbs} 25397883Sgibbs 25497883Sgibbs/* 25597883Sgibbs * Clear SEQ Interrupt 25697883Sgibbs */ 25797883Sgibbsregister CLRSEQINTSTAT { 25897883Sgibbs address 0x0C0 25997883Sgibbs access_mode WO 260102681Sgibbs field CLRSEQ_SWTMRTO 0x10 261102681Sgibbs field CLRSEQ_SEQINT 0x08 262102681Sgibbs field CLRSEQ_SCSIINT 0x04 263102681Sgibbs field CLRSEQ_PCIINT 0x02 264102681Sgibbs field CLRSEQ_SPLTINT 0x01 26597883Sgibbs} 26697883Sgibbs 26797883Sgibbs/* 26897883Sgibbs * Software Timer 26997883Sgibbs */ 27097883Sgibbsregister SWTIMER { 27197883Sgibbs address 0x0E0 27297883Sgibbs access_mode RW 27397883Sgibbs size 2 27497883Sgibbs} 27597883Sgibbs 27697883Sgibbs/* 27797883Sgibbs * SEQ New SCB Queue Offset 27897883Sgibbs */ 27997883Sgibbsregister SNSCB_QOFF { 28097883Sgibbs address 0x010 28197883Sgibbs access_mode RW 28297883Sgibbs size 2 28397883Sgibbs modes M_CCHAN 28497883Sgibbs} 28597883Sgibbs 28697883Sgibbs/* 28797883Sgibbs * SEQ Empty SCB Queue Offset 28897883Sgibbs */ 28997883Sgibbsregister SESCB_QOFF { 29097883Sgibbs address 0x012 29197883Sgibbs access_mode RW 29297883Sgibbs modes M_CCHAN 29397883Sgibbs} 29497883Sgibbs 29597883Sgibbs/* 29697883Sgibbs * SEQ Done SCB Queue Offset 29797883Sgibbs */ 29897883Sgibbsregister SDSCB_QOFF { 29997883Sgibbs address 0x014 30097883Sgibbs access_mode RW 30197883Sgibbs modes M_CCHAN 30297883Sgibbs size 2 30397883Sgibbs} 30497883Sgibbs 30597883Sgibbs/* 30697883Sgibbs * Queue Offset Control & Status 30797883Sgibbs */ 30897883Sgibbsregister QOFF_CTLSTA { 30997883Sgibbs address 0x016 31097883Sgibbs access_mode RW 31197883Sgibbs modes M_CCHAN 312102681Sgibbs field EMPTY_SCB_AVAIL 0x80 313102681Sgibbs field NEW_SCB_AVAIL 0x40 314102681Sgibbs field SDSCB_ROLLOVR 0x20 315102681Sgibbs field HS_MAILBOX_ACT 0x10 316102681Sgibbs field SCB_QSIZE 0x0F { 317102681Sgibbs SCB_QSIZE_4, 318102681Sgibbs SCB_QSIZE_8, 319102681Sgibbs SCB_QSIZE_16, 320102681Sgibbs SCB_QSIZE_32, 321102681Sgibbs SCB_QSIZE_64, 322102681Sgibbs SCB_QSIZE_128, 323102681Sgibbs SCB_QSIZE_256, 324102681Sgibbs SCB_QSIZE_512, 325102681Sgibbs SCB_QSIZE_1024, 326102681Sgibbs SCB_QSIZE_2048, 327102681Sgibbs SCB_QSIZE_4096, 328102681Sgibbs SCB_QSIZE_8192, 329102681Sgibbs SCB_QSIZE_16384 330102681Sgibbs } 33197883Sgibbs} 33297883Sgibbs 33397883Sgibbs/* 33497883Sgibbs * Interrupt Control 33597883Sgibbs */ 33697883Sgibbsregister INTCTL { 33797883Sgibbs address 0x018 33897883Sgibbs access_mode RW 339102681Sgibbs field SWTMINTMASK 0x80 340102681Sgibbs field SWTMINTEN 0x40 341102681Sgibbs field SWTIMER_START 0x20 342102681Sgibbs field AUTOCLRCMDINT 0x10 343102681Sgibbs field PCIINTEN 0x08 344102681Sgibbs field SCSIINTEN 0x04 345102681Sgibbs field SEQINTEN 0x02 346102681Sgibbs field SPLTINTEN 0x01 34797883Sgibbs} 34897883Sgibbs 34997883Sgibbs/* 35097883Sgibbs * Data FIFO Control 35197883Sgibbs */ 35297883Sgibbsregister DFCNTRL { 35397883Sgibbs address 0x019 35497883Sgibbs access_mode RW 35597883Sgibbs modes M_DFF0, M_DFF1 356102681Sgibbs field PRELOADEN 0x80 357102681Sgibbs field SCSIEN 0x20 358102681Sgibbs field SCSIENACK 0x20 359102681Sgibbs field HDMAEN 0x08 360102681Sgibbs field HDMAENACK 0x08 361102681Sgibbs field DIRECTION 0x04 362102681Sgibbs field DIRECTIONACK 0x04 363102681Sgibbs field FIFOFLUSH 0x02 364102681Sgibbs field FIFOFLUSHACK 0x02 365102681Sgibbs field DIRECTIONEN 0x01 36697883Sgibbs} 36797883Sgibbs 36897883Sgibbs/* 36997883Sgibbs * Device Space Command 0 37097883Sgibbs */ 37197883Sgibbsregister DSCOMMAND0 { 37297883Sgibbs address 0x019 37397883Sgibbs access_mode RW 37497883Sgibbs modes M_CFG 375102681Sgibbs field CACHETHEN 0x80 /* Cache Threshold enable */ 376102681Sgibbs field DPARCKEN 0x40 /* Data Parity Check Enable */ 377102681Sgibbs field MPARCKEN 0x20 /* Memory Parity Check Enable */ 378102681Sgibbs field EXTREQLCK 0x10 /* External Request Lock */ 379102681Sgibbs field DISABLE_TWATE 0x02 /* Rev B or greater */ 380102681Sgibbs field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 38197883Sgibbs} 38297883Sgibbs 38397883Sgibbs/* 38497883Sgibbs * Data FIFO Status 38597883Sgibbs */ 38697883Sgibbsregister DFSTATUS { 38797883Sgibbs address 0x01A 38897883Sgibbs access_mode RO 38997883Sgibbs modes M_DFF0, M_DFF1 390102681Sgibbs field PRELOAD_AVAIL 0x80 391102681Sgibbs field PKT_PRELOAD_AVAIL 0x40 392102681Sgibbs field MREQPEND 0x10 393102681Sgibbs field HDONE 0x08 394102681Sgibbs field DFTHRESH 0x04 395102681Sgibbs field FIFOFULL 0x02 396102681Sgibbs field FIFOEMP 0x01 39797883Sgibbs} 39897883Sgibbs 39997883Sgibbs/* 40097883Sgibbs * S/G Cache Pointer 40197883Sgibbs */ 40297883Sgibbsregister SG_CACHE_PRE { 40397883Sgibbs address 0x01B 40497883Sgibbs access_mode WO 40597883Sgibbs modes M_DFF0, M_DFF1 406102681Sgibbs field SG_ADDR_MASK 0xf8 407102681Sgibbs field ODD_SEG 0x04 408102681Sgibbs field LAST_SEG 0x02 40997883Sgibbs} 41097883Sgibbs 41197883Sgibbsregister SG_CACHE_SHADOW { 41297883Sgibbs address 0x01B 41397883Sgibbs access_mode RO 41497883Sgibbs modes M_DFF0, M_DFF1 415102681Sgibbs field SG_ADDR_MASK 0xf8 416102681Sgibbs field ODD_SEG 0x04 417102681Sgibbs field LAST_SEG 0x02 418102681Sgibbs field LAST_SEG_DONE 0x01 41997883Sgibbs} 42097883Sgibbs 42197883Sgibbs/* 42297883Sgibbs * Arbiter Control 42397883Sgibbs */ 42497883Sgibbsregister ARBCTL { 42597883Sgibbs address 0x01B 42697883Sgibbs access_mode RW 42797883Sgibbs modes M_CFG 428102681Sgibbs field RESET_HARB 0x80 429102681Sgibbs field RETRY_SWEN 0x08 430102681Sgibbs field USE_TIME 0x07 43197883Sgibbs} 43297883Sgibbs 43397883Sgibbs/* 43497883Sgibbs * Data Channel Host Address 43597883Sgibbs */ 43697883Sgibbsregister HADDR { 43797883Sgibbs address 0x070 43897883Sgibbs access_mode RW 43997883Sgibbs size 8 44097883Sgibbs modes M_DFF0, M_DFF1 44197883Sgibbs} 44297883Sgibbs 44397883Sgibbs/* 44497883Sgibbs * Host Overlay DMA Address 44597883Sgibbs */ 44697883Sgibbsregister HODMAADR { 44797883Sgibbs address 0x070 44897883Sgibbs access_mode RW 44997883Sgibbs size 8 45097883Sgibbs modes M_SCSI 45197883Sgibbs} 45297883Sgibbs 45397883Sgibbs/* 45497883Sgibbs * Data Channel Host Count 45597883Sgibbs */ 45697883Sgibbsregister HCNT { 45797883Sgibbs address 0x078 45897883Sgibbs access_mode RW 45997883Sgibbs size 3 46097883Sgibbs modes M_DFF0, M_DFF1 46197883Sgibbs} 46297883Sgibbs 46397883Sgibbs/* 46497883Sgibbs * Host Overlay DMA Count 46597883Sgibbs */ 46697883Sgibbsregister HODMACNT { 46797883Sgibbs address 0x078 46897883Sgibbs access_mode RW 46997883Sgibbs size 2 47097883Sgibbs modes M_SCSI 47197883Sgibbs} 47297883Sgibbs 47397883Sgibbs/* 47497883Sgibbs * Host Overlay DMA Enable 47597883Sgibbs */ 47697883Sgibbsregister HODMAEN { 47797883Sgibbs address 0x07A 47897883Sgibbs access_mode RW 47997883Sgibbs modes M_SCSI 48097883Sgibbs} 48197883Sgibbs 48297883Sgibbs/* 48397883Sgibbs * Scatter/Gather Host Address 48497883Sgibbs */ 48597883Sgibbsregister SGHADDR { 48697883Sgibbs address 0x07C 48797883Sgibbs access_mode RW 48897883Sgibbs size 8 48997883Sgibbs modes M_DFF0, M_DFF1 49097883Sgibbs} 49197883Sgibbs 49297883Sgibbs/* 49397883Sgibbs * SCB Host Address 49497883Sgibbs */ 49597883Sgibbsregister SCBHADDR { 49697883Sgibbs address 0x07C 49797883Sgibbs access_mode RW 49897883Sgibbs size 8 49997883Sgibbs modes M_CCHAN 50097883Sgibbs} 50197883Sgibbs 50297883Sgibbs/* 50397883Sgibbs * Scatter/Gather Host Count 50497883Sgibbs */ 50597883Sgibbsregister SGHCNT { 50697883Sgibbs address 0x084 50797883Sgibbs access_mode RW 50897883Sgibbs modes M_DFF0, M_DFF1 50997883Sgibbs} 51097883Sgibbs 51197883Sgibbs/* 51297883Sgibbs * SCB Host Count 51397883Sgibbs */ 51497883Sgibbsregister SCBHCNT { 51597883Sgibbs address 0x084 51697883Sgibbs access_mode RW 51797883Sgibbs modes M_CCHAN 51897883Sgibbs} 51997883Sgibbs 52097883Sgibbs/* 52197883Sgibbs * Data FIFO Threshold 52297883Sgibbs */ 52397883Sgibbsregister DFF_THRSH { 52497883Sgibbs address 0x088 52597883Sgibbs access_mode RW 52697883Sgibbs modes M_CFG 527102681Sgibbs field WR_DFTHRSH 0x70 { 528102681Sgibbs WR_DFTHRSH_MIN, 529102681Sgibbs WR_DFTHRSH_25, 530102681Sgibbs WR_DFTHRSH_50, 531102681Sgibbs WR_DFTHRSH_63, 532102681Sgibbs WR_DFTHRSH_75, 533102681Sgibbs WR_DFTHRSH_85, 534102681Sgibbs WR_DFTHRSH_90, 535102681Sgibbs WR_DFTHRSH_MAX 536102681Sgibbs } 537102681Sgibbs field RD_DFTHRSH 0x07 { 538102681Sgibbs RD_DFTHRSH_MIN, 539102681Sgibbs RD_DFTHRSH_25, 540102681Sgibbs RD_DFTHRSH_50, 541102681Sgibbs RD_DFTHRSH_63, 542102681Sgibbs RD_DFTHRSH_75, 543102681Sgibbs RD_DFTHRSH_85, 544102681Sgibbs RD_DFTHRSH_90, 545102681Sgibbs RD_DFTHRSH_MAX 546102681Sgibbs } 54797883Sgibbs} 54897883Sgibbs 54997883Sgibbs/* 55097883Sgibbs * ROM Address 55197883Sgibbs */ 55297883Sgibbsregister ROMADDR { 55397883Sgibbs address 0x08A 55497883Sgibbs access_mode RW 55597883Sgibbs size 3 55697883Sgibbs} 55797883Sgibbs 55897883Sgibbs/* 55997883Sgibbs * ROM Control 56097883Sgibbs */ 56197883Sgibbsregister ROMCNTRL { 56297883Sgibbs address 0x08D 56397883Sgibbs access_mode RW 564102681Sgibbs field ROMOP 0xE0 565102681Sgibbs field ROMSPD 0x18 566102681Sgibbs field REPEAT 0x02 567102681Sgibbs field RDY 0x01 56897883Sgibbs} 56997883Sgibbs 57097883Sgibbs/* 57197883Sgibbs * ROM Data 57297883Sgibbs */ 57397883Sgibbsregister ROMDATA { 57497883Sgibbs address 0x08E 57597883Sgibbs access_mode RW 57697883Sgibbs} 57797883Sgibbs 57897883Sgibbs/* 57997883Sgibbs * Data Channel Receive Message 0 58097883Sgibbs */ 58197883Sgibbsregister DCHRXMSG0 { 58297883Sgibbs address 0x090 58397883Sgibbs access_mode RO 58497883Sgibbs modes M_DFF0, M_DFF1 585102681Sgibbs field CDNUM 0xF8 586102681Sgibbs field CFNUM 0x07 58797883Sgibbs} 58897883Sgibbs 58997883Sgibbs/* 59097883Sgibbs * CMC Recieve Message 0 59197883Sgibbs */ 59297883Sgibbsregister CMCRXMSG0 { 59397883Sgibbs address 0x090 59497883Sgibbs access_mode RO 59597883Sgibbs modes M_CCHAN 596102681Sgibbs field CDNUM 0xF8 597102681Sgibbs field CFNUM 0x07 59897883Sgibbs} 59997883Sgibbs 60097883Sgibbs/* 60197883Sgibbs * Overlay Recieve Message 0 60297883Sgibbs */ 60397883Sgibbsregister OVLYRXMSG0 { 60497883Sgibbs address 0x090 60597883Sgibbs access_mode RO 60697883Sgibbs modes M_SCSI 607102681Sgibbs field CDNUM 0xF8 608102681Sgibbs field CFNUM 0x07 60997883Sgibbs} 61097883Sgibbs 61197883Sgibbs/* 61297883Sgibbs * Relaxed Order Enable 61397883Sgibbs */ 61497883Sgibbsregister ROENABLE { 61597883Sgibbs address 0x090 61697883Sgibbs access_mode RW 61797883Sgibbs modes M_CFG 618102681Sgibbs field MSIROEN 0x20 619102681Sgibbs field OVLYROEN 0x10 620102681Sgibbs field CMCROEN 0x08 621102681Sgibbs field SGROEN 0x04 622102681Sgibbs field DCH1ROEN 0x02 623102681Sgibbs field DCH0ROEN 0x01 62497883Sgibbs} 62597883Sgibbs 62697883Sgibbs/* 62797883Sgibbs * Data Channel Receive Message 1 62897883Sgibbs */ 62997883Sgibbsregister DCHRXMSG1 { 63097883Sgibbs address 0x091 63197883Sgibbs access_mode RO 63297883Sgibbs modes M_DFF0, M_DFF1 633102681Sgibbs field CBNUM 0xFF 63497883Sgibbs} 63597883Sgibbs 63697883Sgibbs/* 63797883Sgibbs * CMC Recieve Message 1 63897883Sgibbs */ 63997883Sgibbsregister CMCRXMSG1 { 64097883Sgibbs address 0x091 64197883Sgibbs access_mode RO 64297883Sgibbs modes M_CCHAN 643102681Sgibbs field CBNUM 0xFF 64497883Sgibbs} 64597883Sgibbs 64697883Sgibbs/* 64797883Sgibbs * Overlay Recieve Message 1 64897883Sgibbs */ 64997883Sgibbsregister OVLYRXMSG1 { 65097883Sgibbs address 0x091 65197883Sgibbs access_mode RO 65297883Sgibbs modes M_SCSI 653102681Sgibbs field CBNUM 0xFF 65497883Sgibbs} 65597883Sgibbs 65697883Sgibbs/* 65797883Sgibbs * No Snoop Enable 65897883Sgibbs */ 65997883Sgibbsregister NSENABLE { 66097883Sgibbs address 0x091 66197883Sgibbs access_mode RW 66297883Sgibbs modes M_CFG 663102681Sgibbs field MSINSEN 0x20 664102681Sgibbs field OVLYNSEN 0x10 665102681Sgibbs field CMCNSEN 0x08 666102681Sgibbs field SGNSEN 0x04 667102681Sgibbs field DCH1NSEN 0x02 668102681Sgibbs field DCH0NSEN 0x01 66997883Sgibbs} 67097883Sgibbs 67197883Sgibbs/* 67297883Sgibbs * Data Channel Receive Message 2 67397883Sgibbs */ 67497883Sgibbsregister DCHRXMSG2 { 67597883Sgibbs address 0x092 67697883Sgibbs access_mode RO 67797883Sgibbs modes M_DFF0, M_DFF1 678102681Sgibbs field MINDEX 0xFF 67997883Sgibbs} 68097883Sgibbs 68197883Sgibbs/* 68297883Sgibbs * CMC Recieve Message 2 68397883Sgibbs */ 68497883Sgibbsregister CMCRXMSG2 { 68597883Sgibbs address 0x092 68697883Sgibbs access_mode RO 68797883Sgibbs modes M_CCHAN 688102681Sgibbs field MINDEX 0xFF 68997883Sgibbs} 69097883Sgibbs 69197883Sgibbs/* 69297883Sgibbs * Overlay Recieve Message 2 69397883Sgibbs */ 69497883Sgibbsregister OVLYRXMSG2 { 69597883Sgibbs address 0x092 69697883Sgibbs access_mode RO 69797883Sgibbs modes M_SCSI 698102681Sgibbs field MINDEX 0xFF 69997883Sgibbs} 70097883Sgibbs 70197883Sgibbs/* 70297883Sgibbs * Outstanding Split Transactions 70397883Sgibbs */ 70497883Sgibbsregister OST { 70597883Sgibbs address 0x092 70697883Sgibbs access_mode RW 70797883Sgibbs modes M_CFG 70897883Sgibbs} 70997883Sgibbs 71097883Sgibbs/* 71197883Sgibbs * Data Channel Receive Message 3 71297883Sgibbs */ 71397883Sgibbsregister DCHRXMSG3 { 71497883Sgibbs address 0x093 71597883Sgibbs access_mode RO 71697883Sgibbs modes M_DFF0, M_DFF1 717102681Sgibbs field MCLASS 0x0F 71897883Sgibbs} 71997883Sgibbs 72097883Sgibbs/* 72197883Sgibbs * CMC Recieve Message 3 72297883Sgibbs */ 72397883Sgibbsregister CMCRXMSG3 { 72497883Sgibbs address 0x093 72597883Sgibbs access_mode RO 72697883Sgibbs modes M_CCHAN 727102681Sgibbs field MCLASS 0x0F 72897883Sgibbs} 72997883Sgibbs 73097883Sgibbs/* 73197883Sgibbs * Overlay Recieve Message 3 73297883Sgibbs */ 73397883Sgibbsregister OVLYRXMSG3 { 73497883Sgibbs address 0x093 73597883Sgibbs access_mode RO 73697883Sgibbs modes M_SCSI 737102681Sgibbs field MCLASS 0x0F 73897883Sgibbs} 73997883Sgibbs 74097883Sgibbs/* 74197883Sgibbs * PCI-X Control 74297883Sgibbs */ 74397883Sgibbsregister PCIXCTL { 74497883Sgibbs address 0x093 74597883Sgibbs access_mode RW 74697883Sgibbs modes M_CFG 747102681Sgibbs field SERRPULSE 0x80 748102681Sgibbs field UNEXPSCIEN 0x20 749102681Sgibbs field SPLTSMADIS 0x10 750102681Sgibbs field SPLTSTADIS 0x08 751102681Sgibbs field SRSPDPEEN 0x04 752102681Sgibbs field TSCSERREN 0x02 753102681Sgibbs field CMPABCDIS 0x01 75497883Sgibbs} 75597883Sgibbs 75697883Sgibbs/* 75797883Sgibbs * CMC Sequencer Byte Count 75897883Sgibbs */ 75997883Sgibbsregister CMCSEQBCNT { 76097883Sgibbs address 0x094 76197883Sgibbs access_mode RO 76297883Sgibbs modes M_CCHAN 76397883Sgibbs} 76497883Sgibbs 76597883Sgibbs/* 76697883Sgibbs * Overlay Sequencer Byte Count 76797883Sgibbs */ 76897883Sgibbsregister OVLYSEQBCNT { 76997883Sgibbs address 0x094 77097883Sgibbs access_mode RO 77197883Sgibbs modes M_SCSI 77297883Sgibbs} 77397883Sgibbs 77497883Sgibbs/* 77597883Sgibbs * Data Channel Sequencer Byte Count 77697883Sgibbs */ 77797883Sgibbsregister DCHSEQBCNT { 77897883Sgibbs address 0x094 77997883Sgibbs access_mode RO 78097883Sgibbs size 2 78197883Sgibbs modes M_DFF0, M_DFF1 78297883Sgibbs} 78397883Sgibbs 78497883Sgibbs/* 78597883Sgibbs * Data Channel Split Status 0 78697883Sgibbs */ 78797883Sgibbsregister DCHSPLTSTAT0 { 78897883Sgibbs address 0x096 78997883Sgibbs access_mode RW 79097883Sgibbs modes M_DFF0, M_DFF1 791102681Sgibbs field STAETERM 0x80 792102681Sgibbs field SCBCERR 0x40 793102681Sgibbs field SCADERR 0x20 794102681Sgibbs field SCDATBUCKET 0x10 795102681Sgibbs field CNTNOTCMPLT 0x08 796102681Sgibbs field RXOVRUN 0x04 797102681Sgibbs field RXSCEMSG 0x02 798102681Sgibbs field RXSPLTRSP 0x01 79997883Sgibbs} 80097883Sgibbs 80197883Sgibbs/* 80297883Sgibbs * CMC Split Status 0 80397883Sgibbs */ 80497883Sgibbsregister CMCSPLTSTAT0 { 80597883Sgibbs address 0x096 80697883Sgibbs access_mode RW 80797883Sgibbs modes M_CCHAN 808102681Sgibbs field STAETERM 0x80 809102681Sgibbs field SCBCERR 0x40 810102681Sgibbs field SCADERR 0x20 811102681Sgibbs field SCDATBUCKET 0x10 812102681Sgibbs field CNTNOTCMPLT 0x08 813102681Sgibbs field RXOVRUN 0x04 814102681Sgibbs field RXSCEMSG 0x02 815102681Sgibbs field RXSPLTRSP 0x01 81697883Sgibbs} 81797883Sgibbs 81897883Sgibbs/* 81997883Sgibbs * Overlay Split Status 0 82097883Sgibbs */ 82197883Sgibbsregister OVLYSPLTSTAT0 { 82297883Sgibbs address 0x096 82397883Sgibbs access_mode RW 82497883Sgibbs modes M_SCSI 825102681Sgibbs field STAETERM 0x80 826102681Sgibbs field SCBCERR 0x40 827102681Sgibbs field SCADERR 0x20 828102681Sgibbs field SCDATBUCKET 0x10 829102681Sgibbs field CNTNOTCMPLT 0x08 830102681Sgibbs field RXOVRUN 0x04 831102681Sgibbs field RXSCEMSG 0x02 832102681Sgibbs field RXSPLTRSP 0x01 83397883Sgibbs} 83497883Sgibbs 83597883Sgibbs/* 83697883Sgibbs * Data Channel Split Status 1 83797883Sgibbs */ 83897883Sgibbsregister DCHSPLTSTAT1 { 83997883Sgibbs address 0x097 84097883Sgibbs access_mode RW 84197883Sgibbs modes M_DFF0, M_DFF1 842102681Sgibbs field RXDATABUCKET 0x01 84397883Sgibbs} 84497883Sgibbs 84597883Sgibbs/* 84697883Sgibbs * CMC Split Status 1 84797883Sgibbs */ 84897883Sgibbsregister CMCSPLTSTAT1 { 84997883Sgibbs address 0x097 85097883Sgibbs access_mode RW 85197883Sgibbs modes M_CCHAN 852102681Sgibbs field RXDATABUCKET 0x01 85397883Sgibbs} 85497883Sgibbs 85597883Sgibbs/* 85697883Sgibbs * Overlay Split Status 1 85797883Sgibbs */ 85897883Sgibbsregister OVLYSPLTSTAT1 { 85997883Sgibbs address 0x097 86097883Sgibbs access_mode RW 86197883Sgibbs modes M_SCSI 862102681Sgibbs field RXDATABUCKET 0x01 86397883Sgibbs} 86497883Sgibbs 86597883Sgibbs/* 86697883Sgibbs * S/G Receive Message 0 86797883Sgibbs */ 86897883Sgibbsregister SGRXMSG0 { 86997883Sgibbs address 0x098 87097883Sgibbs access_mode RO 87197883Sgibbs modes M_DFF0, M_DFF1 872102681Sgibbs field CDNUM 0xF8 873102681Sgibbs field CFNUM 0x07 87497883Sgibbs} 87597883Sgibbs 87697883Sgibbs/* 87797883Sgibbs * S/G Receive Message 1 87897883Sgibbs */ 87997883Sgibbsregister SGRXMSG1 { 88097883Sgibbs address 0x099 88197883Sgibbs access_mode RO 88297883Sgibbs modes M_DFF0, M_DFF1 883102681Sgibbs field CBNUM 0xFF 88497883Sgibbs} 88597883Sgibbs 88697883Sgibbs/* 88797883Sgibbs * S/G Receive Message 2 88897883Sgibbs */ 88997883Sgibbsregister SGRXMSG2 { 89097883Sgibbs address 0x09A 89197883Sgibbs access_mode RO 89297883Sgibbs modes M_DFF0, M_DFF1 893102681Sgibbs field MINDEX 0xFF 89497883Sgibbs} 89597883Sgibbs 89697883Sgibbs/* 89797883Sgibbs * S/G Receive Message 3 89897883Sgibbs */ 89997883Sgibbsregister SGRXMSG3 { 90097883Sgibbs address 0x09B 90197883Sgibbs access_mode RO 90297883Sgibbs modes M_DFF0, M_DFF1 903102681Sgibbs field MCLASS 0x0F 90497883Sgibbs} 90597883Sgibbs 90697883Sgibbs/* 90797883Sgibbs * Slave Split Out Address 0 90897883Sgibbs */ 90997883Sgibbsregister SLVSPLTOUTADR0 { 91097883Sgibbs address 0x098 91197883Sgibbs access_mode RO 91297883Sgibbs modes M_SCSI 913102681Sgibbs field LOWER_ADDR 0x7F 91497883Sgibbs} 91597883Sgibbs 91697883Sgibbs/* 91797883Sgibbs * Slave Split Out Address 1 91897883Sgibbs */ 91997883Sgibbsregister SLVSPLTOUTADR1 { 92097883Sgibbs address 0x099 92197883Sgibbs access_mode RO 92297883Sgibbs modes M_SCSI 923102681Sgibbs field REQ_DNUM 0xF8 924102681Sgibbs field REQ_FNUM 0x07 92597883Sgibbs} 92697883Sgibbs 92797883Sgibbs/* 92897883Sgibbs * Slave Split Out Address 2 92997883Sgibbs */ 93097883Sgibbsregister SLVSPLTOUTADR2 { 93197883Sgibbs address 0x09A 93297883Sgibbs access_mode RO 93397883Sgibbs modes M_SCSI 934102681Sgibbs field REQ_BNUM 0xFF 93597883Sgibbs} 93697883Sgibbs 93797883Sgibbs/* 93897883Sgibbs * Slave Split Out Address 3 93997883Sgibbs */ 94097883Sgibbsregister SLVSPLTOUTADR3 { 94197883Sgibbs address 0x09B 94297883Sgibbs access_mode RO 94397883Sgibbs modes M_SCSI 944102681Sgibbs field RLXORD 020 945102681Sgibbs field TAG_NUM 0x1F 94697883Sgibbs} 94797883Sgibbs 94897883Sgibbs/* 94997883Sgibbs * SG Sequencer Byte Count 95097883Sgibbs */ 95197883Sgibbsregister SGSEQBCNT { 95297883Sgibbs address 0x09C 95397883Sgibbs access_mode RO 95497883Sgibbs modes M_DFF0, M_DFF1 95597883Sgibbs} 95697883Sgibbs 95797883Sgibbs/* 95897883Sgibbs * Slave Split Out Attribute 0 95997883Sgibbs */ 96097883Sgibbsregister SLVSPLTOUTATTR0 { 96197883Sgibbs address 0x09C 96297883Sgibbs access_mode RO 96397883Sgibbs modes M_SCSI 964102681Sgibbs field LOWER_BCNT 0xFF 96597883Sgibbs} 96697883Sgibbs 96797883Sgibbs/* 96897883Sgibbs * Slave Split Out Attribute 1 96997883Sgibbs */ 97097883Sgibbsregister SLVSPLTOUTATTR1 { 97197883Sgibbs address 0x09D 97297883Sgibbs access_mode RO 97397883Sgibbs modes M_SCSI 974102681Sgibbs field CMPLT_DNUM 0xF8 975102681Sgibbs field CMPLT_FNUM 0x07 97697883Sgibbs} 97797883Sgibbs 97897883Sgibbs/* 97997883Sgibbs * Slave Split Out Attribute 2 98097883Sgibbs */ 98197883Sgibbsregister SLVSPLTOUTATTR2 { 98297883Sgibbs address 0x09E 98397883Sgibbs access_mode RO 98497883Sgibbs size 2 98597883Sgibbs modes M_SCSI 986102681Sgibbs field CMPLT_BNUM 0xFF 98797883Sgibbs} 98897883Sgibbs/* 98997883Sgibbs * S/G Split Status 0 99097883Sgibbs */ 99197883Sgibbsregister SGSPLTSTAT0 { 99297883Sgibbs address 0x09E 99397883Sgibbs access_mode RW 99497883Sgibbs modes M_DFF0, M_DFF1 995102681Sgibbs field STAETERM 0x80 996102681Sgibbs field SCBCERR 0x40 997102681Sgibbs field SCADERR 0x20 998102681Sgibbs field SCDATBUCKET 0x10 999102681Sgibbs field CNTNOTCMPLT 0x08 1000102681Sgibbs field RXOVRUN 0x04 1001102681Sgibbs field RXSCEMSG 0x02 1002102681Sgibbs field RXSPLTRSP 0x01 100397883Sgibbs} 100497883Sgibbs 100597883Sgibbs/* 100697883Sgibbs * S/G Split Status 1 100797883Sgibbs */ 100897883Sgibbsregister SGSPLTSTAT1 { 100997883Sgibbs address 0x09F 101097883Sgibbs access_mode RW 101197883Sgibbs modes M_DFF0, M_DFF1 1012102681Sgibbs field RXDATABUCKET 0x01 101397883Sgibbs} 101497883Sgibbs 101597883Sgibbs/* 101697883Sgibbs * Special Function 101797883Sgibbs */ 101897883Sgibbsregister SFUNCT { 101997883Sgibbs address 0x09f 102097883Sgibbs access_mode RW 102197883Sgibbs modes M_CFG 1022102681Sgibbs field TEST_GROUP 0xF0 1023102681Sgibbs field TEST_NUM 0x0F 102497883Sgibbs} 102597883Sgibbs 102697883Sgibbs/* 102797883Sgibbs * Data FIFO 0 PCI Status 102897883Sgibbs */ 102997883Sgibbsregister DF0PCISTAT { 103097883Sgibbs address 0x0A0 103197883Sgibbs access_mode RW 103297883Sgibbs modes M_CFG 1033102681Sgibbs field DPE 0x80 1034102681Sgibbs field SSE 0x40 1035102681Sgibbs field RMA 0x20 1036102681Sgibbs field RTA 0x10 1037102681Sgibbs field SCAAPERR 0x08 1038102681Sgibbs field RDPERR 0x04 1039102681Sgibbs field TWATERR 0x02 1040102681Sgibbs field DPR 0x01 104197883Sgibbs} 104297883Sgibbs 104397883Sgibbs/* 104497883Sgibbs * Data FIFO 1 PCI Status 104597883Sgibbs */ 104697883Sgibbsregister DF1PCISTAT { 104797883Sgibbs address 0x0A1 104897883Sgibbs access_mode RW 104997883Sgibbs modes M_CFG 1050102681Sgibbs field DPE 0x80 1051102681Sgibbs field SSE 0x40 1052102681Sgibbs field RMA 0x20 1053102681Sgibbs field RTA 0x10 1054102681Sgibbs field SCAAPERR 0x08 1055102681Sgibbs field RDPERR 0x04 1056102681Sgibbs field TWATERR 0x02 1057102681Sgibbs field DPR 0x01 105897883Sgibbs} 105997883Sgibbs 106097883Sgibbs/* 106197883Sgibbs * S/G PCI Status 106297883Sgibbs */ 106397883Sgibbsregister SGPCISTAT { 106497883Sgibbs address 0x0A2 106597883Sgibbs access_mode RW 106697883Sgibbs modes M_CFG 1067102681Sgibbs field DPE 0x80 1068102681Sgibbs field SSE 0x40 1069102681Sgibbs field RMA 0x20 1070102681Sgibbs field RTA 0x10 1071102681Sgibbs field SCAAPERR 0x08 1072102681Sgibbs field RDPERR 0x04 1073102681Sgibbs field DPR 0x01 107497883Sgibbs} 107597883Sgibbs 107697883Sgibbs/* 107797883Sgibbs * CMC PCI Status 107897883Sgibbs */ 107997883Sgibbsregister CMCPCISTAT { 108097883Sgibbs address 0x0A3 108197883Sgibbs access_mode RW 108297883Sgibbs modes M_CFG 1083102681Sgibbs field DPE 0x80 1084102681Sgibbs field SSE 0x40 1085102681Sgibbs field RMA 0x20 1086102681Sgibbs field RTA 0x10 1087102681Sgibbs field SCAAPERR 0x08 1088102681Sgibbs field RDPERR 0x04 1089102681Sgibbs field TWATERR 0x02 1090102681Sgibbs field DPR 0x01 109197883Sgibbs} 109297883Sgibbs 109397883Sgibbs/* 109497883Sgibbs * Overlay PCI Status 109597883Sgibbs */ 109697883Sgibbsregister OVLYPCISTAT { 109797883Sgibbs address 0x0A4 109897883Sgibbs access_mode RW 109997883Sgibbs modes M_CFG 1100102681Sgibbs field DPE 0x80 1101102681Sgibbs field SSE 0x40 1102102681Sgibbs field RMA 0x20 1103102681Sgibbs field RTA 0x10 1104102681Sgibbs field SCAAPERR 0x08 1105102681Sgibbs field RDPERR 0x04 1106102681Sgibbs field DPR 0x01 110797883Sgibbs} 110897883Sgibbs 110997883Sgibbs/* 111097883Sgibbs * PCI Status for MSI Master DMA Transfer 111197883Sgibbs */ 111297883Sgibbsregister MSIPCISTAT { 111397883Sgibbs address 0x0A6 111497883Sgibbs access_mode RW 111597883Sgibbs modes M_CFG 1116102681Sgibbs field SSE 0x40 1117102681Sgibbs field RMA 0x20 1118102681Sgibbs field RTA 0x10 1119102681Sgibbs field CLRPENDMSI 0x08 1120102681Sgibbs field TWATERR 0x02 1121102681Sgibbs field DPR 0x01 112297883Sgibbs} 112397883Sgibbs 112497883Sgibbs/* 112597883Sgibbs * PCI Status for Target 112697883Sgibbs */ 112797883Sgibbsregister TARGPCISTAT { 112897883Sgibbs address 0x0A6 112997883Sgibbs access_mode RW 113097883Sgibbs modes M_CFG 1131102681Sgibbs field DPE 0x80 1132102681Sgibbs field SSE 0x40 1133102681Sgibbs field STA 0x08 1134102681Sgibbs field TWATERR 0x02 113597883Sgibbs} 113697883Sgibbs 113797883Sgibbs/* 113897883Sgibbs * LQ Packet In 113997883Sgibbs * The last LQ Packet recieved 114097883Sgibbs */ 114197883Sgibbsregister LQIN { 114297883Sgibbs address 0x020 114397883Sgibbs access_mode RW 114497883Sgibbs size 20 114597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 114697883Sgibbs} 114797883Sgibbs 114897883Sgibbs/* 114997883Sgibbs * SCB Type Pointer 115097883Sgibbs * SCB offset for Target Mode SCB type information 115197883Sgibbs */ 115297883Sgibbsregister TYPEPTR { 115397883Sgibbs address 0x020 115497883Sgibbs access_mode RW 115597883Sgibbs modes M_CFG 115697883Sgibbs} 115797883Sgibbs 115897883Sgibbs/* 115997883Sgibbs * Queue Tag Pointer 116097883Sgibbs * SCB offset to the Two Byte tag identifier used for target mode. 116197883Sgibbs */ 116297883Sgibbsregister TAGPTR { 116397883Sgibbs address 0x021 116497883Sgibbs access_mode RW 116597883Sgibbs modes M_CFG 116697883Sgibbs} 116797883Sgibbs 116897883Sgibbs/* 116997883Sgibbs * Logical Unit Number Pointer 117097883Sgibbs * SCB offset to the LSB (little endian) of the lun field. 117197883Sgibbs */ 117297883Sgibbsregister LUNPTR { 117397883Sgibbs address 0x022 117497883Sgibbs access_mode RW 117597883Sgibbs modes M_CFG 117697883Sgibbs} 117797883Sgibbs 117897883Sgibbs/* 117997883Sgibbs * Data Length Pointer 118097883Sgibbs * SCB offset for the 4 byte data length field in target mode. 118197883Sgibbs */ 118297883Sgibbsregister DATALENPTR { 118397883Sgibbs address 0x023 118497883Sgibbs access_mode RW 118597883Sgibbs modes M_CFG 118697883Sgibbs} 118797883Sgibbs 118897883Sgibbs/* 118997883Sgibbs * Status Length Pointer 119097883Sgibbs * SCB offset to the two byte status field in target SCBs. 119197883Sgibbs */ 119297883Sgibbsregister STATLENPTR { 119397883Sgibbs address 0x024 119497883Sgibbs access_mode RW 119597883Sgibbs modes M_CFG 119697883Sgibbs} 119797883Sgibbs 119897883Sgibbs/* 119997883Sgibbs * Command Length Pointer 120097883Sgibbs * Scb offset for the CDB length field in initiator SCBs. 120197883Sgibbs */ 120297883Sgibbsregister CMDLENPTR { 120397883Sgibbs address 0x025 120497883Sgibbs access_mode RW 120597883Sgibbs modes M_CFG 120697883Sgibbs} 120797883Sgibbs 120897883Sgibbs/* 120997883Sgibbs * Task Attribute Pointer 121097883Sgibbs * Scb offset for the byte field specifying the attribute byte 121197883Sgibbs * to be used in command packets. 121297883Sgibbs */ 121397883Sgibbsregister ATTRPTR { 121497883Sgibbs address 0x026 121597883Sgibbs access_mode RW 121697883Sgibbs modes M_CFG 121797883Sgibbs} 121897883Sgibbs 121997883Sgibbs/* 122097883Sgibbs * Task Management Flags Pointer 122197883Sgibbs * Scb offset for the byte field specifying the attribute flags 122297883Sgibbs * byte to be used in command packets. 122397883Sgibbs */ 122497883Sgibbsregister FLAGPTR { 122597883Sgibbs address 0x027 122697883Sgibbs access_mode RW 122797883Sgibbs modes M_CFG 122897883Sgibbs} 122997883Sgibbs 123097883Sgibbs/* 123197883Sgibbs * Command Pointer 123297883Sgibbs * Scb offset for the first byte in the CDB for initiator SCBs. 123397883Sgibbs */ 123497883Sgibbsregister CMDPTR { 123597883Sgibbs address 0x028 123697883Sgibbs access_mode RW 123797883Sgibbs modes M_CFG 123897883Sgibbs} 123997883Sgibbs 124097883Sgibbs/* 124197883Sgibbs * Queue Next Pointer 124297883Sgibbs * Scb offset for the 2 byte "next scb link". 124397883Sgibbs */ 124497883Sgibbsregister QNEXTPTR { 124597883Sgibbs address 0x029 124697883Sgibbs access_mode RW 124797883Sgibbs modes M_CFG 124897883Sgibbs} 124997883Sgibbs 125097883Sgibbs/* 125197883Sgibbs * SCSI ID Pointer 125297883Sgibbs * Scb offset to the value to place in the SCSIID register 125397883Sgibbs * during target mode connections. 125497883Sgibbs */ 125597883Sgibbsregister IDPTR { 125697883Sgibbs address 0x02A 125797883Sgibbs access_mode RW 125897883Sgibbs modes M_CFG 125997883Sgibbs} 126097883Sgibbs 126197883Sgibbs/* 126297883Sgibbs * Command Aborted Byte Pointer 126397883Sgibbs * Offset to the SCB flags field that includes the 126497883Sgibbs * "SCB aborted" status bit. 126597883Sgibbs */ 126697883Sgibbsregister ABRTBYTEPTR { 126797883Sgibbs address 0x02B 126897883Sgibbs access_mode RW 126997883Sgibbs modes M_CFG 127097883Sgibbs} 127197883Sgibbs 127297883Sgibbs/* 127397883Sgibbs * Command Aborted Bit Pointer 127497883Sgibbs * Bit offset in the SCB flags field for "SCB aborted" status. 127597883Sgibbs */ 127697883Sgibbsregister ABRTBITPTR { 127797883Sgibbs address 0x02C 127897883Sgibbs access_mode RW 127997883Sgibbs modes M_CFG 128097883Sgibbs} 128197883Sgibbs 128297883Sgibbs/* 1283102681Sgibbs * Rev B or greater. 1284102681Sgibbs */ 1285102681Sgibbsregister MAXCMDBYTES { 1286102681Sgibbs address 0x02D 1287102681Sgibbs access_mode RW 1288102681Sgibbs modes M_CFG 1289102681Sgibbs} 1290102681Sgibbs 1291102681Sgibbs/* 1292102681Sgibbs * Rev B or greater. 1293102681Sgibbs */ 1294102681Sgibbsregister MAXCMD2RCV { 1295102681Sgibbs address 0x02E 1296102681Sgibbs access_mode RW 1297102681Sgibbs modes M_CFG 1298102681Sgibbs} 1299102681Sgibbs 1300102681Sgibbs/* 1301102681Sgibbs * Rev B or greater. 1302102681Sgibbs */ 1303102681Sgibbsregister SHORTTHRESH { 1304102681Sgibbs address 0x02F 1305102681Sgibbs access_mode RW 1306102681Sgibbs modes M_CFG 1307102681Sgibbs} 1308102681Sgibbs 1309102681Sgibbs/* 131097883Sgibbs * Logical Unit Number Length 131197883Sgibbs * The length, in bytes, of the SCB lun field. 131297883Sgibbs */ 131397883Sgibbsregister LUNLEN { 131497883Sgibbs address 0x030 131597883Sgibbs access_mode RW 131697883Sgibbs modes M_CFG 131797883Sgibbs} 131897883Sgibbs 131997883Sgibbs/* 132097883Sgibbs * CDB Limit 132197883Sgibbs * The size, in bytes, of the embedded CDB field in initator SCBs. 132297883Sgibbs */ 132397883Sgibbsregister CDBLIMIT { 132497883Sgibbs address 0x031 132597883Sgibbs access_mode RW 132697883Sgibbs modes M_CFG 132797883Sgibbs} 132897883Sgibbs 132997883Sgibbs/* 133097883Sgibbs * Maximum Commands 133197883Sgibbs * The maximum number of commands to issue during a 133297883Sgibbs * single packetized connection. 133397883Sgibbs */ 133497883Sgibbsregister MAXCMD { 133597883Sgibbs address 0x032 133697883Sgibbs access_mode RW 133797883Sgibbs modes M_CFG 133897883Sgibbs} 133997883Sgibbs 134097883Sgibbs/* 134197883Sgibbs * Maximum Command Counter 134297883Sgibbs * The number of commands already sent during this connection 134397883Sgibbs */ 134497883Sgibbsregister MAXCMDCNT { 134597883Sgibbs address 0x033 134697883Sgibbs access_mode RW 134797883Sgibbs modes M_CFG 134897883Sgibbs} 134997883Sgibbs 135097883Sgibbs/* 135197883Sgibbs * LQ Packet Reserved Bytes 135297883Sgibbs * The bytes to be sent in the currently reserved fileds 135397883Sgibbs * of all LQ packets. 135497883Sgibbs */ 135597883Sgibbsregister LQRSVD01 { 135697883Sgibbs address 0x034 135797883Sgibbs access_mode RW 135897883Sgibbs modes M_SCSI 135997883Sgibbs} 136097883Sgibbsregister LQRSVD16 { 136197883Sgibbs address 0x035 136297883Sgibbs access_mode RW 136397883Sgibbs modes M_SCSI 136497883Sgibbs} 136597883Sgibbsregister LQRSVD17 { 136697883Sgibbs address 0x036 136797883Sgibbs access_mode RW 136897883Sgibbs modes M_SCSI 136997883Sgibbs} 137097883Sgibbs 137197883Sgibbs/* 137297883Sgibbs * Command Reserved 0 137397883Sgibbs * The byte to be sent for the reserved byte 0 of 137497883Sgibbs * outgoing command packets. 137597883Sgibbs */ 137697883Sgibbsregister CMDRSVD0 { 137797883Sgibbs address 0x037 137897883Sgibbs access_mode RW 137997883Sgibbs modes M_CFG 138097883Sgibbs} 138197883Sgibbs 138297883Sgibbs/* 138397883Sgibbs * LQ Manager Control 0 138497883Sgibbs */ 138597883Sgibbsregister LQCTL0 { 138697883Sgibbs address 0x038 138797883Sgibbs access_mode RW 138897883Sgibbs modes M_CFG 1389102681Sgibbs field LQITARGCLT 0xC0 1390102681Sgibbs field LQIINITGCLT 0x30 1391102681Sgibbs field LQ0TARGCLT 0x0C 1392102681Sgibbs field LQ0INITGCLT 0x03 139397883Sgibbs} 139497883Sgibbs 139597883Sgibbs/* 139697883Sgibbs * LQ Manager Control 1 139797883Sgibbs */ 139897883Sgibbsregister LQCTL1 { 139997883Sgibbs address 0x038 140097883Sgibbs access_mode RW 140197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1402102681Sgibbs field PCI2PCI 0x04 1403102681Sgibbs field SINGLECMD 0x02 1404102681Sgibbs field ABORTPENDING 0x01 140597883Sgibbs} 140697883Sgibbs 140797883Sgibbs/* 140897883Sgibbs * LQ Manager Control 2 140997883Sgibbs */ 141097883Sgibbsregister LQCTL2 { 141197883Sgibbs address 0x039 141297883Sgibbs access_mode RW 141397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1414102681Sgibbs field LQIRETRY 0x80 1415102681Sgibbs field LQICONTINUE 0x40 1416102681Sgibbs field LQITOIDLE 0x20 1417102681Sgibbs field LQIPAUSE 0x10 1418102681Sgibbs field LQORETRY 0x08 1419102681Sgibbs field LQOCONTINUE 0x04 1420102681Sgibbs field LQOTOIDLE 0x02 1421102681Sgibbs field LQOPAUSE 0x01 142297883Sgibbs} 142397883Sgibbs 142497883Sgibbs/* 142597883Sgibbs * SCSI RAM BIST0 142697883Sgibbs */ 142797883Sgibbsregister SCSBIST0 { 142897883Sgibbs address 0x039 142997883Sgibbs access_mode RW 143097883Sgibbs modes M_CFG 1431102681Sgibbs field GSBISTERR 0x40 1432102681Sgibbs field GSBISTDONE 0x20 1433102681Sgibbs field GSBISTRUN 0x10 1434102681Sgibbs field OSBISTERR 0x04 1435102681Sgibbs field OSBISTDONE 0x02 1436102681Sgibbs field OSBISTRUN 0x01 143797883Sgibbs} 143897883Sgibbs 143997883Sgibbs/* 144097883Sgibbs * SCSI Sequence Control0 144197883Sgibbs */ 144297883Sgibbsregister SCSISEQ0 { 144397883Sgibbs address 0x03A 144497883Sgibbs access_mode RW 144597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1446102681Sgibbs field TEMODEO 0x80 1447102681Sgibbs field ENSELO 0x40 1448102681Sgibbs field ENARBO 0x20 1449102681Sgibbs field FORCEBUSFREE 0x10 1450102681Sgibbs field SCSIRSTO 0x01 145197883Sgibbs} 145297883Sgibbs 145397883Sgibbs/* 145497883Sgibbs * SCSI RAM BIST 1 145597883Sgibbs */ 145697883Sgibbsregister SCSBIST1 { 145797883Sgibbs address 0x03A 145897883Sgibbs access_mode RW 145997883Sgibbs modes M_CFG 1460102681Sgibbs field NTBISTERR 0x04 1461102681Sgibbs field NTBISTDONE 0x02 1462102681Sgibbs field NTBISTRUN 0x01 146397883Sgibbs} 146497883Sgibbs 146597883Sgibbs/* 146697883Sgibbs * SCSI Sequence Control 1 146797883Sgibbs */ 146897883Sgibbsregister SCSISEQ1 { 146997883Sgibbs address 0x03B 147097883Sgibbs access_mode RW 147197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1472102681Sgibbs field MANUALCTL 0x40 1473102681Sgibbs field ENSELI 0x20 1474102681Sgibbs field ENRSELI 0x10 1475102681Sgibbs field MANUALP 0x0C 1476102681Sgibbs field ENAUTOATNP 0x02 1477102681Sgibbs field ALTSTIM 0x01 147897883Sgibbs} 147997883Sgibbs 148097883Sgibbs/* 148197883Sgibbs * SCSI Transfer Control 0 148297883Sgibbs */ 148397883Sgibbsregister SXFRCTL0 { 148497883Sgibbs address 0x03C 148597883Sgibbs access_mode RW 148697883Sgibbs modes M_SCSI 1487102681Sgibbs field DFON 0x80 1488102681Sgibbs field DFPEXP 0x40 1489102681Sgibbs field BIOSCANCELEN 0x10 1490102681Sgibbs field SPIOEN 0x08 149197883Sgibbs} 149297883Sgibbs 149397883Sgibbs/* 149497883Sgibbs * SCSI Transfer Control 1 149597883Sgibbs */ 149697883Sgibbsregister SXFRCTL1 { 149797883Sgibbs address 0x03D 149897883Sgibbs access_mode RW 149997883Sgibbs modes M_SCSI 1500102681Sgibbs field BITBUCKET 0x80 1501102681Sgibbs field ENSACHK 0x40 1502102681Sgibbs field ENSPCHK 0x20 1503102681Sgibbs field STIMESEL 0x18 1504102681Sgibbs field ENSTIMER 0x04 1505102681Sgibbs field ACTNEGEN 0x02 1506102681Sgibbs field STPWEN 0x01 150797883Sgibbs} 150897883Sgibbs 150997883Sgibbs/* 151097883Sgibbs * SCSI Transfer Control 2 151197883Sgibbs */ 151297883Sgibbsregister SXFRCTL2 { 151397883Sgibbs address 0x03E 151497883Sgibbs access_mode RW 151597883Sgibbs modes M_SCSI 1516102681Sgibbs field AUTORSTDIS 0x10 1517102681Sgibbs field CMDDMAEN 0x08 1518102681Sgibbs field ASU 0x07 151997883Sgibbs} 152097883Sgibbs 152197883Sgibbs/* 152297883Sgibbs * SCSI Bus Initiator IDs 152397883Sgibbs * Bitmask of observed initiators on the bus. 152497883Sgibbs */ 152597883Sgibbsregister BUSINITID { 152697883Sgibbs address 0x03C 152797883Sgibbs access_mode RW 152897883Sgibbs modes M_CFG 152997883Sgibbs size 2 153097883Sgibbs} 153197883Sgibbs 153297883Sgibbs/* 153397883Sgibbs * Data Length Counters 153497883Sgibbs * Packet byte counter. 153597883Sgibbs */ 153697883Sgibbsregister DLCOUNT { 153797883Sgibbs address 0x03C 153897883Sgibbs access_mode RW 153997883Sgibbs modes M_DFF0, M_DFF1 154097883Sgibbs size 3 154197883Sgibbs} 154297883Sgibbs 154397883Sgibbs/* 154497883Sgibbs * Data FIFO Status 154597883Sgibbs */ 154697883Sgibbsregister DFFSTAT { 154797883Sgibbs address 0x03F 154897883Sgibbs access_mode RW 154997883Sgibbs modes M_SCSI 1550102681Sgibbs field FIFO1FREE 0x20 1551102681Sgibbs field FIFO0FREE 0x10 1552102681Sgibbs field CURRFIFO 0x01 155397883Sgibbs} 155497883Sgibbs 155597883Sgibbs/* 155697883Sgibbs * SCSI Bus Target IDs 155797883Sgibbs * Bitmask of observed targets on the bus. 155897883Sgibbs */ 155997883Sgibbsregister BUSTARGID { 156097883Sgibbs address 0x03E 156197883Sgibbs access_mode RW 156297883Sgibbs modes M_CFG 156397883Sgibbs size 2 156497883Sgibbs} 156597883Sgibbs 156697883Sgibbs/* 156797883Sgibbs * SCSI Control Signal Out 156897883Sgibbs */ 156997883Sgibbsregister SCSISIGO { 157097883Sgibbs address 0x040 157197883Sgibbs access_mode RW 157297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1573102681Sgibbs field CDO 0x80 1574102681Sgibbs field IOO 0x40 1575102681Sgibbs field MSGO 0x20 1576102681Sgibbs field ATNO 0x10 1577102681Sgibbs field SELO 0x08 1578102681Sgibbs field BSYO 0x04 1579102681Sgibbs field REQO 0x02 1580102681Sgibbs field ACKO 0x01 158197883Sgibbs/* 158297883Sgibbs * Possible phases to write into SCSISIG0 158397883Sgibbs */ 1584102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1585102681Sgibbs P_DATAOUT 0x0, 1586102681Sgibbs P_DATAIN IOO, 1587102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1588102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1589102681Sgibbs P_COMMAND CDO, 1590102681Sgibbs P_MESGOUT CDO|MSGO, 1591102681Sgibbs P_STATUS CDO|IOO, 1592102681Sgibbs P_MESGIN CDO|IOO|MSGO 1593102681Sgibbs } 159497883Sgibbs} 159597883Sgibbs 159697883Sgibbsregister SCSISIGI { 159797883Sgibbs address 0x041 159897883Sgibbs access_mode RO 159997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1600102681Sgibbs field CDI 0x80 1601102681Sgibbs field IOI 0x40 1602102681Sgibbs field MSGI 0x20 1603102681Sgibbs field ATNI 0x10 1604102681Sgibbs field SELI 0x08 1605102681Sgibbs field BSYI 0x04 1606102681Sgibbs field REQI 0x02 1607102681Sgibbs field ACKI 0x01 160897883Sgibbs/* 160997883Sgibbs * Possible phases in SCSISIGI 161097883Sgibbs */ 1611102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1612102681Sgibbs P_DATAOUT 0x0, 1613102681Sgibbs P_DATAIN IOO, 1614102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1615102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1616102681Sgibbs P_COMMAND CDO, 1617102681Sgibbs P_MESGOUT CDO|MSGO, 1618102681Sgibbs P_STATUS CDO|IOO, 1619102681Sgibbs P_MESGIN CDO|IOO|MSGO 1620102681Sgibbs } 162197883Sgibbs} 162297883Sgibbs 162397883Sgibbs/* 162497883Sgibbs * Multiple Target IDs 162597883Sgibbs * Bitmask of ids to respond as a target. 162697883Sgibbs */ 162797883Sgibbsregister MULTARGID { 162897883Sgibbs address 0x040 162997883Sgibbs access_mode RW 163097883Sgibbs modes M_CFG 163197883Sgibbs size 2 163297883Sgibbs} 163397883Sgibbs 163497883Sgibbs/* 163597883Sgibbs * SCSI Phase 163697883Sgibbs */ 163797883Sgibbsregister SCSIPHASE { 163897883Sgibbs address 0x042 163997883Sgibbs access_mode RO 164097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1641102681Sgibbs field STATUS_PHASE 0x20 1642102681Sgibbs field COMMAND_PHASE 0x10 1643102681Sgibbs field MSG_IN_PHASE 0x08 1644102681Sgibbs field MSG_OUT_PHASE 0x04 1645102681Sgibbs field DATA_PHASE_MASK 0x03 { 1646102681Sgibbs DATA_OUT_PHASE 0x01, 1647102681Sgibbs DATA_IN_PHASE 0x02 1648102681Sgibbs } 164997883Sgibbs} 165097883Sgibbs 165197883Sgibbs/* 165297883Sgibbs * SCSI Data 0 Image 165397883Sgibbs */ 165497883Sgibbsregister SCSIDAT0_IMG { 165597883Sgibbs address 0x043 165697883Sgibbs access_mode RW 165797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 165897883Sgibbs} 165997883Sgibbs 166097883Sgibbs/* 166197883Sgibbs * SCSI Latched Data 166297883Sgibbs */ 166397883Sgibbsregister SCSIDAT { 166497883Sgibbs address 0x044 166597883Sgibbs access_mode RW 166697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 166797883Sgibbs size 2 166897883Sgibbs} 166997883Sgibbs 167097883Sgibbs/* 167197883Sgibbs * SCSI Data Bus 167297883Sgibbs */ 167397883Sgibbsregister SCSIBUS { 167497883Sgibbs address 0x046 167597883Sgibbs access_mode RW 167697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 167797883Sgibbs size 2 167897883Sgibbs} 167997883Sgibbs 168097883Sgibbs/* 168197883Sgibbs * Target ID In 168297883Sgibbs */ 168397883Sgibbsregister TARGIDIN { 168497883Sgibbs address 0x048 168597883Sgibbs access_mode RO 168697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1687102681Sgibbs field CLKOUT 0x80 1688102681Sgibbs field TARGID 0x0F 168997883Sgibbs} 169097883Sgibbs 169197883Sgibbs/* 169297883Sgibbs * Selection/Reselection ID 169397883Sgibbs * Upper four bits are the device id. The ONEBIT is set when the re/selecting 169497883Sgibbs * device did not set its own ID. 169597883Sgibbs */ 169697883Sgibbsregister SELID { 169797883Sgibbs address 0x049 169897883Sgibbs access_mode RW 169997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1700102681Sgibbs field SELID_MASK 0xf0 1701102681Sgibbs field ONEBIT 0x08 170297883Sgibbs} 170397883Sgibbs 170497883Sgibbs/* 170597883Sgibbs * SCSI Block Control 170697883Sgibbs * Controls Bus type and channel selection. SELWIDE allows for the 170797883Sgibbs * coexistence of 8bit and 16bit devices on a wide bus. 170897883Sgibbs */ 170997883Sgibbsregister SBLKCTL { 171097883Sgibbs address 0x04A 171197883Sgibbs access_mode RW 171297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1713102681Sgibbs field DIAGLEDEN 0x80 1714102681Sgibbs field DIAGLEDON 0x40 1715102681Sgibbs field ENAB40 0x08 /* LVD transceiver active */ 1716102681Sgibbs field ENAB20 0x04 /* SE/HVD transceiver active */ 1717102681Sgibbs field SELWIDE 0x02 171897883Sgibbs} 171997883Sgibbs 172097883Sgibbs/* 172197883Sgibbs * Option Mode 172297883Sgibbs */ 172397883Sgibbsregister OPTIONMODE { 172497883Sgibbs address 0x04A 172597883Sgibbs access_mode RW 172697883Sgibbs modes M_CFG 1727102681Sgibbs field BIOSCANCTL 0x80 1728102681Sgibbs field AUTOACKEN 0x40 1729102681Sgibbs field BIASCANCTL 0x20 1730102681Sgibbs field BUSFREEREV 0x10 1731102681Sgibbs field ENDGFORMCHK 0x04 1732102681Sgibbs field AUTO_MSGOUT_DE 0x02 173397883Sgibbs mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 173497883Sgibbs} 173597883Sgibbs 173697883Sgibbs/* 173797883Sgibbs * SCSI Status 0 173897883Sgibbs */ 173997883Sgibbsregister SSTAT0 { 174097883Sgibbs address 0x04B 174197883Sgibbs access_mode RO 174297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1743102681Sgibbs field TARGET 0x80 /* Board acting as target */ 1744102681Sgibbs field SELDO 0x40 /* Selection Done */ 1745102681Sgibbs field SELDI 0x20 /* Board has been selected */ 1746102681Sgibbs field SELINGO 0x10 /* Selection In Progress */ 1747102681Sgibbs field IOERR 0x08 /* LVD Tranceiver mode changed */ 1748102681Sgibbs field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1749102681Sgibbs field SPIORDY 0x02 /* SCSI PIO Ready */ 1750102681Sgibbs field ARBDO 0x01 /* Arbitration Done Out */ 175197883Sgibbs} 175297883Sgibbs 175397883Sgibbs/* 175497883Sgibbs * Clear SCSI Interrupt 0 175597883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 175697883Sgibbs */ 175797883Sgibbsregister CLRSINT0 { 175897883Sgibbs address 0x04B 175997883Sgibbs access_mode WO 176097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1761102681Sgibbs field CLRSELDO 0x40 1762102681Sgibbs field CLRSELDI 0x20 1763102681Sgibbs field CLRSELINGO 0x10 1764102681Sgibbs field CLRIOERR 0x08 1765102681Sgibbs field CLROVERRUN 0x04 1766102681Sgibbs field CLRSPIORDY 0x02 1767102681Sgibbs field CLRARBDO 0x01 176897883Sgibbs} 176997883Sgibbs 177097883Sgibbs/* 177197883Sgibbs * SCSI Interrupt Mode 0 177297883Sgibbs * Setting any bit will enable the corresponding function 177397883Sgibbs * in SIMODE0 to interrupt via the IRQ pin. 177497883Sgibbs */ 177597883Sgibbsregister SIMODE0 { 177697883Sgibbs address 0x04B 177797883Sgibbs access_mode RW 177897883Sgibbs modes M_CFG 1779102681Sgibbs field ENSELDO 0x40 1780102681Sgibbs field ENSELDI 0x20 1781102681Sgibbs field ENSELINGO 0x10 1782102681Sgibbs field ENIOERR 0x08 1783102681Sgibbs field ENOVERRUN 0x04 1784102681Sgibbs field ENSPIORDY 0x02 1785102681Sgibbs field ENARBDO 0x01 178697883Sgibbs} 178797883Sgibbs 178897883Sgibbs/* 178997883Sgibbs * SCSI Status 1 179097883Sgibbs */ 179197883Sgibbsregister SSTAT1 { 179297883Sgibbs address 0x04C 179397883Sgibbs access_mode RO 179497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1795102681Sgibbs field SELTO 0x80 1796102681Sgibbs field ATNTARG 0x40 1797102681Sgibbs field SCSIRSTI 0x20 1798102681Sgibbs field PHASEMIS 0x10 1799102681Sgibbs field BUSFREE 0x08 1800102681Sgibbs field SCSIPERR 0x04 1801102681Sgibbs field STRB2FAST 0x02 1802102681Sgibbs field REQINIT 0x01 180397883Sgibbs} 180497883Sgibbs 180597883Sgibbs/* 180697883Sgibbs * Clear SCSI Interrupt 1 180797883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 180897883Sgibbs */ 180997883Sgibbsregister CLRSINT1 { 181097883Sgibbs address 0x04c 181197883Sgibbs access_mode WO 181297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1813102681Sgibbs field CLRSELTIMEO 0x80 1814102681Sgibbs field CLRATNO 0x40 1815102681Sgibbs field CLRSCSIRSTI 0x20 1816102681Sgibbs field CLRBUSFREE 0x08 1817102681Sgibbs field CLRSCSIPERR 0x04 1818102681Sgibbs field CLRSTRB2FAST 0x02 1819102681Sgibbs field CLRREQINIT 0x01 182097883Sgibbs} 182197883Sgibbs 182297883Sgibbs/* 182397883Sgibbs * SCSI Status 2 182497883Sgibbs */ 182597883Sgibbsregister SSTAT2 { 182697883Sgibbs address 0x04d 182797883Sgibbs access_mode RO 182897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1829102681Sgibbs field BUSFREETIME 0xc0 { 1830102681Sgibbs BUSFREE_LQO 0x40, 1831102681Sgibbs BUSFREE_DFF0 0x80, 1832102681Sgibbs BUSFREE_DFF1 0xC0 1833102681Sgibbs } 1834102681Sgibbs field NONPACKREQ 0x20 1835102681Sgibbs field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1836102681Sgibbs field BSYX 0x08 /* Busy Expander */ 1837102681Sgibbs field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1838102681Sgibbs field SDONE 0x02 /* Modes 0 and 1 only */ 1839102681Sgibbs field DMADONE 0x01 /* Modes 0 and 1 only */ 184097883Sgibbs} 184197883Sgibbs 184297883Sgibbs/* 184397883Sgibbs * Clear SCSI Interrupt 2 184497883Sgibbs */ 184597883Sgibbsregister CLRSINT2 { 184697883Sgibbs address 0x04D 184797883Sgibbs access_mode WO 184897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1849102681Sgibbs field CLRNONPACKREQ 0x20 1850102681Sgibbs field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1851102681Sgibbs field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1852102681Sgibbs field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 185397883Sgibbs} 185497883Sgibbs 185597883Sgibbs/* 185697883Sgibbs * SCSI Interrupt Mode 2 185797883Sgibbs */ 185897883Sgibbsregister SIMODE2 { 185997883Sgibbs address 0x04D 186097883Sgibbs access_mode RW 186197883Sgibbs modes M_CFG 1862102681Sgibbs field ENWIDE_RES 0x04 1863102681Sgibbs field ENSDONE 0x02 1864102681Sgibbs field ENDMADONE 0x01 186597883Sgibbs} 186697883Sgibbs 186797883Sgibbs/* 186897883Sgibbs * Physical Error Diagnosis 186997883Sgibbs */ 187097883Sgibbsregister PERRDIAG { 187197883Sgibbs address 0x04E 187297883Sgibbs access_mode RO 187397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1874102681Sgibbs field HIZERO 0x80 1875102681Sgibbs field HIPERR 0x40 1876102681Sgibbs field PREVPHASE 0x20 1877102681Sgibbs field PARITYERR 0x10 1878102681Sgibbs field AIPERR 0x08 1879102681Sgibbs field CRCERR 0x04 1880102681Sgibbs field DGFORMERR 0x02 1881102681Sgibbs field DTERR 0x01 188297883Sgibbs} 188397883Sgibbs 188497883Sgibbs/* 188597883Sgibbs * LQI Manager Current State 188697883Sgibbs */ 188797883Sgibbsregister LQISTATE { 188897883Sgibbs address 0x04E 188997883Sgibbs access_mode RO 189097883Sgibbs modes M_CFG 189197883Sgibbs} 189297883Sgibbs 189397883Sgibbs/* 189497883Sgibbs * SCSI Offset Count 189597883Sgibbs */ 189697883Sgibbsregister SOFFCNT { 189797883Sgibbs address 0x04F 189897883Sgibbs access_mode RO 189997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 190097883Sgibbs} 190197883Sgibbs 190297883Sgibbs/* 190397883Sgibbs * LQO Manager Current State 190497883Sgibbs */ 190597883Sgibbsregister LQOSTATE { 190697883Sgibbs address 0x04F 190797883Sgibbs access_mode RO 190897883Sgibbs modes M_CFG 190997883Sgibbs} 191097883Sgibbs 191197883Sgibbs/* 191297883Sgibbs * LQI Manager Status 191397883Sgibbs */ 191497883Sgibbsregister LQISTAT0 { 191597883Sgibbs address 0x050 191697883Sgibbs access_mode RO 191797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1918102681Sgibbs field LQIATNQAS 0x20 1919102681Sgibbs field LQICRCT1 0x10 1920102681Sgibbs field LQICRCT2 0x08 1921102681Sgibbs field LQIBADLQT 0x04 1922102681Sgibbs field LQIATNLQ 0x02 1923102681Sgibbs field LQIATNCMD 0x01 192497883Sgibbs} 192597883Sgibbs 192697883Sgibbs/* 192797883Sgibbs * Clear LQI Interrupts 0 192897883Sgibbs */ 1929102681Sgibbsregister CLRLQIINT0 { 193097883Sgibbs address 0x050 193197883Sgibbs access_mode WO 193297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1933102681Sgibbs field CLRLQIATNQAS 0x20 1934102681Sgibbs field CLRLQICRCT1 0x10 1935102681Sgibbs field CLRLQICRCT2 0x08 1936102681Sgibbs field CLRLQIBADLQT 0x04 1937102681Sgibbs field CLRLQIATNLQ 0x02 1938102681Sgibbs field CLRLQIATNCMD 0x01 193997883Sgibbs} 194097883Sgibbs 194197883Sgibbs/* 194297883Sgibbs * LQI Manager Interrupt Mode 0 194397883Sgibbs */ 194497883Sgibbsregister LQIMODE0 { 194597883Sgibbs address 0x050 194697883Sgibbs access_mode RW 194797883Sgibbs modes M_CFG 1948102681Sgibbs field ENLQIATNQASK 0x20 1949102681Sgibbs field ENLQICRCT1 0x10 1950102681Sgibbs field ENLQICRCT2 0x08 1951102681Sgibbs field ENLQIBADLQT 0x04 1952102681Sgibbs field ENLQIATNLQ 0x02 1953102681Sgibbs field ENLQIATNCMD 0x01 195497883Sgibbs} 195597883Sgibbs 195697883Sgibbs/* 195797883Sgibbs * LQI Manager Status 1 195897883Sgibbs */ 195997883Sgibbsregister LQISTAT1 { 196097883Sgibbs address 0x051 196197883Sgibbs access_mode RO 196297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1963102681Sgibbs field LQIPHASE_LQ 0x80 1964102681Sgibbs field LQIPHASE_NLQ 0x40 1965102681Sgibbs field LQIABORT 0x20 1966102681Sgibbs field LQICRCI_LQ 0x10 1967102681Sgibbs field LQICRCI_NLQ 0x08 1968102681Sgibbs field LQIBADLQI 0x04 1969102681Sgibbs field LQIOVERI_LQ 0x02 1970102681Sgibbs field LQIOVERI_NLQ 0x01 197197883Sgibbs} 197297883Sgibbs 197397883Sgibbs/* 197497883Sgibbs * Clear LQI Manager Interrupts1 197597883Sgibbs */ 197697883Sgibbsregister CLRLQIINT1 { 197797883Sgibbs address 0x051 197897883Sgibbs access_mode WO 197997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1980102681Sgibbs field CLRLQIPHASE_LQ 0x80 1981102681Sgibbs field CLRLQIPHASE_NLQ 0x40 1982102681Sgibbs field CLRLIQABORT 0x20 1983102681Sgibbs field CLRLQICRCI_LQ 0x10 1984102681Sgibbs field CLRLQICRCI_NLQ 0x08 1985102681Sgibbs field CLRLQIBADLQI 0x04 1986102681Sgibbs field CLRLQIOVERI_LQ 0x02 1987102681Sgibbs field CLRLQIOVERI_NLQ 0x01 198897883Sgibbs} 198997883Sgibbs 199097883Sgibbs/* 199197883Sgibbs * LQI Manager Interrupt Mode 1 199297883Sgibbs */ 199397883Sgibbsregister LQIMODE1 { 199497883Sgibbs address 0x051 199597883Sgibbs access_mode RW 199697883Sgibbs modes M_CFG 1997102681Sgibbs field ENLQIPHASE_LQ 0x80 1998102681Sgibbs field ENLQIPHASE_NLQ 0x40 1999102681Sgibbs field ENLIQABORT 0x20 2000102681Sgibbs field ENLQICRCI_LQ 0x10 2001102681Sgibbs field ENLQICRCI_NLQ 0x08 2002102681Sgibbs field ENLQIBADLQI 0x04 2003102681Sgibbs field ENLQIOVERI_LQ 0x02 2004102681Sgibbs field ENLQIOVERI_NLQ 0x01 200597883Sgibbs} 200697883Sgibbs 200797883Sgibbs/* 200897883Sgibbs * LQI Manager Status 2 200997883Sgibbs */ 201097883Sgibbsregister LQISTAT2 { 201197883Sgibbs address 0x052 201297883Sgibbs access_mode RO 201397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2014102681Sgibbs field PACKETIZED 0x80 2015102681Sgibbs field LQIPHASE_OUTPKT 0x40 2016102681Sgibbs field LQIWORKONLQ 0x20 2017102681Sgibbs field LQIWAITFIFO 0x10 2018102681Sgibbs field LQISTOPPKT 0x08 2019102681Sgibbs field LQISTOPLQ 0x04 2020102681Sgibbs field LQISTOPCMD 0x02 2021102681Sgibbs field LQIGSAVAIL 0x01 202297883Sgibbs} 202397883Sgibbs 202497883Sgibbs/* 202597883Sgibbs * SCSI Status 3 202697883Sgibbs */ 202797883Sgibbsregister SSTAT3 { 202897883Sgibbs address 0x053 202997883Sgibbs access_mode RO 203097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2031102681Sgibbs field NTRAMPERR 0x02 2032102681Sgibbs field OSRAMPERR 0x01 203397883Sgibbs} 203497883Sgibbs 203597883Sgibbs/* 203697883Sgibbs * Clear SCSI Status 3 203797883Sgibbs */ 203897883Sgibbsregister CLRSINT3 { 203997883Sgibbs address 0x053 204097883Sgibbs access_mode WO 204197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2042102681Sgibbs field CLRNTRAMPERR 0x02 2043102681Sgibbs field CLROSRAMPERR 0x01 204497883Sgibbs} 204597883Sgibbs 204697883Sgibbs/* 204797883Sgibbs * SCSI Interrupt Mode 3 204897883Sgibbs */ 204997883Sgibbsregister SIMODE3 { 205097883Sgibbs address 0x053 205197883Sgibbs access_mode RW 205297883Sgibbs modes M_CFG 2053102681Sgibbs field ENNTRAMPERR 0x02 2054102681Sgibbs field ENOSRAMPERR 0x01 205597883Sgibbs} 205697883Sgibbs 205797883Sgibbs/* 205897883Sgibbs * LQO Manager Status 0 205997883Sgibbs */ 206097883Sgibbsregister LQOSTAT0 { 206197883Sgibbs address 0x054 206297883Sgibbs access_mode RO 206397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2064102681Sgibbs field LQOTARGSCBPERR 0x10 2065102681Sgibbs field LQOSTOPT2 0x08 2066102681Sgibbs field LQOATNLQ 0x04 2067102681Sgibbs field LQOATNPKT 0x02 2068102681Sgibbs field LQOTCRC 0x01 206997883Sgibbs} 207097883Sgibbs 207197883Sgibbs/* 207297883Sgibbs * Clear LQO Manager interrupt 0 207397883Sgibbs */ 207497883Sgibbsregister CLRLQOINT0 { 207597883Sgibbs address 0x054 207697883Sgibbs access_mode WO 207797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2078102681Sgibbs field CLRLQOTARGSCBPERR 0x10 2079102681Sgibbs field CLRLQOSTOPT2 0x08 2080102681Sgibbs field CLRLQOATNLQ 0x04 2081102681Sgibbs field CLRLQOATNPKT 0x02 2082102681Sgibbs field CLRLQOTCRC 0x01 208397883Sgibbs} 208497883Sgibbs 208597883Sgibbs/* 208697883Sgibbs * LQO Manager Interrupt Mode 0 208797883Sgibbs */ 208897883Sgibbsregister LQOMODE0 { 208997883Sgibbs address 0x054 209097883Sgibbs access_mode RW 209197883Sgibbs modes M_CFG 2092102681Sgibbs field ENLQOTARGSCBPERR 0x10 2093102681Sgibbs field ENLQOSTOPT2 0x08 2094102681Sgibbs field ENLQOATNLQ 0x04 2095102681Sgibbs field ENLQOATNPKT 0x02 2096102681Sgibbs field ENLQOTCRC 0x01 209797883Sgibbs} 209897883Sgibbs 209997883Sgibbs/* 210097883Sgibbs * LQO Manager Status 1 210197883Sgibbs */ 210297883Sgibbsregister LQOSTAT1 { 210397883Sgibbs address 0x055 210497883Sgibbs access_mode RO 210597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2106102681Sgibbs field LQOINITSCBPERR 0x10 2107102681Sgibbs field LQOSTOPI2 0x08 2108102681Sgibbs field LQOBADQAS 0x04 2109102681Sgibbs field LQOBUSFREE 0x02 2110102681Sgibbs field LQOPHACHGINPKT 0x01 211197883Sgibbs} 211297883Sgibbs 211397883Sgibbs/* 211497883Sgibbs * Clear LOQ Interrupt 1 211597883Sgibbs */ 211697883Sgibbsregister CLRLQOINT1 { 211797883Sgibbs address 0x055 211897883Sgibbs access_mode WO 211997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2120102681Sgibbs field CLRLQOINITSCBPERR 0x10 2121102681Sgibbs field CLRLQOSTOPI2 0x08 2122102681Sgibbs field CLRLQOBADQAS 0x04 2123102681Sgibbs field CLRLQOBUSFREE 0x02 2124102681Sgibbs field CLRLQOPHACHGINPKT 0x01 212597883Sgibbs} 212697883Sgibbs 212797883Sgibbs/* 212897883Sgibbs * LQO Manager Interrupt Mode 1 212997883Sgibbs */ 213097883Sgibbsregister LQOMODE1 { 213197883Sgibbs address 0x055 213297883Sgibbs access_mode RW 213397883Sgibbs modes M_CFG 2134102681Sgibbs field ENLQOINITSCBPERR 0x10 2135102681Sgibbs field ENLQOSTOPI2 0x08 2136102681Sgibbs field ENLQOBADQAS 0x04 2137102681Sgibbs field ENLQOBUSFREE 0x02 2138102681Sgibbs field ENLQOPHACHGINPKT 0x01 213997883Sgibbs} 214097883Sgibbs 214197883Sgibbs/* 214297883Sgibbs * LQO Manager Status 2 214397883Sgibbs */ 214497883Sgibbsregister LQOSTAT2 { 214597883Sgibbs address 0x056 214697883Sgibbs access_mode RO 214797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2148102681Sgibbs field LQOPKT 0xE0 2149102681Sgibbs field LQOWAITFIFO 0x10 2150102681Sgibbs field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2151102681Sgibbs field LQOSTOP0 0x01 /* Stopped after sending all packets */ 215297883Sgibbs} 215397883Sgibbs 215497883Sgibbs/* 215597883Sgibbs * Output Synchronizer Space Count 215697883Sgibbs */ 215797883Sgibbsregister OS_SPACE_CNT { 215897883Sgibbs address 0x056 215997883Sgibbs access_mode RO 216097883Sgibbs modes M_CFG 216197883Sgibbs} 216297883Sgibbs 216397883Sgibbs/* 216497883Sgibbs * SCSI Interrupt Mode 1 216597883Sgibbs * Setting any bit will enable the corresponding function 216697883Sgibbs * in SIMODE1 to interrupt via the IRQ pin. 216797883Sgibbs */ 216897883Sgibbsregister SIMODE1 { 216997883Sgibbs address 0x057 217097883Sgibbs access_mode RW 217197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2172102681Sgibbs field ENSELTIMO 0x80 2173102681Sgibbs field ENATNTARG 0x40 2174102681Sgibbs field ENSCSIRST 0x20 2175102681Sgibbs field ENPHASEMIS 0x10 2176102681Sgibbs field ENBUSFREE 0x08 2177102681Sgibbs field ENSCSIPERR 0x04 2178102681Sgibbs field ENSTRB2FAST 0x02 2179102681Sgibbs field ENREQINIT 0x01 218097883Sgibbs} 218197883Sgibbs 218297883Sgibbs/* 218397883Sgibbs * Good Status FIFO 218497883Sgibbs */ 218597883Sgibbsregister GSFIFO { 218697883Sgibbs address 0x058 218797883Sgibbs access_mode RO 218897883Sgibbs size 2 218997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 219097883Sgibbs} 219197883Sgibbs 219297883Sgibbs/* 219397883Sgibbs * Data FIFO SCSI Transfer Control 219497883Sgibbs */ 219597883Sgibbsregister DFFSXFRCTL { 219697883Sgibbs address 0x05A 219797883Sgibbs access_mode RW 219897883Sgibbs modes M_DFF0, M_DFF1 2199102681Sgibbs field CLRSHCNT 0x04 2200102681Sgibbs field CLRCHN 0x02 2201102681Sgibbs field RSTCHN 0x01 220297883Sgibbs} 220397883Sgibbs 220497883Sgibbs/* 220597883Sgibbs * Next SCSI Control Block 220697883Sgibbs */ 220797883Sgibbsregister NEXTSCB { 220897883Sgibbs address 0x05A 220997883Sgibbs access_mode RW 221097883Sgibbs size 2 221197883Sgibbs modes M_SCSI 221297883Sgibbs} 221397883Sgibbs 221497883Sgibbs/* 221597883Sgibbs * SEQ Interrupts 221697883Sgibbs */ 221797883Sgibbsregister SEQINTSRC { 221897883Sgibbs address 0x05B 221997883Sgibbs access_mode RO 222097883Sgibbs modes M_DFF0, M_DFF1 2221102681Sgibbs field CTXTDONE 0x40 2222102681Sgibbs field SAVEPTRS 0x20 2223102681Sgibbs field CFG4DATA 0x10 2224102681Sgibbs field CFG4ISTAT 0x08 2225102681Sgibbs field CFG4TSTAT 0x04 2226102681Sgibbs field CFG4ICMD 0x02 2227102681Sgibbs field CFG4TCMD 0x01 222897883Sgibbs} 222997883Sgibbs 223097883Sgibbs/* 223197883Sgibbs * Clear Arp Interrupts 223297883Sgibbs */ 223397883Sgibbsregister CLRSEQINTSRC { 223497883Sgibbs address 0x05B 223597883Sgibbs access_mode WO 223697883Sgibbs modes M_DFF0, M_DFF1 2237102681Sgibbs field CLRCTXTDONE 0x40 2238102681Sgibbs field CLRSAVEPTRS 0x20 2239102681Sgibbs field CLRCFG4DATA 0x10 2240102681Sgibbs field CLRCFG4ISTAT 0x08 2241102681Sgibbs field CLRCFG4TSTAT 0x04 2242102681Sgibbs field CLRCFG4ICMD 0x02 2243102681Sgibbs field CLRCFG4TCMD 0x01 224497883Sgibbs} 224597883Sgibbs 224697883Sgibbs/* 224797883Sgibbs * SEQ Interrupt Enabled (Shared) 224897883Sgibbs */ 224997883Sgibbsregister SEQIMODE { 225097883Sgibbs address 0x05C 225197883Sgibbs access_mode RW 225297883Sgibbs modes M_DFF0, M_DFF1 2253102681Sgibbs field ENCTXTDONE 0x40 2254102681Sgibbs field ENSAVEPTRS 0x20 2255102681Sgibbs field ENCFG4DATA 0x10 2256102681Sgibbs field ENCFG4ISTAT 0x08 2257102681Sgibbs field ENCFG4TSTAT 0x04 2258102681Sgibbs field ENCFG4ICMD 0x02 2259102681Sgibbs field ENCFG4TCMD 0x01 226097883Sgibbs} 226197883Sgibbs 226297883Sgibbs/* 226397883Sgibbs * Current SCSI Control Block 226497883Sgibbs */ 226597883Sgibbsregister CURRSCB { 226697883Sgibbs address 0x05C 226797883Sgibbs access_mode RW 226897883Sgibbs size 2 226997883Sgibbs modes M_SCSI 227097883Sgibbs} 227197883Sgibbs 227297883Sgibbs/* 227397883Sgibbs * Data FIFO Status 227497883Sgibbs */ 227597883Sgibbsregister MDFFSTAT { 227697883Sgibbs address 0x05D 227797883Sgibbs access_mode RO 227897883Sgibbs modes M_DFF0, M_DFF1 2279102681Sgibbs field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2280102681Sgibbs field SHCNTMINUS1 0x20 /* Rev B or higher */ 2281102681Sgibbs field LASTSDONE 0x10 2282102681Sgibbs field SHVALID 0x08 2283102681Sgibbs field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2284102681Sgibbs field DATAINFIFO 0x02 2285102681Sgibbs field FIFOFREE 0x01 228697883Sgibbs} 228797883Sgibbs 228897883Sgibbs/* 228997883Sgibbs * CRC Control 229097883Sgibbs */ 229197883Sgibbsregister CRCCONTROL { 229297883Sgibbs address 0x05d 229397883Sgibbs access_mode RW 229497883Sgibbs modes M_CFG 2295102681Sgibbs field CRCVALCHKEN 0x40 229697883Sgibbs} 229797883Sgibbs 229897883Sgibbs/* 229997883Sgibbs * SCSI Test Control 230097883Sgibbs */ 230197883Sgibbsregister SCSITEST { 230297883Sgibbs address 0x05E 230397883Sgibbs access_mode RW 230497883Sgibbs modes M_CFG 2305102681Sgibbs field CNTRTEST 0x08 2306102681Sgibbs field SEL_TXPLL_DEBUG 0x04 230797883Sgibbs} 230897883Sgibbs 230997883Sgibbs/* 231097883Sgibbs * Data FIFO Queue Tag 231197883Sgibbs */ 231297883Sgibbsregister DFFTAG { 231397883Sgibbs address 0x05E 231497883Sgibbs access_mode RW 231597883Sgibbs size 2 231697883Sgibbs modes M_DFF0, M_DFF1 231797883Sgibbs} 231897883Sgibbs 231997883Sgibbs/* 232097883Sgibbs * Last SCSI Control Block 232197883Sgibbs */ 232297883Sgibbsregister LASTSCB { 232397883Sgibbs address 0x05E 232497883Sgibbs access_mode RW 232597883Sgibbs size 2 232697883Sgibbs modes M_SCSI 232797883Sgibbs} 232897883Sgibbs 232997883Sgibbs/* 233097883Sgibbs * SCSI I/O Cell Power-down Control 233197883Sgibbs */ 233297883Sgibbsregister IOPDNCTL { 233397883Sgibbs address 0x05F 233497883Sgibbs access_mode RW 233597883Sgibbs modes M_CFG 2336102681Sgibbs field DISABLE_OE 0x80 2337102681Sgibbs field PDN_IDIST 0x04 2338102681Sgibbs field PDN_DIFFSENSE 0x01 233997883Sgibbs} 234097883Sgibbs 234197883Sgibbs/* 234297883Sgibbs * Shaddow Host Address. 234397883Sgibbs */ 234497883Sgibbsregister SHADDR { 234597883Sgibbs address 0x060 234697883Sgibbs access_mode RO 234797883Sgibbs size 8 234897883Sgibbs modes M_DFF0, M_DFF1 234997883Sgibbs} 235097883Sgibbs 235197883Sgibbs/* 235297883Sgibbs * Data Group CRC Interval. 235397883Sgibbs */ 235497883Sgibbsregister DGRPCRCI { 235597883Sgibbs address 0x060 235697883Sgibbs access_mode RW 235797883Sgibbs size 2 235897883Sgibbs modes M_CFG 235997883Sgibbs} 236097883Sgibbs 236197883Sgibbs/* 236297883Sgibbs * Data Transfer Negotiation Address 236397883Sgibbs */ 236497883Sgibbsregister NEGOADDR { 236597883Sgibbs address 0x060 236697883Sgibbs access_mode RW 236797883Sgibbs modes M_SCSI 236897883Sgibbs} 236997883Sgibbs 237097883Sgibbs/* 237197883Sgibbs * Data Transfer Negotiation Data - Period Byte 237297883Sgibbs */ 237397883Sgibbsregister NEGPERIOD { 237497883Sgibbs address 0x061 237597883Sgibbs access_mode RW 237697883Sgibbs modes M_SCSI 237797883Sgibbs} 237897883Sgibbs 237997883Sgibbs/* 238097883Sgibbs * Packetized CRC Interval 238197883Sgibbs */ 238297883Sgibbsregister PACKCRCI { 238397883Sgibbs address 0x062 238497883Sgibbs access_mode RW 238597883Sgibbs size 2 238697883Sgibbs modes M_CFG 238797883Sgibbs} 238897883Sgibbs 238997883Sgibbs/* 239097883Sgibbs * Data Transfer Negotiation Data - Offset Byte 239197883Sgibbs */ 239297883Sgibbsregister NEGOFFSET { 239397883Sgibbs address 0x062 239497883Sgibbs access_mode RW 239597883Sgibbs modes M_SCSI 239697883Sgibbs} 239797883Sgibbs 239897883Sgibbs/* 239997883Sgibbs * Data Transfer Negotiation Data - PPR Options 240097883Sgibbs */ 240197883Sgibbsregister NEGPPROPTS { 240297883Sgibbs address 0x063 240397883Sgibbs access_mode RW 240497883Sgibbs modes M_SCSI 2405102681Sgibbs field PPROPT_PACE 0x08 2406102681Sgibbs field PPROPT_QAS 0x04 2407102681Sgibbs field PPROPT_DT 0x02 2408102681Sgibbs field PPROPT_IUT 0x01 240997883Sgibbs} 241097883Sgibbs 241197883Sgibbs/* 241297883Sgibbs * Data Transfer Negotiation Data - Connection Options 241397883Sgibbs */ 241497883Sgibbsregister NEGCONOPTS { 241597883Sgibbs address 0x064 241697883Sgibbs access_mode RW 241797883Sgibbs modes M_SCSI 2418102681Sgibbs field ENAIP 0x08 2419102681Sgibbs field ENAUTOATNI 0x04 2420102681Sgibbs field ENAUTOATNO 0x02 2421102681Sgibbs field WIDEXFER 0x01 242297883Sgibbs} 242397883Sgibbs 242497883Sgibbs/* 242597883Sgibbs * Negotiation Table Annex Column Index. 242697883Sgibbs */ 242797883Sgibbsregister ANNEXCOL { 242897883Sgibbs address 0x065 242997883Sgibbs access_mode RW 243097883Sgibbs modes M_SCSI 243197883Sgibbs} 243297883Sgibbs 2433102681Sgibbsregister SCSCHKN { 2434102681Sgibbs address 0x066 2435102681Sgibbs access_mode RW 2436102681Sgibbs modes M_CFG 2437102681Sgibbs field STSELSKIDDIS 0x40 2438102681Sgibbs field CURFIFODEF 0x20 2439102681Sgibbs field WIDERESEN 0x10 2440102681Sgibbs field SDONEMSKDIS 0x08 2441102681Sgibbs field DFFACTCLR 0x04 2442102681Sgibbs field SHVALIDSTDIS 0x02 2443102681Sgibbs field LSTSGCLRDIS 0x01 2444102681Sgibbs} 2445102681Sgibbs 244697883Sgibbsconst AHD_ANNEXCOL_PRECOMP 4 244797883Sgibbsconst AHD_PRECOMP_MASK 0x07 244897883Sgibbsconst AHD_PRECOMP_CUTBACK_17 0x04 244997883Sgibbsconst AHD_PRECOMP_CUTBACK_29 0x06 245097883Sgibbsconst AHD_PRECOMP_CUTBACK_37 0x07 245197883Sgibbsconst AHD_PRECOMP_FASTSLEW 0x40 245297883Sgibbsconst AHD_NUM_ANNEXCOLS 4 245397883Sgibbs 245497883Sgibbs/* 245597883Sgibbs * Negotiation Table Annex Data Port. 245697883Sgibbs */ 245797883Sgibbsregister ANNEXDAT { 245897883Sgibbs address 0x066 245997883Sgibbs access_mode RW 246097883Sgibbs modes M_SCSI 246197883Sgibbs} 246297883Sgibbs 246397883Sgibbs/* 246497883Sgibbs * Initiator's Own Id. 246597883Sgibbs * The SCSI ID to use for Selection Out and seen during a reselection.. 246697883Sgibbs */ 246797883Sgibbsregister IOWNID { 246897883Sgibbs address 0x067 246997883Sgibbs access_mode RW 247097883Sgibbs modes M_SCSI 247197883Sgibbs} 247297883Sgibbs 247397883Sgibbs/* 247497883Sgibbs * 960MHz Phase-Locked Loop Control 0 247597883Sgibbs */ 247697883Sgibbsregister PLL960CTL0 { 247797883Sgibbs address 0x068 247897883Sgibbs access_mode RW 247997883Sgibbs modes M_CFG 2480102681Sgibbs field PLL_VCOSEL 0x80 2481102681Sgibbs field PLL_PWDN 0x40 2482102681Sgibbs field PLL_NS 0x30 2483102681Sgibbs field PLL_ENLUD 0x08 2484102681Sgibbs field PLL_ENLPF 0x04 2485102681Sgibbs field PLL_DLPF 0x02 2486102681Sgibbs field PLL_ENFBM 0x01 248797883Sgibbs} 248897883Sgibbs 248997883Sgibbs/* 249097883Sgibbs * Target Own Id 249197883Sgibbs */ 249297883Sgibbsregister TOWNID { 249397883Sgibbs address 0x069 249497883Sgibbs access_mode RW 249597883Sgibbs modes M_SCSI 249697883Sgibbs} 249797883Sgibbs 249897883Sgibbs/* 249997883Sgibbs * 960MHz Phase-Locked Loop Control 1 250097883Sgibbs */ 250197883Sgibbsregister PLL960CTL1 { 250297883Sgibbs address 0x069 250397883Sgibbs access_mode RW 250497883Sgibbs modes M_CFG 2505102681Sgibbs field PLL_CNTEN 0x80 2506102681Sgibbs field PLL_CNTCLR 0x40 2507102681Sgibbs field PLL_RST 0x01 250897883Sgibbs} 250997883Sgibbs 251097883Sgibbs/* 251197883Sgibbs * Expander Signature 251297883Sgibbs */ 251397883Sgibbsregister XSIG { 251497883Sgibbs address 0x06A 251597883Sgibbs access_mode RW 251697883Sgibbs modes M_SCSI 251797883Sgibbs} 251897883Sgibbs 251997883Sgibbs/* 252097883Sgibbs * Shadow Byte Count 252197883Sgibbs */ 252297883Sgibbsregister SHCNT { 252397883Sgibbs address 0x068 252497883Sgibbs access_mode RW 252597883Sgibbs size 3 252697883Sgibbs modes M_DFF0, M_DFF1 252797883Sgibbs} 252897883Sgibbs 252997883Sgibbs/* 253097883Sgibbs * Selection Out ID 253197883Sgibbs */ 253297883Sgibbsregister SELOID { 253397883Sgibbs address 0x06B 253497883Sgibbs access_mode RW 253597883Sgibbs modes M_SCSI 253697883Sgibbs} 253797883Sgibbs 253897883Sgibbs/* 253997883Sgibbs * 960-MHz Phase-Locked Loop Test Count 254097883Sgibbs */ 254197883Sgibbsregister PLL960CNT0 { 254297883Sgibbs address 0x06A 254397883Sgibbs access_mode RO 254497883Sgibbs size 2 254597883Sgibbs modes M_CFG 254697883Sgibbs} 254797883Sgibbs 254897883Sgibbs/* 254997883Sgibbs * 400-MHz Phase-Locked Loop Control 0 255097883Sgibbs */ 255197883Sgibbsregister PLL400CTL0 { 255297883Sgibbs address 0x06C 255397883Sgibbs access_mode RW 255497883Sgibbs modes M_CFG 2555102681Sgibbs field PLL_VCOSEL 0x80 2556102681Sgibbs field PLL_PWDN 0x40 2557102681Sgibbs field PLL_NS 0x30 2558102681Sgibbs field PLL_ENLUD 0x08 2559102681Sgibbs field PLL_ENLPF 0x04 2560102681Sgibbs field PLL_DLPF 0x02 2561102681Sgibbs field PLL_ENFBM 0x01 256297883Sgibbs} 256397883Sgibbs 256497883Sgibbs/* 256597883Sgibbs * Arbitration Fairness 256697883Sgibbs */ 256797883Sgibbsregister FAIRNESS { 256897883Sgibbs address 0x06C 256997883Sgibbs access_mode RW 257097883Sgibbs size 2 257197883Sgibbs modes M_SCSI 257297883Sgibbs} 257397883Sgibbs 257497883Sgibbs/* 257597883Sgibbs * 400-MHz Phase-Locked Loop Control 1 257697883Sgibbs */ 257797883Sgibbsregister PLL400CTL1 { 257897883Sgibbs address 0x06D 257997883Sgibbs access_mode RW 258097883Sgibbs modes M_CFG 2581102681Sgibbs field PLL_CNTEN 0x80 2582102681Sgibbs field PLL_CNTCLR 0x40 2583102681Sgibbs field PLL_RST 0x01 258497883Sgibbs} 258597883Sgibbs 258697883Sgibbs/* 258797883Sgibbs * Arbitration Unfairness 258897883Sgibbs */ 258997883Sgibbsregister UNFAIRNESS { 259097883Sgibbs address 0x06E 259197883Sgibbs access_mode RW 259297883Sgibbs size 2 259397883Sgibbs modes M_SCSI 259497883Sgibbs} 259597883Sgibbs 259697883Sgibbs/* 259797883Sgibbs * 400-MHz Phase-Locked Loop Test Count 259897883Sgibbs */ 259997883Sgibbsregister PLL400CNT0 { 260097883Sgibbs address 0x06E 260197883Sgibbs access_mode RO 260297883Sgibbs size 2 260397883Sgibbs modes M_CFG 260497883Sgibbs} 260597883Sgibbs 260697883Sgibbs/* 260797883Sgibbs * SCB Page Pointer 260897883Sgibbs */ 260997883Sgibbsregister SCBPTR { 261097883Sgibbs address 0x0A8 261197883Sgibbs access_mode RW 261297883Sgibbs size 2 261397883Sgibbs modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 261497883Sgibbs} 261597883Sgibbs 261697883Sgibbs/* 261797883Sgibbs * CMC SCB Array Count 261897883Sgibbs * Number of bytes to transfer between CMC SCB memory and SCBRAM. 261997883Sgibbs * Transfers must be 8byte aligned and sized. 262097883Sgibbs */ 262197883Sgibbsregister CCSCBACNT { 262297883Sgibbs address 0x0AB 262397883Sgibbs access_mode RW 262497883Sgibbs modes M_CCHAN 262597883Sgibbs} 262697883Sgibbs 262797883Sgibbs/* 262897883Sgibbs * SCB Autopointer 262997883Sgibbs * SCB-Next Address Snooping logic. When an SCB is transferred to 263097883Sgibbs * the card, the next SCB address to be used by the CMC array can 263197883Sgibbs * be autoloaded from that transfer. 263297883Sgibbs */ 263397883Sgibbsregister SCBAUTOPTR { 263497883Sgibbs address 0x0AB 263597883Sgibbs access_mode RW 263697883Sgibbs modes M_CFG 2637102681Sgibbs field AUSCBPTR_EN 0x80 2638102681Sgibbs field SCBPTR_ADDR 0x38 2639102681Sgibbs field SCBPTR_OFF 0x07 264097883Sgibbs} 264197883Sgibbs 264297883Sgibbs/* 264397883Sgibbs * CMC SG Ram Address Pointer 264497883Sgibbs */ 264597883Sgibbsregister CCSGADDR { 264697883Sgibbs address 0x0AC 264797883Sgibbs access_mode RW 264897883Sgibbs modes M_DFF0, M_DFF1 264997883Sgibbs} 265097883Sgibbs 265197883Sgibbs/* 265297883Sgibbs * CMC SCB RAM Address Pointer 265397883Sgibbs */ 265497883Sgibbsregister CCSCBADDR { 265597883Sgibbs address 0x0AC 265697883Sgibbs access_mode RW 265797883Sgibbs modes M_CCHAN 265897883Sgibbs} 265997883Sgibbs 266097883Sgibbs/* 266197883Sgibbs * CMC SCB Ram Back-up Address Pointer 266297883Sgibbs * Indicates the true stop location of transfers halted prior 266397883Sgibbs * to SCBHCNT going to 0. 266497883Sgibbs */ 266597883Sgibbsregister CCSCBADR_BK { 266697883Sgibbs address 0x0AC 266797883Sgibbs access_mode RO 266897883Sgibbs modes M_CFG 266997883Sgibbs} 267097883Sgibbs 267197883Sgibbs/* 267297883Sgibbs * CMC SG Control 267397883Sgibbs */ 267497883Sgibbsregister CCSGCTL { 267597883Sgibbs address 0x0AD 267697883Sgibbs access_mode RW 267797883Sgibbs modes M_DFF0, M_DFF1 2678102681Sgibbs field CCSGDONE 0x80 2679102681Sgibbs field SG_CACHE_AVAIL 0x10 2680102681Sgibbs field CCSGEN 0x08 2681102681Sgibbs field SG_FETCH_REQ 0x02 2682102681Sgibbs field CCSGRESET 0x01 268397883Sgibbs} 268497883Sgibbs 268597883Sgibbs/* 268697883Sgibbs * CMD SCB Control 268797883Sgibbs */ 268897883Sgibbsregister CCSCBCTL { 268997883Sgibbs address 0x0AD 269097883Sgibbs access_mode RW 269197883Sgibbs modes M_CCHAN 2692102681Sgibbs field CCSCBDONE 0x80 2693102681Sgibbs field ARRDONE 0x40 2694102681Sgibbs field CCARREN 0x10 2695102681Sgibbs field CCSCBEN 0x08 2696102681Sgibbs field CCSCBDIR 0x04 2697102681Sgibbs field CCSCBRESET 0x01 269897883Sgibbs} 269997883Sgibbs 270097883Sgibbs/* 270197883Sgibbs * CMC Ram BIST 270297883Sgibbs */ 270397883Sgibbsregister CMC_RAMBIST { 270497883Sgibbs address 0x0AD 270597883Sgibbs access_mode RW 270697883Sgibbs modes M_CFG 2707102681Sgibbs field SG_ELEMENT_SIZE 0x80 2708102681Sgibbs field SCBRAMBIST_FAIL 0x40 2709102681Sgibbs field SG_BIST_FAIL 0x20 2710102681Sgibbs field SG_BIST_EN 0x10 2711102681Sgibbs field CMC_BUFFER_BIST_FAIL 0x02 2712102681Sgibbs field CMC_BUFFER_BIST_EN 0x01 271397883Sgibbs} 271497883Sgibbs 271597883Sgibbs/* 271697883Sgibbs * CMC SG RAM Data Port 271797883Sgibbs */ 271897883Sgibbsregister CCSGRAM { 271997883Sgibbs address 0x0B0 272097883Sgibbs access_mode RW 272197883Sgibbs modes M_DFF0, M_DFF1 272297883Sgibbs} 272397883Sgibbs 272497883Sgibbs/* 272597883Sgibbs * CMC SCB RAM Data Port 272697883Sgibbs */ 272797883Sgibbsregister CCSCBRAM { 272897883Sgibbs address 0x0B0 272997883Sgibbs access_mode RW 273097883Sgibbs modes M_CCHAN 273197883Sgibbs} 273297883Sgibbs 273397883Sgibbs/* 273497883Sgibbs * Flex DMA Address. 273597883Sgibbs */ 273697883Sgibbsregister FLEXADR { 273797883Sgibbs address 0x0B0 273897883Sgibbs access_mode RW 273997883Sgibbs size 3 274097883Sgibbs modes M_SCSI 274197883Sgibbs} 274297883Sgibbs 274397883Sgibbs/* 274497883Sgibbs * Flex DMA Byte Count 274597883Sgibbs */ 274697883Sgibbsregister FLEXCNT { 274797883Sgibbs address 0x0B3 274897883Sgibbs access_mode RW 274997883Sgibbs size 2 275097883Sgibbs modes M_SCSI 275197883Sgibbs} 275297883Sgibbs 275397883Sgibbs/* 275497883Sgibbs * Flex DMA Status 275597883Sgibbs */ 275697883Sgibbsregister FLEXDMASTAT { 275797883Sgibbs address 0x0B5 275897883Sgibbs access_mode RW 275997883Sgibbs modes M_SCSI 2760102681Sgibbs field FLEXDMAERR 0x02 2761102681Sgibbs field FLEXDMADONE 0x01 276297883Sgibbs} 276397883Sgibbs 276497883Sgibbs/* 276597883Sgibbs * Flex DMA Data Port 276697883Sgibbs */ 276797883Sgibbsregister FLEXDATA { 276897883Sgibbs address 0x0B6 276997883Sgibbs access_mode RW 277097883Sgibbs modes M_SCSI 277197883Sgibbs} 277297883Sgibbs 277397883Sgibbs/* 277497883Sgibbs * Board Data 277597883Sgibbs */ 277697883Sgibbsregister BRDDAT { 277797883Sgibbs address 0x0B8 277897883Sgibbs access_mode RW 277997883Sgibbs modes M_SCSI 278097883Sgibbs} 278197883Sgibbs 278297883Sgibbs/* 278397883Sgibbs * Board Control 278497883Sgibbs */ 278597883Sgibbsregister BRDCTL { 278697883Sgibbs address 0x0B9 278797883Sgibbs access_mode RW 278897883Sgibbs modes M_SCSI 2789102681Sgibbs field FLXARBACK 0x80 2790102681Sgibbs field FLXARBREQ 0x40 2791102681Sgibbs field BRDADDR 0x38 2792102681Sgibbs field BRDEN 0x04 2793102681Sgibbs field BRDRW 0x02 2794102681Sgibbs field BRDSTB 0x01 279597883Sgibbs} 279697883Sgibbs 279797883Sgibbs/* 279897883Sgibbs * Serial EEPROM Address 279997883Sgibbs */ 280097883Sgibbsregister SEEADR { 280197883Sgibbs address 0x0BA 280297883Sgibbs access_mode RW 280397883Sgibbs modes M_SCSI 280497883Sgibbs} 280597883Sgibbs 280697883Sgibbs/* 280797883Sgibbs * Serial EEPROM Data 280897883Sgibbs */ 280997883Sgibbsregister SEEDAT { 281097883Sgibbs address 0x0BC 281197883Sgibbs access_mode RW 281297883Sgibbs size 2 281397883Sgibbs modes M_SCSI 281497883Sgibbs} 281597883Sgibbs 281697883Sgibbs/* 281797883Sgibbs * Serial EEPROM Status 281897883Sgibbs */ 281997883Sgibbsregister SEESTAT { 282097883Sgibbs address 0x0BE 282197883Sgibbs access_mode RO 282297883Sgibbs modes M_SCSI 2823102681Sgibbs field INIT_DONE 0x80 2824102681Sgibbs field SEEOPCODE 0x70 2825102681Sgibbs field LDALTID_L 0x08 2826102681Sgibbs field SEEARBACK 0x04 2827102681Sgibbs field SEEBUSY 0x02 2828102681Sgibbs field SEESTART 0x01 282997883Sgibbs} 283097883Sgibbs 283197883Sgibbs/* 283297883Sgibbs * Serial EEPROM Control 283397883Sgibbs */ 283497883Sgibbsregister SEECTL { 283597883Sgibbs address 0x0BE 283697883Sgibbs access_mode RW 283797883Sgibbs modes M_SCSI 2838102681Sgibbs field SEEOPCODE 0x70 { 2839102681Sgibbs SEEOP_ERASE 0x70, 2840102681Sgibbs SEEOP_READ 0x60, 2841102681Sgibbs SEEOP_WRITE 0x50, 284297883Sgibbs /* 284397883Sgibbs * The following four commands use special 284497883Sgibbs * addresses for differentiation. 284597883Sgibbs */ 2846102681Sgibbs SEEOP_ERAL 0x40 2847102681Sgibbs } 284897883Sgibbs mask SEEOP_EWEN 0x40 284997883Sgibbs mask SEEOP_WALL 0x40 285097883Sgibbs mask SEEOP_EWDS 0x40 2851102681Sgibbs field SEERST 0x02 2852102681Sgibbs field SEESTART 0x01 285397883Sgibbs} 285497883Sgibbs 285597883Sgibbsconst SEEOP_ERAL_ADDR 0x80 285697883Sgibbsconst SEEOP_EWEN_ADDR 0xC0 285797883Sgibbsconst SEEOP_WRAL_ADDR 0x40 285897883Sgibbsconst SEEOP_EWDS_ADDR 0x00 285997883Sgibbs 286097883Sgibbs/* 286197883Sgibbs * SCB Counter 286297883Sgibbs */ 286397883Sgibbsregister SCBCNT { 286497883Sgibbs address 0x0BF 286597883Sgibbs access_mode RW 286697883Sgibbs modes M_SCSI 286797883Sgibbs} 286897883Sgibbs 286997883Sgibbs/* 287097883Sgibbs * Data FIFO Write Address 287197883Sgibbs * Pointer to the next QWD location to be written to the data FIFO. 287297883Sgibbs */ 287397883Sgibbsregister DFWADDR { 287497883Sgibbs address 0x0C0 287597883Sgibbs access_mode RW 287697883Sgibbs size 2 287797883Sgibbs modes M_DFF0, M_DFF1 287897883Sgibbs} 287997883Sgibbs 288097883Sgibbs/* 288197883Sgibbs * DSP Filter Control 288297883Sgibbs */ 288397883Sgibbsregister DSPFLTRCTL { 288497883Sgibbs address 0x0C0 288597883Sgibbs access_mode RW 288697883Sgibbs modes M_CFG 2887102681Sgibbs field FLTRDISABLE 0x20 2888102681Sgibbs field EDGESENSE 0x10 2889102681Sgibbs field DSPFCNTSEL 0x0F 289097883Sgibbs} 289197883Sgibbs 289297883Sgibbs/* 289397883Sgibbs * DSP Data Channel Control 289497883Sgibbs */ 289597883Sgibbsregister DSPDATACTL { 289697883Sgibbs address 0x0C1 289797883Sgibbs access_mode RW 289897883Sgibbs modes M_CFG 2899102681Sgibbs field BYPASSENAB 0x80 2900102681Sgibbs field DESQDIS 0x10 2901102681Sgibbs field RCVROFFSTDIS 0x04 2902102681Sgibbs field XMITOFFSTDIS 0x02 290397883Sgibbs} 290497883Sgibbs 290597883Sgibbs/* 290697883Sgibbs * Data FIFO Read Address 290797883Sgibbs * Pointer to the next QWD location to be read from the data FIFO. 290897883Sgibbs */ 290997883Sgibbsregister DFRADDR { 291097883Sgibbs address 0x0C2 291197883Sgibbs access_mode RW 291297883Sgibbs size 2 291397883Sgibbs modes M_DFF0, M_DFF1 291497883Sgibbs} 291597883Sgibbs 291697883Sgibbs/* 291797883Sgibbs * DSP REQ Control 291897883Sgibbs */ 291997883Sgibbsregister DSPREQCTL { 292097883Sgibbs address 0x0C2 292197883Sgibbs access_mode RW 292297883Sgibbs modes M_CFG 2923102681Sgibbs field MANREQCTL 0xC0 2924102681Sgibbs field MANREQDLY 0x3F 292597883Sgibbs} 292697883Sgibbs 292797883Sgibbs/* 292897883Sgibbs * DSP ACK Control 292997883Sgibbs */ 293097883Sgibbsregister DSPACKCTL { 293197883Sgibbs address 0x0C3 293297883Sgibbs access_mode RW 293397883Sgibbs modes M_CFG 2934102681Sgibbs field MANACKCTL 0xC0 2935102681Sgibbs field MANACKDLY 0x3F 293697883Sgibbs} 293797883Sgibbs 293897883Sgibbs/* 293997883Sgibbs * Data FIFO Data 294097883Sgibbs * Read/Write byte port into the data FIFO. The read and write 294197883Sgibbs * FIFO pointers increment with each read and write respectively 294297883Sgibbs * to this port. 294397883Sgibbs */ 294497883Sgibbsregister DFDAT { 294597883Sgibbs address 0x0C4 294697883Sgibbs access_mode RW 294797883Sgibbs modes M_DFF0, M_DFF1 294897883Sgibbs} 294997883Sgibbs 295097883Sgibbs/* 295197883Sgibbs * DSP Channel Select 295297883Sgibbs */ 295397883Sgibbsregister DSPSELECT { 295497883Sgibbs address 0x0C4 295597883Sgibbs access_mode RW 295697883Sgibbs modes M_CFG 2957102681Sgibbs field AUTOINCEN 0x80 2958102681Sgibbs field DSPSEL 0x1F 295997883Sgibbs} 296097883Sgibbs 296197883Sgibbsconst NUMDSPS 0x14 296297883Sgibbs 296397883Sgibbs/* 296497883Sgibbs * Write Bias Control 296597883Sgibbs */ 296697883Sgibbsregister WRTBIASCTL { 296797883Sgibbs address 0x0C5 296897883Sgibbs access_mode WO 296997883Sgibbs modes M_CFG 2970102681Sgibbs field AUTOXBCDIS 0x80 2971102681Sgibbs field XMITMANVAL 0x3F 297297883Sgibbs} 297397883Sgibbs 297497883Sgibbsconst WRTBIASCTL_CPQ_DEFAULT 0x97 297597883Sgibbs 297697883Sgibbs/* 297797883Sgibbs * Receiver Bias Control 297897883Sgibbs */ 297997883Sgibbsregister RCVRBIOSCTL { 298097883Sgibbs address 0x0C6 298197883Sgibbs access_mode WO 298297883Sgibbs modes M_CFG 2983102681Sgibbs field AUTORBCDIS 0x80 2984102681Sgibbs field RCVRMANVAL 0x3F 298597883Sgibbs} 298697883Sgibbs 298797883Sgibbs/* 298897883Sgibbs * Write Bias Calculator 298997883Sgibbs */ 299097883Sgibbsregister WRTBIASCALC { 299197883Sgibbs address 0x0C7 299297883Sgibbs access_mode RO 299397883Sgibbs modes M_CFG 299497883Sgibbs} 299597883Sgibbs 299697883Sgibbs/* 299797883Sgibbs * Data FIFO Pointers 299897883Sgibbs * Contains the byte offset from DFWADDR and DWRADDR to the current 299997883Sgibbs * FIFO write/read locations. 300097883Sgibbs */ 300197883Sgibbsregister DFPTRS { 300297883Sgibbs address 0x0C8 300397883Sgibbs access_mode RW 300497883Sgibbs modes M_DFF0, M_DFF1 300597883Sgibbs} 300697883Sgibbs 300797883Sgibbs/* 300897883Sgibbs * Receiver Bias Calculator 300997883Sgibbs */ 301097883Sgibbsregister RCVRBIASCALC { 301197883Sgibbs address 0x0C8 301297883Sgibbs access_mode RO 301397883Sgibbs modes M_CFG 301497883Sgibbs} 301597883Sgibbs 301697883Sgibbs/* 301797883Sgibbs * Data FIFO Debug Control 301897883Sgibbs */ 301997883Sgibbsregister DFDBCTL { 302097883Sgibbs address 0x0C8 302197883Sgibbs access_mode RW 302297883Sgibbs modes M_DFF0, M_DFF1 3023102681Sgibbs field DFF_CIO_WR_RDY 0x20 3024102681Sgibbs field DFF_CIO_RD_RDY 0x10 3025102681Sgibbs field DFF_DIR_ERR 0x08 3026102681Sgibbs field DFF_RAMBIST_FAIL 0x04 3027102681Sgibbs field DFF_RAMBIST_DONE 0x02 3028102681Sgibbs field DFF_RAMBIST_EN 0x01 302997883Sgibbs} 303097883Sgibbs 303197883Sgibbs/* 303297883Sgibbs * Data FIFO Backup Read Pointer 303397883Sgibbs * Contains the data FIFO address to be restored if the last 303497883Sgibbs * data accessed from the data FIFO was not transferred successfully. 303597883Sgibbs */ 303697883Sgibbsregister DFBKPTR { 303797883Sgibbs address 0x0C9 303897883Sgibbs access_mode RW 303997883Sgibbs size 2 304097883Sgibbs modes M_DFF0, M_DFF1 304197883Sgibbs} 304297883Sgibbs 304397883Sgibbs/* 304497883Sgibbs * Skew Calculator 304597883Sgibbs */ 304697883Sgibbsregister SKEWCALC { 304797883Sgibbs address 0x0C9 304897883Sgibbs access_mode RO 304997883Sgibbs modes M_CFG 305097883Sgibbs} 305197883Sgibbs 305297883Sgibbs/* 305397883Sgibbs * Data FIFO Space Count 305497883Sgibbs * Number of FIFO locations that are free. 305597883Sgibbs */ 305697883Sgibbsregister DFSCNT { 305797883Sgibbs address 0x0CC 305897883Sgibbs access_mode RO 305997883Sgibbs size 2 306097883Sgibbs modes M_DFF0, M_DFF1 306197883Sgibbs} 306297883Sgibbs 306397883Sgibbs/* 306497883Sgibbs * Data FIFO Byte Count 306597883Sgibbs * Number of filled FIFO locations. 306697883Sgibbs */ 306797883Sgibbsregister DFBCNT { 306897883Sgibbs address 0x0CE 306997883Sgibbs access_mode RO 307097883Sgibbs size 2 307197883Sgibbs modes M_DFF0, M_DFF1 307297883Sgibbs} 307397883Sgibbs 307497883Sgibbs/* 307597883Sgibbs * Sequencer Program Overlay Address. 307697883Sgibbs * Low address must be written prior to high address. 307797883Sgibbs */ 307897883Sgibbsregister OVLYADDR { 307997883Sgibbs address 0x0D4 308097883Sgibbs modes M_SCSI 308197883Sgibbs size 2 308297883Sgibbs access_mode RW 308397883Sgibbs} 308497883Sgibbs 308597883Sgibbs/* 308697883Sgibbs * Sequencer Control 0 308797883Sgibbs * Error detection mode, speed configuration, 308897883Sgibbs * single step, breakpoints and program load. 308997883Sgibbs */ 309097883Sgibbsregister SEQCTL0 { 309197883Sgibbs address 0x0D6 309297883Sgibbs access_mode RW 3093102681Sgibbs field PERRORDIS 0x80 3094102681Sgibbs field PAUSEDIS 0x40 3095102681Sgibbs field FAILDIS 0x20 3096102681Sgibbs field FASTMODE 0x10 3097102681Sgibbs field BRKADRINTEN 0x08 3098102681Sgibbs field STEP 0x04 3099102681Sgibbs field SEQRESET 0x02 3100102681Sgibbs field LOADRAM 0x01 310197883Sgibbs} 310297883Sgibbs 310397883Sgibbs/* 310497883Sgibbs * Sequencer Control 1 310597883Sgibbs * Instruction RAM Diagnostics 310697883Sgibbs */ 310797883Sgibbsregister SEQCTL1 { 310897883Sgibbs address 0x0D7 310997883Sgibbs access_mode RW 3110102681Sgibbs field OVRLAY_DATA_CHK 0x08 3111102681Sgibbs field RAMBIST_DONE 0x04 3112102681Sgibbs field RAMBIST_FAIL 0x02 3113102681Sgibbs field RAMBIST_EN 0x01 311497883Sgibbs} 311597883Sgibbs 311697883Sgibbs/* 311797883Sgibbs * Sequencer Flags 311897883Sgibbs * Zero and Carry state of the ALU. 311997883Sgibbs */ 312097883Sgibbsregister FLAGS { 312197883Sgibbs address 0x0D8 312297883Sgibbs access_mode RO 3123102681Sgibbs field ZERO 0x02 3124102681Sgibbs field CARRY 0x01 312597883Sgibbs} 312697883Sgibbs 312797883Sgibbs/* 312897883Sgibbs * Sequencer Interrupt Control 312997883Sgibbs */ 313097883Sgibbsregister SEQINTCTL { 313197883Sgibbs address 0x0D9 313297883Sgibbs access_mode RW 3133102681Sgibbs field INTVEC1DSL 0x80 3134102681Sgibbs field INT1_CONTEXT 0x20 3135102681Sgibbs field SCS_SEQ_INT1M1 0x10 3136102681Sgibbs field SCS_SEQ_INT1M0 0x08 3137102681Sgibbs field INTMASK 0x06 3138102681Sgibbs field IRET 0x01 313997883Sgibbs} 314097883Sgibbs 314197883Sgibbs/* 314297883Sgibbs * Sequencer RAM Data Port 314397883Sgibbs * Single byte window into the Sequencer Instruction Ram area starting 314497883Sgibbs * at the address specified by OVLYADDR. To write a full instruction word, 314597883Sgibbs * simply write four bytes in succession. OVLYADDR will increment after the 314697883Sgibbs * most significant instrution byte (the byte with the parity bit) is written. 314797883Sgibbs */ 314897883Sgibbsregister SEQRAM { 314997883Sgibbs address 0x0DA 315097883Sgibbs access_mode RW 315197883Sgibbs} 315297883Sgibbs 315397883Sgibbs/* 315497883Sgibbs * Sequencer Program Counter 315597883Sgibbs * Low byte must be written prior to high byte. 315697883Sgibbs */ 315797883Sgibbsregister PRGMCNT { 315897883Sgibbs address 0x0DE 315997883Sgibbs access_mode RW 316097883Sgibbs size 2 316197883Sgibbs} 316297883Sgibbs 316397883Sgibbs/* 316497883Sgibbs * Accumulator 316597883Sgibbs */ 316697883Sgibbsregister ACCUM { 316797883Sgibbs address 0x0E0 316897883Sgibbs access_mode RW 316997883Sgibbs accumulator 317097883Sgibbs} 317197883Sgibbs 317297883Sgibbs/* 317397883Sgibbs * Source Index Register 317497883Sgibbs * Incrementing index for reads of SINDIR and the destination (low byte only) 317597883Sgibbs * for any immediate operands passed in jmp, jc, jnc, call instructions. 317697883Sgibbs * Example: 317797883Sgibbs * mvi 0xFF call some_routine; 317897883Sgibbs * 317997883Sgibbs * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 318097883Sgibbs */ 318197883Sgibbsregister SINDEX { 318297883Sgibbs address 0x0E2 318397883Sgibbs access_mode RW 318497883Sgibbs size 2 318597883Sgibbs sindex 318697883Sgibbs} 318797883Sgibbs 318897883Sgibbs/* 318997883Sgibbs * Destination Index Register 319097883Sgibbs * Incrementing index for writes to DINDIR. Can be used as a scratch register. 319197883Sgibbs */ 319297883Sgibbsregister DINDEX { 319397883Sgibbs address 0x0E4 319497883Sgibbs access_mode RW 319597883Sgibbs size 2 319697883Sgibbs} 319797883Sgibbs 319897883Sgibbs/* 319997883Sgibbs * Break Address 320097883Sgibbs * Sequencer instruction breakpoint address address. 320197883Sgibbs */ 320297883Sgibbsregister BRKADDR0 { 320397883Sgibbs address 0x0E6 320497883Sgibbs access_mode RW 320597883Sgibbs} 320697883Sgibbs 320797883Sgibbsregister BRKADDR1 { 320897883Sgibbs address 0x0E6 320997883Sgibbs access_mode RW 3210102681Sgibbs field BRKDIS 0x80 /* Disable Breakpoint */ 321197883Sgibbs} 321297883Sgibbs 321397883Sgibbs/* 321497883Sgibbs * All Ones 321597883Sgibbs * All reads to this register return the value 0xFF. 321697883Sgibbs */ 321797883Sgibbsregister ALLONES { 321897883Sgibbs address 0x0E8 321997883Sgibbs access_mode RO 322097883Sgibbs allones 322197883Sgibbs} 322297883Sgibbs 322397883Sgibbs/* 322497883Sgibbs * All Zeros 322597883Sgibbs * All reads to this register return the value 0. 322697883Sgibbs */ 322797883Sgibbsregister ALLZEROS { 322897883Sgibbs address 0x0EA 322997883Sgibbs access_mode RO 323097883Sgibbs allzeros 323197883Sgibbs} 323297883Sgibbs 323397883Sgibbs/* 323497883Sgibbs * No Destination 323597883Sgibbs * Writes to this register have no effect. 323697883Sgibbs */ 323797883Sgibbsregister NONE { 323897883Sgibbs address 0x0EA 323997883Sgibbs access_mode WO 324097883Sgibbs none 324197883Sgibbs} 324297883Sgibbs 324397883Sgibbs/* 324497883Sgibbs * Source Index Indirect 324597883Sgibbs * Reading this register is equivalent to reading (register_base + SINDEX) and 324697883Sgibbs * incrementing SINDEX by 1. 324797883Sgibbs */ 324897883Sgibbsregister SINDIR { 324997883Sgibbs address 0x0EC 325097883Sgibbs access_mode RO 325197883Sgibbs} 325297883Sgibbs 325397883Sgibbs/* 325497883Sgibbs * Destination Index Indirect 325597883Sgibbs * Writing this register is equivalent to writing to (register_base + DINDEX) 325697883Sgibbs * and incrementing DINDEX by 1. 325797883Sgibbs */ 325897883Sgibbsregister DINDIR { 325997883Sgibbs address 0x0ED 326097883Sgibbs access_mode WO 326197883Sgibbs} 326297883Sgibbs 326397883Sgibbs/* 326497883Sgibbs * Function One 326597883Sgibbs * 2's complement to bit value conversion. Write the 2's complement value 326697883Sgibbs * (0-7 only) to the top nibble and retrieve the bit indexed by that value 326797883Sgibbs * on the next read of this register. 326897883Sgibbs * Example: 326997883Sgibbs * Write 0x60 327097883Sgibbs * Read 0x40 327197883Sgibbs */ 327297883Sgibbsregister FUNCTION1 { 327397883Sgibbs address 0x0F0 327497883Sgibbs access_mode RW 327597883Sgibbs} 327697883Sgibbs 327797883Sgibbs/* 327897883Sgibbs * Stack 327997883Sgibbs * Window into the stack. Each stack location is 10 bits wide reported 328097883Sgibbs * low byte followed by high byte. There are 8 stack locations. 328197883Sgibbs */ 328297883Sgibbsregister STACK { 328397883Sgibbs address 0x0F2 328497883Sgibbs access_mode RW 328597883Sgibbs} 328697883Sgibbs 328797883Sgibbs/* 328897883Sgibbs * Interrupt Vector 1 Address 328997883Sgibbs * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 329097883Sgibbs */ 329197883Sgibbsregister INTVEC1_ADDR { 329297883Sgibbs address 0x0F4 329397883Sgibbs access_mode RW 329497883Sgibbs size 2 329597883Sgibbs modes M_CFG 329697883Sgibbs} 329797883Sgibbs 329897883Sgibbs/* 329997883Sgibbs * Current Address 330097883Sgibbs * Address of the SEQRAM instruction currently executing instruction. 330197883Sgibbs */ 330297883Sgibbsregister CURADDR { 330397883Sgibbs address 0x0F4 330497883Sgibbs access_mode RW 330597883Sgibbs size 2 330697883Sgibbs modes M_SCSI 330797883Sgibbs} 330897883Sgibbs 330997883Sgibbs/* 331097883Sgibbs * Interrupt Vector 2 Address 331197883Sgibbs * Interrupt branch address for HST_SEQ_INT2 interrupts. 331297883Sgibbs */ 331397883Sgibbsregister INTVEC2_ADDR { 331497883Sgibbs address 0x0F6 331597883Sgibbs access_mode RW 331697883Sgibbs size 2 331797883Sgibbs modes M_CFG 331897883Sgibbs} 331997883Sgibbs 332097883Sgibbs/* 332197883Sgibbs * Last Address 332297883Sgibbs * Address of the SEQRAM instruction executed prior to the current instruction. 332397883Sgibbs */ 332497883Sgibbsregister LASTADDR { 332597883Sgibbs address 0x0F6 332697883Sgibbs access_mode RW 332797883Sgibbs size 2 332897883Sgibbs modes M_SCSI 332997883Sgibbs} 333097883Sgibbs 333197883Sgibbsregister AHD_PCI_CONFIG_BASE { 333297883Sgibbs address 0x100 333397883Sgibbs access_mode RW 333497883Sgibbs size 256 333597883Sgibbs modes M_CFG 333697883Sgibbs} 333797883Sgibbs 333897883Sgibbs/* ---------------------- Scratch RAM Offsets ------------------------- */ 333997883Sgibbsscratch_ram { 334097883Sgibbs /* Mode Specific */ 334197883Sgibbs address 0x0A0 334297883Sgibbs size 8 334397883Sgibbs modes 0, 1, 2, 3 334497883Sgibbs REG0 { 334597883Sgibbs size 2 334697883Sgibbs } 334797883Sgibbs REG1 { 334897883Sgibbs size 2 334997883Sgibbs } 335097883Sgibbs REG2 { 335197883Sgibbs size 2 335297883Sgibbs } 335397883Sgibbs SG_STATE { 335497883Sgibbs size 1 3355102681Sgibbs field SEGS_AVAIL 0x01 3356102681Sgibbs field LOADING_NEEDED 0x02 3357102681Sgibbs field FETCH_INPROG 0x04 335897883Sgibbs } 335997883Sgibbs /* 336097883Sgibbs * Track whether the transfer byte count for 336197883Sgibbs * the current data phase is odd. 336297883Sgibbs */ 336397883Sgibbs DATA_COUNT_ODD { 336497883Sgibbs size 1 336597883Sgibbs } 336697883Sgibbs} 336797883Sgibbs 336897883Sgibbsscratch_ram { 336997883Sgibbs /* Mode Specific */ 337097883Sgibbs address 0x0F8 337197883Sgibbs size 8 337297883Sgibbs modes 0, 1, 2, 3 337397883Sgibbs LONGJMP_ADDR { 337497883Sgibbs size 2 337597883Sgibbs } 337697883Sgibbs LONGJMP_SCB { 337797883Sgibbs size 2 337897883Sgibbs } 337997883Sgibbs ACCUM_SAVE { 338097883Sgibbs size 1 338197883Sgibbs } 338297883Sgibbs} 338397883Sgibbs 338497883Sgibbs 338597883Sgibbsscratch_ram { 338697883Sgibbs address 0x100 338797883Sgibbs size 128 338897883Sgibbs modes 0, 1, 2, 3 338997883Sgibbs /* 339097883Sgibbs * Per "other-id" execution queues. We use an array of 339197883Sgibbs * tail pointers into lists of SCBs sorted by "other-id". 339297883Sgibbs * The execution head pointer threads the head SCBs for 339397883Sgibbs * each list. 339497883Sgibbs */ 339597883Sgibbs WAITING_SCB_TAILS { 339697883Sgibbs size 32 339797883Sgibbs } 339897883Sgibbs WAITING_TID_HEAD { 339997883Sgibbs size 2 340097883Sgibbs } 340197883Sgibbs WAITING_TID_TAIL { 340297883Sgibbs size 2 340397883Sgibbs } 340497883Sgibbs /* 340597883Sgibbs * SCBID of the next SCB in the new SCB queue. 340697883Sgibbs */ 340797883Sgibbs NEXT_QUEUED_SCB_ADDR { 340897883Sgibbs size 4 340997883Sgibbs } 341097883Sgibbs /* 341197883Sgibbs * head of list of SCBs that have 341297883Sgibbs * completed but have not been 341397883Sgibbs * put into the qoutfifo. 341497883Sgibbs */ 341597883Sgibbs COMPLETE_SCB_HEAD { 341697883Sgibbs size 2 341797883Sgibbs } 341897883Sgibbs /* 341997883Sgibbs * The list of completed SCBs in 342097883Sgibbs * the active DMA. 342197883Sgibbs */ 342297883Sgibbs COMPLETE_SCB_DMAINPROG_HEAD { 342397883Sgibbs size 2 342497883Sgibbs } 342597883Sgibbs /* 342697883Sgibbs * head of list of SCBs that have 342797883Sgibbs * completed but need to be uploaded 342897883Sgibbs * to the host prior to being completed. 342997883Sgibbs */ 343097883Sgibbs COMPLETE_DMA_SCB_HEAD { 343197883Sgibbs size 2 343297883Sgibbs } 343397883Sgibbs /* Counting semaphore to prevent new select-outs */ 343497883Sgibbs QFREEZE_COUNT { 343597883Sgibbs size 2 343697883Sgibbs } 343797883Sgibbs /* 343897883Sgibbs * Mode to restore on idle_loop exit. 343997883Sgibbs */ 344097883Sgibbs SAVED_MODE { 344197883Sgibbs size 1 344297883Sgibbs } 344397883Sgibbs /* 344497883Sgibbs * Single byte buffer used to designate the type or message 344597883Sgibbs * to send to a target. 344697883Sgibbs */ 344797883Sgibbs MSG_OUT { 344897883Sgibbs size 1 344997883Sgibbs } 345097883Sgibbs /* Parameters for DMA Logic */ 345197883Sgibbs DMAPARAMS { 345297883Sgibbs size 1 3453102681Sgibbs field PRELOADEN 0x80 3454102681Sgibbs field WIDEODD 0x40 3455102681Sgibbs field SCSIEN 0x20 3456102681Sgibbs field SDMAEN 0x10 3457102681Sgibbs field SDMAENACK 0x10 3458102681Sgibbs field HDMAEN 0x08 3459102681Sgibbs field HDMAENACK 0x08 3460102681Sgibbs field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3461102681Sgibbs field FIFOFLUSH 0x02 3462102681Sgibbs field FIFORESET 0x01 346397883Sgibbs } 346497883Sgibbs SEQ_FLAGS { 346597883Sgibbs size 1 3466102681Sgibbs field NOT_IDENTIFIED 0x80 3467102681Sgibbs field TARGET_CMD_IS_TAGGED 0x40 3468102681Sgibbs field NO_CDB_SENT 0x40 3469102681Sgibbs field DPHASE 0x20 347097883Sgibbs /* Target flags */ 3471102681Sgibbs field TARG_CMD_PENDING 0x10 3472102681Sgibbs field CMDPHASE_PENDING 0x08 3473102681Sgibbs field DPHASE_PENDING 0x04 3474102681Sgibbs field SPHASE_PENDING 0x02 3475102681Sgibbs field NO_DISCONNECT 0x01 347697883Sgibbs } 347797883Sgibbs /* 347897883Sgibbs * Temporary storage for the 347997883Sgibbs * target/channel/lun of a 348097883Sgibbs * reconnecting target 348197883Sgibbs */ 348297883Sgibbs SAVED_SCSIID { 348397883Sgibbs size 1 348497883Sgibbs } 348597883Sgibbs SAVED_LUN { 348697883Sgibbs size 1 348797883Sgibbs } 348897883Sgibbs /* 348997883Sgibbs * The last bus phase as seen by the sequencer. 349097883Sgibbs */ 349197883Sgibbs LASTPHASE { 349297883Sgibbs size 1 3493102681Sgibbs field CDI 0x80 3494102681Sgibbs field IOI 0x40 3495102681Sgibbs field MSGI 0x20 3496102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 3497102681Sgibbs P_DATAOUT 0x0, 3498102681Sgibbs P_DATAIN IOO, 3499102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 3500102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 3501102681Sgibbs P_COMMAND CDO, 3502102681Sgibbs P_MESGOUT CDO|MSGO, 3503102681Sgibbs P_STATUS CDO|IOO, 3504102681Sgibbs P_MESGIN CDO|IOO|MSGO, 3505102681Sgibbs P_BUSFREE 0x01 3506102681Sgibbs } 350797883Sgibbs } 350897883Sgibbs /* 350997883Sgibbs * Base address of our shared data with the kernel driver in host 351097883Sgibbs * memory. This includes the qoutfifo and target mode 351197883Sgibbs * incoming command queue. 351297883Sgibbs */ 351397883Sgibbs SHARED_DATA_ADDR { 351497883Sgibbs size 4 351597883Sgibbs } 351697883Sgibbs /* 351797883Sgibbs * Pointer to location in host memory for next 351897883Sgibbs * position in the qoutfifo. 351997883Sgibbs */ 352097883Sgibbs QOUTFIFO_NEXT_ADDR { 352197883Sgibbs size 4 352297883Sgibbs } 352397883Sgibbs /* 3524102681Sgibbs * Value to "or" into the SCBPTR[1] value to 3525102681Sgibbs * indicate that an entry in the QINFIFO is valid. 3526102681Sgibbs */ 3527102681Sgibbs QOUTFIFO_ENTRY_VALID_TAG { 3528102681Sgibbs size 1 3529102681Sgibbs } 3530102681Sgibbs /* 353197883Sgibbs * Kernel and sequencer offsets into the queue of 353297883Sgibbs * incoming target mode command descriptors. The 353397883Sgibbs * queue is full when the KERNEL_TQINPOS == TQINPOS. 353497883Sgibbs */ 353597883Sgibbs KERNEL_TQINPOS { 353697883Sgibbs size 1 353797883Sgibbs } 353897883Sgibbs TQINPOS { 353997883Sgibbs size 1 354097883Sgibbs } 354197883Sgibbs ARG_1 { 354297883Sgibbs size 1 354397883Sgibbs mask SEND_MSG 0x80 354497883Sgibbs mask SEND_SENSE 0x40 354597883Sgibbs mask SEND_REJ 0x20 354697883Sgibbs mask MSGOUT_PHASEMIS 0x10 354797883Sgibbs mask EXIT_MSG_LOOP 0x08 354897883Sgibbs mask CONT_MSG_LOOP_WRITE 0x04 354997883Sgibbs mask CONT_MSG_LOOP_READ 0x03 355097883Sgibbs mask CONT_MSG_LOOP_TARG 0x02 355197883Sgibbs alias RETURN_1 355297883Sgibbs } 355397883Sgibbs ARG_2 { 355497883Sgibbs size 1 355597883Sgibbs alias RETURN_2 355697883Sgibbs } 355797883Sgibbs 355897883Sgibbs /* 355997883Sgibbs * Snapshot of MSG_OUT taken after each message is sent. 356097883Sgibbs */ 356197883Sgibbs LAST_MSG { 356297883Sgibbs size 1 356397883Sgibbs } 356497883Sgibbs 356597883Sgibbs /* 356697883Sgibbs * Sequences the kernel driver has okayed for us. This allows 356797883Sgibbs * the driver to do things like prevent initiator or target 356897883Sgibbs * operations. 356997883Sgibbs */ 357097883Sgibbs SCSISEQ_TEMPLATE { 357197883Sgibbs size 1 3572102681Sgibbs field MANUALCTL 0x40 3573102681Sgibbs field ENSELI 0x20 3574102681Sgibbs field ENRSELI 0x10 3575102681Sgibbs field MANUALP 0x0C 3576102681Sgibbs field ENAUTOATNP 0x02 3577102681Sgibbs field ALTSTIM 0x01 357897883Sgibbs } 357997883Sgibbs 358097883Sgibbs /* 358197883Sgibbs * The initiator specified tag for this target mode transaction. 358297883Sgibbs */ 358397883Sgibbs INITIATOR_TAG { 358497883Sgibbs size 1 358597883Sgibbs } 358697883Sgibbs 358797883Sgibbs SEQ_FLAGS2 { 358897883Sgibbs size 1 3589102681Sgibbs field SCB_DMA 0x01 3590102681Sgibbs field TARGET_MSG_PENDING 0x02 3591102681Sgibbs field SELECTOUT_QFROZEN 0x04 359297883Sgibbs } 359397883Sgibbs /* 359497883Sgibbs * Target-mode CDB type to CDB length table used 359597883Sgibbs * in non-packetized operation. 359697883Sgibbs */ 359797883Sgibbs CMDSIZE_TABLE { 359897883Sgibbs size 8 359997883Sgibbs } 360097883Sgibbs} 360197883Sgibbs 360297883Sgibbs/************************* Hardware SCB Definition ****************************/ 360397883Sgibbsscb { 360497883Sgibbs address 0x180 360597883Sgibbs size 64 360697883Sgibbs modes 0, 1, 2, 3 360797883Sgibbs SCB_RESIDUAL_DATACNT { 360897883Sgibbs size 4 360997883Sgibbs alias SCB_CDB_STORE 361097883Sgibbs } 361197883Sgibbs SCB_RESIDUAL_SGPTR { 361297883Sgibbs size 4 361397883Sgibbs alias SCB_CDB_PTR 3614102681Sgibbs field SG_ADDR_MASK 0xf8 /* In the last byte */ 3615102681Sgibbs field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3616102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 361797883Sgibbs } 361897883Sgibbs SCB_SCSI_STATUS { 361997883Sgibbs size 1 362097883Sgibbs } 362197883Sgibbs SCB_TARGET_PHASES { 362297883Sgibbs size 1 362397883Sgibbs } 362497883Sgibbs SCB_TARGET_DATA_DIR { 362597883Sgibbs size 1 362697883Sgibbs } 362797883Sgibbs SCB_TARGET_ITAG { 362897883Sgibbs size 1 362997883Sgibbs } 363097883Sgibbs SCB_SENSE_BUSADDR { 363197883Sgibbs /* 363297883Sgibbs * Only valid if CDB length is less than 13 bytes or 363397883Sgibbs * we are using a CDB pointer. Otherwise contains 363497883Sgibbs * the last 4 bytes of embedded cdb information. 363597883Sgibbs */ 363697883Sgibbs size 4 363797883Sgibbs alias SCB_NEXT_COMPLETE 363897883Sgibbs } 363997883Sgibbs SCB_CDB_LEN { 364097883Sgibbs size 1 3641102681Sgibbs field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 364297883Sgibbs } 364397883Sgibbs SCB_TASK_MANAGEMENT { 364497883Sgibbs size 1 364597883Sgibbs } 364697883Sgibbs SCB_TAG { 364797883Sgibbs size 2 364897883Sgibbs } 364997883Sgibbs SCB_NEXT { 365097883Sgibbs alias SCB_NEXT_SCB_BUSADDR 365197883Sgibbs size 2 365297883Sgibbs } 365397883Sgibbs SCB_NEXT2 { 365497883Sgibbs size 2 365597883Sgibbs } 365697883Sgibbs SCB_DATAPTR { 365797883Sgibbs size 8 365897883Sgibbs } 365997883Sgibbs SCB_DATACNT { 366097883Sgibbs /* 366197883Sgibbs * The last byte is really the high address bits for 366297883Sgibbs * the data address. 366397883Sgibbs */ 366497883Sgibbs size 4 3665102681Sgibbs field SG_LAST_SEG 0x80 /* In the fourth byte */ 3666102681Sgibbs field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 366797883Sgibbs } 366897883Sgibbs SCB_SGPTR { 366997883Sgibbs size 4 3670102681Sgibbs field SG_STATUS_VALID 0x04 /* In the first byte */ 3671102681Sgibbs field SG_FULL_RESID 0x02 /* In the first byte */ 3672102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 367397883Sgibbs } 367497883Sgibbs SCB_CONTROL { 367597883Sgibbs size 1 3676102681Sgibbs field TARGET_SCB 0x80 3677102681Sgibbs field DISCENB 0x40 3678102681Sgibbs field TAG_ENB 0x20 3679102681Sgibbs field MK_MESSAGE 0x10 3680102681Sgibbs field STATUS_RCVD 0x08 3681102681Sgibbs field DISCONNECTED 0x04 3682102681Sgibbs field SCB_TAG_TYPE 0x03 368397883Sgibbs } 368497883Sgibbs SCB_SCSIID { 368597883Sgibbs size 1 3686102681Sgibbs field TID 0xF0 3687102681Sgibbs field OID 0x0F 368897883Sgibbs } 368997883Sgibbs SCB_LUN { 369097883Sgibbs size 1 3691102681Sgibbs field LID 0xff 369297883Sgibbs } 369397883Sgibbs SCB_TASK_ATTRIBUTE { 369497883Sgibbs size 1 369597883Sgibbs } 369697883Sgibbs SCB_BUSADDR { 369797883Sgibbs size 4 369897883Sgibbs } 3699102681Sgibbs SCB_SPARE { 3700102681Sgibbs size 8 3701102681Sgibbs alias SCB_PKT_LUN 3702102681Sgibbs } 370397883Sgibbs SCB_DISCONNECTED_LISTS { 3704102681Sgibbs size 8 370597883Sgibbs } 370697883Sgibbs} 370797883Sgibbs 370897883Sgibbs/*********************************** Constants ********************************/ 370997883Sgibbsconst SEQ_STACK_SIZE 8 371097883Sgibbsconst MK_MESSAGE_BIT_OFFSET 4 371197883Sgibbsconst TID_SHIFT 4 371297883Sgibbsconst TARGET_CMD_CMPLT 0xfe 371397883Sgibbsconst INVALID_ADDR 0x80 371497883Sgibbs#define SCB_LIST_NULL 0xff 3715102681Sgibbs#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 371697883Sgibbs 371797883Sgibbsconst CCSGADDR_MAX 0x80 371897883Sgibbsconst CCSCBADDR_MAX 0x80 371997883Sgibbsconst CCSGRAM_MAXSEGS 16 372097883Sgibbs 372197883Sgibbs/* Selection Timeout Timer Constants */ 372297883Sgibbsconst STIMESEL_SHIFT 3 372397883Sgibbsconst STIMESEL_MIN 0x18 372497883Sgibbsconst STIMESEL_BUG_ADJ 0x8 372597883Sgibbs 372697883Sgibbs/* WDTR Message values */ 372797883Sgibbsconst BUS_8_BIT 0x00 372897883Sgibbsconst BUS_16_BIT 0x01 372997883Sgibbsconst BUS_32_BIT 0x02 373097883Sgibbs 373197883Sgibbs/* Offset maximums */ 373297883Sgibbsconst MAX_OFFSET 0xfe 373397883Sgibbsconst MAX_OFFSET_PACED 0x7f 373497883Sgibbsconst HOST_MSG 0xff 373597883Sgibbs 373697883Sgibbs/* 373797883Sgibbs * The size of our sense buffers. 373897883Sgibbs * Sense buffer mapping can be handled in either of two ways. 373997883Sgibbs * The first is to allocate a dmamap for each transaction. 374097883Sgibbs * Depending on the architecture, dmamaps can be costly. The 374197883Sgibbs * alternative is to statically map the buffers in much the same 374297883Sgibbs * way we handle our scatter gather lists. The driver implements 374397883Sgibbs * the later. 374497883Sgibbs */ 374597883Sgibbsconst AHD_SENSE_BUFSIZE 256 374697883Sgibbs 374797883Sgibbs/* Target mode command processing constants */ 374897883Sgibbsconst CMD_GROUP_CODE_SHIFT 0x05 374997883Sgibbs 375097883Sgibbsconst STATUS_BUSY 0x08 375197883Sgibbsconst STATUS_QUEUE_FULL 0x28 375297883Sgibbsconst STATUS_PKT_SENSE 0xFF 375397883Sgibbsconst TARGET_DATA_IN 1 375497883Sgibbs 3755102681Sgibbsconst SCB_TRANSFER_SIZE_FULL_LUN 56 3756102681Sgibbsconst SCB_TRANSFER_SIZE_1BYTE_LUN 48 375797883Sgibbs/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 375897883Sgibbsconst PKT_OVERRUN_BUFSIZE 512 375997883Sgibbs 376097883Sgibbs/* 376197883Sgibbs * Downloaded (kernel inserted) constants 376297883Sgibbs */ 376397883Sgibbsconst SG_PREFETCH_CNT download 376497883Sgibbsconst SG_PREFETCH_CNT_LIMIT download 376597883Sgibbsconst SG_PREFETCH_ALIGN_MASK download 376697883Sgibbsconst SG_PREFETCH_ADDR_MASK download 376797883Sgibbsconst SG_SIZEOF download 376897883Sgibbsconst PKT_OVERRUN_BUFOFFSET download 3769102681Sgibbsconst SCB_TRANSFER_SIZE download 377097883Sgibbs 377197883Sgibbs/* 377297883Sgibbs * BIOS SCB offsets 377397883Sgibbs */ 377497883Sgibbsconst NVRAM_SCB_OFFSET 0x2C 3775