1139749Simp/*- 297883Sgibbs * Aic79xx register and scratch ram definitions. 397883Sgibbs * 4133122Sgibbs * Copyright (c) 1994-2001, 2004 Justin T. Gibbs. 5102681Sgibbs * Copyright (c) 2000-2002 Adaptec Inc. 697883Sgibbs * All rights reserved. 797883Sgibbs * 897883Sgibbs * Redistribution and use in source and binary forms, with or without 997883Sgibbs * modification, are permitted provided that the following conditions 1097883Sgibbs * are met: 1197883Sgibbs * 1. Redistributions of source code must retain the above copyright 1297883Sgibbs * notice, this list of conditions, and the following disclaimer, 1397883Sgibbs * without modification. 1497883Sgibbs * 2. Redistributions in binary form must reproduce at minimum a disclaimer 1597883Sgibbs * substantially similar to the "NO WARRANTY" disclaimer below 1697883Sgibbs * ("Disclaimer") and any redistribution must be conditioned upon 1797883Sgibbs * including a substantially similar Disclaimer requirement for further 1897883Sgibbs * binary redistribution. 1997883Sgibbs * 3. Neither the names of the above-listed copyright holders nor the names 2097883Sgibbs * of any contributors may be used to endorse or promote products derived 2197883Sgibbs * from this software without specific prior written permission. 2297883Sgibbs * 2397883Sgibbs * Alternatively, this software may be distributed under the terms of the 2497883Sgibbs * GNU General Public License ("GPL") version 2 as published by the Free 2597883Sgibbs * Software Foundation. 2697883Sgibbs * 2797883Sgibbs * NO WARRANTY 2897883Sgibbs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2997883Sgibbs * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3097883Sgibbs * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 3197883Sgibbs * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3297883Sgibbs * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3397883Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3497883Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3597883Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 3697883Sgibbs * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 3797883Sgibbs * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3897883Sgibbs * POSSIBILITY OF SUCH DAMAGES. 3997883Sgibbs * 4097883Sgibbs * $FreeBSD$ 4197883Sgibbs */ 42129134SgibbsVERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $" 4397883Sgibbs 4497883Sgibbs/* 4597883Sgibbs * This file is processed by the aic7xxx_asm utility for use in assembling 4697883Sgibbs * firmware for the aic79xx family of SCSI host adapters as well as to generate 4797883Sgibbs * a C header file for use in the kernel portion of the Aic79xx driver. 4897883Sgibbs */ 4997883Sgibbs 5097883Sgibbs/* Register window Modes */ 5197883Sgibbs#define M_DFF0 0 5297883Sgibbs#define M_DFF1 1 5397883Sgibbs#define M_CCHAN 2 5497883Sgibbs#define M_SCSI 3 5597883Sgibbs#define M_CFG 4 5697883Sgibbs#define M_DST_SHIFT 4 5797883Sgibbs 5897883Sgibbs#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59104023Sgibbs#define SET_MODE(src, dst) \ 60104023Sgibbs SET_SRC_MODE src; \ 61104023Sgibbs SET_DST_MODE dst; \ 62104023Sgibbs if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63104023Sgibbs mvi MK_MODE(src, dst) call set_mode_work_around; \ 64104023Sgibbs } else { \ 65104023Sgibbs mvi MODE_PTR, MK_MODE(src, dst); \ 66104023Sgibbs } 6797883Sgibbs 68107441Sscottl#define RESTORE_MODE(mode) \ 69107441Sscottl if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70107441Sscottl mov mode call set_mode_work_around; \ 71107441Sscottl } else { \ 72107441Sscottl mov MODE_PTR, mode; \ 73107441Sscottl } 74104023Sgibbs 75107441Sscottl#define SET_SEQINTCODE(code) \ 76107441Sscottl if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 77107441Sscottl mvi code call set_seqint_work_around; \ 78107441Sscottl } else { \ 79107441Sscottl mvi SEQINTCODE, code; \ 80107441Sscottl } 81107441Sscottl 8297883Sgibbs/* 8397883Sgibbs * Mode Pointer 8497883Sgibbs * Controls which of the 5, 512byte, address spaces should be used 8597883Sgibbs * as the source and destination of any register accesses in our 8697883Sgibbs * register window. 8797883Sgibbs */ 8897883Sgibbsregister MODE_PTR { 8997883Sgibbs address 0x000 9097883Sgibbs access_mode RW 91102681Sgibbs field DST_MODE 0x70 92102681Sgibbs field SRC_MODE 0x07 9397883Sgibbs mode_pointer 9497883Sgibbs} 9597883Sgibbs 9697883Sgibbsconst SRC_MODE_SHIFT 0 9797883Sgibbsconst DST_MODE_SHIFT 4 9897883Sgibbs 9997883Sgibbs/* 10097883Sgibbs * Host Interrupt Status 10197883Sgibbs */ 10297883Sgibbsregister INTSTAT { 10397883Sgibbs address 0x001 10497883Sgibbs access_mode RW 105102681Sgibbs field HWERRINT 0x80 106102681Sgibbs field BRKADRINT 0x40 107102681Sgibbs field SWTMINT 0x20 108102681Sgibbs field PCIINT 0x10 109102681Sgibbs field SCSIINT 0x08 110102681Sgibbs field SEQINT 0x04 111102681Sgibbs field CMDCMPLT 0x02 112102681Sgibbs field SPLTINT 0x01 11397883Sgibbs mask INT_PEND 0xFF 11497883Sgibbs} 11597883Sgibbs 11697883Sgibbs/* 11797883Sgibbs * Sequencer Interrupt Code 11897883Sgibbs */ 11997883Sgibbsregister SEQINTCODE { 12097883Sgibbs address 0x002 12197883Sgibbs access_mode RW 122102681Sgibbs field { 123107441Sscottl NO_SEQINT, /* No seqint pending. */ 124107441Sscottl BAD_PHASE, /* unknown scsi bus phase */ 125102681Sgibbs SEND_REJECT, /* sending a message reject */ 126102681Sgibbs PROTO_VIOLATION, /* Protocol Violation */ 127102681Sgibbs NO_MATCH, /* no cmd match for reconnect */ 128102681Sgibbs IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 129102681Sgibbs PDATA_REINIT, /* 13097883Sgibbs * Returned to data phase 13197883Sgibbs * that requires data 13297883Sgibbs * transfer pointers to be 13397883Sgibbs * recalculated from the 13497883Sgibbs * transfer residual. 13597883Sgibbs */ 136102681Sgibbs HOST_MSG_LOOP, /* 13797883Sgibbs * The bus is ready for the 13897883Sgibbs * host to perform another 13997883Sgibbs * message transaction. This 14097883Sgibbs * mechanism is used for things 14197883Sgibbs * like sync/wide negotiation 14297883Sgibbs * that require a kernel based 14397883Sgibbs * message state engine. 14497883Sgibbs */ 145102681Sgibbs BAD_STATUS, /* Bad status from target */ 146102681Sgibbs DATA_OVERRUN, /* 14797883Sgibbs * Target attempted to write 14897883Sgibbs * beyond the bounds of its 14997883Sgibbs * command. 15097883Sgibbs */ 151102681Sgibbs MKMSG_FAILED, /* 15297883Sgibbs * Target completed command 15397883Sgibbs * without honoring our ATN 15497883Sgibbs * request to issue a message. 15597883Sgibbs */ 156102681Sgibbs MISSED_BUSFREE, /* 15797883Sgibbs * The sequencer never saw 15897883Sgibbs * the bus go free after 15997883Sgibbs * either a command complete 16097883Sgibbs * or disconnect message. 16197883Sgibbs */ 162102681Sgibbs DUMP_CARD_STATE, 163102681Sgibbs ILLEGAL_PHASE, 164102681Sgibbs INVALID_SEQINT, 165102681Sgibbs CFG4ISTAT_INTR, 166102681Sgibbs STATUS_OVERRUN, 167102681Sgibbs CFG4OVERRUN, 168107441Sscottl ENTERING_NONPACK, 169109588Sgibbs TASKMGMT_FUNC_COMPLETE, /* 170109588Sgibbs * Task management function 171109588Sgibbs * request completed with 172109588Sgibbs * an expected busfree. 173109588Sgibbs */ 174109588Sgibbs TASKMGMT_CMD_CMPLT_OKAY, /* 175109588Sgibbs * A command with a non-zero 176109588Sgibbs * task management function 177109588Sgibbs * has completed via the normal 178109588Sgibbs * command completion method 179109588Sgibbs * for commands with a zero 180109588Sgibbs * task management function. 181109588Sgibbs * This happens when an attempt 182109588Sgibbs * to abort a command loses 183109588Sgibbs * the race for the command to 184109588Sgibbs * complete normally. 185109588Sgibbs */ 186107441Sscottl TRACEPOINT0, 187107441Sscottl TRACEPOINT1, 188107441Sscottl TRACEPOINT2, 189107441Sscottl TRACEPOINT3, 190114623Sgibbs SAW_HWERR, 191114623Sgibbs BAD_SCB_STATUS 192102681Sgibbs } 19397883Sgibbs} 19497883Sgibbs 19597883Sgibbs/* 19697883Sgibbs * Clear Host Interrupt 19797883Sgibbs */ 19897883Sgibbsregister CLRINT { 19997883Sgibbs address 0x003 20097883Sgibbs access_mode WO 201102681Sgibbs field CLRHWERRINT 0x80 /* Rev B or greater */ 202102681Sgibbs field CLRBRKADRINT 0x40 203102681Sgibbs field CLRSWTMINT 0x20 204107623Sscottl field CLRPCIINT 0x10 205102681Sgibbs field CLRSCSIINT 0x08 206102681Sgibbs field CLRSEQINT 0x04 207102681Sgibbs field CLRCMDINT 0x02 208102681Sgibbs field CLRSPLTINT 0x01 20997883Sgibbs} 21097883Sgibbs 21197883Sgibbs/* 21297883Sgibbs * Error Register 21397883Sgibbs */ 21497883Sgibbsregister ERROR { 21597883Sgibbs address 0x004 21697883Sgibbs access_mode RO 217102681Sgibbs field CIOPARERR 0x80 218102681Sgibbs field CIOACCESFAIL 0x40 /* Rev B or greater */ 219102681Sgibbs field MPARERR 0x20 220102681Sgibbs field DPARERR 0x10 221102681Sgibbs field SQPARERR 0x08 222102681Sgibbs field ILLOPCODE 0x04 223102681Sgibbs field DSCTMOUT 0x02 22497883Sgibbs} 22597883Sgibbs 22697883Sgibbs/* 22797883Sgibbs * Clear Error 22897883Sgibbs */ 22997883Sgibbsregister CLRERR { 23097883Sgibbs address 0x004 23197883Sgibbs access_mode WO 232102681Sgibbs field CLRCIOPARERR 0x80 233102681Sgibbs field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 234102681Sgibbs field CLRMPARERR 0x20 235102681Sgibbs field CLRDPARERR 0x10 236102681Sgibbs field CLRSQPARERR 0x08 237102681Sgibbs field CLRILLOPCODE 0x04 238102681Sgibbs field CLRDSCTMOUT 0x02 23997883Sgibbs} 24097883Sgibbs 24197883Sgibbs/* 24297883Sgibbs * Host Control Register 24397883Sgibbs * Overall host control of the device. 24497883Sgibbs */ 24597883Sgibbsregister HCNTRL { 24697883Sgibbs address 0x005 24797883Sgibbs access_mode RW 248102681Sgibbs field SEQ_RESET 0x80 /* Rev B or greater */ 249102681Sgibbs field POWRDN 0x40 250102681Sgibbs field SWINT 0x10 251102681Sgibbs field SWTIMER_START_B 0x08 /* Rev B or greater */ 252102681Sgibbs field PAUSE 0x04 253102681Sgibbs field INTEN 0x02 254102681Sgibbs field CHIPRST 0x01 255102681Sgibbs field CHIPRSTACK 0x01 25697883Sgibbs} 25797883Sgibbs 25897883Sgibbs/* 25997883Sgibbs * Host New SCB Queue Offset 26097883Sgibbs */ 26197883Sgibbsregister HNSCB_QOFF { 26297883Sgibbs address 0x006 26397883Sgibbs access_mode RW 26497883Sgibbs size 2 26597883Sgibbs} 26697883Sgibbs 26797883Sgibbs/* 26897883Sgibbs * Host Empty SCB Queue Offset 26997883Sgibbs */ 27097883Sgibbsregister HESCB_QOFF { 27197883Sgibbs address 0x008 27297883Sgibbs access_mode RW 27397883Sgibbs} 27497883Sgibbs 27597883Sgibbs/* 27697883Sgibbs * Host Mailbox 27797883Sgibbs */ 27897883Sgibbsregister HS_MAILBOX { 279109588Sgibbs address 0x00B 28097883Sgibbs access_mode RW 28197883Sgibbs mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 282115329Sgibbs mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ 28397883Sgibbs} 28497883Sgibbs 28597883Sgibbs/* 286299375Spfg * Sequencer Interrupt Status 28797883Sgibbs */ 28897883Sgibbsregister SEQINTSTAT { 289109588Sgibbs address 0x00C 29097883Sgibbs access_mode RO 291102681Sgibbs field SEQ_SWTMRTO 0x10 292102681Sgibbs field SEQ_SEQINT 0x08 293102681Sgibbs field SEQ_SCSIINT 0x04 294102681Sgibbs field SEQ_PCIINT 0x02 295102681Sgibbs field SEQ_SPLTINT 0x01 29697883Sgibbs} 29797883Sgibbs 29897883Sgibbs/* 29997883Sgibbs * Clear SEQ Interrupt 30097883Sgibbs */ 30197883Sgibbsregister CLRSEQINTSTAT { 302109588Sgibbs address 0x00C 30397883Sgibbs access_mode WO 304102681Sgibbs field CLRSEQ_SWTMRTO 0x10 305102681Sgibbs field CLRSEQ_SEQINT 0x08 306102681Sgibbs field CLRSEQ_SCSIINT 0x04 307102681Sgibbs field CLRSEQ_PCIINT 0x02 308102681Sgibbs field CLRSEQ_SPLTINT 0x01 30997883Sgibbs} 31097883Sgibbs 31197883Sgibbs/* 31297883Sgibbs * Software Timer 31397883Sgibbs */ 31497883Sgibbsregister SWTIMER { 315109588Sgibbs address 0x00E 31697883Sgibbs access_mode RW 31797883Sgibbs size 2 31897883Sgibbs} 31997883Sgibbs 32097883Sgibbs/* 32197883Sgibbs * SEQ New SCB Queue Offset 32297883Sgibbs */ 32397883Sgibbsregister SNSCB_QOFF { 32497883Sgibbs address 0x010 32597883Sgibbs access_mode RW 32697883Sgibbs size 2 32797883Sgibbs modes M_CCHAN 32897883Sgibbs} 32997883Sgibbs 33097883Sgibbs/* 33197883Sgibbs * SEQ Empty SCB Queue Offset 33297883Sgibbs */ 33397883Sgibbsregister SESCB_QOFF { 33497883Sgibbs address 0x012 33597883Sgibbs access_mode RW 33697883Sgibbs modes M_CCHAN 33797883Sgibbs} 33897883Sgibbs 33997883Sgibbs/* 34097883Sgibbs * SEQ Done SCB Queue Offset 34197883Sgibbs */ 34297883Sgibbsregister SDSCB_QOFF { 34397883Sgibbs address 0x014 34497883Sgibbs access_mode RW 34597883Sgibbs modes M_CCHAN 34697883Sgibbs size 2 34797883Sgibbs} 34897883Sgibbs 34997883Sgibbs/* 35097883Sgibbs * Queue Offset Control & Status 35197883Sgibbs */ 35297883Sgibbsregister QOFF_CTLSTA { 35397883Sgibbs address 0x016 35497883Sgibbs access_mode RW 35597883Sgibbs modes M_CCHAN 356102681Sgibbs field EMPTY_SCB_AVAIL 0x80 357102681Sgibbs field NEW_SCB_AVAIL 0x40 358102681Sgibbs field SDSCB_ROLLOVR 0x20 359102681Sgibbs field HS_MAILBOX_ACT 0x10 360102681Sgibbs field SCB_QSIZE 0x0F { 361102681Sgibbs SCB_QSIZE_4, 362102681Sgibbs SCB_QSIZE_8, 363102681Sgibbs SCB_QSIZE_16, 364102681Sgibbs SCB_QSIZE_32, 365102681Sgibbs SCB_QSIZE_64, 366102681Sgibbs SCB_QSIZE_128, 367102681Sgibbs SCB_QSIZE_256, 368102681Sgibbs SCB_QSIZE_512, 369102681Sgibbs SCB_QSIZE_1024, 370102681Sgibbs SCB_QSIZE_2048, 371102681Sgibbs SCB_QSIZE_4096, 372102681Sgibbs SCB_QSIZE_8192, 373102681Sgibbs SCB_QSIZE_16384 374102681Sgibbs } 37597883Sgibbs} 37697883Sgibbs 37797883Sgibbs/* 37897883Sgibbs * Interrupt Control 37997883Sgibbs */ 38097883Sgibbsregister INTCTL { 38197883Sgibbs address 0x018 38297883Sgibbs access_mode RW 383102681Sgibbs field SWTMINTMASK 0x80 384102681Sgibbs field SWTMINTEN 0x40 385102681Sgibbs field SWTIMER_START 0x20 386102681Sgibbs field AUTOCLRCMDINT 0x10 387102681Sgibbs field PCIINTEN 0x08 388102681Sgibbs field SCSIINTEN 0x04 389102681Sgibbs field SEQINTEN 0x02 390102681Sgibbs field SPLTINTEN 0x01 39197883Sgibbs} 39297883Sgibbs 39397883Sgibbs/* 39497883Sgibbs * Data FIFO Control 39597883Sgibbs */ 39697883Sgibbsregister DFCNTRL { 39797883Sgibbs address 0x019 39897883Sgibbs access_mode RW 39997883Sgibbs modes M_DFF0, M_DFF1 400102681Sgibbs field PRELOADEN 0x80 401107441Sscottl field SCSIENWRDIS 0x40 /* Rev B only. */ 402102681Sgibbs field SCSIEN 0x20 403102681Sgibbs field SCSIENACK 0x20 404102681Sgibbs field HDMAEN 0x08 405102681Sgibbs field HDMAENACK 0x08 406102681Sgibbs field DIRECTION 0x04 407102681Sgibbs field DIRECTIONACK 0x04 408102681Sgibbs field FIFOFLUSH 0x02 409102681Sgibbs field FIFOFLUSHACK 0x02 410102681Sgibbs field DIRECTIONEN 0x01 41197883Sgibbs} 41297883Sgibbs 41397883Sgibbs/* 41497883Sgibbs * Device Space Command 0 41597883Sgibbs */ 41697883Sgibbsregister DSCOMMAND0 { 41797883Sgibbs address 0x019 41897883Sgibbs access_mode RW 41997883Sgibbs modes M_CFG 420102681Sgibbs field CACHETHEN 0x80 /* Cache Threshold enable */ 421102681Sgibbs field DPARCKEN 0x40 /* Data Parity Check Enable */ 422102681Sgibbs field MPARCKEN 0x20 /* Memory Parity Check Enable */ 423102681Sgibbs field EXTREQLCK 0x10 /* External Request Lock */ 424102681Sgibbs field DISABLE_TWATE 0x02 /* Rev B or greater */ 425102681Sgibbs field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 42697883Sgibbs} 42797883Sgibbs 42897883Sgibbs/* 42997883Sgibbs * Data FIFO Status 43097883Sgibbs */ 43197883Sgibbsregister DFSTATUS { 43297883Sgibbs address 0x01A 43397883Sgibbs access_mode RO 43497883Sgibbs modes M_DFF0, M_DFF1 435102681Sgibbs field PRELOAD_AVAIL 0x80 436102681Sgibbs field PKT_PRELOAD_AVAIL 0x40 437102681Sgibbs field MREQPEND 0x10 438102681Sgibbs field HDONE 0x08 439102681Sgibbs field DFTHRESH 0x04 440102681Sgibbs field FIFOFULL 0x02 441102681Sgibbs field FIFOEMP 0x01 44297883Sgibbs} 44397883Sgibbs 44497883Sgibbs/* 44597883Sgibbs * S/G Cache Pointer 44697883Sgibbs */ 44797883Sgibbsregister SG_CACHE_PRE { 44897883Sgibbs address 0x01B 44997883Sgibbs access_mode WO 45097883Sgibbs modes M_DFF0, M_DFF1 451102681Sgibbs field SG_ADDR_MASK 0xf8 452102681Sgibbs field ODD_SEG 0x04 453102681Sgibbs field LAST_SEG 0x02 45497883Sgibbs} 45597883Sgibbs 45697883Sgibbsregister SG_CACHE_SHADOW { 45797883Sgibbs address 0x01B 45897883Sgibbs access_mode RO 45997883Sgibbs modes M_DFF0, M_DFF1 460102681Sgibbs field SG_ADDR_MASK 0xf8 461102681Sgibbs field ODD_SEG 0x04 462102681Sgibbs field LAST_SEG 0x02 463102681Sgibbs field LAST_SEG_DONE 0x01 46497883Sgibbs} 46597883Sgibbs 46697883Sgibbs/* 46797883Sgibbs * Arbiter Control 46897883Sgibbs */ 46997883Sgibbsregister ARBCTL { 47097883Sgibbs address 0x01B 47197883Sgibbs access_mode RW 47297883Sgibbs modes M_CFG 473102681Sgibbs field RESET_HARB 0x80 474102681Sgibbs field RETRY_SWEN 0x08 475102681Sgibbs field USE_TIME 0x07 47697883Sgibbs} 47797883Sgibbs 47897883Sgibbs/* 47997883Sgibbs * Data Channel Host Address 48097883Sgibbs */ 48197883Sgibbsregister HADDR { 48297883Sgibbs address 0x070 48397883Sgibbs access_mode RW 48497883Sgibbs size 8 48597883Sgibbs modes M_DFF0, M_DFF1 48697883Sgibbs} 48797883Sgibbs 48897883Sgibbs/* 48997883Sgibbs * Host Overlay DMA Address 49097883Sgibbs */ 49197883Sgibbsregister HODMAADR { 49297883Sgibbs address 0x070 49397883Sgibbs access_mode RW 49497883Sgibbs size 8 49597883Sgibbs modes M_SCSI 49697883Sgibbs} 49797883Sgibbs 49897883Sgibbs/* 499107441Sscottl * PCI PLL Delay. 500107441Sscottl */ 501107441Sscottlregister PLLDELAY { 502107441Sscottl address 0x070 503107441Sscottl access_mode RW 504107441Sscottl size 1 505107441Sscottl modes M_CFG 506107441Sscottl field SPLIT_DROP_REQ 0x80 507107441Sscottl} 508107441Sscottl 509107441Sscottl/* 51097883Sgibbs * Data Channel Host Count 51197883Sgibbs */ 51297883Sgibbsregister HCNT { 51397883Sgibbs address 0x078 51497883Sgibbs access_mode RW 51597883Sgibbs size 3 51697883Sgibbs modes M_DFF0, M_DFF1 51797883Sgibbs} 51897883Sgibbs 51997883Sgibbs/* 52097883Sgibbs * Host Overlay DMA Count 52197883Sgibbs */ 52297883Sgibbsregister HODMACNT { 52397883Sgibbs address 0x078 52497883Sgibbs access_mode RW 52597883Sgibbs size 2 52697883Sgibbs modes M_SCSI 52797883Sgibbs} 52897883Sgibbs 52997883Sgibbs/* 53097883Sgibbs * Host Overlay DMA Enable 53197883Sgibbs */ 53297883Sgibbsregister HODMAEN { 53397883Sgibbs address 0x07A 53497883Sgibbs access_mode RW 53597883Sgibbs modes M_SCSI 53697883Sgibbs} 53797883Sgibbs 53897883Sgibbs/* 53997883Sgibbs * Scatter/Gather Host Address 54097883Sgibbs */ 54197883Sgibbsregister SGHADDR { 54297883Sgibbs address 0x07C 54397883Sgibbs access_mode RW 54497883Sgibbs size 8 54597883Sgibbs modes M_DFF0, M_DFF1 54697883Sgibbs} 54797883Sgibbs 54897883Sgibbs/* 54997883Sgibbs * SCB Host Address 55097883Sgibbs */ 55197883Sgibbsregister SCBHADDR { 55297883Sgibbs address 0x07C 55397883Sgibbs access_mode RW 55497883Sgibbs size 8 55597883Sgibbs modes M_CCHAN 55697883Sgibbs} 55797883Sgibbs 55897883Sgibbs/* 55997883Sgibbs * Scatter/Gather Host Count 56097883Sgibbs */ 56197883Sgibbsregister SGHCNT { 56297883Sgibbs address 0x084 56397883Sgibbs access_mode RW 56497883Sgibbs modes M_DFF0, M_DFF1 56597883Sgibbs} 56697883Sgibbs 56797883Sgibbs/* 56897883Sgibbs * SCB Host Count 56997883Sgibbs */ 57097883Sgibbsregister SCBHCNT { 57197883Sgibbs address 0x084 57297883Sgibbs access_mode RW 57397883Sgibbs modes M_CCHAN 57497883Sgibbs} 57597883Sgibbs 57697883Sgibbs/* 57797883Sgibbs * Data FIFO Threshold 57897883Sgibbs */ 57997883Sgibbsregister DFF_THRSH { 58097883Sgibbs address 0x088 58197883Sgibbs access_mode RW 58297883Sgibbs modes M_CFG 583102681Sgibbs field WR_DFTHRSH 0x70 { 584102681Sgibbs WR_DFTHRSH_MIN, 585102681Sgibbs WR_DFTHRSH_25, 586102681Sgibbs WR_DFTHRSH_50, 587102681Sgibbs WR_DFTHRSH_63, 588102681Sgibbs WR_DFTHRSH_75, 589102681Sgibbs WR_DFTHRSH_85, 590102681Sgibbs WR_DFTHRSH_90, 591102681Sgibbs WR_DFTHRSH_MAX 592102681Sgibbs } 593102681Sgibbs field RD_DFTHRSH 0x07 { 594102681Sgibbs RD_DFTHRSH_MIN, 595102681Sgibbs RD_DFTHRSH_25, 596102681Sgibbs RD_DFTHRSH_50, 597102681Sgibbs RD_DFTHRSH_63, 598102681Sgibbs RD_DFTHRSH_75, 599102681Sgibbs RD_DFTHRSH_85, 600102681Sgibbs RD_DFTHRSH_90, 601102681Sgibbs RD_DFTHRSH_MAX 602102681Sgibbs } 60397883Sgibbs} 60497883Sgibbs 60597883Sgibbs/* 60697883Sgibbs * ROM Address 60797883Sgibbs */ 60897883Sgibbsregister ROMADDR { 60997883Sgibbs address 0x08A 61097883Sgibbs access_mode RW 61197883Sgibbs size 3 61297883Sgibbs} 61397883Sgibbs 61497883Sgibbs/* 61597883Sgibbs * ROM Control 61697883Sgibbs */ 61797883Sgibbsregister ROMCNTRL { 61897883Sgibbs address 0x08D 61997883Sgibbs access_mode RW 620102681Sgibbs field ROMOP 0xE0 621102681Sgibbs field ROMSPD 0x18 622102681Sgibbs field REPEAT 0x02 623102681Sgibbs field RDY 0x01 62497883Sgibbs} 62597883Sgibbs 62697883Sgibbs/* 62797883Sgibbs * ROM Data 62897883Sgibbs */ 62997883Sgibbsregister ROMDATA { 63097883Sgibbs address 0x08E 63197883Sgibbs access_mode RW 63297883Sgibbs} 63397883Sgibbs 63497883Sgibbs/* 63597883Sgibbs * Data Channel Receive Message 0 63697883Sgibbs */ 63797883Sgibbsregister DCHRXMSG0 { 63897883Sgibbs address 0x090 63997883Sgibbs access_mode RO 64097883Sgibbs modes M_DFF0, M_DFF1 641102681Sgibbs field CDNUM 0xF8 642102681Sgibbs field CFNUM 0x07 64397883Sgibbs} 64497883Sgibbs 64597883Sgibbs/* 646299375Spfg * CMC Receive Message 0 64797883Sgibbs */ 64897883Sgibbsregister CMCRXMSG0 { 64997883Sgibbs address 0x090 65097883Sgibbs access_mode RO 65197883Sgibbs modes M_CCHAN 652102681Sgibbs field CDNUM 0xF8 653102681Sgibbs field CFNUM 0x07 65497883Sgibbs} 65597883Sgibbs 65697883Sgibbs/* 657299375Spfg * Overlay Receive Message 0 65897883Sgibbs */ 65997883Sgibbsregister OVLYRXMSG0 { 66097883Sgibbs address 0x090 66197883Sgibbs access_mode RO 66297883Sgibbs modes M_SCSI 663102681Sgibbs field CDNUM 0xF8 664102681Sgibbs field CFNUM 0x07 66597883Sgibbs} 66697883Sgibbs 66797883Sgibbs/* 66897883Sgibbs * Relaxed Order Enable 66997883Sgibbs */ 67097883Sgibbsregister ROENABLE { 67197883Sgibbs address 0x090 67297883Sgibbs access_mode RW 67397883Sgibbs modes M_CFG 674102681Sgibbs field MSIROEN 0x20 675102681Sgibbs field OVLYROEN 0x10 676102681Sgibbs field CMCROEN 0x08 677102681Sgibbs field SGROEN 0x04 678102681Sgibbs field DCH1ROEN 0x02 679102681Sgibbs field DCH0ROEN 0x01 68097883Sgibbs} 68197883Sgibbs 68297883Sgibbs/* 68397883Sgibbs * Data Channel Receive Message 1 68497883Sgibbs */ 68597883Sgibbsregister DCHRXMSG1 { 68697883Sgibbs address 0x091 68797883Sgibbs access_mode RO 68897883Sgibbs modes M_DFF0, M_DFF1 689102681Sgibbs field CBNUM 0xFF 69097883Sgibbs} 69197883Sgibbs 69297883Sgibbs/* 693299375Spfg * CMC Receive Message 1 69497883Sgibbs */ 69597883Sgibbsregister CMCRXMSG1 { 69697883Sgibbs address 0x091 69797883Sgibbs access_mode RO 69897883Sgibbs modes M_CCHAN 699102681Sgibbs field CBNUM 0xFF 70097883Sgibbs} 70197883Sgibbs 70297883Sgibbs/* 703299375Spfg * Overlay Receive Message 1 70497883Sgibbs */ 70597883Sgibbsregister OVLYRXMSG1 { 70697883Sgibbs address 0x091 70797883Sgibbs access_mode RO 70897883Sgibbs modes M_SCSI 709102681Sgibbs field CBNUM 0xFF 71097883Sgibbs} 71197883Sgibbs 71297883Sgibbs/* 71397883Sgibbs * No Snoop Enable 71497883Sgibbs */ 71597883Sgibbsregister NSENABLE { 71697883Sgibbs address 0x091 71797883Sgibbs access_mode RW 71897883Sgibbs modes M_CFG 719102681Sgibbs field MSINSEN 0x20 720102681Sgibbs field OVLYNSEN 0x10 721102681Sgibbs field CMCNSEN 0x08 722102681Sgibbs field SGNSEN 0x04 723102681Sgibbs field DCH1NSEN 0x02 724102681Sgibbs field DCH0NSEN 0x01 72597883Sgibbs} 72697883Sgibbs 72797883Sgibbs/* 72897883Sgibbs * Data Channel Receive Message 2 72997883Sgibbs */ 73097883Sgibbsregister DCHRXMSG2 { 73197883Sgibbs address 0x092 73297883Sgibbs access_mode RO 73397883Sgibbs modes M_DFF0, M_DFF1 734102681Sgibbs field MINDEX 0xFF 73597883Sgibbs} 73697883Sgibbs 73797883Sgibbs/* 738299375Spfg * CMC Receive Message 2 73997883Sgibbs */ 74097883Sgibbsregister CMCRXMSG2 { 74197883Sgibbs address 0x092 74297883Sgibbs access_mode RO 74397883Sgibbs modes M_CCHAN 744102681Sgibbs field MINDEX 0xFF 74597883Sgibbs} 74697883Sgibbs 74797883Sgibbs/* 748299375Spfg * Overlay Receive Message 2 74997883Sgibbs */ 75097883Sgibbsregister OVLYRXMSG2 { 75197883Sgibbs address 0x092 75297883Sgibbs access_mode RO 75397883Sgibbs modes M_SCSI 754102681Sgibbs field MINDEX 0xFF 75597883Sgibbs} 75697883Sgibbs 75797883Sgibbs/* 75897883Sgibbs * Outstanding Split Transactions 75997883Sgibbs */ 76097883Sgibbsregister OST { 76197883Sgibbs address 0x092 76297883Sgibbs access_mode RW 76397883Sgibbs modes M_CFG 76497883Sgibbs} 76597883Sgibbs 76697883Sgibbs/* 76797883Sgibbs * Data Channel Receive Message 3 76897883Sgibbs */ 76997883Sgibbsregister DCHRXMSG3 { 77097883Sgibbs address 0x093 77197883Sgibbs access_mode RO 77297883Sgibbs modes M_DFF0, M_DFF1 773102681Sgibbs field MCLASS 0x0F 77497883Sgibbs} 77597883Sgibbs 77697883Sgibbs/* 777299375Spfg * CMC Receive Message 3 77897883Sgibbs */ 77997883Sgibbsregister CMCRXMSG3 { 78097883Sgibbs address 0x093 78197883Sgibbs access_mode RO 78297883Sgibbs modes M_CCHAN 783102681Sgibbs field MCLASS 0x0F 78497883Sgibbs} 78597883Sgibbs 78697883Sgibbs/* 787299375Spfg * Overlay Receive Message 3 78897883Sgibbs */ 78997883Sgibbsregister OVLYRXMSG3 { 79097883Sgibbs address 0x093 79197883Sgibbs access_mode RO 79297883Sgibbs modes M_SCSI 793102681Sgibbs field MCLASS 0x0F 79497883Sgibbs} 79597883Sgibbs 79697883Sgibbs/* 79797883Sgibbs * PCI-X Control 79897883Sgibbs */ 79997883Sgibbsregister PCIXCTL { 80097883Sgibbs address 0x093 80197883Sgibbs access_mode RW 80297883Sgibbs modes M_CFG 803102681Sgibbs field SERRPULSE 0x80 804102681Sgibbs field UNEXPSCIEN 0x20 805102681Sgibbs field SPLTSMADIS 0x10 806102681Sgibbs field SPLTSTADIS 0x08 807102681Sgibbs field SRSPDPEEN 0x04 808102681Sgibbs field TSCSERREN 0x02 809102681Sgibbs field CMPABCDIS 0x01 81097883Sgibbs} 81197883Sgibbs 81297883Sgibbs/* 81397883Sgibbs * CMC Sequencer Byte Count 81497883Sgibbs */ 81597883Sgibbsregister CMCSEQBCNT { 81697883Sgibbs address 0x094 81797883Sgibbs access_mode RO 81897883Sgibbs modes M_CCHAN 81997883Sgibbs} 82097883Sgibbs 82197883Sgibbs/* 82297883Sgibbs * Overlay Sequencer Byte Count 82397883Sgibbs */ 82497883Sgibbsregister OVLYSEQBCNT { 82597883Sgibbs address 0x094 82697883Sgibbs access_mode RO 82797883Sgibbs modes M_SCSI 82897883Sgibbs} 82997883Sgibbs 83097883Sgibbs/* 83197883Sgibbs * Data Channel Sequencer Byte Count 83297883Sgibbs */ 83397883Sgibbsregister DCHSEQBCNT { 83497883Sgibbs address 0x094 83597883Sgibbs access_mode RO 83697883Sgibbs size 2 83797883Sgibbs modes M_DFF0, M_DFF1 83897883Sgibbs} 83997883Sgibbs 84097883Sgibbs/* 84197883Sgibbs * Data Channel Split Status 0 84297883Sgibbs */ 84397883Sgibbsregister DCHSPLTSTAT0 { 84497883Sgibbs address 0x096 84597883Sgibbs access_mode RW 84697883Sgibbs modes M_DFF0, M_DFF1 847102681Sgibbs field STAETERM 0x80 848102681Sgibbs field SCBCERR 0x40 849102681Sgibbs field SCADERR 0x20 850102681Sgibbs field SCDATBUCKET 0x10 851102681Sgibbs field CNTNOTCMPLT 0x08 852102681Sgibbs field RXOVRUN 0x04 853102681Sgibbs field RXSCEMSG 0x02 854102681Sgibbs field RXSPLTRSP 0x01 85597883Sgibbs} 85697883Sgibbs 85797883Sgibbs/* 85897883Sgibbs * CMC Split Status 0 85997883Sgibbs */ 86097883Sgibbsregister CMCSPLTSTAT0 { 86197883Sgibbs address 0x096 86297883Sgibbs access_mode RW 86397883Sgibbs modes M_CCHAN 864102681Sgibbs field STAETERM 0x80 865102681Sgibbs field SCBCERR 0x40 866102681Sgibbs field SCADERR 0x20 867102681Sgibbs field SCDATBUCKET 0x10 868102681Sgibbs field CNTNOTCMPLT 0x08 869102681Sgibbs field RXOVRUN 0x04 870102681Sgibbs field RXSCEMSG 0x02 871102681Sgibbs field RXSPLTRSP 0x01 87297883Sgibbs} 87397883Sgibbs 87497883Sgibbs/* 87597883Sgibbs * Overlay Split Status 0 87697883Sgibbs */ 87797883Sgibbsregister OVLYSPLTSTAT0 { 87897883Sgibbs address 0x096 87997883Sgibbs access_mode RW 88097883Sgibbs modes M_SCSI 881102681Sgibbs field STAETERM 0x80 882102681Sgibbs field SCBCERR 0x40 883102681Sgibbs field SCADERR 0x20 884102681Sgibbs field SCDATBUCKET 0x10 885102681Sgibbs field CNTNOTCMPLT 0x08 886102681Sgibbs field RXOVRUN 0x04 887102681Sgibbs field RXSCEMSG 0x02 888102681Sgibbs field RXSPLTRSP 0x01 88997883Sgibbs} 89097883Sgibbs 89197883Sgibbs/* 89297883Sgibbs * Data Channel Split Status 1 89397883Sgibbs */ 89497883Sgibbsregister DCHSPLTSTAT1 { 89597883Sgibbs address 0x097 89697883Sgibbs access_mode RW 89797883Sgibbs modes M_DFF0, M_DFF1 898102681Sgibbs field RXDATABUCKET 0x01 89997883Sgibbs} 90097883Sgibbs 90197883Sgibbs/* 90297883Sgibbs * CMC Split Status 1 90397883Sgibbs */ 90497883Sgibbsregister CMCSPLTSTAT1 { 90597883Sgibbs address 0x097 90697883Sgibbs access_mode RW 90797883Sgibbs modes M_CCHAN 908102681Sgibbs field RXDATABUCKET 0x01 90997883Sgibbs} 91097883Sgibbs 91197883Sgibbs/* 91297883Sgibbs * Overlay Split Status 1 91397883Sgibbs */ 91497883Sgibbsregister OVLYSPLTSTAT1 { 91597883Sgibbs address 0x097 91697883Sgibbs access_mode RW 91797883Sgibbs modes M_SCSI 918102681Sgibbs field RXDATABUCKET 0x01 91997883Sgibbs} 92097883Sgibbs 92197883Sgibbs/* 92297883Sgibbs * S/G Receive Message 0 92397883Sgibbs */ 92497883Sgibbsregister SGRXMSG0 { 92597883Sgibbs address 0x098 92697883Sgibbs access_mode RO 92797883Sgibbs modes M_DFF0, M_DFF1 928102681Sgibbs field CDNUM 0xF8 929102681Sgibbs field CFNUM 0x07 93097883Sgibbs} 93197883Sgibbs 93297883Sgibbs/* 93397883Sgibbs * S/G Receive Message 1 93497883Sgibbs */ 93597883Sgibbsregister SGRXMSG1 { 93697883Sgibbs address 0x099 93797883Sgibbs access_mode RO 93897883Sgibbs modes M_DFF0, M_DFF1 939102681Sgibbs field CBNUM 0xFF 94097883Sgibbs} 94197883Sgibbs 94297883Sgibbs/* 94397883Sgibbs * S/G Receive Message 2 94497883Sgibbs */ 94597883Sgibbsregister SGRXMSG2 { 94697883Sgibbs address 0x09A 94797883Sgibbs access_mode RO 94897883Sgibbs modes M_DFF0, M_DFF1 949102681Sgibbs field MINDEX 0xFF 95097883Sgibbs} 95197883Sgibbs 95297883Sgibbs/* 95397883Sgibbs * S/G Receive Message 3 95497883Sgibbs */ 95597883Sgibbsregister SGRXMSG3 { 95697883Sgibbs address 0x09B 95797883Sgibbs access_mode RO 95897883Sgibbs modes M_DFF0, M_DFF1 959102681Sgibbs field MCLASS 0x0F 96097883Sgibbs} 96197883Sgibbs 96297883Sgibbs/* 96397883Sgibbs * Slave Split Out Address 0 96497883Sgibbs */ 96597883Sgibbsregister SLVSPLTOUTADR0 { 96697883Sgibbs address 0x098 96797883Sgibbs access_mode RO 96897883Sgibbs modes M_SCSI 969102681Sgibbs field LOWER_ADDR 0x7F 97097883Sgibbs} 97197883Sgibbs 97297883Sgibbs/* 97397883Sgibbs * Slave Split Out Address 1 97497883Sgibbs */ 97597883Sgibbsregister SLVSPLTOUTADR1 { 97697883Sgibbs address 0x099 97797883Sgibbs access_mode RO 97897883Sgibbs modes M_SCSI 979102681Sgibbs field REQ_DNUM 0xF8 980102681Sgibbs field REQ_FNUM 0x07 98197883Sgibbs} 98297883Sgibbs 98397883Sgibbs/* 98497883Sgibbs * Slave Split Out Address 2 98597883Sgibbs */ 98697883Sgibbsregister SLVSPLTOUTADR2 { 98797883Sgibbs address 0x09A 98897883Sgibbs access_mode RO 98997883Sgibbs modes M_SCSI 990102681Sgibbs field REQ_BNUM 0xFF 99197883Sgibbs} 99297883Sgibbs 99397883Sgibbs/* 99497883Sgibbs * Slave Split Out Address 3 99597883Sgibbs */ 99697883Sgibbsregister SLVSPLTOUTADR3 { 99797883Sgibbs address 0x09B 99897883Sgibbs access_mode RO 99997883Sgibbs modes M_SCSI 1000102681Sgibbs field RLXORD 020 1001102681Sgibbs field TAG_NUM 0x1F 100297883Sgibbs} 100397883Sgibbs 100497883Sgibbs/* 100597883Sgibbs * SG Sequencer Byte Count 100697883Sgibbs */ 100797883Sgibbsregister SGSEQBCNT { 100897883Sgibbs address 0x09C 100997883Sgibbs access_mode RO 101097883Sgibbs modes M_DFF0, M_DFF1 101197883Sgibbs} 101297883Sgibbs 101397883Sgibbs/* 101497883Sgibbs * Slave Split Out Attribute 0 101597883Sgibbs */ 101697883Sgibbsregister SLVSPLTOUTATTR0 { 101797883Sgibbs address 0x09C 101897883Sgibbs access_mode RO 101997883Sgibbs modes M_SCSI 1020102681Sgibbs field LOWER_BCNT 0xFF 102197883Sgibbs} 102297883Sgibbs 102397883Sgibbs/* 102497883Sgibbs * Slave Split Out Attribute 1 102597883Sgibbs */ 102697883Sgibbsregister SLVSPLTOUTATTR1 { 102797883Sgibbs address 0x09D 102897883Sgibbs access_mode RO 102997883Sgibbs modes M_SCSI 1030102681Sgibbs field CMPLT_DNUM 0xF8 1031102681Sgibbs field CMPLT_FNUM 0x07 103297883Sgibbs} 103397883Sgibbs 103497883Sgibbs/* 103597883Sgibbs * Slave Split Out Attribute 2 103697883Sgibbs */ 103797883Sgibbsregister SLVSPLTOUTATTR2 { 103897883Sgibbs address 0x09E 103997883Sgibbs access_mode RO 104097883Sgibbs size 2 104197883Sgibbs modes M_SCSI 1042102681Sgibbs field CMPLT_BNUM 0xFF 104397883Sgibbs} 104497883Sgibbs/* 104597883Sgibbs * S/G Split Status 0 104697883Sgibbs */ 104797883Sgibbsregister SGSPLTSTAT0 { 104897883Sgibbs address 0x09E 104997883Sgibbs access_mode RW 105097883Sgibbs modes M_DFF0, M_DFF1 1051102681Sgibbs field STAETERM 0x80 1052102681Sgibbs field SCBCERR 0x40 1053102681Sgibbs field SCADERR 0x20 1054102681Sgibbs field SCDATBUCKET 0x10 1055102681Sgibbs field CNTNOTCMPLT 0x08 1056102681Sgibbs field RXOVRUN 0x04 1057102681Sgibbs field RXSCEMSG 0x02 1058102681Sgibbs field RXSPLTRSP 0x01 105997883Sgibbs} 106097883Sgibbs 106197883Sgibbs/* 106297883Sgibbs * S/G Split Status 1 106397883Sgibbs */ 106497883Sgibbsregister SGSPLTSTAT1 { 106597883Sgibbs address 0x09F 106697883Sgibbs access_mode RW 106797883Sgibbs modes M_DFF0, M_DFF1 1068102681Sgibbs field RXDATABUCKET 0x01 106997883Sgibbs} 107097883Sgibbs 107197883Sgibbs/* 107297883Sgibbs * Special Function 107397883Sgibbs */ 107497883Sgibbsregister SFUNCT { 107597883Sgibbs address 0x09f 107697883Sgibbs access_mode RW 107797883Sgibbs modes M_CFG 1078102681Sgibbs field TEST_GROUP 0xF0 1079102681Sgibbs field TEST_NUM 0x0F 108097883Sgibbs} 108197883Sgibbs 108297883Sgibbs/* 108397883Sgibbs * Data FIFO 0 PCI Status 108497883Sgibbs */ 108597883Sgibbsregister DF0PCISTAT { 108697883Sgibbs address 0x0A0 108797883Sgibbs access_mode RW 108897883Sgibbs modes M_CFG 1089102681Sgibbs field DPE 0x80 1090102681Sgibbs field SSE 0x40 1091102681Sgibbs field RMA 0x20 1092102681Sgibbs field RTA 0x10 1093102681Sgibbs field SCAAPERR 0x08 1094102681Sgibbs field RDPERR 0x04 1095102681Sgibbs field TWATERR 0x02 1096102681Sgibbs field DPR 0x01 109797883Sgibbs} 109897883Sgibbs 109997883Sgibbs/* 110097883Sgibbs * Data FIFO 1 PCI Status 110197883Sgibbs */ 110297883Sgibbsregister DF1PCISTAT { 110397883Sgibbs address 0x0A1 110497883Sgibbs access_mode RW 110597883Sgibbs modes M_CFG 1106102681Sgibbs field DPE 0x80 1107102681Sgibbs field SSE 0x40 1108102681Sgibbs field RMA 0x20 1109102681Sgibbs field RTA 0x10 1110102681Sgibbs field SCAAPERR 0x08 1111102681Sgibbs field RDPERR 0x04 1112102681Sgibbs field TWATERR 0x02 1113102681Sgibbs field DPR 0x01 111497883Sgibbs} 111597883Sgibbs 111697883Sgibbs/* 111797883Sgibbs * S/G PCI Status 111897883Sgibbs */ 111997883Sgibbsregister SGPCISTAT { 112097883Sgibbs address 0x0A2 112197883Sgibbs access_mode RW 112297883Sgibbs modes M_CFG 1123102681Sgibbs field DPE 0x80 1124102681Sgibbs field SSE 0x40 1125102681Sgibbs field RMA 0x20 1126102681Sgibbs field RTA 0x10 1127102681Sgibbs field SCAAPERR 0x08 1128102681Sgibbs field RDPERR 0x04 1129102681Sgibbs field DPR 0x01 113097883Sgibbs} 113197883Sgibbs 113297883Sgibbs/* 113397883Sgibbs * CMC PCI Status 113497883Sgibbs */ 113597883Sgibbsregister CMCPCISTAT { 113697883Sgibbs address 0x0A3 113797883Sgibbs access_mode RW 113897883Sgibbs modes M_CFG 1139102681Sgibbs field DPE 0x80 1140102681Sgibbs field SSE 0x40 1141102681Sgibbs field RMA 0x20 1142102681Sgibbs field RTA 0x10 1143102681Sgibbs field SCAAPERR 0x08 1144102681Sgibbs field RDPERR 0x04 1145102681Sgibbs field TWATERR 0x02 1146102681Sgibbs field DPR 0x01 114797883Sgibbs} 114897883Sgibbs 114997883Sgibbs/* 115097883Sgibbs * Overlay PCI Status 115197883Sgibbs */ 115297883Sgibbsregister OVLYPCISTAT { 115397883Sgibbs address 0x0A4 115497883Sgibbs access_mode RW 115597883Sgibbs modes M_CFG 1156102681Sgibbs field DPE 0x80 1157102681Sgibbs field SSE 0x40 1158102681Sgibbs field RMA 0x20 1159102681Sgibbs field RTA 0x10 1160102681Sgibbs field SCAAPERR 0x08 1161102681Sgibbs field RDPERR 0x04 1162102681Sgibbs field DPR 0x01 116397883Sgibbs} 116497883Sgibbs 116597883Sgibbs/* 116697883Sgibbs * PCI Status for MSI Master DMA Transfer 116797883Sgibbs */ 116897883Sgibbsregister MSIPCISTAT { 116997883Sgibbs address 0x0A6 117097883Sgibbs access_mode RW 117197883Sgibbs modes M_CFG 1172102681Sgibbs field SSE 0x40 1173102681Sgibbs field RMA 0x20 1174102681Sgibbs field RTA 0x10 1175102681Sgibbs field CLRPENDMSI 0x08 1176102681Sgibbs field TWATERR 0x02 1177102681Sgibbs field DPR 0x01 117897883Sgibbs} 117997883Sgibbs 118097883Sgibbs/* 118197883Sgibbs * PCI Status for Target 118297883Sgibbs */ 118397883Sgibbsregister TARGPCISTAT { 1184107623Sscottl address 0x0A7 118597883Sgibbs access_mode RW 118697883Sgibbs modes M_CFG 1187102681Sgibbs field DPE 0x80 1188102681Sgibbs field SSE 0x40 1189102681Sgibbs field STA 0x08 1190102681Sgibbs field TWATERR 0x02 119197883Sgibbs} 119297883Sgibbs 119397883Sgibbs/* 119497883Sgibbs * LQ Packet In 1195299375Spfg * The last LQ Packet received 119697883Sgibbs */ 119797883Sgibbsregister LQIN { 119897883Sgibbs address 0x020 119997883Sgibbs access_mode RW 120097883Sgibbs size 20 120197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 120297883Sgibbs} 120397883Sgibbs 120497883Sgibbs/* 120597883Sgibbs * SCB Type Pointer 120697883Sgibbs * SCB offset for Target Mode SCB type information 120797883Sgibbs */ 120897883Sgibbsregister TYPEPTR { 120997883Sgibbs address 0x020 121097883Sgibbs access_mode RW 121197883Sgibbs modes M_CFG 121297883Sgibbs} 121397883Sgibbs 121497883Sgibbs/* 121597883Sgibbs * Queue Tag Pointer 121697883Sgibbs * SCB offset to the Two Byte tag identifier used for target mode. 121797883Sgibbs */ 121897883Sgibbsregister TAGPTR { 121997883Sgibbs address 0x021 122097883Sgibbs access_mode RW 122197883Sgibbs modes M_CFG 122297883Sgibbs} 122397883Sgibbs 122497883Sgibbs/* 122597883Sgibbs * Logical Unit Number Pointer 122697883Sgibbs * SCB offset to the LSB (little endian) of the lun field. 122797883Sgibbs */ 122897883Sgibbsregister LUNPTR { 122997883Sgibbs address 0x022 123097883Sgibbs access_mode RW 123197883Sgibbs modes M_CFG 123297883Sgibbs} 123397883Sgibbs 123497883Sgibbs/* 123597883Sgibbs * Data Length Pointer 123697883Sgibbs * SCB offset for the 4 byte data length field in target mode. 123797883Sgibbs */ 123897883Sgibbsregister DATALENPTR { 123997883Sgibbs address 0x023 124097883Sgibbs access_mode RW 124197883Sgibbs modes M_CFG 124297883Sgibbs} 124397883Sgibbs 124497883Sgibbs/* 124597883Sgibbs * Status Length Pointer 124697883Sgibbs * SCB offset to the two byte status field in target SCBs. 124797883Sgibbs */ 124897883Sgibbsregister STATLENPTR { 124997883Sgibbs address 0x024 125097883Sgibbs access_mode RW 125197883Sgibbs modes M_CFG 125297883Sgibbs} 125397883Sgibbs 125497883Sgibbs/* 125597883Sgibbs * Command Length Pointer 125697883Sgibbs * Scb offset for the CDB length field in initiator SCBs. 125797883Sgibbs */ 125897883Sgibbsregister CMDLENPTR { 125997883Sgibbs address 0x025 126097883Sgibbs access_mode RW 126197883Sgibbs modes M_CFG 126297883Sgibbs} 126397883Sgibbs 126497883Sgibbs/* 126597883Sgibbs * Task Attribute Pointer 126697883Sgibbs * Scb offset for the byte field specifying the attribute byte 126797883Sgibbs * to be used in command packets. 126897883Sgibbs */ 126997883Sgibbsregister ATTRPTR { 127097883Sgibbs address 0x026 127197883Sgibbs access_mode RW 127297883Sgibbs modes M_CFG 127397883Sgibbs} 127497883Sgibbs 127597883Sgibbs/* 127697883Sgibbs * Task Management Flags Pointer 127797883Sgibbs * Scb offset for the byte field specifying the attribute flags 127897883Sgibbs * byte to be used in command packets. 127997883Sgibbs */ 128097883Sgibbsregister FLAGPTR { 128197883Sgibbs address 0x027 128297883Sgibbs access_mode RW 128397883Sgibbs modes M_CFG 128497883Sgibbs} 128597883Sgibbs 128697883Sgibbs/* 128797883Sgibbs * Command Pointer 128897883Sgibbs * Scb offset for the first byte in the CDB for initiator SCBs. 128997883Sgibbs */ 129097883Sgibbsregister CMDPTR { 129197883Sgibbs address 0x028 129297883Sgibbs access_mode RW 129397883Sgibbs modes M_CFG 129497883Sgibbs} 129597883Sgibbs 129697883Sgibbs/* 129797883Sgibbs * Queue Next Pointer 129897883Sgibbs * Scb offset for the 2 byte "next scb link". 129997883Sgibbs */ 130097883Sgibbsregister QNEXTPTR { 130197883Sgibbs address 0x029 130297883Sgibbs access_mode RW 130397883Sgibbs modes M_CFG 130497883Sgibbs} 130597883Sgibbs 130697883Sgibbs/* 130797883Sgibbs * SCSI ID Pointer 130897883Sgibbs * Scb offset to the value to place in the SCSIID register 130997883Sgibbs * during target mode connections. 131097883Sgibbs */ 131197883Sgibbsregister IDPTR { 131297883Sgibbs address 0x02A 131397883Sgibbs access_mode RW 131497883Sgibbs modes M_CFG 131597883Sgibbs} 131697883Sgibbs 131797883Sgibbs/* 131897883Sgibbs * Command Aborted Byte Pointer 131997883Sgibbs * Offset to the SCB flags field that includes the 132097883Sgibbs * "SCB aborted" status bit. 132197883Sgibbs */ 132297883Sgibbsregister ABRTBYTEPTR { 132397883Sgibbs address 0x02B 132497883Sgibbs access_mode RW 132597883Sgibbs modes M_CFG 132697883Sgibbs} 132797883Sgibbs 132897883Sgibbs/* 132997883Sgibbs * Command Aborted Bit Pointer 133097883Sgibbs * Bit offset in the SCB flags field for "SCB aborted" status. 133197883Sgibbs */ 133297883Sgibbsregister ABRTBITPTR { 133397883Sgibbs address 0x02C 133497883Sgibbs access_mode RW 133597883Sgibbs modes M_CFG 133697883Sgibbs} 133797883Sgibbs 133897883Sgibbs/* 1339102681Sgibbs * Rev B or greater. 1340102681Sgibbs */ 1341102681Sgibbsregister MAXCMDBYTES { 1342102681Sgibbs address 0x02D 1343102681Sgibbs access_mode RW 1344102681Sgibbs modes M_CFG 1345102681Sgibbs} 1346102681Sgibbs 1347102681Sgibbs/* 1348102681Sgibbs * Rev B or greater. 1349102681Sgibbs */ 1350102681Sgibbsregister MAXCMD2RCV { 1351102681Sgibbs address 0x02E 1352102681Sgibbs access_mode RW 1353102681Sgibbs modes M_CFG 1354102681Sgibbs} 1355102681Sgibbs 1356102681Sgibbs/* 1357102681Sgibbs * Rev B or greater. 1358102681Sgibbs */ 1359102681Sgibbsregister SHORTTHRESH { 1360102681Sgibbs address 0x02F 1361102681Sgibbs access_mode RW 1362102681Sgibbs modes M_CFG 1363102681Sgibbs} 1364102681Sgibbs 1365102681Sgibbs/* 136697883Sgibbs * Logical Unit Number Length 136797883Sgibbs * The length, in bytes, of the SCB lun field. 136897883Sgibbs */ 136997883Sgibbsregister LUNLEN { 137097883Sgibbs address 0x030 137197883Sgibbs access_mode RW 137297883Sgibbs modes M_CFG 1373115407Sscottl mask ILUNLEN 0x0F 1374115407Sscottl mask TLUNLEN 0xF0 137597883Sgibbs} 1376115407Sscottlconst LUNLEN_SINGLE_LEVEL_LUN 0xF 137797883Sgibbs 137897883Sgibbs/* 137997883Sgibbs * CDB Limit 138097883Sgibbs * The size, in bytes, of the embedded CDB field in initator SCBs. 138197883Sgibbs */ 138297883Sgibbsregister CDBLIMIT { 138397883Sgibbs address 0x031 138497883Sgibbs access_mode RW 138597883Sgibbs modes M_CFG 138697883Sgibbs} 138797883Sgibbs 138897883Sgibbs/* 138997883Sgibbs * Maximum Commands 139097883Sgibbs * The maximum number of commands to issue during a 139197883Sgibbs * single packetized connection. 139297883Sgibbs */ 139397883Sgibbsregister MAXCMD { 139497883Sgibbs address 0x032 139597883Sgibbs access_mode RW 139697883Sgibbs modes M_CFG 139797883Sgibbs} 139897883Sgibbs 139997883Sgibbs/* 140097883Sgibbs * Maximum Command Counter 140197883Sgibbs * The number of commands already sent during this connection 140297883Sgibbs */ 140397883Sgibbsregister MAXCMDCNT { 140497883Sgibbs address 0x033 140597883Sgibbs access_mode RW 140697883Sgibbs modes M_CFG 140797883Sgibbs} 140897883Sgibbs 140997883Sgibbs/* 141097883Sgibbs * LQ Packet Reserved Bytes 141197883Sgibbs * The bytes to be sent in the currently reserved fileds 141297883Sgibbs * of all LQ packets. 141397883Sgibbs */ 141497883Sgibbsregister LQRSVD01 { 141597883Sgibbs address 0x034 141697883Sgibbs access_mode RW 141797883Sgibbs modes M_SCSI 141897883Sgibbs} 141997883Sgibbsregister LQRSVD16 { 142097883Sgibbs address 0x035 142197883Sgibbs access_mode RW 142297883Sgibbs modes M_SCSI 142397883Sgibbs} 142497883Sgibbsregister LQRSVD17 { 142597883Sgibbs address 0x036 142697883Sgibbs access_mode RW 142797883Sgibbs modes M_SCSI 142897883Sgibbs} 142997883Sgibbs 143097883Sgibbs/* 143197883Sgibbs * Command Reserved 0 143297883Sgibbs * The byte to be sent for the reserved byte 0 of 143397883Sgibbs * outgoing command packets. 143497883Sgibbs */ 143597883Sgibbsregister CMDRSVD0 { 143697883Sgibbs address 0x037 143797883Sgibbs access_mode RW 143897883Sgibbs modes M_CFG 143997883Sgibbs} 144097883Sgibbs 144197883Sgibbs/* 144297883Sgibbs * LQ Manager Control 0 144397883Sgibbs */ 144497883Sgibbsregister LQCTL0 { 144597883Sgibbs address 0x038 144697883Sgibbs access_mode RW 144797883Sgibbs modes M_CFG 1448102681Sgibbs field LQITARGCLT 0xC0 1449102681Sgibbs field LQIINITGCLT 0x30 1450102681Sgibbs field LQ0TARGCLT 0x0C 1451102681Sgibbs field LQ0INITGCLT 0x03 145297883Sgibbs} 145397883Sgibbs 145497883Sgibbs/* 145597883Sgibbs * LQ Manager Control 1 145697883Sgibbs */ 145797883Sgibbsregister LQCTL1 { 145897883Sgibbs address 0x038 145997883Sgibbs access_mode RW 146097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1461102681Sgibbs field PCI2PCI 0x04 1462102681Sgibbs field SINGLECMD 0x02 1463102681Sgibbs field ABORTPENDING 0x01 146497883Sgibbs} 146597883Sgibbs 146697883Sgibbs/* 146797883Sgibbs * LQ Manager Control 2 146897883Sgibbs */ 146997883Sgibbsregister LQCTL2 { 147097883Sgibbs address 0x039 147197883Sgibbs access_mode RW 147297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1473102681Sgibbs field LQIRETRY 0x80 1474102681Sgibbs field LQICONTINUE 0x40 1475102681Sgibbs field LQITOIDLE 0x20 1476102681Sgibbs field LQIPAUSE 0x10 1477102681Sgibbs field LQORETRY 0x08 1478102681Sgibbs field LQOCONTINUE 0x04 1479102681Sgibbs field LQOTOIDLE 0x02 1480102681Sgibbs field LQOPAUSE 0x01 148197883Sgibbs} 148297883Sgibbs 148397883Sgibbs/* 148497883Sgibbs * SCSI RAM BIST0 148597883Sgibbs */ 148697883Sgibbsregister SCSBIST0 { 148797883Sgibbs address 0x039 148897883Sgibbs access_mode RW 148997883Sgibbs modes M_CFG 1490102681Sgibbs field GSBISTERR 0x40 1491102681Sgibbs field GSBISTDONE 0x20 1492102681Sgibbs field GSBISTRUN 0x10 1493102681Sgibbs field OSBISTERR 0x04 1494102681Sgibbs field OSBISTDONE 0x02 1495102681Sgibbs field OSBISTRUN 0x01 149697883Sgibbs} 149797883Sgibbs 149897883Sgibbs/* 149997883Sgibbs * SCSI Sequence Control0 150097883Sgibbs */ 150197883Sgibbsregister SCSISEQ0 { 150297883Sgibbs address 0x03A 150397883Sgibbs access_mode RW 150497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1505102681Sgibbs field TEMODEO 0x80 1506102681Sgibbs field ENSELO 0x40 1507102681Sgibbs field ENARBO 0x20 1508102681Sgibbs field FORCEBUSFREE 0x10 1509102681Sgibbs field SCSIRSTO 0x01 151097883Sgibbs} 151197883Sgibbs 151297883Sgibbs/* 151397883Sgibbs * SCSI RAM BIST 1 151497883Sgibbs */ 151597883Sgibbsregister SCSBIST1 { 151697883Sgibbs address 0x03A 151797883Sgibbs access_mode RW 151897883Sgibbs modes M_CFG 1519102681Sgibbs field NTBISTERR 0x04 1520102681Sgibbs field NTBISTDONE 0x02 1521102681Sgibbs field NTBISTRUN 0x01 152297883Sgibbs} 152397883Sgibbs 152497883Sgibbs/* 152597883Sgibbs * SCSI Sequence Control 1 152697883Sgibbs */ 152797883Sgibbsregister SCSISEQ1 { 152897883Sgibbs address 0x03B 152997883Sgibbs access_mode RW 153097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1531102681Sgibbs field MANUALCTL 0x40 1532102681Sgibbs field ENSELI 0x20 1533102681Sgibbs field ENRSELI 0x10 1534102681Sgibbs field MANUALP 0x0C 1535102681Sgibbs field ENAUTOATNP 0x02 1536102681Sgibbs field ALTSTIM 0x01 153797883Sgibbs} 153897883Sgibbs 153997883Sgibbs/* 154097883Sgibbs * SCSI Transfer Control 0 154197883Sgibbs */ 154297883Sgibbsregister SXFRCTL0 { 154397883Sgibbs address 0x03C 154497883Sgibbs access_mode RW 154597883Sgibbs modes M_SCSI 1546102681Sgibbs field DFON 0x80 1547102681Sgibbs field DFPEXP 0x40 1548102681Sgibbs field BIOSCANCELEN 0x10 1549102681Sgibbs field SPIOEN 0x08 155097883Sgibbs} 155197883Sgibbs 155297883Sgibbs/* 155397883Sgibbs * SCSI Transfer Control 1 155497883Sgibbs */ 155597883Sgibbsregister SXFRCTL1 { 155697883Sgibbs address 0x03D 155797883Sgibbs access_mode RW 155897883Sgibbs modes M_SCSI 1559102681Sgibbs field BITBUCKET 0x80 1560102681Sgibbs field ENSACHK 0x40 1561102681Sgibbs field ENSPCHK 0x20 1562102681Sgibbs field STIMESEL 0x18 1563102681Sgibbs field ENSTIMER 0x04 1564102681Sgibbs field ACTNEGEN 0x02 1565102681Sgibbs field STPWEN 0x01 156697883Sgibbs} 156797883Sgibbs 156897883Sgibbs/* 156997883Sgibbs * SCSI Transfer Control 2 157097883Sgibbs */ 157197883Sgibbsregister SXFRCTL2 { 157297883Sgibbs address 0x03E 157397883Sgibbs access_mode RW 157497883Sgibbs modes M_SCSI 1575102681Sgibbs field AUTORSTDIS 0x10 1576102681Sgibbs field CMDDMAEN 0x08 1577102681Sgibbs field ASU 0x07 157897883Sgibbs} 157997883Sgibbs 158097883Sgibbs/* 158197883Sgibbs * SCSI Bus Initiator IDs 158297883Sgibbs * Bitmask of observed initiators on the bus. 158397883Sgibbs */ 158497883Sgibbsregister BUSINITID { 158597883Sgibbs address 0x03C 158697883Sgibbs access_mode RW 158797883Sgibbs modes M_CFG 158897883Sgibbs size 2 158997883Sgibbs} 159097883Sgibbs 159197883Sgibbs/* 159297883Sgibbs * Data Length Counters 159397883Sgibbs * Packet byte counter. 159497883Sgibbs */ 159597883Sgibbsregister DLCOUNT { 159697883Sgibbs address 0x03C 159797883Sgibbs access_mode RW 159897883Sgibbs modes M_DFF0, M_DFF1 159997883Sgibbs size 3 160097883Sgibbs} 160197883Sgibbs 160297883Sgibbs/* 160397883Sgibbs * Data FIFO Status 160497883Sgibbs */ 160597883Sgibbsregister DFFSTAT { 160697883Sgibbs address 0x03F 160797883Sgibbs access_mode RW 160897883Sgibbs modes M_SCSI 1609102681Sgibbs field FIFO1FREE 0x20 1610102681Sgibbs field FIFO0FREE 0x10 1611107441Sscottl /* 1612107441Sscottl * On the B, this enum only works 1613107441Sscottl * in the read direction. For writes, 1614107441Sscottl * you must use the B version of the 1615107441Sscottl * CURRFIFO_0 definition which is defined 1616107441Sscottl * as a constant outside of this register 1617107441Sscottl * definition to avoid confusing the 1618107441Sscottl * register pretty printing code. 1619107441Sscottl */ 1620107441Sscottl enum CURRFIFO 0x03 { 1621107441Sscottl CURRFIFO_0, 1622107441Sscottl CURRFIFO_1, 1623107441Sscottl CURRFIFO_NONE 0x3 1624107441Sscottl } 162597883Sgibbs} 162697883Sgibbs 1627107441Sscottlconst B_CURRFIFO_0 0x2 1628107441Sscottl 162997883Sgibbs/* 163097883Sgibbs * SCSI Bus Target IDs 163197883Sgibbs * Bitmask of observed targets on the bus. 163297883Sgibbs */ 163397883Sgibbsregister BUSTARGID { 163497883Sgibbs address 0x03E 163597883Sgibbs access_mode RW 163697883Sgibbs modes M_CFG 163797883Sgibbs size 2 163897883Sgibbs} 163997883Sgibbs 164097883Sgibbs/* 164197883Sgibbs * SCSI Control Signal Out 164297883Sgibbs */ 164397883Sgibbsregister SCSISIGO { 164497883Sgibbs address 0x040 164597883Sgibbs access_mode RW 164697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1647102681Sgibbs field CDO 0x80 1648102681Sgibbs field IOO 0x40 1649102681Sgibbs field MSGO 0x20 1650102681Sgibbs field ATNO 0x10 1651102681Sgibbs field SELO 0x08 1652102681Sgibbs field BSYO 0x04 1653102681Sgibbs field REQO 0x02 1654102681Sgibbs field ACKO 0x01 165597883Sgibbs/* 165697883Sgibbs * Possible phases to write into SCSISIG0 165797883Sgibbs */ 1658102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1659102681Sgibbs P_DATAOUT 0x0, 1660102681Sgibbs P_DATAIN IOO, 1661102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1662102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1663102681Sgibbs P_COMMAND CDO, 1664102681Sgibbs P_MESGOUT CDO|MSGO, 1665102681Sgibbs P_STATUS CDO|IOO, 1666102681Sgibbs P_MESGIN CDO|IOO|MSGO 1667102681Sgibbs } 166897883Sgibbs} 166997883Sgibbs 167097883Sgibbsregister SCSISIGI { 167197883Sgibbs address 0x041 167297883Sgibbs access_mode RO 167397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1674102681Sgibbs field CDI 0x80 1675102681Sgibbs field IOI 0x40 1676102681Sgibbs field MSGI 0x20 1677102681Sgibbs field ATNI 0x10 1678102681Sgibbs field SELI 0x08 1679102681Sgibbs field BSYI 0x04 1680102681Sgibbs field REQI 0x02 1681102681Sgibbs field ACKI 0x01 168297883Sgibbs/* 168397883Sgibbs * Possible phases in SCSISIGI 168497883Sgibbs */ 1685102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 1686102681Sgibbs P_DATAOUT 0x0, 1687102681Sgibbs P_DATAIN IOO, 1688102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 1689102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 1690102681Sgibbs P_COMMAND CDO, 1691102681Sgibbs P_MESGOUT CDO|MSGO, 1692102681Sgibbs P_STATUS CDO|IOO, 1693102681Sgibbs P_MESGIN CDO|IOO|MSGO 1694102681Sgibbs } 169597883Sgibbs} 169697883Sgibbs 169797883Sgibbs/* 169897883Sgibbs * Multiple Target IDs 169997883Sgibbs * Bitmask of ids to respond as a target. 170097883Sgibbs */ 170197883Sgibbsregister MULTARGID { 170297883Sgibbs address 0x040 170397883Sgibbs access_mode RW 170497883Sgibbs modes M_CFG 170597883Sgibbs size 2 170697883Sgibbs} 170797883Sgibbs 170897883Sgibbs/* 170997883Sgibbs * SCSI Phase 171097883Sgibbs */ 171197883Sgibbsregister SCSIPHASE { 171297883Sgibbs address 0x042 171397883Sgibbs access_mode RO 171497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1715102681Sgibbs field STATUS_PHASE 0x20 1716102681Sgibbs field COMMAND_PHASE 0x10 1717102681Sgibbs field MSG_IN_PHASE 0x08 1718102681Sgibbs field MSG_OUT_PHASE 0x04 1719102681Sgibbs field DATA_PHASE_MASK 0x03 { 1720102681Sgibbs DATA_OUT_PHASE 0x01, 1721102681Sgibbs DATA_IN_PHASE 0x02 1722102681Sgibbs } 172397883Sgibbs} 172497883Sgibbs 172597883Sgibbs/* 172697883Sgibbs * SCSI Data 0 Image 172797883Sgibbs */ 172897883Sgibbsregister SCSIDAT0_IMG { 172997883Sgibbs address 0x043 173097883Sgibbs access_mode RW 173197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 173297883Sgibbs} 173397883Sgibbs 173497883Sgibbs/* 173597883Sgibbs * SCSI Latched Data 173697883Sgibbs */ 173797883Sgibbsregister SCSIDAT { 173897883Sgibbs address 0x044 173997883Sgibbs access_mode RW 174097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 174197883Sgibbs size 2 174297883Sgibbs} 174397883Sgibbs 174497883Sgibbs/* 174597883Sgibbs * SCSI Data Bus 174697883Sgibbs */ 174797883Sgibbsregister SCSIBUS { 174897883Sgibbs address 0x046 174997883Sgibbs access_mode RW 175097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 175197883Sgibbs size 2 175297883Sgibbs} 175397883Sgibbs 175497883Sgibbs/* 175597883Sgibbs * Target ID In 175697883Sgibbs */ 175797883Sgibbsregister TARGIDIN { 175897883Sgibbs address 0x048 175997883Sgibbs access_mode RO 176097883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1761102681Sgibbs field CLKOUT 0x80 1762102681Sgibbs field TARGID 0x0F 176397883Sgibbs} 176497883Sgibbs 176597883Sgibbs/* 176697883Sgibbs * Selection/Reselection ID 176797883Sgibbs * Upper four bits are the device id. The ONEBIT is set when the re/selecting 176897883Sgibbs * device did not set its own ID. 176997883Sgibbs */ 177097883Sgibbsregister SELID { 177197883Sgibbs address 0x049 177297883Sgibbs access_mode RW 177397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1774102681Sgibbs field SELID_MASK 0xf0 1775102681Sgibbs field ONEBIT 0x08 177697883Sgibbs} 177797883Sgibbs 177897883Sgibbs/* 177997883Sgibbs * SCSI Block Control 178097883Sgibbs * Controls Bus type and channel selection. SELWIDE allows for the 178197883Sgibbs * coexistence of 8bit and 16bit devices on a wide bus. 178297883Sgibbs */ 178397883Sgibbsregister SBLKCTL { 178497883Sgibbs address 0x04A 178597883Sgibbs access_mode RW 178697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1787102681Sgibbs field DIAGLEDEN 0x80 1788102681Sgibbs field DIAGLEDON 0x40 1789102681Sgibbs field ENAB40 0x08 /* LVD transceiver active */ 1790102681Sgibbs field ENAB20 0x04 /* SE/HVD transceiver active */ 1791102681Sgibbs field SELWIDE 0x02 179297883Sgibbs} 179397883Sgibbs 179497883Sgibbs/* 179597883Sgibbs * Option Mode 179697883Sgibbs */ 179797883Sgibbsregister OPTIONMODE { 179897883Sgibbs address 0x04A 179997883Sgibbs access_mode RW 180097883Sgibbs modes M_CFG 1801102681Sgibbs field BIOSCANCTL 0x80 1802102681Sgibbs field AUTOACKEN 0x40 1803102681Sgibbs field BIASCANCTL 0x20 1804102681Sgibbs field BUSFREEREV 0x10 1805102681Sgibbs field ENDGFORMCHK 0x04 1806102681Sgibbs field AUTO_MSGOUT_DE 0x02 180797883Sgibbs mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 180897883Sgibbs} 180997883Sgibbs 181097883Sgibbs/* 181197883Sgibbs * SCSI Status 0 181297883Sgibbs */ 181397883Sgibbsregister SSTAT0 { 181497883Sgibbs address 0x04B 181597883Sgibbs access_mode RO 181697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1817102681Sgibbs field TARGET 0x80 /* Board acting as target */ 1818102681Sgibbs field SELDO 0x40 /* Selection Done */ 1819102681Sgibbs field SELDI 0x20 /* Board has been selected */ 1820102681Sgibbs field SELINGO 0x10 /* Selection In Progress */ 1821102681Sgibbs field IOERR 0x08 /* LVD Tranceiver mode changed */ 1822102681Sgibbs field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1823102681Sgibbs field SPIORDY 0x02 /* SCSI PIO Ready */ 1824102681Sgibbs field ARBDO 0x01 /* Arbitration Done Out */ 182597883Sgibbs} 182697883Sgibbs 182797883Sgibbs/* 182897883Sgibbs * Clear SCSI Interrupt 0 182997883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 183097883Sgibbs */ 183197883Sgibbsregister CLRSINT0 { 183297883Sgibbs address 0x04B 183397883Sgibbs access_mode WO 183497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1835102681Sgibbs field CLRSELDO 0x40 1836102681Sgibbs field CLRSELDI 0x20 1837102681Sgibbs field CLRSELINGO 0x10 1838102681Sgibbs field CLRIOERR 0x08 1839102681Sgibbs field CLROVERRUN 0x04 1840102681Sgibbs field CLRSPIORDY 0x02 1841102681Sgibbs field CLRARBDO 0x01 184297883Sgibbs} 184397883Sgibbs 184497883Sgibbs/* 184597883Sgibbs * SCSI Interrupt Mode 0 184697883Sgibbs * Setting any bit will enable the corresponding function 184797883Sgibbs * in SIMODE0 to interrupt via the IRQ pin. 184897883Sgibbs */ 184997883Sgibbsregister SIMODE0 { 185097883Sgibbs address 0x04B 185197883Sgibbs access_mode RW 185297883Sgibbs modes M_CFG 1853102681Sgibbs field ENSELDO 0x40 1854102681Sgibbs field ENSELDI 0x20 1855102681Sgibbs field ENSELINGO 0x10 1856102681Sgibbs field ENIOERR 0x08 1857102681Sgibbs field ENOVERRUN 0x04 1858102681Sgibbs field ENSPIORDY 0x02 1859102681Sgibbs field ENARBDO 0x01 186097883Sgibbs} 186197883Sgibbs 186297883Sgibbs/* 186397883Sgibbs * SCSI Status 1 186497883Sgibbs */ 186597883Sgibbsregister SSTAT1 { 186697883Sgibbs address 0x04C 186797883Sgibbs access_mode RO 186897883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1869102681Sgibbs field SELTO 0x80 1870102681Sgibbs field ATNTARG 0x40 1871102681Sgibbs field SCSIRSTI 0x20 1872102681Sgibbs field PHASEMIS 0x10 1873102681Sgibbs field BUSFREE 0x08 1874102681Sgibbs field SCSIPERR 0x04 1875102681Sgibbs field STRB2FAST 0x02 1876102681Sgibbs field REQINIT 0x01 187797883Sgibbs} 187897883Sgibbs 187997883Sgibbs/* 188097883Sgibbs * Clear SCSI Interrupt 1 188197883Sgibbs * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 188297883Sgibbs */ 188397883Sgibbsregister CLRSINT1 { 1884104023Sgibbs address 0x04C 188597883Sgibbs access_mode WO 188697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1887102681Sgibbs field CLRSELTIMEO 0x80 1888102681Sgibbs field CLRATNO 0x40 1889102681Sgibbs field CLRSCSIRSTI 0x20 1890102681Sgibbs field CLRBUSFREE 0x08 1891102681Sgibbs field CLRSCSIPERR 0x04 1892102681Sgibbs field CLRSTRB2FAST 0x02 1893102681Sgibbs field CLRREQINIT 0x01 189497883Sgibbs} 189597883Sgibbs 189697883Sgibbs/* 189797883Sgibbs * SCSI Status 2 189897883Sgibbs */ 189997883Sgibbsregister SSTAT2 { 190097883Sgibbs address 0x04d 190197883Sgibbs access_mode RO 190297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1903102681Sgibbs field BUSFREETIME 0xc0 { 1904102681Sgibbs BUSFREE_LQO 0x40, 1905102681Sgibbs BUSFREE_DFF0 0x80, 1906102681Sgibbs BUSFREE_DFF1 0xC0 1907102681Sgibbs } 1908102681Sgibbs field NONPACKREQ 0x20 1909102681Sgibbs field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1910102681Sgibbs field BSYX 0x08 /* Busy Expander */ 1911102681Sgibbs field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1912102681Sgibbs field SDONE 0x02 /* Modes 0 and 1 only */ 1913102681Sgibbs field DMADONE 0x01 /* Modes 0 and 1 only */ 191497883Sgibbs} 191597883Sgibbs 191697883Sgibbs/* 191797883Sgibbs * Clear SCSI Interrupt 2 191897883Sgibbs */ 191997883Sgibbsregister CLRSINT2 { 192097883Sgibbs address 0x04D 192197883Sgibbs access_mode WO 192297883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1923102681Sgibbs field CLRNONPACKREQ 0x20 1924102681Sgibbs field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1925102681Sgibbs field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1926102681Sgibbs field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 192797883Sgibbs} 192897883Sgibbs 192997883Sgibbs/* 193097883Sgibbs * SCSI Interrupt Mode 2 193197883Sgibbs */ 193297883Sgibbsregister SIMODE2 { 193397883Sgibbs address 0x04D 193497883Sgibbs access_mode RW 193597883Sgibbs modes M_CFG 1936102681Sgibbs field ENWIDE_RES 0x04 1937102681Sgibbs field ENSDONE 0x02 1938102681Sgibbs field ENDMADONE 0x01 193997883Sgibbs} 194097883Sgibbs 194197883Sgibbs/* 194297883Sgibbs * Physical Error Diagnosis 194397883Sgibbs */ 194497883Sgibbsregister PERRDIAG { 194597883Sgibbs address 0x04E 194697883Sgibbs access_mode RO 194797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1948102681Sgibbs field HIZERO 0x80 1949102681Sgibbs field HIPERR 0x40 1950102681Sgibbs field PREVPHASE 0x20 1951102681Sgibbs field PARITYERR 0x10 1952102681Sgibbs field AIPERR 0x08 1953102681Sgibbs field CRCERR 0x04 1954102681Sgibbs field DGFORMERR 0x02 1955102681Sgibbs field DTERR 0x01 195697883Sgibbs} 195797883Sgibbs 195897883Sgibbs/* 195997883Sgibbs * LQI Manager Current State 196097883Sgibbs */ 196197883Sgibbsregister LQISTATE { 196297883Sgibbs address 0x04E 196397883Sgibbs access_mode RO 196497883Sgibbs modes M_CFG 196597883Sgibbs} 196697883Sgibbs 196797883Sgibbs/* 196897883Sgibbs * SCSI Offset Count 196997883Sgibbs */ 197097883Sgibbsregister SOFFCNT { 197197883Sgibbs address 0x04F 197297883Sgibbs access_mode RO 197397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 197497883Sgibbs} 197597883Sgibbs 197697883Sgibbs/* 197797883Sgibbs * LQO Manager Current State 197897883Sgibbs */ 197997883Sgibbsregister LQOSTATE { 198097883Sgibbs address 0x04F 198197883Sgibbs access_mode RO 198297883Sgibbs modes M_CFG 198397883Sgibbs} 198497883Sgibbs 198597883Sgibbs/* 198697883Sgibbs * LQI Manager Status 198797883Sgibbs */ 198897883Sgibbsregister LQISTAT0 { 198997883Sgibbs address 0x050 199097883Sgibbs access_mode RO 199197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 1992102681Sgibbs field LQIATNQAS 0x20 1993102681Sgibbs field LQICRCT1 0x10 1994102681Sgibbs field LQICRCT2 0x08 1995102681Sgibbs field LQIBADLQT 0x04 1996102681Sgibbs field LQIATNLQ 0x02 1997102681Sgibbs field LQIATNCMD 0x01 199897883Sgibbs} 199997883Sgibbs 200097883Sgibbs/* 200197883Sgibbs * Clear LQI Interrupts 0 200297883Sgibbs */ 2003102681Sgibbsregister CLRLQIINT0 { 200497883Sgibbs address 0x050 200597883Sgibbs access_mode WO 200697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2007102681Sgibbs field CLRLQIATNQAS 0x20 2008102681Sgibbs field CLRLQICRCT1 0x10 2009102681Sgibbs field CLRLQICRCT2 0x08 2010102681Sgibbs field CLRLQIBADLQT 0x04 2011102681Sgibbs field CLRLQIATNLQ 0x02 2012102681Sgibbs field CLRLQIATNCMD 0x01 201397883Sgibbs} 201497883Sgibbs 201597883Sgibbs/* 201697883Sgibbs * LQI Manager Interrupt Mode 0 201797883Sgibbs */ 201897883Sgibbsregister LQIMODE0 { 201997883Sgibbs address 0x050 202097883Sgibbs access_mode RW 202197883Sgibbs modes M_CFG 2022102681Sgibbs field ENLQIATNQASK 0x20 2023102681Sgibbs field ENLQICRCT1 0x10 2024102681Sgibbs field ENLQICRCT2 0x08 2025102681Sgibbs field ENLQIBADLQT 0x04 2026102681Sgibbs field ENLQIATNLQ 0x02 2027102681Sgibbs field ENLQIATNCMD 0x01 202897883Sgibbs} 202997883Sgibbs 203097883Sgibbs/* 203197883Sgibbs * LQI Manager Status 1 203297883Sgibbs */ 203397883Sgibbsregister LQISTAT1 { 203497883Sgibbs address 0x051 203597883Sgibbs access_mode RO 203697883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2037102681Sgibbs field LQIPHASE_LQ 0x80 2038102681Sgibbs field LQIPHASE_NLQ 0x40 2039102681Sgibbs field LQIABORT 0x20 2040102681Sgibbs field LQICRCI_LQ 0x10 2041102681Sgibbs field LQICRCI_NLQ 0x08 2042102681Sgibbs field LQIBADLQI 0x04 2043102681Sgibbs field LQIOVERI_LQ 0x02 2044102681Sgibbs field LQIOVERI_NLQ 0x01 204597883Sgibbs} 204697883Sgibbs 204797883Sgibbs/* 204897883Sgibbs * Clear LQI Manager Interrupts1 204997883Sgibbs */ 205097883Sgibbsregister CLRLQIINT1 { 205197883Sgibbs address 0x051 205297883Sgibbs access_mode WO 205397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2054102681Sgibbs field CLRLQIPHASE_LQ 0x80 2055102681Sgibbs field CLRLQIPHASE_NLQ 0x40 2056102681Sgibbs field CLRLIQABORT 0x20 2057102681Sgibbs field CLRLQICRCI_LQ 0x10 2058102681Sgibbs field CLRLQICRCI_NLQ 0x08 2059102681Sgibbs field CLRLQIBADLQI 0x04 2060102681Sgibbs field CLRLQIOVERI_LQ 0x02 2061102681Sgibbs field CLRLQIOVERI_NLQ 0x01 206297883Sgibbs} 206397883Sgibbs 206497883Sgibbs/* 206597883Sgibbs * LQI Manager Interrupt Mode 1 206697883Sgibbs */ 206797883Sgibbsregister LQIMODE1 { 206897883Sgibbs address 0x051 206997883Sgibbs access_mode RW 207097883Sgibbs modes M_CFG 2071111653Sgibbs field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2072111653Sgibbs field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2073102681Sgibbs field ENLIQABORT 0x20 2074111653Sgibbs field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ 2075111653Sgibbs field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ 2076102681Sgibbs field ENLQIBADLQI 0x04 2077111653Sgibbs field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ 2078111653Sgibbs field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ 207997883Sgibbs} 208097883Sgibbs 208197883Sgibbs/* 208297883Sgibbs * LQI Manager Status 2 208397883Sgibbs */ 208497883Sgibbsregister LQISTAT2 { 208597883Sgibbs address 0x052 208697883Sgibbs access_mode RO 208797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2088102681Sgibbs field PACKETIZED 0x80 2089102681Sgibbs field LQIPHASE_OUTPKT 0x40 2090102681Sgibbs field LQIWORKONLQ 0x20 2091102681Sgibbs field LQIWAITFIFO 0x10 2092102681Sgibbs field LQISTOPPKT 0x08 2093102681Sgibbs field LQISTOPLQ 0x04 2094102681Sgibbs field LQISTOPCMD 0x02 2095102681Sgibbs field LQIGSAVAIL 0x01 209697883Sgibbs} 209797883Sgibbs 209897883Sgibbs/* 209997883Sgibbs * SCSI Status 3 210097883Sgibbs */ 210197883Sgibbsregister SSTAT3 { 210297883Sgibbs address 0x053 210397883Sgibbs access_mode RO 210497883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2105102681Sgibbs field NTRAMPERR 0x02 2106102681Sgibbs field OSRAMPERR 0x01 210797883Sgibbs} 210897883Sgibbs 210997883Sgibbs/* 211097883Sgibbs * Clear SCSI Status 3 211197883Sgibbs */ 211297883Sgibbsregister CLRSINT3 { 211397883Sgibbs address 0x053 211497883Sgibbs access_mode WO 211597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2116102681Sgibbs field CLRNTRAMPERR 0x02 2117102681Sgibbs field CLROSRAMPERR 0x01 211897883Sgibbs} 211997883Sgibbs 212097883Sgibbs/* 212197883Sgibbs * SCSI Interrupt Mode 3 212297883Sgibbs */ 212397883Sgibbsregister SIMODE3 { 212497883Sgibbs address 0x053 212597883Sgibbs access_mode RW 212697883Sgibbs modes M_CFG 2127102681Sgibbs field ENNTRAMPERR 0x02 2128102681Sgibbs field ENOSRAMPERR 0x01 212997883Sgibbs} 213097883Sgibbs 213197883Sgibbs/* 213297883Sgibbs * LQO Manager Status 0 213397883Sgibbs */ 213497883Sgibbsregister LQOSTAT0 { 213597883Sgibbs address 0x054 213697883Sgibbs access_mode RO 213797883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2138102681Sgibbs field LQOTARGSCBPERR 0x10 2139102681Sgibbs field LQOSTOPT2 0x08 2140102681Sgibbs field LQOATNLQ 0x04 2141102681Sgibbs field LQOATNPKT 0x02 2142102681Sgibbs field LQOTCRC 0x01 214397883Sgibbs} 214497883Sgibbs 214597883Sgibbs/* 214697883Sgibbs * Clear LQO Manager interrupt 0 214797883Sgibbs */ 214897883Sgibbsregister CLRLQOINT0 { 214997883Sgibbs address 0x054 215097883Sgibbs access_mode WO 215197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2152102681Sgibbs field CLRLQOTARGSCBPERR 0x10 2153102681Sgibbs field CLRLQOSTOPT2 0x08 2154102681Sgibbs field CLRLQOATNLQ 0x04 2155102681Sgibbs field CLRLQOATNPKT 0x02 2156102681Sgibbs field CLRLQOTCRC 0x01 215797883Sgibbs} 215897883Sgibbs 215997883Sgibbs/* 216097883Sgibbs * LQO Manager Interrupt Mode 0 216197883Sgibbs */ 216297883Sgibbsregister LQOMODE0 { 216397883Sgibbs address 0x054 216497883Sgibbs access_mode RW 216597883Sgibbs modes M_CFG 2166102681Sgibbs field ENLQOTARGSCBPERR 0x10 2167102681Sgibbs field ENLQOSTOPT2 0x08 2168102681Sgibbs field ENLQOATNLQ 0x04 2169102681Sgibbs field ENLQOATNPKT 0x02 2170102681Sgibbs field ENLQOTCRC 0x01 217197883Sgibbs} 217297883Sgibbs 217397883Sgibbs/* 217497883Sgibbs * LQO Manager Status 1 217597883Sgibbs */ 217697883Sgibbsregister LQOSTAT1 { 217797883Sgibbs address 0x055 217897883Sgibbs access_mode RO 217997883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2180102681Sgibbs field LQOINITSCBPERR 0x10 2181102681Sgibbs field LQOSTOPI2 0x08 2182102681Sgibbs field LQOBADQAS 0x04 2183102681Sgibbs field LQOBUSFREE 0x02 2184102681Sgibbs field LQOPHACHGINPKT 0x01 218597883Sgibbs} 218697883Sgibbs 218797883Sgibbs/* 218897883Sgibbs * Clear LOQ Interrupt 1 218997883Sgibbs */ 219097883Sgibbsregister CLRLQOINT1 { 219197883Sgibbs address 0x055 219297883Sgibbs access_mode WO 219397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2194102681Sgibbs field CLRLQOINITSCBPERR 0x10 2195102681Sgibbs field CLRLQOSTOPI2 0x08 2196102681Sgibbs field CLRLQOBADQAS 0x04 2197102681Sgibbs field CLRLQOBUSFREE 0x02 2198102681Sgibbs field CLRLQOPHACHGINPKT 0x01 219997883Sgibbs} 220097883Sgibbs 220197883Sgibbs/* 220297883Sgibbs * LQO Manager Interrupt Mode 1 220397883Sgibbs */ 220497883Sgibbsregister LQOMODE1 { 220597883Sgibbs address 0x055 220697883Sgibbs access_mode RW 220797883Sgibbs modes M_CFG 2208102681Sgibbs field ENLQOINITSCBPERR 0x10 2209102681Sgibbs field ENLQOSTOPI2 0x08 2210102681Sgibbs field ENLQOBADQAS 0x04 2211102681Sgibbs field ENLQOBUSFREE 0x02 2212102681Sgibbs field ENLQOPHACHGINPKT 0x01 221397883Sgibbs} 221497883Sgibbs 221597883Sgibbs/* 221697883Sgibbs * LQO Manager Status 2 221797883Sgibbs */ 221897883Sgibbsregister LQOSTAT2 { 221997883Sgibbs address 0x056 222097883Sgibbs access_mode RO 222197883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2222102681Sgibbs field LQOPKT 0xE0 2223102681Sgibbs field LQOWAITFIFO 0x10 2224102681Sgibbs field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2225102681Sgibbs field LQOSTOP0 0x01 /* Stopped after sending all packets */ 222697883Sgibbs} 222797883Sgibbs 222897883Sgibbs/* 222997883Sgibbs * Output Synchronizer Space Count 223097883Sgibbs */ 223197883Sgibbsregister OS_SPACE_CNT { 223297883Sgibbs address 0x056 223397883Sgibbs access_mode RO 223497883Sgibbs modes M_CFG 223597883Sgibbs} 223697883Sgibbs 223797883Sgibbs/* 223897883Sgibbs * SCSI Interrupt Mode 1 223997883Sgibbs * Setting any bit will enable the corresponding function 224097883Sgibbs * in SIMODE1 to interrupt via the IRQ pin. 224197883Sgibbs */ 224297883Sgibbsregister SIMODE1 { 224397883Sgibbs address 0x057 224497883Sgibbs access_mode RW 224597883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 2246102681Sgibbs field ENSELTIMO 0x80 2247102681Sgibbs field ENATNTARG 0x40 2248102681Sgibbs field ENSCSIRST 0x20 2249102681Sgibbs field ENPHASEMIS 0x10 2250102681Sgibbs field ENBUSFREE 0x08 2251102681Sgibbs field ENSCSIPERR 0x04 2252102681Sgibbs field ENSTRB2FAST 0x02 2253102681Sgibbs field ENREQINIT 0x01 225497883Sgibbs} 225597883Sgibbs 225697883Sgibbs/* 225797883Sgibbs * Good Status FIFO 225897883Sgibbs */ 225997883Sgibbsregister GSFIFO { 226097883Sgibbs address 0x058 226197883Sgibbs access_mode RO 226297883Sgibbs size 2 226397883Sgibbs modes M_DFF0, M_DFF1, M_SCSI 226497883Sgibbs} 226597883Sgibbs 226697883Sgibbs/* 226797883Sgibbs * Data FIFO SCSI Transfer Control 226897883Sgibbs */ 226997883Sgibbsregister DFFSXFRCTL { 227097883Sgibbs address 0x05A 227197883Sgibbs access_mode RW 227297883Sgibbs modes M_DFF0, M_DFF1 2273107441Sscottl field DFFBITBUCKET 0x08 2274102681Sgibbs field CLRSHCNT 0x04 2275102681Sgibbs field CLRCHN 0x02 2276102681Sgibbs field RSTCHN 0x01 227797883Sgibbs} 227897883Sgibbs 227997883Sgibbs/* 228097883Sgibbs * Next SCSI Control Block 228197883Sgibbs */ 228297883Sgibbsregister NEXTSCB { 228397883Sgibbs address 0x05A 228497883Sgibbs access_mode RW 228597883Sgibbs size 2 228697883Sgibbs modes M_SCSI 228797883Sgibbs} 2288107441Sscottl 2289107441Sscottl/* Rev B only. */ 2290107441Sscottlregister LQOSCSCTL { 2291107441Sscottl address 0x05A 2292107441Sscottl access_mode RW 2293107441Sscottl size 1 2294107441Sscottl modes M_CFG 2295107441Sscottl field LQOH2A_VERSION 0x80 2296107441Sscottl field LQONOCHKOVER 0x01 2297107441Sscottl} 2298107441Sscottl 229997883Sgibbs/* 230097883Sgibbs * SEQ Interrupts 230197883Sgibbs */ 230297883Sgibbsregister SEQINTSRC { 230397883Sgibbs address 0x05B 230497883Sgibbs access_mode RO 230597883Sgibbs modes M_DFF0, M_DFF1 2306102681Sgibbs field CTXTDONE 0x40 2307102681Sgibbs field SAVEPTRS 0x20 2308102681Sgibbs field CFG4DATA 0x10 2309102681Sgibbs field CFG4ISTAT 0x08 2310102681Sgibbs field CFG4TSTAT 0x04 2311102681Sgibbs field CFG4ICMD 0x02 2312102681Sgibbs field CFG4TCMD 0x01 231397883Sgibbs} 231497883Sgibbs 231597883Sgibbs/* 231697883Sgibbs * Clear Arp Interrupts 231797883Sgibbs */ 231897883Sgibbsregister CLRSEQINTSRC { 231997883Sgibbs address 0x05B 232097883Sgibbs access_mode WO 232197883Sgibbs modes M_DFF0, M_DFF1 2322102681Sgibbs field CLRCTXTDONE 0x40 2323102681Sgibbs field CLRSAVEPTRS 0x20 2324102681Sgibbs field CLRCFG4DATA 0x10 2325102681Sgibbs field CLRCFG4ISTAT 0x08 2326102681Sgibbs field CLRCFG4TSTAT 0x04 2327102681Sgibbs field CLRCFG4ICMD 0x02 2328102681Sgibbs field CLRCFG4TCMD 0x01 232997883Sgibbs} 233097883Sgibbs 233197883Sgibbs/* 233297883Sgibbs * SEQ Interrupt Enabled (Shared) 233397883Sgibbs */ 233497883Sgibbsregister SEQIMODE { 233597883Sgibbs address 0x05C 233697883Sgibbs access_mode RW 233797883Sgibbs modes M_DFF0, M_DFF1 2338102681Sgibbs field ENCTXTDONE 0x40 2339102681Sgibbs field ENSAVEPTRS 0x20 2340102681Sgibbs field ENCFG4DATA 0x10 2341102681Sgibbs field ENCFG4ISTAT 0x08 2342102681Sgibbs field ENCFG4TSTAT 0x04 2343102681Sgibbs field ENCFG4ICMD 0x02 2344102681Sgibbs field ENCFG4TCMD 0x01 234597883Sgibbs} 234697883Sgibbs 234797883Sgibbs/* 234897883Sgibbs * Current SCSI Control Block 234997883Sgibbs */ 235097883Sgibbsregister CURRSCB { 235197883Sgibbs address 0x05C 235297883Sgibbs access_mode RW 235397883Sgibbs size 2 235497883Sgibbs modes M_SCSI 235597883Sgibbs} 235697883Sgibbs 235797883Sgibbs/* 235897883Sgibbs * Data FIFO Status 235997883Sgibbs */ 236097883Sgibbsregister MDFFSTAT { 236197883Sgibbs address 0x05D 236297883Sgibbs access_mode RO 236397883Sgibbs modes M_DFF0, M_DFF1 2364102681Sgibbs field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2365102681Sgibbs field SHCNTMINUS1 0x20 /* Rev B or higher */ 2366102681Sgibbs field LASTSDONE 0x10 2367102681Sgibbs field SHVALID 0x08 2368102681Sgibbs field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2369102681Sgibbs field DATAINFIFO 0x02 2370102681Sgibbs field FIFOFREE 0x01 237197883Sgibbs} 237297883Sgibbs 237397883Sgibbs/* 237497883Sgibbs * CRC Control 237597883Sgibbs */ 237697883Sgibbsregister CRCCONTROL { 237797883Sgibbs address 0x05d 237897883Sgibbs access_mode RW 237997883Sgibbs modes M_CFG 2380102681Sgibbs field CRCVALCHKEN 0x40 238197883Sgibbs} 238297883Sgibbs 238397883Sgibbs/* 238497883Sgibbs * SCSI Test Control 238597883Sgibbs */ 238697883Sgibbsregister SCSITEST { 238797883Sgibbs address 0x05E 238897883Sgibbs access_mode RW 238997883Sgibbs modes M_CFG 2390102681Sgibbs field CNTRTEST 0x08 2391102681Sgibbs field SEL_TXPLL_DEBUG 0x04 239297883Sgibbs} 239397883Sgibbs 239497883Sgibbs/* 239597883Sgibbs * Data FIFO Queue Tag 239697883Sgibbs */ 239797883Sgibbsregister DFFTAG { 239897883Sgibbs address 0x05E 239997883Sgibbs access_mode RW 240097883Sgibbs size 2 240197883Sgibbs modes M_DFF0, M_DFF1 240297883Sgibbs} 240397883Sgibbs 240497883Sgibbs/* 240597883Sgibbs * Last SCSI Control Block 240697883Sgibbs */ 240797883Sgibbsregister LASTSCB { 240897883Sgibbs address 0x05E 240997883Sgibbs access_mode RW 241097883Sgibbs size 2 241197883Sgibbs modes M_SCSI 241297883Sgibbs} 241397883Sgibbs 241497883Sgibbs/* 241597883Sgibbs * SCSI I/O Cell Power-down Control 241697883Sgibbs */ 241797883Sgibbsregister IOPDNCTL { 241897883Sgibbs address 0x05F 241997883Sgibbs access_mode RW 242097883Sgibbs modes M_CFG 2421102681Sgibbs field DISABLE_OE 0x80 2422102681Sgibbs field PDN_IDIST 0x04 2423102681Sgibbs field PDN_DIFFSENSE 0x01 242497883Sgibbs} 242597883Sgibbs 242697883Sgibbs/* 2427299375Spfg * Shadow Host Address. 242897883Sgibbs */ 242997883Sgibbsregister SHADDR { 243097883Sgibbs address 0x060 243197883Sgibbs access_mode RO 243297883Sgibbs size 8 243397883Sgibbs modes M_DFF0, M_DFF1 243497883Sgibbs} 243597883Sgibbs 243697883Sgibbs/* 243797883Sgibbs * Data Group CRC Interval. 243897883Sgibbs */ 243997883Sgibbsregister DGRPCRCI { 244097883Sgibbs address 0x060 244197883Sgibbs access_mode RW 244297883Sgibbs size 2 244397883Sgibbs modes M_CFG 244497883Sgibbs} 244597883Sgibbs 244697883Sgibbs/* 244797883Sgibbs * Data Transfer Negotiation Address 244897883Sgibbs */ 244997883Sgibbsregister NEGOADDR { 245097883Sgibbs address 0x060 245197883Sgibbs access_mode RW 245297883Sgibbs modes M_SCSI 245397883Sgibbs} 245497883Sgibbs 245597883Sgibbs/* 245697883Sgibbs * Data Transfer Negotiation Data - Period Byte 245797883Sgibbs */ 245897883Sgibbsregister NEGPERIOD { 245997883Sgibbs address 0x061 246097883Sgibbs access_mode RW 246197883Sgibbs modes M_SCSI 246297883Sgibbs} 246397883Sgibbs 246497883Sgibbs/* 246597883Sgibbs * Packetized CRC Interval 246697883Sgibbs */ 246797883Sgibbsregister PACKCRCI { 246897883Sgibbs address 0x062 246997883Sgibbs access_mode RW 247097883Sgibbs size 2 247197883Sgibbs modes M_CFG 247297883Sgibbs} 247397883Sgibbs 247497883Sgibbs/* 247597883Sgibbs * Data Transfer Negotiation Data - Offset Byte 247697883Sgibbs */ 247797883Sgibbsregister NEGOFFSET { 247897883Sgibbs address 0x062 247997883Sgibbs access_mode RW 248097883Sgibbs modes M_SCSI 248197883Sgibbs} 248297883Sgibbs 248397883Sgibbs/* 248497883Sgibbs * Data Transfer Negotiation Data - PPR Options 248597883Sgibbs */ 248697883Sgibbsregister NEGPPROPTS { 248797883Sgibbs address 0x063 248897883Sgibbs access_mode RW 248997883Sgibbs modes M_SCSI 2490102681Sgibbs field PPROPT_PACE 0x08 2491102681Sgibbs field PPROPT_QAS 0x04 2492102681Sgibbs field PPROPT_DT 0x02 2493102681Sgibbs field PPROPT_IUT 0x01 249497883Sgibbs} 249597883Sgibbs 249697883Sgibbs/* 249797883Sgibbs * Data Transfer Negotiation Data - Connection Options 249897883Sgibbs */ 249997883Sgibbsregister NEGCONOPTS { 250097883Sgibbs address 0x064 250197883Sgibbs access_mode RW 250297883Sgibbs modes M_SCSI 2503107441Sscottl field ENSNAPSHOT 0x40 2504107441Sscottl field RTI_WRTDIS 0x20 2505107441Sscottl field RTI_OVRDTRN 0x10 2506107441Sscottl field ENSLOWCRC 0x08 2507102681Sgibbs field ENAUTOATNI 0x04 2508102681Sgibbs field ENAUTOATNO 0x02 2509102681Sgibbs field WIDEXFER 0x01 251097883Sgibbs} 251197883Sgibbs 251297883Sgibbs/* 251397883Sgibbs * Negotiation Table Annex Column Index. 251497883Sgibbs */ 251597883Sgibbsregister ANNEXCOL { 251697883Sgibbs address 0x065 251797883Sgibbs access_mode RW 251897883Sgibbs modes M_SCSI 251997883Sgibbs} 252097883Sgibbs 2521102681Sgibbsregister SCSCHKN { 2522102681Sgibbs address 0x066 2523102681Sgibbs access_mode RW 2524102681Sgibbs modes M_CFG 2525102681Sgibbs field STSELSKIDDIS 0x40 2526107441Sscottl field CURRFIFODEF 0x20 2527102681Sgibbs field WIDERESEN 0x10 2528102681Sgibbs field SDONEMSKDIS 0x08 2529102681Sgibbs field DFFACTCLR 0x04 2530102681Sgibbs field SHVALIDSTDIS 0x02 2531102681Sgibbs field LSTSGCLRDIS 0x01 2532102681Sgibbs} 2533102681Sgibbs 2534107441Sscottlconst AHD_ANNEXCOL_PER_DEV0 4 2535107441Sscottlconst AHD_NUM_PER_DEV_ANNEXCOLS 4 2536107441Sscottlconst AHD_ANNEXCOL_PRECOMP_SLEW 4 253797883Sgibbsconst AHD_PRECOMP_MASK 0x07 2538107441Sscottlconst AHD_PRECOMP_SHIFT 0 253997883Sgibbsconst AHD_PRECOMP_CUTBACK_17 0x04 254097883Sgibbsconst AHD_PRECOMP_CUTBACK_29 0x06 254197883Sgibbsconst AHD_PRECOMP_CUTBACK_37 0x07 2542107441Sscottlconst AHD_SLEWRATE_MASK 0x78 2543107441Sscottlconst AHD_SLEWRATE_SHIFT 3 2544107441Sscottl/* 2545112641Sscottl * Rev A has only a single bit (high bit of field) of slew adjustment. 2546112641Sscottl * Rev B has 4 bits. The current default happens to be the same for both. 2547107441Sscottl */ 2548112641Sscottlconst AHD_SLEWRATE_DEF_REVA 0x08 2549107441Sscottlconst AHD_SLEWRATE_DEF_REVB 0x08 255097883Sgibbs 2551107441Sscottl/* Rev A does not have any amplitude setting. */ 2552107441Sscottlconst AHD_ANNEXCOL_AMPLITUDE 6 2553107441Sscottlconst AHD_AMPLITUDE_MASK 0x7 2554107441Sscottlconst AHD_AMPLITUDE_SHIFT 0 2555107441Sscottlconst AHD_AMPLITUDE_DEF 0x7 2556107441Sscottl 255797883Sgibbs/* 255897883Sgibbs * Negotiation Table Annex Data Port. 255997883Sgibbs */ 256097883Sgibbsregister ANNEXDAT { 256197883Sgibbs address 0x066 256297883Sgibbs access_mode RW 256397883Sgibbs modes M_SCSI 256497883Sgibbs} 256597883Sgibbs 256697883Sgibbs/* 256797883Sgibbs * Initiator's Own Id. 256897883Sgibbs * The SCSI ID to use for Selection Out and seen during a reselection.. 256997883Sgibbs */ 257097883Sgibbsregister IOWNID { 257197883Sgibbs address 0x067 257297883Sgibbs access_mode RW 257397883Sgibbs modes M_SCSI 257497883Sgibbs} 257597883Sgibbs 257697883Sgibbs/* 257797883Sgibbs * 960MHz Phase-Locked Loop Control 0 257897883Sgibbs */ 257997883Sgibbsregister PLL960CTL0 { 258097883Sgibbs address 0x068 258197883Sgibbs access_mode RW 258297883Sgibbs modes M_CFG 2583102681Sgibbs field PLL_VCOSEL 0x80 2584102681Sgibbs field PLL_PWDN 0x40 2585102681Sgibbs field PLL_NS 0x30 2586102681Sgibbs field PLL_ENLUD 0x08 2587102681Sgibbs field PLL_ENLPF 0x04 2588102681Sgibbs field PLL_DLPF 0x02 2589102681Sgibbs field PLL_ENFBM 0x01 259097883Sgibbs} 259197883Sgibbs 259297883Sgibbs/* 259397883Sgibbs * Target Own Id 259497883Sgibbs */ 259597883Sgibbsregister TOWNID { 259697883Sgibbs address 0x069 259797883Sgibbs access_mode RW 259897883Sgibbs modes M_SCSI 259997883Sgibbs} 260097883Sgibbs 260197883Sgibbs/* 260297883Sgibbs * 960MHz Phase-Locked Loop Control 1 260397883Sgibbs */ 260497883Sgibbsregister PLL960CTL1 { 260597883Sgibbs address 0x069 260697883Sgibbs access_mode RW 260797883Sgibbs modes M_CFG 2608102681Sgibbs field PLL_CNTEN 0x80 2609102681Sgibbs field PLL_CNTCLR 0x40 2610102681Sgibbs field PLL_RST 0x01 261197883Sgibbs} 261297883Sgibbs 261397883Sgibbs/* 261497883Sgibbs * Expander Signature 261597883Sgibbs */ 261697883Sgibbsregister XSIG { 261797883Sgibbs address 0x06A 261897883Sgibbs access_mode RW 261997883Sgibbs modes M_SCSI 262097883Sgibbs} 262197883Sgibbs 262297883Sgibbs/* 262397883Sgibbs * Shadow Byte Count 262497883Sgibbs */ 262597883Sgibbsregister SHCNT { 262697883Sgibbs address 0x068 262797883Sgibbs access_mode RW 262897883Sgibbs size 3 262997883Sgibbs modes M_DFF0, M_DFF1 263097883Sgibbs} 263197883Sgibbs 263297883Sgibbs/* 263397883Sgibbs * Selection Out ID 263497883Sgibbs */ 263597883Sgibbsregister SELOID { 263697883Sgibbs address 0x06B 263797883Sgibbs access_mode RW 263897883Sgibbs modes M_SCSI 263997883Sgibbs} 264097883Sgibbs 264197883Sgibbs/* 264297883Sgibbs * 960-MHz Phase-Locked Loop Test Count 264397883Sgibbs */ 264497883Sgibbsregister PLL960CNT0 { 264597883Sgibbs address 0x06A 264697883Sgibbs access_mode RO 264797883Sgibbs size 2 264897883Sgibbs modes M_CFG 264997883Sgibbs} 265097883Sgibbs 265197883Sgibbs/* 265297883Sgibbs * 400-MHz Phase-Locked Loop Control 0 265397883Sgibbs */ 265497883Sgibbsregister PLL400CTL0 { 265597883Sgibbs address 0x06C 265697883Sgibbs access_mode RW 265797883Sgibbs modes M_CFG 2658102681Sgibbs field PLL_VCOSEL 0x80 2659102681Sgibbs field PLL_PWDN 0x40 2660102681Sgibbs field PLL_NS 0x30 2661102681Sgibbs field PLL_ENLUD 0x08 2662102681Sgibbs field PLL_ENLPF 0x04 2663102681Sgibbs field PLL_DLPF 0x02 2664102681Sgibbs field PLL_ENFBM 0x01 266597883Sgibbs} 266697883Sgibbs 266797883Sgibbs/* 266897883Sgibbs * Arbitration Fairness 266997883Sgibbs */ 267097883Sgibbsregister FAIRNESS { 267197883Sgibbs address 0x06C 267297883Sgibbs access_mode RW 267397883Sgibbs size 2 267497883Sgibbs modes M_SCSI 267597883Sgibbs} 267697883Sgibbs 267797883Sgibbs/* 267897883Sgibbs * 400-MHz Phase-Locked Loop Control 1 267997883Sgibbs */ 268097883Sgibbsregister PLL400CTL1 { 268197883Sgibbs address 0x06D 268297883Sgibbs access_mode RW 268397883Sgibbs modes M_CFG 2684102681Sgibbs field PLL_CNTEN 0x80 2685102681Sgibbs field PLL_CNTCLR 0x40 2686102681Sgibbs field PLL_RST 0x01 268797883Sgibbs} 268897883Sgibbs 268997883Sgibbs/* 269097883Sgibbs * Arbitration Unfairness 269197883Sgibbs */ 269297883Sgibbsregister UNFAIRNESS { 269397883Sgibbs address 0x06E 269497883Sgibbs access_mode RW 269597883Sgibbs size 2 269697883Sgibbs modes M_SCSI 269797883Sgibbs} 269897883Sgibbs 269997883Sgibbs/* 270097883Sgibbs * 400-MHz Phase-Locked Loop Test Count 270197883Sgibbs */ 270297883Sgibbsregister PLL400CNT0 { 270397883Sgibbs address 0x06E 270497883Sgibbs access_mode RO 270597883Sgibbs size 2 270697883Sgibbs modes M_CFG 270797883Sgibbs} 270897883Sgibbs 270997883Sgibbs/* 271097883Sgibbs * SCB Page Pointer 271197883Sgibbs */ 271297883Sgibbsregister SCBPTR { 271397883Sgibbs address 0x0A8 271497883Sgibbs access_mode RW 271597883Sgibbs size 2 271697883Sgibbs modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 271797883Sgibbs} 271897883Sgibbs 271997883Sgibbs/* 272097883Sgibbs * CMC SCB Array Count 272197883Sgibbs * Number of bytes to transfer between CMC SCB memory and SCBRAM. 272297883Sgibbs * Transfers must be 8byte aligned and sized. 272397883Sgibbs */ 272497883Sgibbsregister CCSCBACNT { 272597883Sgibbs address 0x0AB 272697883Sgibbs access_mode RW 272797883Sgibbs modes M_CCHAN 272897883Sgibbs} 272997883Sgibbs 273097883Sgibbs/* 273197883Sgibbs * SCB Autopointer 273297883Sgibbs * SCB-Next Address Snooping logic. When an SCB is transferred to 273397883Sgibbs * the card, the next SCB address to be used by the CMC array can 273497883Sgibbs * be autoloaded from that transfer. 273597883Sgibbs */ 273697883Sgibbsregister SCBAUTOPTR { 273797883Sgibbs address 0x0AB 273897883Sgibbs access_mode RW 273997883Sgibbs modes M_CFG 2740102681Sgibbs field AUSCBPTR_EN 0x80 2741102681Sgibbs field SCBPTR_ADDR 0x38 2742102681Sgibbs field SCBPTR_OFF 0x07 274397883Sgibbs} 274497883Sgibbs 274597883Sgibbs/* 274697883Sgibbs * CMC SG Ram Address Pointer 274797883Sgibbs */ 274897883Sgibbsregister CCSGADDR { 274997883Sgibbs address 0x0AC 275097883Sgibbs access_mode RW 275197883Sgibbs modes M_DFF0, M_DFF1 275297883Sgibbs} 275397883Sgibbs 275497883Sgibbs/* 275597883Sgibbs * CMC SCB RAM Address Pointer 275697883Sgibbs */ 275797883Sgibbsregister CCSCBADDR { 275897883Sgibbs address 0x0AC 275997883Sgibbs access_mode RW 276097883Sgibbs modes M_CCHAN 276197883Sgibbs} 276297883Sgibbs 276397883Sgibbs/* 276497883Sgibbs * CMC SCB Ram Back-up Address Pointer 276597883Sgibbs * Indicates the true stop location of transfers halted prior 276697883Sgibbs * to SCBHCNT going to 0. 276797883Sgibbs */ 276897883Sgibbsregister CCSCBADR_BK { 276997883Sgibbs address 0x0AC 277097883Sgibbs access_mode RO 277197883Sgibbs modes M_CFG 277297883Sgibbs} 277397883Sgibbs 277497883Sgibbs/* 277597883Sgibbs * CMC SG Control 277697883Sgibbs */ 277797883Sgibbsregister CCSGCTL { 277897883Sgibbs address 0x0AD 277997883Sgibbs access_mode RW 278097883Sgibbs modes M_DFF0, M_DFF1 2781102681Sgibbs field CCSGDONE 0x80 2782102681Sgibbs field SG_CACHE_AVAIL 0x10 2783107441Sscottl field CCSGENACK 0x08 2784107441Sscottl mask CCSGEN 0x0C 2785102681Sgibbs field SG_FETCH_REQ 0x02 2786102681Sgibbs field CCSGRESET 0x01 278797883Sgibbs} 278897883Sgibbs 278997883Sgibbs/* 279097883Sgibbs * CMD SCB Control 279197883Sgibbs */ 279297883Sgibbsregister CCSCBCTL { 279397883Sgibbs address 0x0AD 279497883Sgibbs access_mode RW 279597883Sgibbs modes M_CCHAN 2796102681Sgibbs field CCSCBDONE 0x80 2797102681Sgibbs field ARRDONE 0x40 2798102681Sgibbs field CCARREN 0x10 2799102681Sgibbs field CCSCBEN 0x08 2800102681Sgibbs field CCSCBDIR 0x04 2801102681Sgibbs field CCSCBRESET 0x01 280297883Sgibbs} 280397883Sgibbs 280497883Sgibbs/* 280597883Sgibbs * CMC Ram BIST 280697883Sgibbs */ 280797883Sgibbsregister CMC_RAMBIST { 280897883Sgibbs address 0x0AD 280997883Sgibbs access_mode RW 281097883Sgibbs modes M_CFG 2811102681Sgibbs field SG_ELEMENT_SIZE 0x80 2812102681Sgibbs field SCBRAMBIST_FAIL 0x40 2813102681Sgibbs field SG_BIST_FAIL 0x20 2814102681Sgibbs field SG_BIST_EN 0x10 2815102681Sgibbs field CMC_BUFFER_BIST_FAIL 0x02 2816102681Sgibbs field CMC_BUFFER_BIST_EN 0x01 281797883Sgibbs} 281897883Sgibbs 281997883Sgibbs/* 282097883Sgibbs * CMC SG RAM Data Port 282197883Sgibbs */ 282297883Sgibbsregister CCSGRAM { 282397883Sgibbs address 0x0B0 282497883Sgibbs access_mode RW 282597883Sgibbs modes M_DFF0, M_DFF1 282697883Sgibbs} 282797883Sgibbs 282897883Sgibbs/* 282997883Sgibbs * CMC SCB RAM Data Port 283097883Sgibbs */ 283197883Sgibbsregister CCSCBRAM { 283297883Sgibbs address 0x0B0 283397883Sgibbs access_mode RW 283497883Sgibbs modes M_CCHAN 283597883Sgibbs} 283697883Sgibbs 283797883Sgibbs/* 283897883Sgibbs * Flex DMA Address. 283997883Sgibbs */ 284097883Sgibbsregister FLEXADR { 284197883Sgibbs address 0x0B0 284297883Sgibbs access_mode RW 284397883Sgibbs size 3 284497883Sgibbs modes M_SCSI 284597883Sgibbs} 284697883Sgibbs 284797883Sgibbs/* 284897883Sgibbs * Flex DMA Byte Count 284997883Sgibbs */ 285097883Sgibbsregister FLEXCNT { 285197883Sgibbs address 0x0B3 285297883Sgibbs access_mode RW 285397883Sgibbs size 2 285497883Sgibbs modes M_SCSI 285597883Sgibbs} 285697883Sgibbs 285797883Sgibbs/* 285897883Sgibbs * Flex DMA Status 285997883Sgibbs */ 286097883Sgibbsregister FLEXDMASTAT { 286197883Sgibbs address 0x0B5 286297883Sgibbs access_mode RW 286397883Sgibbs modes M_SCSI 2864102681Sgibbs field FLEXDMAERR 0x02 2865102681Sgibbs field FLEXDMADONE 0x01 286697883Sgibbs} 286797883Sgibbs 286897883Sgibbs/* 286997883Sgibbs * Flex DMA Data Port 287097883Sgibbs */ 287197883Sgibbsregister FLEXDATA { 287297883Sgibbs address 0x0B6 287397883Sgibbs access_mode RW 287497883Sgibbs modes M_SCSI 287597883Sgibbs} 287697883Sgibbs 287797883Sgibbs/* 287897883Sgibbs * Board Data 287997883Sgibbs */ 288097883Sgibbsregister BRDDAT { 288197883Sgibbs address 0x0B8 288297883Sgibbs access_mode RW 288397883Sgibbs modes M_SCSI 288497883Sgibbs} 288597883Sgibbs 288697883Sgibbs/* 288797883Sgibbs * Board Control 288897883Sgibbs */ 288997883Sgibbsregister BRDCTL { 289097883Sgibbs address 0x0B9 289197883Sgibbs access_mode RW 289297883Sgibbs modes M_SCSI 2893102681Sgibbs field FLXARBACK 0x80 2894102681Sgibbs field FLXARBREQ 0x40 2895102681Sgibbs field BRDADDR 0x38 2896102681Sgibbs field BRDEN 0x04 2897102681Sgibbs field BRDRW 0x02 2898102681Sgibbs field BRDSTB 0x01 289997883Sgibbs} 290097883Sgibbs 290197883Sgibbs/* 290297883Sgibbs * Serial EEPROM Address 290397883Sgibbs */ 290497883Sgibbsregister SEEADR { 290597883Sgibbs address 0x0BA 290697883Sgibbs access_mode RW 290797883Sgibbs modes M_SCSI 290897883Sgibbs} 290997883Sgibbs 291097883Sgibbs/* 291197883Sgibbs * Serial EEPROM Data 291297883Sgibbs */ 291397883Sgibbsregister SEEDAT { 291497883Sgibbs address 0x0BC 291597883Sgibbs access_mode RW 291697883Sgibbs size 2 291797883Sgibbs modes M_SCSI 291897883Sgibbs} 291997883Sgibbs 292097883Sgibbs/* 292197883Sgibbs * Serial EEPROM Status 292297883Sgibbs */ 292397883Sgibbsregister SEESTAT { 292497883Sgibbs address 0x0BE 292597883Sgibbs access_mode RO 292697883Sgibbs modes M_SCSI 2927102681Sgibbs field INIT_DONE 0x80 2928102681Sgibbs field SEEOPCODE 0x70 2929102681Sgibbs field LDALTID_L 0x08 2930102681Sgibbs field SEEARBACK 0x04 2931102681Sgibbs field SEEBUSY 0x02 2932102681Sgibbs field SEESTART 0x01 293397883Sgibbs} 293497883Sgibbs 293597883Sgibbs/* 293697883Sgibbs * Serial EEPROM Control 293797883Sgibbs */ 293897883Sgibbsregister SEECTL { 293997883Sgibbs address 0x0BE 294097883Sgibbs access_mode RW 294197883Sgibbs modes M_SCSI 2942102681Sgibbs field SEEOPCODE 0x70 { 2943102681Sgibbs SEEOP_ERASE 0x70, 2944102681Sgibbs SEEOP_READ 0x60, 2945102681Sgibbs SEEOP_WRITE 0x50, 294697883Sgibbs /* 294797883Sgibbs * The following four commands use special 294897883Sgibbs * addresses for differentiation. 294997883Sgibbs */ 2950102681Sgibbs SEEOP_ERAL 0x40 2951102681Sgibbs } 295297883Sgibbs mask SEEOP_EWEN 0x40 295397883Sgibbs mask SEEOP_WALL 0x40 295497883Sgibbs mask SEEOP_EWDS 0x40 2955102681Sgibbs field SEERST 0x02 2956102681Sgibbs field SEESTART 0x01 295797883Sgibbs} 295897883Sgibbs 295997883Sgibbsconst SEEOP_ERAL_ADDR 0x80 296097883Sgibbsconst SEEOP_EWEN_ADDR 0xC0 296197883Sgibbsconst SEEOP_WRAL_ADDR 0x40 296297883Sgibbsconst SEEOP_EWDS_ADDR 0x00 296397883Sgibbs 296497883Sgibbs/* 296597883Sgibbs * SCB Counter 296697883Sgibbs */ 296797883Sgibbsregister SCBCNT { 296897883Sgibbs address 0x0BF 296997883Sgibbs access_mode RW 297097883Sgibbs modes M_SCSI 297197883Sgibbs} 297297883Sgibbs 297397883Sgibbs/* 297497883Sgibbs * Data FIFO Write Address 297597883Sgibbs * Pointer to the next QWD location to be written to the data FIFO. 297697883Sgibbs */ 297797883Sgibbsregister DFWADDR { 297897883Sgibbs address 0x0C0 297997883Sgibbs access_mode RW 298097883Sgibbs size 2 298197883Sgibbs modes M_DFF0, M_DFF1 298297883Sgibbs} 298397883Sgibbs 298497883Sgibbs/* 298597883Sgibbs * DSP Filter Control 298697883Sgibbs */ 298797883Sgibbsregister DSPFLTRCTL { 298897883Sgibbs address 0x0C0 298997883Sgibbs access_mode RW 299097883Sgibbs modes M_CFG 2991102681Sgibbs field FLTRDISABLE 0x20 2992102681Sgibbs field EDGESENSE 0x10 2993102681Sgibbs field DSPFCNTSEL 0x0F 299497883Sgibbs} 299597883Sgibbs 299697883Sgibbs/* 299797883Sgibbs * DSP Data Channel Control 299897883Sgibbs */ 299997883Sgibbsregister DSPDATACTL { 300097883Sgibbs address 0x0C1 300197883Sgibbs access_mode RW 300297883Sgibbs modes M_CFG 3003102681Sgibbs field BYPASSENAB 0x80 3004102681Sgibbs field DESQDIS 0x10 3005102681Sgibbs field RCVROFFSTDIS 0x04 3006102681Sgibbs field XMITOFFSTDIS 0x02 300797883Sgibbs} 300897883Sgibbs 300997883Sgibbs/* 301097883Sgibbs * Data FIFO Read Address 301197883Sgibbs * Pointer to the next QWD location to be read from the data FIFO. 301297883Sgibbs */ 301397883Sgibbsregister DFRADDR { 301497883Sgibbs address 0x0C2 301597883Sgibbs access_mode RW 301697883Sgibbs size 2 301797883Sgibbs modes M_DFF0, M_DFF1 301897883Sgibbs} 301997883Sgibbs 302097883Sgibbs/* 302197883Sgibbs * DSP REQ Control 302297883Sgibbs */ 302397883Sgibbsregister DSPREQCTL { 302497883Sgibbs address 0x0C2 302597883Sgibbs access_mode RW 302697883Sgibbs modes M_CFG 3027102681Sgibbs field MANREQCTL 0xC0 3028102681Sgibbs field MANREQDLY 0x3F 302997883Sgibbs} 303097883Sgibbs 303197883Sgibbs/* 303297883Sgibbs * DSP ACK Control 303397883Sgibbs */ 303497883Sgibbsregister DSPACKCTL { 303597883Sgibbs address 0x0C3 303697883Sgibbs access_mode RW 303797883Sgibbs modes M_CFG 3038102681Sgibbs field MANACKCTL 0xC0 3039102681Sgibbs field MANACKDLY 0x3F 304097883Sgibbs} 304197883Sgibbs 304297883Sgibbs/* 304397883Sgibbs * Data FIFO Data 304497883Sgibbs * Read/Write byte port into the data FIFO. The read and write 304597883Sgibbs * FIFO pointers increment with each read and write respectively 304697883Sgibbs * to this port. 304797883Sgibbs */ 304897883Sgibbsregister DFDAT { 304997883Sgibbs address 0x0C4 305097883Sgibbs access_mode RW 305197883Sgibbs modes M_DFF0, M_DFF1 305297883Sgibbs} 305397883Sgibbs 305497883Sgibbs/* 305597883Sgibbs * DSP Channel Select 305697883Sgibbs */ 305797883Sgibbsregister DSPSELECT { 305897883Sgibbs address 0x0C4 305997883Sgibbs access_mode RW 306097883Sgibbs modes M_CFG 3061102681Sgibbs field AUTOINCEN 0x80 3062102681Sgibbs field DSPSEL 0x1F 306397883Sgibbs} 306497883Sgibbs 306597883Sgibbsconst NUMDSPS 0x14 306697883Sgibbs 306797883Sgibbs/* 306897883Sgibbs * Write Bias Control 306997883Sgibbs */ 307097883Sgibbsregister WRTBIASCTL { 307197883Sgibbs address 0x0C5 307297883Sgibbs access_mode WO 307397883Sgibbs modes M_CFG 3074102681Sgibbs field AUTOXBCDIS 0x80 3075102681Sgibbs field XMITMANVAL 0x3F 307697883Sgibbs} 307797883Sgibbs 3078107441Sscottl/* 3079107441Sscottl * Currently the WRTBIASCTL is the same as the default. 3080107441Sscottl */ 3081107441Sscottlconst WRTBIASCTL_HP_DEFAULT 0x0 308297883Sgibbs 308397883Sgibbs/* 308497883Sgibbs * Receiver Bias Control 308597883Sgibbs */ 308697883Sgibbsregister RCVRBIOSCTL { 308797883Sgibbs address 0x0C6 308897883Sgibbs access_mode WO 308997883Sgibbs modes M_CFG 3090102681Sgibbs field AUTORBCDIS 0x80 3091102681Sgibbs field RCVRMANVAL 0x3F 309297883Sgibbs} 309397883Sgibbs 309497883Sgibbs/* 309597883Sgibbs * Write Bias Calculator 309697883Sgibbs */ 309797883Sgibbsregister WRTBIASCALC { 309897883Sgibbs address 0x0C7 309997883Sgibbs access_mode RO 310097883Sgibbs modes M_CFG 310197883Sgibbs} 310297883Sgibbs 310397883Sgibbs/* 310497883Sgibbs * Data FIFO Pointers 310597883Sgibbs * Contains the byte offset from DFWADDR and DWRADDR to the current 310697883Sgibbs * FIFO write/read locations. 310797883Sgibbs */ 310897883Sgibbsregister DFPTRS { 310997883Sgibbs address 0x0C8 311097883Sgibbs access_mode RW 311197883Sgibbs modes M_DFF0, M_DFF1 311297883Sgibbs} 311397883Sgibbs 311497883Sgibbs/* 311597883Sgibbs * Receiver Bias Calculator 311697883Sgibbs */ 311797883Sgibbsregister RCVRBIASCALC { 311897883Sgibbs address 0x0C8 311997883Sgibbs access_mode RO 312097883Sgibbs modes M_CFG 312197883Sgibbs} 312297883Sgibbs 312397883Sgibbs/* 312497883Sgibbs * Data FIFO Backup Read Pointer 312597883Sgibbs * Contains the data FIFO address to be restored if the last 312697883Sgibbs * data accessed from the data FIFO was not transferred successfully. 312797883Sgibbs */ 312897883Sgibbsregister DFBKPTR { 312997883Sgibbs address 0x0C9 313097883Sgibbs access_mode RW 313197883Sgibbs size 2 313297883Sgibbs modes M_DFF0, M_DFF1 313397883Sgibbs} 313497883Sgibbs 313597883Sgibbs/* 313697883Sgibbs * Skew Calculator 313797883Sgibbs */ 313897883Sgibbsregister SKEWCALC { 313997883Sgibbs address 0x0C9 314097883Sgibbs access_mode RO 314197883Sgibbs modes M_CFG 314297883Sgibbs} 314397883Sgibbs 314497883Sgibbs/* 3145109588Sgibbs * Data FIFO Debug Control 3146109588Sgibbs */ 3147109588Sgibbsregister DFDBCTL { 3148109588Sgibbs address 0x0CB 3149109588Sgibbs access_mode RW 3150109588Sgibbs modes M_DFF0, M_DFF1 3151109588Sgibbs field DFF_CIO_WR_RDY 0x20 3152109588Sgibbs field DFF_CIO_RD_RDY 0x10 3153109588Sgibbs field DFF_DIR_ERR 0x08 3154109588Sgibbs field DFF_RAMBIST_FAIL 0x04 3155109588Sgibbs field DFF_RAMBIST_DONE 0x02 3156109588Sgibbs field DFF_RAMBIST_EN 0x01 3157109588Sgibbs} 3158109588Sgibbs 3159109588Sgibbs/* 316097883Sgibbs * Data FIFO Space Count 316197883Sgibbs * Number of FIFO locations that are free. 316297883Sgibbs */ 316397883Sgibbsregister DFSCNT { 316497883Sgibbs address 0x0CC 316597883Sgibbs access_mode RO 316697883Sgibbs size 2 316797883Sgibbs modes M_DFF0, M_DFF1 316897883Sgibbs} 316997883Sgibbs 317097883Sgibbs/* 317197883Sgibbs * Data FIFO Byte Count 317297883Sgibbs * Number of filled FIFO locations. 317397883Sgibbs */ 317497883Sgibbsregister DFBCNT { 317597883Sgibbs address 0x0CE 317697883Sgibbs access_mode RO 317797883Sgibbs size 2 317897883Sgibbs modes M_DFF0, M_DFF1 317997883Sgibbs} 318097883Sgibbs 318197883Sgibbs/* 318297883Sgibbs * Sequencer Program Overlay Address. 318397883Sgibbs * Low address must be written prior to high address. 318497883Sgibbs */ 318597883Sgibbsregister OVLYADDR { 318697883Sgibbs address 0x0D4 318797883Sgibbs modes M_SCSI 318897883Sgibbs size 2 318997883Sgibbs access_mode RW 319097883Sgibbs} 319197883Sgibbs 319297883Sgibbs/* 319397883Sgibbs * Sequencer Control 0 319497883Sgibbs * Error detection mode, speed configuration, 319597883Sgibbs * single step, breakpoints and program load. 319697883Sgibbs */ 319797883Sgibbsregister SEQCTL0 { 319897883Sgibbs address 0x0D6 319997883Sgibbs access_mode RW 3200102681Sgibbs field PERRORDIS 0x80 3201102681Sgibbs field PAUSEDIS 0x40 3202102681Sgibbs field FAILDIS 0x20 3203102681Sgibbs field FASTMODE 0x10 3204102681Sgibbs field BRKADRINTEN 0x08 3205102681Sgibbs field STEP 0x04 3206102681Sgibbs field SEQRESET 0x02 3207102681Sgibbs field LOADRAM 0x01 320897883Sgibbs} 320997883Sgibbs 321097883Sgibbs/* 321197883Sgibbs * Sequencer Control 1 321297883Sgibbs * Instruction RAM Diagnostics 321397883Sgibbs */ 321497883Sgibbsregister SEQCTL1 { 321597883Sgibbs address 0x0D7 321697883Sgibbs access_mode RW 3217102681Sgibbs field OVRLAY_DATA_CHK 0x08 3218102681Sgibbs field RAMBIST_DONE 0x04 3219102681Sgibbs field RAMBIST_FAIL 0x02 3220102681Sgibbs field RAMBIST_EN 0x01 322197883Sgibbs} 322297883Sgibbs 322397883Sgibbs/* 322497883Sgibbs * Sequencer Flags 322597883Sgibbs * Zero and Carry state of the ALU. 322697883Sgibbs */ 322797883Sgibbsregister FLAGS { 322897883Sgibbs address 0x0D8 322997883Sgibbs access_mode RO 3230102681Sgibbs field ZERO 0x02 3231102681Sgibbs field CARRY 0x01 323297883Sgibbs} 323397883Sgibbs 323497883Sgibbs/* 323597883Sgibbs * Sequencer Interrupt Control 323697883Sgibbs */ 323797883Sgibbsregister SEQINTCTL { 323897883Sgibbs address 0x0D9 323997883Sgibbs access_mode RW 3240102681Sgibbs field INTVEC1DSL 0x80 3241102681Sgibbs field INT1_CONTEXT 0x20 3242102681Sgibbs field SCS_SEQ_INT1M1 0x10 3243102681Sgibbs field SCS_SEQ_INT1M0 0x08 3244109588Sgibbs field INTMASK2 0x04 3245109588Sgibbs field INTMASK1 0x02 3246102681Sgibbs field IRET 0x01 324797883Sgibbs} 324897883Sgibbs 324997883Sgibbs/* 325097883Sgibbs * Sequencer RAM Data Port 325197883Sgibbs * Single byte window into the Sequencer Instruction Ram area starting 325297883Sgibbs * at the address specified by OVLYADDR. To write a full instruction word, 325397883Sgibbs * simply write four bytes in succession. OVLYADDR will increment after the 325497883Sgibbs * most significant instrution byte (the byte with the parity bit) is written. 325597883Sgibbs */ 325697883Sgibbsregister SEQRAM { 325797883Sgibbs address 0x0DA 325897883Sgibbs access_mode RW 325997883Sgibbs} 326097883Sgibbs 326197883Sgibbs/* 326297883Sgibbs * Sequencer Program Counter 326397883Sgibbs * Low byte must be written prior to high byte. 326497883Sgibbs */ 326597883Sgibbsregister PRGMCNT { 326697883Sgibbs address 0x0DE 326797883Sgibbs access_mode RW 326897883Sgibbs size 2 326997883Sgibbs} 327097883Sgibbs 327197883Sgibbs/* 327297883Sgibbs * Accumulator 327397883Sgibbs */ 327497883Sgibbsregister ACCUM { 327597883Sgibbs address 0x0E0 327697883Sgibbs access_mode RW 327797883Sgibbs accumulator 327897883Sgibbs} 327997883Sgibbs 328097883Sgibbs/* 328197883Sgibbs * Source Index Register 328297883Sgibbs * Incrementing index for reads of SINDIR and the destination (low byte only) 328397883Sgibbs * for any immediate operands passed in jmp, jc, jnc, call instructions. 328497883Sgibbs * Example: 328597883Sgibbs * mvi 0xFF call some_routine; 328697883Sgibbs * 328797883Sgibbs * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 328897883Sgibbs */ 328997883Sgibbsregister SINDEX { 329097883Sgibbs address 0x0E2 329197883Sgibbs access_mode RW 329297883Sgibbs size 2 329397883Sgibbs sindex 329497883Sgibbs} 329597883Sgibbs 329697883Sgibbs/* 329797883Sgibbs * Destination Index Register 329897883Sgibbs * Incrementing index for writes to DINDIR. Can be used as a scratch register. 329997883Sgibbs */ 330097883Sgibbsregister DINDEX { 330197883Sgibbs address 0x0E4 330297883Sgibbs access_mode RW 330397883Sgibbs size 2 330497883Sgibbs} 330597883Sgibbs 330697883Sgibbs/* 330797883Sgibbs * Break Address 330897883Sgibbs * Sequencer instruction breakpoint address address. 330997883Sgibbs */ 331097883Sgibbsregister BRKADDR0 { 331197883Sgibbs address 0x0E6 331297883Sgibbs access_mode RW 331397883Sgibbs} 331497883Sgibbs 331597883Sgibbsregister BRKADDR1 { 331697883Sgibbs address 0x0E6 331797883Sgibbs access_mode RW 3318102681Sgibbs field BRKDIS 0x80 /* Disable Breakpoint */ 331997883Sgibbs} 332097883Sgibbs 332197883Sgibbs/* 332297883Sgibbs * All Ones 332397883Sgibbs * All reads to this register return the value 0xFF. 332497883Sgibbs */ 332597883Sgibbsregister ALLONES { 332697883Sgibbs address 0x0E8 332797883Sgibbs access_mode RO 332897883Sgibbs allones 332997883Sgibbs} 333097883Sgibbs 333197883Sgibbs/* 333297883Sgibbs * All Zeros 333397883Sgibbs * All reads to this register return the value 0. 333497883Sgibbs */ 333597883Sgibbsregister ALLZEROS { 333697883Sgibbs address 0x0EA 333797883Sgibbs access_mode RO 333897883Sgibbs allzeros 333997883Sgibbs} 334097883Sgibbs 334197883Sgibbs/* 334297883Sgibbs * No Destination 334397883Sgibbs * Writes to this register have no effect. 334497883Sgibbs */ 334597883Sgibbsregister NONE { 334697883Sgibbs address 0x0EA 334797883Sgibbs access_mode WO 334897883Sgibbs none 334997883Sgibbs} 335097883Sgibbs 335197883Sgibbs/* 335297883Sgibbs * Source Index Indirect 335397883Sgibbs * Reading this register is equivalent to reading (register_base + SINDEX) and 335497883Sgibbs * incrementing SINDEX by 1. 335597883Sgibbs */ 335697883Sgibbsregister SINDIR { 335797883Sgibbs address 0x0EC 335897883Sgibbs access_mode RO 335997883Sgibbs} 336097883Sgibbs 336197883Sgibbs/* 336297883Sgibbs * Destination Index Indirect 336397883Sgibbs * Writing this register is equivalent to writing to (register_base + DINDEX) 336497883Sgibbs * and incrementing DINDEX by 1. 336597883Sgibbs */ 336697883Sgibbsregister DINDIR { 336797883Sgibbs address 0x0ED 336897883Sgibbs access_mode WO 336997883Sgibbs} 337097883Sgibbs 337197883Sgibbs/* 337297883Sgibbs * Function One 337397883Sgibbs * 2's complement to bit value conversion. Write the 2's complement value 337497883Sgibbs * (0-7 only) to the top nibble and retrieve the bit indexed by that value 337597883Sgibbs * on the next read of this register. 337697883Sgibbs * Example: 337797883Sgibbs * Write 0x60 337897883Sgibbs * Read 0x40 337997883Sgibbs */ 338097883Sgibbsregister FUNCTION1 { 338197883Sgibbs address 0x0F0 338297883Sgibbs access_mode RW 338397883Sgibbs} 338497883Sgibbs 338597883Sgibbs/* 338697883Sgibbs * Stack 338797883Sgibbs * Window into the stack. Each stack location is 10 bits wide reported 338897883Sgibbs * low byte followed by high byte. There are 8 stack locations. 338997883Sgibbs */ 339097883Sgibbsregister STACK { 339197883Sgibbs address 0x0F2 339297883Sgibbs access_mode RW 339397883Sgibbs} 339497883Sgibbs 339597883Sgibbs/* 339697883Sgibbs * Interrupt Vector 1 Address 339797883Sgibbs * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 339897883Sgibbs */ 339997883Sgibbsregister INTVEC1_ADDR { 340097883Sgibbs address 0x0F4 340197883Sgibbs access_mode RW 340297883Sgibbs size 2 340397883Sgibbs modes M_CFG 340497883Sgibbs} 340597883Sgibbs 340697883Sgibbs/* 340797883Sgibbs * Current Address 340897883Sgibbs * Address of the SEQRAM instruction currently executing instruction. 340997883Sgibbs */ 341097883Sgibbsregister CURADDR { 341197883Sgibbs address 0x0F4 341297883Sgibbs access_mode RW 341397883Sgibbs size 2 341497883Sgibbs modes M_SCSI 341597883Sgibbs} 341697883Sgibbs 341797883Sgibbs/* 341897883Sgibbs * Interrupt Vector 2 Address 341997883Sgibbs * Interrupt branch address for HST_SEQ_INT2 interrupts. 342097883Sgibbs */ 342197883Sgibbsregister INTVEC2_ADDR { 342297883Sgibbs address 0x0F6 342397883Sgibbs access_mode RW 342497883Sgibbs size 2 342597883Sgibbs modes M_CFG 342697883Sgibbs} 342797883Sgibbs 342897883Sgibbs/* 342997883Sgibbs * Last Address 343097883Sgibbs * Address of the SEQRAM instruction executed prior to the current instruction. 343197883Sgibbs */ 343297883Sgibbsregister LASTADDR { 343397883Sgibbs address 0x0F6 343497883Sgibbs access_mode RW 343597883Sgibbs size 2 343697883Sgibbs modes M_SCSI 343797883Sgibbs} 343897883Sgibbs 343997883Sgibbsregister AHD_PCI_CONFIG_BASE { 344097883Sgibbs address 0x100 344197883Sgibbs access_mode RW 344297883Sgibbs size 256 344397883Sgibbs modes M_CFG 344497883Sgibbs} 344597883Sgibbs 344697883Sgibbs/* ---------------------- Scratch RAM Offsets ------------------------- */ 344797883Sgibbsscratch_ram { 344897883Sgibbs /* Mode Specific */ 344997883Sgibbs address 0x0A0 345097883Sgibbs size 8 345197883Sgibbs modes 0, 1, 2, 3 345297883Sgibbs REG0 { 345397883Sgibbs size 2 345497883Sgibbs } 345597883Sgibbs REG1 { 345697883Sgibbs size 2 345797883Sgibbs } 3458104023Sgibbs REG_ISR { 345997883Sgibbs size 2 346097883Sgibbs } 346197883Sgibbs SG_STATE { 346297883Sgibbs size 1 3463102681Sgibbs field SEGS_AVAIL 0x01 3464102681Sgibbs field LOADING_NEEDED 0x02 3465102681Sgibbs field FETCH_INPROG 0x04 346697883Sgibbs } 346797883Sgibbs /* 346897883Sgibbs * Track whether the transfer byte count for 346997883Sgibbs * the current data phase is odd. 347097883Sgibbs */ 347197883Sgibbs DATA_COUNT_ODD { 347297883Sgibbs size 1 347397883Sgibbs } 347497883Sgibbs} 347597883Sgibbs 347697883Sgibbsscratch_ram { 347797883Sgibbs /* Mode Specific */ 347897883Sgibbs address 0x0F8 347997883Sgibbs size 8 348097883Sgibbs modes 0, 1, 2, 3 348197883Sgibbs LONGJMP_ADDR { 348297883Sgibbs size 2 348397883Sgibbs } 348497883Sgibbs ACCUM_SAVE { 348597883Sgibbs size 1 348697883Sgibbs } 348797883Sgibbs} 348897883Sgibbs 348997883Sgibbs 349097883Sgibbsscratch_ram { 349197883Sgibbs address 0x100 349297883Sgibbs size 128 349397883Sgibbs modes 0, 1, 2, 3 349497883Sgibbs /* 349597883Sgibbs * Per "other-id" execution queues. We use an array of 349697883Sgibbs * tail pointers into lists of SCBs sorted by "other-id". 349797883Sgibbs * The execution head pointer threads the head SCBs for 349897883Sgibbs * each list. 349997883Sgibbs */ 350097883Sgibbs WAITING_SCB_TAILS { 350197883Sgibbs size 32 350297883Sgibbs } 350397883Sgibbs WAITING_TID_HEAD { 350497883Sgibbs size 2 350597883Sgibbs } 350697883Sgibbs WAITING_TID_TAIL { 350797883Sgibbs size 2 350897883Sgibbs } 350997883Sgibbs /* 351097883Sgibbs * SCBID of the next SCB in the new SCB queue. 351197883Sgibbs */ 351297883Sgibbs NEXT_QUEUED_SCB_ADDR { 351397883Sgibbs size 4 351497883Sgibbs } 351597883Sgibbs /* 351697883Sgibbs * head of list of SCBs that have 351797883Sgibbs * completed but have not been 351897883Sgibbs * put into the qoutfifo. 351997883Sgibbs */ 352097883Sgibbs COMPLETE_SCB_HEAD { 352197883Sgibbs size 2 352297883Sgibbs } 352397883Sgibbs /* 352497883Sgibbs * The list of completed SCBs in 352597883Sgibbs * the active DMA. 352697883Sgibbs */ 352797883Sgibbs COMPLETE_SCB_DMAINPROG_HEAD { 352897883Sgibbs size 2 352997883Sgibbs } 353097883Sgibbs /* 353197883Sgibbs * head of list of SCBs that have 353297883Sgibbs * completed but need to be uploaded 353397883Sgibbs * to the host prior to being completed. 353497883Sgibbs */ 353597883Sgibbs COMPLETE_DMA_SCB_HEAD { 353697883Sgibbs size 2 353797883Sgibbs } 3538125448Sgibbs /* 3539125448Sgibbs * tail of list of SCBs that have 3540125448Sgibbs * completed but need to be uploaded 3541125448Sgibbs * to the host prior to being completed. 3542125448Sgibbs */ 3543125448Sgibbs COMPLETE_DMA_SCB_TAIL { 3544125448Sgibbs size 2 3545125448Sgibbs } 3546125448Sgibbs /* 3547125448Sgibbs * head of list of SCBs that have 3548125448Sgibbs * been uploaded to the host, but cannot 3549125448Sgibbs * be completed until the QFREEZE is in 3550125448Sgibbs * full effect (i.e. no selections pending). 3551125448Sgibbs */ 3552125448Sgibbs COMPLETE_ON_QFREEZE_HEAD { 3553125448Sgibbs size 2 3554125448Sgibbs } 3555125448Sgibbs /* 3556125448Sgibbs * Counting semaphore to prevent new select-outs 3557125448Sgibbs * The queue is frozen so long as the sequencer 3558125448Sgibbs * and kernel freeze counts differ. 3559125448Sgibbs */ 356097883Sgibbs QFREEZE_COUNT { 356197883Sgibbs size 2 356297883Sgibbs } 3563125448Sgibbs KERNEL_QFREEZE_COUNT { 3564125448Sgibbs size 2 3565125448Sgibbs } 356697883Sgibbs /* 3567107441Sscottl * Mode to restore on legacy idle loop exit. 356897883Sgibbs */ 356997883Sgibbs SAVED_MODE { 357097883Sgibbs size 1 357197883Sgibbs } 357297883Sgibbs /* 357397883Sgibbs * Single byte buffer used to designate the type or message 357497883Sgibbs * to send to a target. 357597883Sgibbs */ 357697883Sgibbs MSG_OUT { 357797883Sgibbs size 1 357897883Sgibbs } 357997883Sgibbs /* Parameters for DMA Logic */ 358097883Sgibbs DMAPARAMS { 358197883Sgibbs size 1 3582102681Sgibbs field PRELOADEN 0x80 3583102681Sgibbs field WIDEODD 0x40 3584102681Sgibbs field SCSIEN 0x20 3585102681Sgibbs field SDMAEN 0x10 3586102681Sgibbs field SDMAENACK 0x10 3587102681Sgibbs field HDMAEN 0x08 3588102681Sgibbs field HDMAENACK 0x08 3589102681Sgibbs field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3590102681Sgibbs field FIFOFLUSH 0x02 3591102681Sgibbs field FIFORESET 0x01 359297883Sgibbs } 359397883Sgibbs SEQ_FLAGS { 359497883Sgibbs size 1 3595102681Sgibbs field NOT_IDENTIFIED 0x80 3596104023Sgibbs field NO_CDB_SENT 0x40 3597102681Sgibbs field TARGET_CMD_IS_TAGGED 0x40 3598102681Sgibbs field DPHASE 0x20 359997883Sgibbs /* Target flags */ 3600102681Sgibbs field TARG_CMD_PENDING 0x10 3601102681Sgibbs field CMDPHASE_PENDING 0x08 3602102681Sgibbs field DPHASE_PENDING 0x04 3603102681Sgibbs field SPHASE_PENDING 0x02 3604102681Sgibbs field NO_DISCONNECT 0x01 360597883Sgibbs } 360697883Sgibbs /* 360797883Sgibbs * Temporary storage for the 360897883Sgibbs * target/channel/lun of a 360997883Sgibbs * reconnecting target 361097883Sgibbs */ 361197883Sgibbs SAVED_SCSIID { 361297883Sgibbs size 1 361397883Sgibbs } 361497883Sgibbs SAVED_LUN { 361597883Sgibbs size 1 361697883Sgibbs } 361797883Sgibbs /* 361897883Sgibbs * The last bus phase as seen by the sequencer. 361997883Sgibbs */ 362097883Sgibbs LASTPHASE { 362197883Sgibbs size 1 3622102681Sgibbs field CDI 0x80 3623102681Sgibbs field IOI 0x40 3624102681Sgibbs field MSGI 0x20 3625104023Sgibbs field P_BUSFREE 0x01 3626102681Sgibbs enum PHASE_MASK CDO|IOO|MSGO { 3627102681Sgibbs P_DATAOUT 0x0, 3628102681Sgibbs P_DATAIN IOO, 3629102681Sgibbs P_DATAOUT_DT P_DATAOUT|MSGO, 3630102681Sgibbs P_DATAIN_DT P_DATAIN|MSGO, 3631102681Sgibbs P_COMMAND CDO, 3632102681Sgibbs P_MESGOUT CDO|MSGO, 3633102681Sgibbs P_STATUS CDO|IOO, 3634104023Sgibbs P_MESGIN CDO|IOO|MSGO 3635102681Sgibbs } 363697883Sgibbs } 363797883Sgibbs /* 3638107441Sscottl * Value to "or" into the SCBPTR[1] value to 3639107441Sscottl * indicate that an entry in the QINFIFO is valid. 3640107441Sscottl */ 3641107441Sscottl QOUTFIFO_ENTRY_VALID_TAG { 3642107441Sscottl size 1 3643107441Sscottl } 3644107441Sscottl /* 3645125448Sgibbs * Kernel and sequencer offsets into the queue of 3646125448Sgibbs * incoming target mode command descriptors. The 3647125448Sgibbs * queue is full when the KERNEL_TQINPOS == TQINPOS. 3648125448Sgibbs */ 3649125448Sgibbs KERNEL_TQINPOS { 3650125448Sgibbs size 1 3651125448Sgibbs } 3652125448Sgibbs TQINPOS { 3653125448Sgibbs size 1 3654125448Sgibbs } 3655125448Sgibbs /* 365697883Sgibbs * Base address of our shared data with the kernel driver in host 365797883Sgibbs * memory. This includes the qoutfifo and target mode 365897883Sgibbs * incoming command queue. 365997883Sgibbs */ 366097883Sgibbs SHARED_DATA_ADDR { 366197883Sgibbs size 4 366297883Sgibbs } 366397883Sgibbs /* 366497883Sgibbs * Pointer to location in host memory for next 366597883Sgibbs * position in the qoutfifo. 366697883Sgibbs */ 366797883Sgibbs QOUTFIFO_NEXT_ADDR { 366897883Sgibbs size 4 366997883Sgibbs } 367097883Sgibbs ARG_1 { 367197883Sgibbs size 1 367297883Sgibbs mask SEND_MSG 0x80 367397883Sgibbs mask SEND_SENSE 0x40 367497883Sgibbs mask SEND_REJ 0x20 367597883Sgibbs mask MSGOUT_PHASEMIS 0x10 367697883Sgibbs mask EXIT_MSG_LOOP 0x08 367797883Sgibbs mask CONT_MSG_LOOP_WRITE 0x04 367897883Sgibbs mask CONT_MSG_LOOP_READ 0x03 367997883Sgibbs mask CONT_MSG_LOOP_TARG 0x02 368097883Sgibbs alias RETURN_1 368197883Sgibbs } 368297883Sgibbs ARG_2 { 368397883Sgibbs size 1 368497883Sgibbs alias RETURN_2 368597883Sgibbs } 368697883Sgibbs 368797883Sgibbs /* 368897883Sgibbs * Snapshot of MSG_OUT taken after each message is sent. 368997883Sgibbs */ 369097883Sgibbs LAST_MSG { 369197883Sgibbs size 1 369297883Sgibbs } 369397883Sgibbs 369497883Sgibbs /* 369597883Sgibbs * Sequences the kernel driver has okayed for us. This allows 369697883Sgibbs * the driver to do things like prevent initiator or target 369797883Sgibbs * operations. 369897883Sgibbs */ 369997883Sgibbs SCSISEQ_TEMPLATE { 370097883Sgibbs size 1 3701102681Sgibbs field MANUALCTL 0x40 3702102681Sgibbs field ENSELI 0x20 3703102681Sgibbs field ENRSELI 0x10 3704102681Sgibbs field MANUALP 0x0C 3705102681Sgibbs field ENAUTOATNP 0x02 3706102681Sgibbs field ALTSTIM 0x01 370797883Sgibbs } 370897883Sgibbs 370997883Sgibbs /* 371097883Sgibbs * The initiator specified tag for this target mode transaction. 371197883Sgibbs */ 371297883Sgibbs INITIATOR_TAG { 371397883Sgibbs size 1 371497883Sgibbs } 371597883Sgibbs 371697883Sgibbs SEQ_FLAGS2 { 371797883Sgibbs size 1 3718133122Sgibbs field PENDING_MK_MESSAGE 0x01 3719133122Sgibbs field TARGET_MSG_PENDING 0x02 3720133122Sgibbs field SELECTOUT_QFROZEN 0x04 372197883Sgibbs } 3722104023Sgibbs 3723104023Sgibbs ALLOCFIFO_SCBPTR { 3724104023Sgibbs size 2 3725104023Sgibbs } 3726104023Sgibbs 372797883Sgibbs /* 3728115329Sgibbs * The maximum amount of time to wait, when interrupt coalescing 3729299375Spfg * is enabled, before issuing a CMDCMPLT interrupt for a completed 3730109588Sgibbs * command. 3731109588Sgibbs */ 3732115329Sgibbs INT_COALESCING_TIMER { 3733109588Sgibbs size 2 3734109588Sgibbs } 3735109588Sgibbs 3736109588Sgibbs /* 3737115329Sgibbs * The maximum number of commands to coalesce into a single interrupt. 3738109588Sgibbs * Actually the 2's complement of that value to simplify sequencer 3739109588Sgibbs * code. 3740109588Sgibbs */ 3741115329Sgibbs INT_COALESCING_MAXCMDS { 3742109588Sgibbs size 1 3743109588Sgibbs } 3744109588Sgibbs 3745109588Sgibbs /* 3746109588Sgibbs * The minimum number of commands still outstanding required 3747115329Sgibbs * to continue coalescing (2's complement of value). 3748109588Sgibbs */ 3749115329Sgibbs INT_COALESCING_MINCMDS { 3750109588Sgibbs size 1 3751109588Sgibbs } 3752109588Sgibbs 3753109588Sgibbs /* 3754109588Sgibbs * Number of commands "in-flight". 3755109588Sgibbs */ 3756109588Sgibbs CMDS_PENDING { 3757109588Sgibbs size 2 3758109588Sgibbs } 3759109588Sgibbs 3760109588Sgibbs /* 3761115329Sgibbs * The count of commands that have been coalesced. 3762109588Sgibbs */ 3763115329Sgibbs INT_COALESCING_CMDCOUNT { 3764109588Sgibbs size 1 3765109588Sgibbs } 3766109588Sgibbs 3767109588Sgibbs /* 3768109588Sgibbs * Since the HS_MAIBOX is self clearing, copy its contents to 3769109588Sgibbs * this position in scratch ram every time it changes. 3770109588Sgibbs */ 3771109588Sgibbs LOCAL_HS_MAILBOX { 3772109588Sgibbs size 1 3773109588Sgibbs } 3774109588Sgibbs /* 377597883Sgibbs * Target-mode CDB type to CDB length table used 377697883Sgibbs * in non-packetized operation. 377797883Sgibbs */ 377897883Sgibbs CMDSIZE_TABLE { 377997883Sgibbs size 8 378097883Sgibbs } 3781133122Sgibbs /* 3782133122Sgibbs * When an SCB with the MK_MESSAGE flag is 3783133122Sgibbs * queued to the controller, it cannot enter 3784133122Sgibbs * the waiting for selection list until the 3785133122Sgibbs * selections for any previously queued 3786133122Sgibbs * commands to that target complete. During 3787133122Sgibbs * the wait, the MK_MESSAGE SCB is queued 3788133122Sgibbs * here. 3789133122Sgibbs */ 3790133122Sgibbs MK_MESSAGE_SCB { 3791133122Sgibbs size 2 3792133122Sgibbs } 3793133122Sgibbs /* 3794133122Sgibbs * Saved SCSIID of MK_MESSAGE_SCB to avoid 3795133122Sgibbs * an extra SCBPTR operation when deciding 3796133122Sgibbs * if the MK_MESSAGE_SCB can be run. 3797133122Sgibbs */ 3798133122Sgibbs MK_MESSAGE_SCSIID { 3799133122Sgibbs size 1 3800133122Sgibbs } 380197883Sgibbs} 380297883Sgibbs 380397883Sgibbs/************************* Hardware SCB Definition ****************************/ 380497883Sgibbsscb { 380597883Sgibbs address 0x180 380697883Sgibbs size 64 380797883Sgibbs modes 0, 1, 2, 3 380897883Sgibbs SCB_RESIDUAL_DATACNT { 380997883Sgibbs size 4 381097883Sgibbs alias SCB_CDB_STORE 3811111653Sgibbs alias SCB_HOST_CDB_PTR 381297883Sgibbs } 381397883Sgibbs SCB_RESIDUAL_SGPTR { 381497883Sgibbs size 4 3815102681Sgibbs field SG_ADDR_MASK 0xf8 /* In the last byte */ 3816210055Sgibbs field SG_ADDR_BIT 0x04 3817102681Sgibbs field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3818102681Sgibbs field SG_LIST_NULL 0x01 /* In the first byte */ 381997883Sgibbs } 382097883Sgibbs SCB_SCSI_STATUS { 382197883Sgibbs size 1 3822111653Sgibbs alias SCB_HOST_CDB_LEN 382397883Sgibbs } 382497883Sgibbs SCB_TARGET_PHASES { 382597883Sgibbs size 1 382697883Sgibbs } 382797883Sgibbs SCB_TARGET_DATA_DIR { 382897883Sgibbs size 1 382997883Sgibbs } 383097883Sgibbs SCB_TARGET_ITAG { 383197883Sgibbs size 1 383297883Sgibbs } 383397883Sgibbs SCB_SENSE_BUSADDR { 383497883Sgibbs /* 383597883Sgibbs * Only valid if CDB length is less than 13 bytes or 383697883Sgibbs * we are using a CDB pointer. Otherwise contains 383797883Sgibbs * the last 4 bytes of embedded cdb information. 383897883Sgibbs */ 383997883Sgibbs size 4 384097883Sgibbs alias SCB_NEXT_COMPLETE 384197883Sgibbs } 3842115407Sscottl SCB_TAG { 3843115407Sscottl alias SCB_FIFO_USE_COUNT 3844114623Sgibbs size 2 3845114623Sgibbs } 384697883Sgibbs SCB_CONTROL { 384797883Sgibbs size 1 3848102681Sgibbs field TARGET_SCB 0x80 3849102681Sgibbs field DISCENB 0x40 3850102681Sgibbs field TAG_ENB 0x20 3851102681Sgibbs field MK_MESSAGE 0x10 3852102681Sgibbs field STATUS_RCVD 0x08 3853102681Sgibbs field DISCONNECTED 0x04 3854102681Sgibbs field SCB_TAG_TYPE 0x03 385597883Sgibbs } 385697883Sgibbs SCB_SCSIID { 385797883Sgibbs size 1 3858102681Sgibbs field TID 0xF0 3859102681Sgibbs field OID 0x0F 386097883Sgibbs } 386197883Sgibbs SCB_LUN { 386297883Sgibbs size 1 3863115335Sgibbs field LID 0xff 386497883Sgibbs } 386597883Sgibbs SCB_TASK_ATTRIBUTE { 386697883Sgibbs size 1 3867115335Sgibbs /* 3868115335Sgibbs * Overloaded field for non-packetized 3869115335Sgibbs * ignore wide residue message handling. 3870115335Sgibbs */ 3871115335Sgibbs field SCB_XFERLEN_ODD 0x01 387297883Sgibbs } 3873114623Sgibbs SCB_CDB_LEN { 3874114623Sgibbs size 1 3875114623Sgibbs field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 387697883Sgibbs } 3877114623Sgibbs SCB_TASK_MANAGEMENT { 3878114623Sgibbs size 1 3879114623Sgibbs } 3880115407Sscottl SCB_DATAPTR { 3881115407Sscottl size 8 3882115407Sscottl } 3883115407Sscottl SCB_DATACNT { 3884115407Sscottl /* 3885115407Sscottl * The last byte is really the high address bits for 3886115407Sscottl * the data address. 3887115407Sscottl */ 3888115407Sscottl size 4 3889115407Sscottl field SG_LAST_SEG 0x80 /* In the fourth byte */ 3890115407Sscottl field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3891115407Sscottl } 3892115407Sscottl SCB_SGPTR { 3893115407Sscottl size 4 3894115407Sscottl field SG_STATUS_VALID 0x04 /* In the first byte */ 3895115407Sscottl field SG_FULL_RESID 0x02 /* In the first byte */ 3896115407Sscottl field SG_LIST_NULL 0x01 /* In the first byte */ 3897115407Sscottl } 3898115407Sscottl SCB_BUSADDR { 3899115407Sscottl size 4 3900115407Sscottl } 3901115407Sscottl SCB_NEXT { 3902115407Sscottl alias SCB_NEXT_SCB_BUSADDR 3903114623Sgibbs size 2 3904114623Sgibbs } 3905115407Sscottl SCB_NEXT2 { 3906115407Sscottl size 2 3907115407Sscottl } 3908102681Sgibbs SCB_SPARE { 3909102681Sgibbs size 8 3910102681Sgibbs alias SCB_PKT_LUN 3911102681Sgibbs } 391297883Sgibbs SCB_DISCONNECTED_LISTS { 3913102681Sgibbs size 8 391497883Sgibbs } 391597883Sgibbs} 391697883Sgibbs 391797883Sgibbs/*********************************** Constants ********************************/ 391897883Sgibbsconst MK_MESSAGE_BIT_OFFSET 4 391997883Sgibbsconst TID_SHIFT 4 392097883Sgibbsconst TARGET_CMD_CMPLT 0xfe 392197883Sgibbsconst INVALID_ADDR 0x80 392297883Sgibbs#define SCB_LIST_NULL 0xff 3923102681Sgibbs#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 392497883Sgibbs 392597883Sgibbsconst CCSGADDR_MAX 0x80 392697883Sgibbsconst CCSCBADDR_MAX 0x80 392797883Sgibbsconst CCSGRAM_MAXSEGS 16 392897883Sgibbs 392997883Sgibbs/* Selection Timeout Timer Constants */ 393097883Sgibbsconst STIMESEL_SHIFT 3 393197883Sgibbsconst STIMESEL_MIN 0x18 393297883Sgibbsconst STIMESEL_BUG_ADJ 0x8 393397883Sgibbs 393497883Sgibbs/* WDTR Message values */ 393597883Sgibbsconst BUS_8_BIT 0x00 393697883Sgibbsconst BUS_16_BIT 0x01 393797883Sgibbsconst BUS_32_BIT 0x02 393897883Sgibbs 393997883Sgibbs/* Offset maximums */ 394097883Sgibbsconst MAX_OFFSET 0xfe 3941107441Sscottlconst MAX_OFFSET_PACED 0xfe 3942107441Sscottlconst MAX_OFFSET_PACED_BUG 0x7f 3943107441Sscottl/* 3944107441Sscottl * Some 160 devices incorrectly accept 0xfe as a 3945107441Sscottl * sync offset, but will overrun this value. Limit 3946107441Sscottl * to 0x7f for speed lower than U320 which will 3947107441Sscottl * avoid the persistent sync offset overruns. 3948107441Sscottl */ 3949107441Sscottlconst MAX_OFFSET_NON_PACED 0x7f 395097883Sgibbsconst HOST_MSG 0xff 395197883Sgibbs 395297883Sgibbs/* 395397883Sgibbs * The size of our sense buffers. 395497883Sgibbs * Sense buffer mapping can be handled in either of two ways. 395597883Sgibbs * The first is to allocate a dmamap for each transaction. 395697883Sgibbs * Depending on the architecture, dmamaps can be costly. The 395797883Sgibbs * alternative is to statically map the buffers in much the same 395897883Sgibbs * way we handle our scatter gather lists. The driver implements 395997883Sgibbs * the later. 396097883Sgibbs */ 396197883Sgibbsconst AHD_SENSE_BUFSIZE 256 396297883Sgibbs 396397883Sgibbs/* Target mode command processing constants */ 396497883Sgibbsconst CMD_GROUP_CODE_SHIFT 0x05 396597883Sgibbs 396697883Sgibbsconst STATUS_BUSY 0x08 396797883Sgibbsconst STATUS_QUEUE_FULL 0x28 396897883Sgibbsconst STATUS_PKT_SENSE 0xFF 396997883Sgibbsconst TARGET_DATA_IN 1 397097883Sgibbs 3971102681Sgibbsconst SCB_TRANSFER_SIZE_FULL_LUN 56 3972102681Sgibbsconst SCB_TRANSFER_SIZE_1BYTE_LUN 48 397397883Sgibbs/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 397497883Sgibbsconst PKT_OVERRUN_BUFSIZE 512 397597883Sgibbs 397697883Sgibbs/* 3977109588Sgibbs * Timer parameters. 3978109588Sgibbs */ 3979109588Sgibbsconst AHD_TIMER_US_PER_TICK 25 3980109588Sgibbsconst AHD_TIMER_MAX_TICKS 0xFFFF 3981109709Sgibbsconst AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) 3982109588Sgibbs 3983109588Sgibbs/* 398497883Sgibbs * Downloaded (kernel inserted) constants 398597883Sgibbs */ 398697883Sgibbsconst SG_PREFETCH_CNT download 398797883Sgibbsconst SG_PREFETCH_CNT_LIMIT download 398897883Sgibbsconst SG_PREFETCH_ALIGN_MASK download 398997883Sgibbsconst SG_PREFETCH_ADDR_MASK download 399097883Sgibbsconst SG_SIZEOF download 399197883Sgibbsconst PKT_OVERRUN_BUFOFFSET download 3992102681Sgibbsconst SCB_TRANSFER_SIZE download 3993129134Sgibbsconst CACHELINE_MASK download 399497883Sgibbs 399597883Sgibbs/* 399697883Sgibbs * BIOS SCB offsets 399797883Sgibbs */ 399897883Sgibbsconst NVRAM_SCB_OFFSET 0x2C 3999