aic79xx.h revision 133122
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 133122 2004-08-04 17:55:34Z gibbs $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x80 79#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 80 81#define SCSIID_TARGET(ahd, scsiid) \ 82 (((scsiid) & TID) >> TID_SHIFT) 83#define SCSIID_OUR_ID(scsiid) \ 84 ((scsiid) & OID) 85#define SCSIID_CHANNEL(ahd, scsiid) ('A') 86#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 87#define SCB_GET_OUR_ID(scb) \ 88 SCSIID_OUR_ID((scb)->hscb->scsiid) 89#define SCB_GET_TARGET(ahd, scb) \ 90 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 91#define SCB_GET_CHANNEL(ahd, scb) \ 92 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 93#define SCB_GET_LUN(scb) \ 94 ((scb)->hscb->lun) 95#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 96 SCB_GET_TARGET(ahd, scb) 97#define SCB_GET_TARGET_MASK(ahd, scb) \ 98 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 99#ifdef AHD_DEBUG 100#define SCB_IS_SILENT(scb) \ 101 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 102 && (((scb)->flags & SCB_SILENT) != 0)) 103#else 104#define SCB_IS_SILENT(scb) \ 105 (((scb)->flags & SCB_SILENT) != 0) 106#endif 107/* 108 * TCLs have the following format: TTTTLLLLLLLL 109 */ 110#define TCL_TARGET_OFFSET(tcl) \ 111 ((((tcl) >> 4) & TID) >> 4) 112#define TCL_LUN(tcl) \ 113 (tcl & (AHD_NUM_LUNS - 1)) 114#define BUILD_TCL(scsiid, lun) \ 115 ((lun) | (((scsiid) & TID) << 4)) 116#define BUILD_TCL_RAW(target, channel, lun) \ 117 ((lun) | ((target) << 8)) 118 119#define SCB_GET_TAG(scb) \ 120 aic_le16toh(scb->hscb->tag) 121 122#ifndef AHD_TARGET_MODE 123#undef AHD_TMODE_ENABLE 124#define AHD_TMODE_ENABLE 0 125#endif 126 127#define AHD_BUILD_COL_IDX(target, lun) \ 128 (((lun) << 4) | target) 129 130#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 131 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 132 133#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 134do { \ 135 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 136 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 137} while (0) 138 139#define AHD_COPY_SCB_COL_IDX(dst, src) \ 140do { \ 141 dst->hscb->scsiid = src->hscb->scsiid; \ 142 dst->hscb->lun = src->hscb->lun; \ 143} while (0) 144 145#define AHD_NEVER_COL_IDX 0xFFFF 146 147/**************************** Driver Constants ********************************/ 148/* 149 * The maximum number of supported targets. 150 */ 151#define AHD_NUM_TARGETS 16 152 153/* 154 * The maximum number of supported luns. 155 * The identify message only supports 64 luns in non-packetized transfers. 156 * You can have 2^64 luns when information unit transfers are enabled, 157 * but until we see a need to support that many, we support 256. 158 */ 159#define AHD_NUM_LUNS_NONPKT 64 160#define AHD_NUM_LUNS 256 161 162/* 163 * The maximum transfer per S/G segment. 164 */ 165#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 166 167/* 168 * The maximum amount of SCB storage in hardware on a controller. 169 * This value represents an upper bound. Due to software design, 170 * we may not be able to use this number. 171 */ 172#define AHD_SCB_MAX 512 173 174/* 175 * The maximum number of concurrent transactions supported per driver instance. 176 * Sequencer Control Blocks (SCBs) store per-transaction information. 177 */ 178#define AHD_MAX_QUEUE AHD_SCB_MAX 179 180/* 181 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 182 * in size and accommodate as many transactions as can be queued concurrently. 183 */ 184#define AHD_QIN_SIZE AHD_MAX_QUEUE 185#define AHD_QOUT_SIZE AHD_MAX_QUEUE 186 187#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 188/* 189 * The maximum amount of SCB storage we allocate in host memory. 190 */ 191#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 192 193/* 194 * Ring Buffer of incoming target commands. 195 * We allocate 256 to simplify the logic in the sequencer 196 * by using the natural wrap point of an 8bit counter. 197 */ 198#define AHD_TMODE_CMDS 256 199 200/* Reset line assertion time in us */ 201#define AHD_BUSRESET_DELAY 25 202 203/******************* Chip Characteristics/Operating Settings *****************/ 204extern uint32_t ahd_attach_to_HostRAID_controllers; 205 206/* 207 * Chip Type 208 * The chip order is from least sophisticated to most sophisticated. 209 */ 210typedef enum { 211 AHD_NONE = 0x0000, 212 AHD_CHIPID_MASK = 0x00FF, 213 AHD_AIC7901 = 0x0001, 214 AHD_AIC7902 = 0x0002, 215 AHD_AIC7901A = 0x0003, 216 AHD_PCI = 0x0100, /* Bus type PCI */ 217 AHD_PCIX = 0x0200, /* Bus type PCIX */ 218 AHD_BUS_MASK = 0x0F00 219} ahd_chip; 220 221/* 222 * Features available in each chip type. 223 */ 224typedef enum { 225 AHD_FENONE = 0x00000, 226 AHD_WIDE = 0x00001,/* Wide Channel */ 227 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 228 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 229 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 230 AHD_RTI = 0x04000,/* Retained Training Support */ 231 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 232 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 233 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */ 234 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 235 AHD_AIC7901_FE = AHD_FENONE, 236 AHD_AIC7901A_FE = AHD_FENONE, 237 AHD_AIC7902_FE = AHD_MULTI_FUNC 238} ahd_feature; 239 240/* 241 * Bugs in the silicon that we work around in software. 242 */ 243typedef enum { 244 AHD_BUGNONE = 0x0000, 245 /* 246 * Rev A hardware fails to update LAST/CURR/NEXTSCB 247 * correctly in certain packetized selection cases. 248 */ 249 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 250 /* The wrong SCB is accessed to check the abort pending bit. */ 251 AHD_ABORT_LQI_BUG = 0x0002, 252 /* Packetized bitbucket crosses packet boundaries. */ 253 AHD_PKT_BITBUCKET_BUG = 0x0004, 254 /* The selection timer runs twice as long as its setting. */ 255 AHD_LONG_SETIMO_BUG = 0x0008, 256 /* The Non-LQ CRC error status is delayed until phase change. */ 257 AHD_NLQICRC_DELAYED_BUG = 0x0010, 258 /* The chip must be reset for all outgoing bus resets. */ 259 AHD_SCSIRST_BUG = 0x0020, 260 /* Some PCIX fields must be saved and restored across chip reset. */ 261 AHD_PCIX_CHIPRST_BUG = 0x0040, 262 /* MMAPIO is not functional in PCI-X mode. */ 263 AHD_PCIX_MMAPIO_BUG = 0x0080, 264 /* Reads to SCBRAM fail to reset the discard timer. */ 265 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 266 /* Bug workarounds that can be disabled on non-PCIX busses. */ 267 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 268 | AHD_PCIX_MMAPIO_BUG 269 | AHD_PCIX_SCBRAM_RD_BUG, 270 /* 271 * LQOSTOP0 status set even for forced selections with ATN 272 * to perform non-packetized message delivery. 273 */ 274 AHD_LQO_ATNO_BUG = 0x0200, 275 /* FIFO auto-flush does not always trigger. */ 276 AHD_AUTOFLUSH_BUG = 0x0400, 277 /* The CLRLQO registers are not self-clearing. */ 278 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 279 /* The PACKETIZED status bit refers to the previous connection. */ 280 AHD_PKTIZED_STATUS_BUG = 0x1000, 281 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 282 AHD_PKT_LUN_BUG = 0x2000, 283 /* 284 * Only the FIFO allocated to the non-packetized connection may 285 * be in use during a non-packetzied connection. 286 */ 287 AHD_NONPACKFIFO_BUG = 0x4000, 288 /* 289 * Writing to a DFF SCBPTR register may fail if concurent with 290 * a hardware write to the other DFF SCBPTR register. This is 291 * not currently a concern in our sequencer since all chips with 292 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 293 * occur in non-packetized connections. 294 */ 295 AHD_MDFF_WSCBPTR_BUG = 0x8000, 296 /* SGHADDR updates are slow. */ 297 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 298 /* 299 * Changing the MODE_PTR coincident with an interrupt that 300 * switches to a different mode will cause the interrupt to 301 * be in the mode written outside of interrupt context. 302 */ 303 AHD_SET_MODE_BUG = 0x20000, 304 /* Non-packetized busfree revision does not work. */ 305 AHD_BUSFREEREV_BUG = 0x40000, 306 /* 307 * Paced transfers are indicated with a non-standard PPR 308 * option bit in the neg table, 160MHz is indicated by 309 * sync factor 0x7, and the offset if off by a factor of 2. 310 */ 311 AHD_PACED_NEGTABLE_BUG = 0x80000, 312 /* LQOOVERRUN false positives. */ 313 AHD_LQOOVERRUN_BUG = 0x100000, 314 /* 315 * Controller write to INTSTAT will lose to a host 316 * write to CLRINT. 317 */ 318 AHD_INTCOLLISION_BUG = 0x200000, 319 /* 320 * The GEM318 violates the SCSI spec by not waiting 321 * the mandated bus settle delay between phase changes 322 * in some situations. Some aic79xx chip revs. are more 323 * strict in this regard and will treat REQ assertions 324 * that fall within the bus settle delay window as 325 * glitches. This flag tells the firmware to tolerate 326 * early REQ assertions. 327 */ 328 AHD_EARLY_REQ_BUG = 0x400000, 329 /* 330 * The LED does not stay on long enough in packetized modes. 331 */ 332 AHD_FAINT_LED_BUG = 0x800000 333} ahd_bug; 334 335/* 336 * Configuration specific settings. 337 * The driver determines these settings by probing the 338 * chip/controller's configuration. 339 */ 340typedef enum { 341 AHD_FNONE = 0x00000, 342 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 343 AHD_USEDEFAULTS = 0x00004,/* 344 * For cards without an seeprom 345 * or a BIOS to initialize the chip's 346 * SRAM, we use the default target 347 * settings. 348 */ 349 AHD_SEQUENCER_DEBUG = 0x00008, 350 AHD_RESET_BUS_A = 0x00010, 351 AHD_EXTENDED_TRANS_A = 0x00020, 352 AHD_TERM_ENB_A = 0x00040, 353 AHD_SPCHK_ENB_A = 0x00080, 354 AHD_STPWLEVEL_A = 0x00100, 355 AHD_INITIATORROLE = 0x00200,/* 356 * Allow initiator operations on 357 * this controller. 358 */ 359 AHD_TARGETROLE = 0x00400,/* 360 * Allow target operations on this 361 * controller. 362 */ 363 AHD_RESOURCE_SHORTAGE = 0x00800, 364 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 365 AHD_INT50_SPEEDFLEX = 0x02000,/* 366 * Internal 50pin connector 367 * sits behind an aic3860 368 */ 369 AHD_BIOS_ENABLED = 0x04000, 370 AHD_ALL_INTERRUPTS = 0x08000, 371 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 372 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 373 AHD_CURRENT_SENSING = 0x40000, 374 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 375 AHD_HP_BOARD = 0x100000, 376 AHD_RESET_POLL_ACTIVE = 0x200000, 377 AHD_UPDATE_PEND_CMDS = 0x400000, 378 AHD_RUNNING_QOUTFIFO = 0x800000, 379 AHD_HAD_FIRST_SEL = 0x1000000, 380 AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */ 381 AHD_HOSTRAID_BOARD = 0x4000000 382} ahd_flag; 383 384/************************* Hardware SCB Definition ***************************/ 385 386/* 387 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 388 * consists of a "hardware SCB" mirroring the fields available on the card 389 * and additional information the kernel stores for each transaction. 390 * 391 * To minimize space utilization, a portion of the hardware scb stores 392 * different data during different portions of a SCSI transaction. 393 * As initialized by the host driver for the initiator role, this area 394 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 395 * the cdb has been presented to the target, this area serves to store 396 * residual transfer information and the SCSI status byte. 397 * For the target role, the contents of this area do not change, but 398 * still serve a different purpose than for the initiator role. See 399 * struct target_data for details. 400 */ 401 402/* 403 * Status information embedded in the shared poriton of 404 * an SCB after passing the cdb to the target. The kernel 405 * driver will only read this data for transactions that 406 * complete abnormally. 407 */ 408struct initiator_status { 409 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 410 uint32_t residual_sgptr; /* The next S/G for this transfer */ 411 uint8_t scsi_status; /* Standard SCSI status byte */ 412}; 413 414struct target_status { 415 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 416 uint32_t residual_sgptr; /* The next S/G for this transfer */ 417 uint8_t scsi_status; /* SCSI status to give to initiator */ 418 uint8_t target_phases; /* Bitmap of phases to execute */ 419 uint8_t data_phase; /* Data-In or Data-Out */ 420 uint8_t initiator_tag; /* Initiator's transaction tag */ 421}; 422 423/* 424 * Initiator mode SCB shared data area. 425 * If the embedded CDB is 12 bytes or less, we embed 426 * the sense buffer address in the SCB. This allows 427 * us to retrieve sense information without interrupting 428 * the host in packetized mode. 429 */ 430typedef uint32_t sense_addr_t; 431#define MAX_CDB_LEN 16 432#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 433union initiator_data { 434 struct { 435 uint64_t cdbptr; 436 uint8_t cdblen; 437 } cdb_from_host; 438 uint8_t cdb[MAX_CDB_LEN]; 439 struct { 440 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 441 sense_addr_t sense_addr; 442 } cdb_plus_saddr; 443}; 444 445/* 446 * Target mode version of the shared data SCB segment. 447 */ 448struct target_data { 449 uint32_t spare[2]; 450 uint8_t scsi_status; /* SCSI status to give to initiator */ 451 uint8_t target_phases; /* Bitmap of phases to execute */ 452 uint8_t data_phase; /* Data-In or Data-Out */ 453 uint8_t initiator_tag; /* Initiator's transaction tag */ 454}; 455 456struct hardware_scb { 457/*0*/ union { 458 union initiator_data idata; 459 struct target_data tdata; 460 struct initiator_status istatus; 461 struct target_status tstatus; 462 } shared_data; 463/* 464 * A word about residuals. 465 * The scb is presented to the sequencer with the dataptr and datacnt 466 * fields initialized to the contents of the first S/G element to 467 * transfer. The sgptr field is initialized to the bus address for 468 * the S/G element that follows the first in the in core S/G array 469 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 470 * S/G entry for this transfer (single S/G element transfer with the 471 * first elements address and length preloaded in the dataptr/datacnt 472 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 473 * The SG_FULL_RESID flag ensures that the residual will be correctly 474 * noted even if no data transfers occur. Once the data phase is entered, 475 * the residual sgptr and datacnt are loaded from the sgptr and the 476 * datacnt fields. After each S/G element's dataptr and length are 477 * loaded into the hardware, the residual sgptr is advanced. After 478 * each S/G element is expired, its datacnt field is checked to see 479 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 480 * residual sg ptr and the transfer is considered complete. If the 481 * sequencer determines that there is a residual in the tranfer, or 482 * there is non-zero status, it will set the SG_STATUS_VALID flag in 483 * sgptr and dma the scb back into host memory. To sumarize: 484 * 485 * Sequencer: 486 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 487 * or residual_sgptr does not have SG_LIST_NULL set. 488 * 489 * o We are transfering the last segment if residual_datacnt has 490 * the SG_LAST_SEG flag set. 491 * 492 * Host: 493 * o A residual can only have occurred if a completed scb has the 494 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 495 * the residual_datacnt, and the residual_sgptr field will tell 496 * for sure. 497 * 498 * o residual_sgptr and sgptr refer to the "next" sg entry 499 * and so may point beyond the last valid sg entry for the 500 * transfer. 501 */ 502#define SG_PTR_MASK 0xFFFFFFF8 503/*16*/ uint16_t tag; /* Reused by Sequencer. */ 504/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 505/*19*/ uint8_t scsiid; /* 506 * Selection out Id 507 * Our Id (bits 0-3) Their ID (bits 4-7) 508 */ 509/*20*/ uint8_t lun; 510/*21*/ uint8_t task_attribute; 511/*22*/ uint8_t cdb_len; 512/*23*/ uint8_t task_management; 513/*24*/ uint64_t dataptr; 514/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 515/*36*/ uint32_t sgptr; 516/*40*/ uint32_t hscb_busaddr; 517/*44*/ uint32_t next_hscb_busaddr; 518/********** Long lun field only downloaded for full 8 byte lun support ********/ 519/*48*/ uint8_t pkt_long_lun[8]; 520/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 521/*56*/ uint8_t spare[8]; 522}; 523 524/************************ Kernel SCB Definitions ******************************/ 525/* 526 * Some fields of the SCB are OS dependent. Here we collect the 527 * definitions for elements that all OS platforms need to include 528 * in there SCB definition. 529 */ 530 531/* 532 * Definition of a scatter/gather element as transfered to the controller. 533 * The aic7xxx chips only support a 24bit length. We use the top byte of 534 * the length to store additional address bits and a flag to indicate 535 * that a given segment terminates the transfer. This gives us an 536 * addressable range of 512GB on machines with 64bit PCI or with chips 537 * that can support dual address cycles on 32bit PCI busses. 538 */ 539struct ahd_dma_seg { 540 uint32_t addr; 541 uint32_t len; 542#define AHD_DMA_LAST_SEG 0x80000000 543#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 544#define AHD_SG_LEN_MASK 0x00FFFFFF 545}; 546 547struct ahd_dma64_seg { 548 uint64_t addr; 549 uint32_t len; 550 uint32_t pad; 551}; 552 553struct map_node { 554 bus_dmamap_t dmamap; 555 bus_addr_t busaddr; 556 uint8_t *vaddr; 557 SLIST_ENTRY(map_node) links; 558}; 559 560/* 561 * The current state of this SCB. 562 */ 563typedef enum { 564 SCB_FLAG_NONE = 0x00000, 565 SCB_TRANSMISSION_ERROR = 0x00001,/* 566 * We detected a parity or CRC 567 * error that has effected the 568 * payload of the command. This 569 * flag is checked when normal 570 * status is returned to catch 571 * the case of a target not 572 * responding to our attempt 573 * to report the error. 574 */ 575 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 576 * Another device was active 577 * during the first timeout for 578 * this SCB so we gave ourselves 579 * an additional timeout period 580 * in case it was hogging the 581 * bus. 582 */ 583 SCB_DEVICE_RESET = 0x00004, 584 SCB_SENSE = 0x00008, 585 SCB_CDB32_PTR = 0x00010, 586 SCB_RECOVERY_SCB = 0x00020, 587 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 588 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 589 SCB_ABORT = 0x00100, 590 SCB_ACTIVE = 0x00200, 591 SCB_TARGET_IMMEDIATE = 0x00400, 592 SCB_PACKETIZED = 0x00800, 593 SCB_EXPECT_PPR_BUSFREE = 0x01000, 594 SCB_PKT_SENSE = 0x02000, 595 SCB_CMDPHASE_ABORT = 0x04000, 596 SCB_ON_COL_LIST = 0x08000, 597 SCB_SILENT = 0x10000,/* 598 * Be quiet about transmission type 599 * errors. They are expected and we 600 * don't want to upset the user. This 601 * flag is typically used during DV. 602 */ 603 SCB_TIMEDOUT = 0x20000/* 604 * SCB has timed out and is on the 605 * timedout list. 606 */ 607} scb_flag; 608 609struct scb { 610 struct hardware_scb *hscb; 611 union { 612 SLIST_ENTRY(scb) sle; 613 LIST_ENTRY(scb) le; 614 TAILQ_ENTRY(scb) tqe; 615 } links; 616 union { 617 SLIST_ENTRY(scb) sle; 618 LIST_ENTRY(scb) le; 619 TAILQ_ENTRY(scb) tqe; 620 } links2; 621#define pending_links links2.le 622#define collision_links links2.le 623 LIST_ENTRY(scb) timedout_links; 624 struct scb *col_scb; 625 aic_io_ctx_t io_ctx; 626 struct ahd_softc *ahd_softc; 627 scb_flag flags; 628#ifndef __linux__ 629 bus_dmamap_t dmamap; 630#endif 631 struct scb_platform_data *platform_data; 632 struct map_node *hscb_map; 633 struct map_node *sg_map; 634 struct map_node *sense_map; 635 void *sg_list; 636 uint8_t *sense_data; 637 bus_addr_t sg_list_busaddr; 638 bus_addr_t sense_busaddr; 639 u_int sg_count;/* How full ahd_dma_seg is */ 640#define AHD_MAX_LQ_CRC_ERRORS 5 641 u_int crc_retry_count; 642}; 643 644TAILQ_HEAD(scb_tailq, scb); 645LIST_HEAD(scb_list, scb); 646 647struct scb_data { 648 /* 649 * TAILQ of lists of free SCBs grouped by device 650 * collision domains. 651 */ 652 struct scb_tailq free_scbs; 653 654 /* 655 * Per-device lists of SCBs whose tag ID would collide 656 * with an already active tag on the device. 657 */ 658 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 659 660 /* 661 * SCBs that will not collide with any active device. 662 */ 663 struct scb_list any_dev_free_scb_list; 664 665 /* 666 * Mapping from tag to SCB. 667 */ 668 struct scb *scbindex[AHD_SCB_MAX]; 669 670 /* 671 * "Bus" addresses of our data structures. 672 */ 673 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 674 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 675 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 676 SLIST_HEAD(, map_node) hscb_maps; 677 SLIST_HEAD(, map_node) sg_maps; 678 SLIST_HEAD(, map_node) sense_maps; 679 int scbs_left; /* unallocated scbs in head map_node */ 680 int sgs_left; /* unallocated sgs in head map_node */ 681 int sense_left; /* unallocated sense in head map_node */ 682 uint16_t numscbs; 683 uint16_t maxhscbs; /* Number of SCBs on the card */ 684 uint8_t init_level; /* 685 * How far we've initialized 686 * this structure. 687 */ 688}; 689 690/************************ Target Mode Definitions *****************************/ 691 692/* 693 * Connection desciptor for select-in requests in target mode. 694 */ 695struct target_cmd { 696 uint8_t scsiid; /* Our ID and the initiator's ID */ 697 uint8_t identify; /* Identify message */ 698 uint8_t bytes[22]; /* 699 * Bytes contains any additional message 700 * bytes terminated by 0xFF. The remainder 701 * is the cdb to execute. 702 */ 703 uint8_t cmd_valid; /* 704 * When a command is complete, the firmware 705 * will set cmd_valid to all bits set. 706 * After the host has seen the command, 707 * the bits are cleared. This allows us 708 * to just peek at host memory to determine 709 * if more work is complete. cmd_valid is on 710 * an 8 byte boundary to simplify setting 711 * it on aic7880 hardware which only has 712 * limited direct access to the DMA FIFO. 713 */ 714 uint8_t pad[7]; 715}; 716 717/* 718 * Number of events we can buffer up if we run out 719 * of immediate notify ccbs. 720 */ 721#define AHD_TMODE_EVENT_BUFFER_SIZE 8 722struct ahd_tmode_event { 723 uint8_t initiator_id; 724 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 725#define EVENT_TYPE_BUS_RESET 0xFF 726 uint8_t event_arg; 727}; 728 729/* 730 * Per enabled lun target mode state. 731 * As this state is directly influenced by the host OS'es target mode 732 * environment, we let the OS module define it. Forward declare the 733 * structure here so we can store arrays of them, etc. in OS neutral 734 * data structures. 735 */ 736#ifdef AHD_TARGET_MODE 737struct ahd_tmode_lstate { 738 struct cam_path *path; 739 struct ccb_hdr_slist accept_tios; 740 struct ccb_hdr_slist immed_notifies; 741 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 742 uint8_t event_r_idx; 743 uint8_t event_w_idx; 744}; 745#else 746struct ahd_tmode_lstate; 747#endif 748 749/******************** Transfer Negotiation Datastructures *********************/ 750#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 751#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 752#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 753#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 754#define AHD_PERIOD_10MHz 0x19 755 756#define AHD_WIDTH_UNKNOWN 0xFF 757#define AHD_PERIOD_UNKNOWN 0xFF 758#define AHD_OFFSET_UNKNOWN 0xFF 759#define AHD_PPR_OPTS_UNKNOWN 0xFF 760 761/* 762 * Transfer Negotiation Information. 763 */ 764struct ahd_transinfo { 765 uint8_t protocol_version; /* SCSI Revision level */ 766 uint8_t transport_version; /* SPI Revision level */ 767 uint8_t width; /* Bus width */ 768 uint8_t period; /* Sync rate factor */ 769 uint8_t offset; /* Sync offset */ 770 uint8_t ppr_options; /* Parallel Protocol Request options */ 771}; 772 773/* 774 * Per-initiator current, goal and user transfer negotiation information. */ 775struct ahd_initiator_tinfo { 776 struct ahd_transinfo curr; 777 struct ahd_transinfo goal; 778 struct ahd_transinfo user; 779}; 780 781/* 782 * Per enabled target ID state. 783 * Pointers to lun target state as well as sync/wide negotiation information 784 * for each initiator<->target mapping. For the initiator role we pretend 785 * that we are the target and the targets are the initiators since the 786 * negotiation is the same regardless of role. 787 */ 788struct ahd_tmode_tstate { 789 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 790 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 791 792 /* 793 * Per initiator state bitmasks. 794 */ 795 uint16_t auto_negotiate;/* Auto Negotiation Required */ 796 uint16_t discenable; /* Disconnection allowed */ 797 uint16_t tagenable; /* Tagged Queuing allowed */ 798}; 799 800/* 801 * Points of interest along the negotiated transfer scale. 802 */ 803#define AHD_SYNCRATE_160 0x8 804#define AHD_SYNCRATE_PACED 0x8 805#define AHD_SYNCRATE_DT 0x9 806#define AHD_SYNCRATE_ULTRA2 0xa 807#define AHD_SYNCRATE_ULTRA 0xc 808#define AHD_SYNCRATE_FAST 0x19 809#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 810#define AHD_SYNCRATE_SYNC 0x32 811#define AHD_SYNCRATE_MIN 0x60 812#define AHD_SYNCRATE_ASYNC 0xFF 813#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 814 815/* Safe and valid period for async negotiations. */ 816#define AHD_ASYNC_XFER_PERIOD 0x44 817 818/* 819 * In RevA, the synctable uses a 120MHz rate for the period 820 * factor 8 and 160MHz for the period factor 7. The 120MHz 821 * rate never made it into the official SCSI spec, so we must 822 * compensate when setting the negotiation table for Rev A 823 * parts. 824 */ 825#define AHD_SYNCRATE_REVA_120 0x8 826#define AHD_SYNCRATE_REVA_160 0x7 827 828/***************************** Lookup Tables **********************************/ 829/* 830 * Phase -> name and message out response 831 * to parity errors in each phase table. 832 */ 833struct ahd_phase_table_entry { 834 uint8_t phase; 835 uint8_t mesg_out; /* Message response to parity errors */ 836 char *phasemsg; 837}; 838 839/************************** Serial EEPROM Format ******************************/ 840 841struct seeprom_config { 842/* 843 * Per SCSI ID Configuration Flags 844 */ 845 uint16_t device_flags[16]; /* words 0-15 */ 846#define CFXFER 0x003F /* synchronous transfer rate */ 847#define CFXFER_ASYNC 0x3F 848#define CFQAS 0x0040 /* Negotiate QAS */ 849#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 850#define CFSTART 0x0100 /* send start unit SCSI command */ 851#define CFINCBIOS 0x0200 /* include in BIOS scan */ 852#define CFDISC 0x0400 /* enable disconnection */ 853#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 854#define CFWIDEB 0x1000 /* wide bus device */ 855#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 856 857/* 858 * BIOS Control Bits 859 */ 860 uint16_t bios_control; /* word 16 */ 861#define CFSUPREM 0x0001 /* support all removeable drives */ 862#define CFSUPREMB 0x0002 /* support removeable boot drives */ 863#define CFBIOSSTATE 0x000C /* BIOS Action State */ 864#define CFBS_DISABLED 0x00 865#define CFBS_ENABLED 0x04 866#define CFBS_DISABLED_SCAN 0x08 867#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 868#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 869#define CFSPARITY 0x0040 /* SCSI parity */ 870#define CFEXTEND 0x0080 /* extended translation enabled */ 871#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 872#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 873#define CFMSG_VERBOSE 0x0000 874#define CFMSG_SILENT 0x0200 875#define CFMSG_DIAG 0x0400 876#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 877/* UNUSED 0xf000 */ 878 879/* 880 * Host Adapter Control Bits 881 */ 882 uint16_t adapter_control; /* word 17 */ 883#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 884#define CFSTERM 0x0002 /* SCSI low byte termination */ 885#define CFWSTERM 0x0004 /* SCSI high byte termination */ 886#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 887#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 888#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 889#define CFSTPWLEVEL 0x0040 /* Termination level control */ 890#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 891#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 892#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 893 894/* 895 * Bus Release Time, Host Adapter ID 896 */ 897 uint16_t brtime_id; /* word 18 */ 898#define CFSCSIID 0x000f /* host adapter SCSI ID */ 899/* UNUSED 0x00f0 */ 900#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 901 902/* 903 * Maximum targets 904 */ 905 uint16_t max_targets; /* word 19 */ 906#define CFMAXTARG 0x00ff /* maximum targets */ 907#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 908#define CFBOOTID 0xf000 /* Target to boot from */ 909 uint16_t res_1[10]; /* words 20-29 */ 910 uint16_t signature; /* BIOS Signature */ 911#define CFSIGNATURE 0x400 912 uint16_t checksum; /* word 31 */ 913}; 914 915/* 916 * Vital Product Data used during POST and by the BIOS. 917 */ 918struct vpd_config { 919 uint8_t bios_flags; 920#define VPDMASTERBIOS 0x0001 921#define VPDBOOTHOST 0x0002 922 uint8_t reserved_1[21]; 923 uint8_t resource_type; 924 uint8_t resource_len[2]; 925 uint8_t resource_data[8]; 926 uint8_t vpd_tag; 927 uint16_t vpd_len; 928 uint8_t vpd_keyword[2]; 929 uint8_t length; 930 uint8_t revision; 931 uint8_t device_flags; 932 uint8_t termnation_menus[2]; 933 uint8_t fifo_threshold; 934 uint8_t end_tag; 935 uint8_t vpd_checksum; 936 uint16_t default_target_flags; 937 uint16_t default_bios_flags; 938 uint16_t default_ctrl_flags; 939 uint8_t default_irq; 940 uint8_t pci_lattime; 941 uint8_t max_target; 942 uint8_t boot_lun; 943 uint16_t signature; 944 uint8_t reserved_2; 945 uint8_t checksum; 946 uint8_t reserved_3[4]; 947}; 948 949/****************************** Flexport Logic ********************************/ 950#define FLXADDR_TERMCTL 0x0 951#define FLX_TERMCTL_ENSECHIGH 0x8 952#define FLX_TERMCTL_ENSECLOW 0x4 953#define FLX_TERMCTL_ENPRIHIGH 0x2 954#define FLX_TERMCTL_ENPRILOW 0x1 955#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 956#define FLX_ROMSTAT_SEECFG 0xF0 957#define FLX_ROMSTAT_EECFG 0x0F 958#define FLX_ROMSTAT_SEE_93C66 0x00 959#define FLX_ROMSTAT_SEE_NONE 0xF0 960#define FLX_ROMSTAT_EE_512x8 0x0 961#define FLX_ROMSTAT_EE_1MBx8 0x1 962#define FLX_ROMSTAT_EE_2MBx8 0x2 963#define FLX_ROMSTAT_EE_4MBx8 0x3 964#define FLX_ROMSTAT_EE_16MBx8 0x4 965#define CURSENSE_ENB 0x1 966#define FLXADDR_FLEXSTAT 0x2 967#define FLX_FSTAT_BUSY 0x1 968#define FLXADDR_CURRENT_STAT 0x4 969#define FLX_CSTAT_SEC_HIGH 0xC0 970#define FLX_CSTAT_SEC_LOW 0x30 971#define FLX_CSTAT_PRI_HIGH 0x0C 972#define FLX_CSTAT_PRI_LOW 0x03 973#define FLX_CSTAT_MASK 0x03 974#define FLX_CSTAT_SHIFT 2 975#define FLX_CSTAT_OKAY 0x0 976#define FLX_CSTAT_OVER 0x1 977#define FLX_CSTAT_UNDER 0x2 978#define FLX_CSTAT_INVALID 0x3 979 980int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 981 u_int start_addr, u_int count, int bstream); 982 983int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 984 u_int start_addr, u_int count); 985int ahd_wait_seeprom(struct ahd_softc *ahd); 986int ahd_verify_vpd_cksum(struct vpd_config *vpd); 987int ahd_verify_cksum(struct seeprom_config *sc); 988int ahd_acquire_seeprom(struct ahd_softc *ahd); 989void ahd_release_seeprom(struct ahd_softc *ahd); 990 991/**************************** Message Buffer *********************************/ 992typedef enum { 993 MSG_FLAG_NONE = 0x00, 994 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 995 MSG_FLAG_IU_REQ_CHANGED = 0x02, 996 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 997 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 998 MSG_FLAG_PACKETIZED = 0x10 999} ahd_msg_flags; 1000 1001typedef enum { 1002 MSG_TYPE_NONE = 0x00, 1003 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 1004 MSG_TYPE_INITIATOR_MSGIN = 0x02, 1005 MSG_TYPE_TARGET_MSGOUT = 0x03, 1006 MSG_TYPE_TARGET_MSGIN = 0x04 1007} ahd_msg_type; 1008 1009typedef enum { 1010 MSGLOOP_IN_PROG, 1011 MSGLOOP_MSGCOMPLETE, 1012 MSGLOOP_TERMINATED 1013} msg_loop_stat; 1014 1015/*********************** Software Configuration Structure *********************/ 1016struct ahd_suspend_channel_state { 1017 uint8_t scsiseq; 1018 uint8_t sxfrctl0; 1019 uint8_t sxfrctl1; 1020 uint8_t simode0; 1021 uint8_t simode1; 1022 uint8_t seltimer; 1023 uint8_t seqctl; 1024}; 1025 1026struct ahd_suspend_state { 1027 struct ahd_suspend_channel_state channel[2]; 1028 uint8_t optionmode; 1029 uint8_t dscommand0; 1030 uint8_t dspcistatus; 1031 /* hsmailbox */ 1032 uint8_t crccontrol1; 1033 uint8_t scbbaddr; 1034 /* Host and sequencer SCB counts */ 1035 uint8_t dff_thrsh; 1036 uint8_t *scratch_ram; 1037 uint8_t *btt; 1038}; 1039 1040typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1041 1042typedef enum { 1043 AHD_MODE_DFF0, 1044 AHD_MODE_DFF1, 1045 AHD_MODE_CCHAN, 1046 AHD_MODE_SCSI, 1047 AHD_MODE_CFG, 1048 AHD_MODE_UNKNOWN 1049} ahd_mode; 1050 1051#define AHD_MK_MSK(x) (0x01 << (x)) 1052#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1053#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1054#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1055#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1056#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1057#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1058#define AHD_MODE_ANY_MSK (~0) 1059 1060typedef uint8_t ahd_mode_state; 1061 1062typedef void ahd_callback_t (void *); 1063 1064struct ahd_completion 1065{ 1066 uint16_t tag; 1067 uint8_t sg_status; 1068 uint8_t valid_tag; 1069}; 1070 1071struct ahd_softc { 1072 bus_space_tag_t tags[2]; 1073 bus_space_handle_t bshs[2]; 1074#ifndef __linux__ 1075 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1076#endif 1077 struct scb_data scb_data; 1078 1079 struct hardware_scb *next_queued_hscb; 1080 struct map_node *next_queued_hscb_map; 1081 1082 /* 1083 * SCBs that have been sent to the controller 1084 */ 1085 LIST_HEAD(, scb) pending_scbs; 1086 1087 /* 1088 * SCBs whose timeout routine has been called. 1089 */ 1090 LIST_HEAD(, scb) timedout_scbs; 1091 1092 /* 1093 * Current register window mode information. 1094 */ 1095 ahd_mode dst_mode; 1096 ahd_mode src_mode; 1097 1098 /* 1099 * Saved register window mode information 1100 * used for restore on next unpause. 1101 */ 1102 ahd_mode saved_dst_mode; 1103 ahd_mode saved_src_mode; 1104 1105 /* 1106 * Platform specific data. 1107 */ 1108 struct ahd_platform_data *platform_data; 1109 1110 /* 1111 * Platform specific device information. 1112 */ 1113 aic_dev_softc_t dev_softc; 1114 1115 /* 1116 * Bus specific device information. 1117 */ 1118 ahd_bus_intr_t bus_intr; 1119 1120 /* 1121 * Target mode related state kept on a per enabled lun basis. 1122 * Targets that are not enabled will have null entries. 1123 * As an initiator, we keep one target entry for our initiator 1124 * ID to store our sync/wide transfer settings. 1125 */ 1126 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1127 1128 /* 1129 * The black hole device responsible for handling requests for 1130 * disabled luns on enabled targets. 1131 */ 1132 struct ahd_tmode_lstate *black_hole; 1133 1134 /* 1135 * Device instance currently on the bus awaiting a continue TIO 1136 * for a command that was not given the disconnect priveledge. 1137 */ 1138 struct ahd_tmode_lstate *pending_device; 1139 1140 /* 1141 * Timer handles for timer driven callbacks. 1142 */ 1143 aic_timer_t reset_timer; 1144 aic_timer_t stat_timer; 1145 1146 /* 1147 * Statistics. 1148 */ 1149#define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1150#define AHD_STAT_BUCKETS 4 1151 u_int cmdcmplt_bucket; 1152 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1153 uint32_t cmdcmplt_total; 1154 1155 /* 1156 * Card characteristics 1157 */ 1158 ahd_chip chip; 1159 ahd_feature features; 1160 ahd_bug bugs; 1161 ahd_flag flags; 1162 struct seeprom_config *seep_config; 1163 1164 /* Command Queues */ 1165 struct ahd_completion *qoutfifo; 1166 uint16_t qoutfifonext; 1167 uint16_t qoutfifonext_valid_tag; 1168 uint16_t qinfifonext; 1169 uint16_t qinfifo[AHD_SCB_MAX]; 1170 1171 /* 1172 * Our qfreeze count. The sequencer compares 1173 * this value with its own counter to determine 1174 * whether to allow selections to occur. 1175 */ 1176 uint16_t qfreeze_cnt; 1177 1178 /* Values to store in the SEQCTL register for pause and unpause */ 1179 uint8_t unpause; 1180 uint8_t pause; 1181 1182 /* Critical Section Data */ 1183 struct cs *critical_sections; 1184 u_int num_critical_sections; 1185 1186 /* Buffer for handling packetized bitbucket. */ 1187 uint8_t *overrun_buf; 1188 1189 /* Links for chaining softcs */ 1190 TAILQ_ENTRY(ahd_softc) links; 1191 1192 /* Channel Names ('A', 'B', etc.) */ 1193 char channel; 1194 1195 /* Initiator Bus ID */ 1196 uint8_t our_id; 1197 1198 /* 1199 * Target incoming command FIFO. 1200 */ 1201 struct target_cmd *targetcmds; 1202 uint8_t tqinfifonext; 1203 1204 /* 1205 * Cached verson of the hs_mailbox so we can avoid 1206 * pausing the sequencer during mailbox updates. 1207 */ 1208 uint8_t hs_mailbox; 1209 1210 /* 1211 * Incoming and outgoing message handling. 1212 */ 1213 uint8_t send_msg_perror; 1214 ahd_msg_flags msg_flags; 1215 ahd_msg_type msg_type; 1216 uint8_t msgout_buf[12];/* Message we are sending */ 1217 uint8_t msgin_buf[12];/* Message we are receiving */ 1218 u_int msgout_len; /* Length of message to send */ 1219 u_int msgout_index; /* Current index in msgout */ 1220 u_int msgin_index; /* Current index in msgin */ 1221 1222 /* 1223 * Mapping information for data structures shared 1224 * between the sequencer and kernel. 1225 */ 1226 bus_dma_tag_t parent_dmat; 1227 bus_dma_tag_t shared_data_dmat; 1228 struct map_node shared_data_map; 1229 1230 /* Information saved through suspend/resume cycles */ 1231 struct ahd_suspend_state suspend_state; 1232 1233 /* Number of enabled target mode device on this card */ 1234 u_int enabled_luns; 1235 1236 /* Initialization level of this data structure */ 1237 u_int init_level; 1238 1239 /* PCI cacheline size. */ 1240 u_int pci_cachesize; 1241 1242 /* IO Cell Parameters */ 1243 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1244 1245 u_int stack_size; 1246 uint16_t *saved_stack; 1247 1248 /* Per-Unit descriptive information */ 1249 const char *description; 1250 const char *bus_description; 1251 char *name; 1252 int unit; 1253 1254 /* Selection Timer settings */ 1255 int seltime; 1256 1257 /* 1258 * Interrupt coalescing settings. 1259 */ 1260#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1261#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1262#define AHD_INT_COALESCING_MAXCMDS_MAX 127 1263#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1264#define AHD_INT_COALESCING_MINCMDS_MAX 127 1265#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1266#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1267 u_int int_coalescing_timer; 1268 u_int int_coalescing_maxcmds; 1269 u_int int_coalescing_mincmds; 1270 u_int int_coalescing_threshold; 1271 u_int int_coalescing_stop_threshold; 1272 1273 uint16_t user_discenable;/* Disconnection allowed */ 1274 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1275}; 1276 1277TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1278extern struct ahd_softc_tailq ahd_tailq; 1279 1280/*************************** IO Cell Configuration ****************************/ 1281#define AHD_PRECOMP_SLEW_INDEX \ 1282 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1283 1284#define AHD_AMPLITUDE_INDEX \ 1285 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1286 1287#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1288do { \ 1289 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1290 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1291 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1292} while (0) 1293 1294#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1295do { \ 1296 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1297 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1298 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1299} while (0) 1300 1301#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1302do { \ 1303 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1304 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1305 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1306} while (0) 1307 1308/************************ Active Device Information ***************************/ 1309typedef enum { 1310 ROLE_UNKNOWN, 1311 ROLE_INITIATOR, 1312 ROLE_TARGET 1313} role_t; 1314 1315struct ahd_devinfo { 1316 int our_scsiid; 1317 int target_offset; 1318 uint16_t target_mask; 1319 u_int target; 1320 u_int lun; 1321 char channel; 1322 role_t role; /* 1323 * Only guaranteed to be correct if not 1324 * in the busfree state. 1325 */ 1326}; 1327 1328/****************************** PCI Structures ********************************/ 1329#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ 1330#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ 1331#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ 1332 1333typedef int (ahd_device_setup_t)(struct ahd_softc *); 1334 1335struct ahd_pci_identity { 1336 uint64_t full_id; 1337 uint64_t id_mask; 1338 char *name; 1339 ahd_device_setup_t *setup; 1340}; 1341extern struct ahd_pci_identity ahd_pci_ident_table []; 1342extern const u_int ahd_num_pci_devs; 1343 1344/***************************** VL/EISA Declarations ***************************/ 1345struct aic7770_identity { 1346 uint32_t full_id; 1347 uint32_t id_mask; 1348 char *name; 1349 ahd_device_setup_t *setup; 1350}; 1351extern struct aic7770_identity aic7770_ident_table []; 1352extern const int ahd_num_aic7770_devs; 1353 1354#define AHD_EISA_SLOT_OFFSET 0xc00 1355#define AHD_EISA_IOSIZE 0x100 1356 1357/*************************** Function Declarations ****************************/ 1358/******************************************************************************/ 1359void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1360u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1361void ahd_busy_tcl(struct ahd_softc *ahd, 1362 u_int tcl, u_int busyid); 1363static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1364static __inline void 1365ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1366{ 1367 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1368} 1369 1370/***************************** PCI Front End *********************************/ 1371struct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t); 1372int ahd_pci_config(struct ahd_softc *, 1373 struct ahd_pci_identity *); 1374int ahd_pci_test_register_access(struct ahd_softc *); 1375 1376/************************** SCB and SCB queue management **********************/ 1377int ahd_probe_scbs(struct ahd_softc *); 1378void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1379 struct scb *scb); 1380int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1381 int target, char channel, int lun, 1382 u_int tag, role_t role); 1383 1384/****************************** Initialization ********************************/ 1385struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1386int ahd_softc_init(struct ahd_softc *); 1387void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1388int ahd_init(struct ahd_softc *ahd); 1389int ahd_default_config(struct ahd_softc *ahd); 1390int ahd_parse_vpddata(struct ahd_softc *ahd, 1391 struct vpd_config *vpd); 1392int ahd_parse_cfgdata(struct ahd_softc *ahd, 1393 struct seeprom_config *sc); 1394void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1395void ahd_update_coalescing_values(struct ahd_softc *ahd, 1396 u_int timer, 1397 u_int maxcmds, 1398 u_int mincmds); 1399void ahd_enable_coalescing(struct ahd_softc *ahd, 1400 int enable); 1401void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1402int ahd_suspend(struct ahd_softc *ahd); 1403int ahd_resume(struct ahd_softc *ahd); 1404void ahd_softc_insert(struct ahd_softc *); 1405struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1406void ahd_set_unit(struct ahd_softc *, int); 1407void ahd_set_name(struct ahd_softc *, char *); 1408struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1409void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1410void ahd_alloc_scbs(struct ahd_softc *ahd); 1411void ahd_free(struct ahd_softc *ahd); 1412int ahd_reset(struct ahd_softc *ahd, int reinit); 1413void ahd_shutdown(void *arg); 1414int ahd_write_flexport(struct ahd_softc *ahd, 1415 u_int addr, u_int value); 1416int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1417 uint8_t *value); 1418int ahd_wait_flexport(struct ahd_softc *ahd); 1419 1420/*************************** Interrupt Services *******************************/ 1421void ahd_pci_intr(struct ahd_softc *ahd); 1422void ahd_clear_intstat(struct ahd_softc *ahd); 1423void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1424void ahd_run_qoutfifo(struct ahd_softc *ahd); 1425#ifdef AHD_TARGET_MODE 1426void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1427#endif 1428void ahd_handle_hwerrint(struct ahd_softc *ahd); 1429void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1430void ahd_handle_scsiint(struct ahd_softc *ahd, 1431 u_int intstat); 1432void ahd_clear_critical_section(struct ahd_softc *ahd); 1433 1434/***************************** Error Recovery *********************************/ 1435typedef enum { 1436 SEARCH_COMPLETE, 1437 SEARCH_COUNT, 1438 SEARCH_REMOVE, 1439 SEARCH_PRINT 1440} ahd_search_action; 1441void ahd_done_with_status(struct ahd_softc *ahd, 1442 struct scb *scb, uint32_t status); 1443int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1444 char channel, int lun, u_int tag, 1445 role_t role, uint32_t status, 1446 ahd_search_action action); 1447int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1448 char channel, int lun, u_int tag, 1449 int stop_on_first, int remove, 1450 int save_state); 1451void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1452int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1453 int initiate_reset); 1454int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1455 char channel, int lun, u_int tag, 1456 role_t role, uint32_t status); 1457void ahd_restart(struct ahd_softc *ahd); 1458void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1459void ahd_handle_scb_status(struct ahd_softc *ahd, 1460 struct scb *scb); 1461void ahd_handle_scsi_status(struct ahd_softc *ahd, 1462 struct scb *scb); 1463void ahd_calc_residual(struct ahd_softc *ahd, 1464 struct scb *scb); 1465void ahd_timeout(struct scb *scb); 1466void ahd_recover_commands(struct ahd_softc *ahd); 1467/*************************** Utility Functions ********************************/ 1468struct ahd_phase_table_entry* 1469 ahd_lookup_phase_entry(int phase); 1470void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1471 u_int our_id, u_int target, 1472 u_int lun, char channel, 1473 role_t role); 1474/************************** Transfer Negotiation ******************************/ 1475void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1476 u_int *ppr_options, u_int maxsync); 1477void ahd_validate_offset(struct ahd_softc *ahd, 1478 struct ahd_initiator_tinfo *tinfo, 1479 u_int period, u_int *offset, 1480 int wide, role_t role); 1481void ahd_validate_width(struct ahd_softc *ahd, 1482 struct ahd_initiator_tinfo *tinfo, 1483 u_int *bus_width, 1484 role_t role); 1485/* 1486 * Negotiation types. These are used to qualify if we should renegotiate 1487 * even if our goal and current transport parameters are identical. 1488 */ 1489typedef enum { 1490 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1491 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1492 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1493} ahd_neg_type; 1494int ahd_update_neg_request(struct ahd_softc*, 1495 struct ahd_devinfo*, 1496 struct ahd_tmode_tstate*, 1497 struct ahd_initiator_tinfo*, 1498 ahd_neg_type); 1499void ahd_set_width(struct ahd_softc *ahd, 1500 struct ahd_devinfo *devinfo, 1501 u_int width, u_int type, int paused); 1502void ahd_set_syncrate(struct ahd_softc *ahd, 1503 struct ahd_devinfo *devinfo, 1504 u_int period, u_int offset, 1505 u_int ppr_options, 1506 u_int type, int paused); 1507typedef enum { 1508 AHD_QUEUE_NONE, 1509 AHD_QUEUE_BASIC, 1510 AHD_QUEUE_TAGGED 1511} ahd_queue_alg; 1512 1513void ahd_set_tags(struct ahd_softc *ahd, 1514 struct ahd_devinfo *devinfo, 1515 ahd_queue_alg alg); 1516 1517/**************************** Target Mode *************************************/ 1518#ifdef AHD_TARGET_MODE 1519void ahd_send_lstate_events(struct ahd_softc *, 1520 struct ahd_tmode_lstate *); 1521void ahd_handle_en_lun(struct ahd_softc *ahd, 1522 struct cam_sim *sim, union ccb *ccb); 1523cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1524 struct cam_sim *sim, union ccb *ccb, 1525 struct ahd_tmode_tstate **tstate, 1526 struct ahd_tmode_lstate **lstate, 1527 int notfound_failure); 1528#ifndef AHD_TMODE_ENABLE 1529#define AHD_TMODE_ENABLE 0 1530#endif 1531#endif 1532/******************************* Debug ***************************************/ 1533#ifdef AHD_DEBUG 1534extern uint32_t ahd_debug; 1535#define AHD_SHOW_MISC 0x00001 1536#define AHD_SHOW_SENSE 0x00002 1537#define AHD_SHOW_RECOVERY 0x00004 1538#define AHD_DUMP_SEEPROM 0x00008 1539#define AHD_SHOW_TERMCTL 0x00010 1540#define AHD_SHOW_MEMORY 0x00020 1541#define AHD_SHOW_MESSAGES 0x00040 1542#define AHD_SHOW_MODEPTR 0x00080 1543#define AHD_SHOW_SELTO 0x00100 1544#define AHD_SHOW_FIFOS 0x00200 1545#define AHD_SHOW_QFULL 0x00400 1546#define AHD_SHOW_DV 0x00800 1547#define AHD_SHOW_MASKED_ERRORS 0x01000 1548#define AHD_SHOW_QUEUE 0x02000 1549#define AHD_SHOW_TQIN 0x04000 1550#define AHD_SHOW_SG 0x08000 1551#define AHD_SHOW_INT_COALESCING 0x10000 1552#define AHD_DEBUG_SEQUENCER 0x20000 1553#endif 1554void ahd_print_scb(struct scb *scb); 1555void ahd_print_devinfo(struct ahd_softc *ahd, 1556 struct ahd_devinfo *devinfo); 1557void ahd_dump_sglist(struct scb *scb); 1558void ahd_dump_all_cards_state(void); 1559void ahd_dump_card_state(struct ahd_softc *ahd); 1560int ahd_print_register(ahd_reg_parse_entry_t *table, 1561 u_int num_entries, 1562 const char *name, 1563 u_int address, 1564 u_int value, 1565 u_int *cur_column, 1566 u_int wrap_point); 1567void ahd_dump_scbs(struct ahd_softc *ahd); 1568#endif /* _AIC79XX_H_ */ 1569