aic79xx.h revision 123579
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#101 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 123579 2003-12-17 00:02:10Z gibbs $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x8000 79#define QOUTFIFO_ENTRY_VALID_LE (aic_htole16(0x8000)) 80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82#define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84#define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86#define SCSIID_CHANNEL(ahd, scsiid) ('A') 87#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88#define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90#define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92#define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94#define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98#define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100#ifdef AHD_DEBUG 101#define SCB_IS_SILENT(scb) \ 102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 103 && (((scb)->flags & SCB_SILENT) != 0)) 104#else 105#define SCB_IS_SILENT(scb) \ 106 (((scb)->flags & SCB_SILENT) != 0) 107#endif 108/* 109 * TCLs have the following format: TTTTLLLLLLLL 110 */ 111#define TCL_TARGET_OFFSET(tcl) \ 112 ((((tcl) >> 4) & TID) >> 4) 113#define TCL_LUN(tcl) \ 114 (tcl & (AHD_NUM_LUNS - 1)) 115#define BUILD_TCL(scsiid, lun) \ 116 ((lun) | (((scsiid) & TID) << 4)) 117#define BUILD_TCL_RAW(target, channel, lun) \ 118 ((lun) | ((target) << 8)) 119 120#define SCB_GET_TAG(scb) \ 121 aic_le16toh(scb->hscb->tag) 122 123#ifndef AHD_TARGET_MODE 124#undef AHD_TMODE_ENABLE 125#define AHD_TMODE_ENABLE 0 126#endif 127 128#define AHD_BUILD_COL_IDX(target, lun) \ 129 (((lun) << 4) | target) 130 131#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 133 134#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 135do { \ 136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 138} while (0) 139 140#define AHD_COPY_SCB_COL_IDX(dst, src) \ 141do { \ 142 dst->hscb->scsiid = src->hscb->scsiid; \ 143 dst->hscb->lun = src->hscb->lun; \ 144} while (0) 145 146#define AHD_NEVER_COL_IDX 0xFFFF 147 148/**************************** Driver Constants ********************************/ 149/* 150 * The maximum number of supported targets. 151 */ 152#define AHD_NUM_TARGETS 16 153 154/* 155 * The maximum number of supported luns. 156 * The identify message only supports 64 luns in non-packetized transfers. 157 * You can have 2^64 luns when information unit transfers are enabled, 158 * but until we see a need to support that many, we support 256. 159 */ 160#define AHD_NUM_LUNS_NONPKT 64 161#define AHD_NUM_LUNS 256 162 163/* 164 * The maximum transfer per S/G segment. 165 */ 166#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 167 168/* 169 * The maximum amount of SCB storage in hardware on a controller. 170 * This value represents an upper bound. Due to software design, 171 * we may not be able to use this number. 172 */ 173#define AHD_SCB_MAX 512 174 175/* 176 * The maximum number of concurrent transactions supported per driver instance. 177 * Sequencer Control Blocks (SCBs) store per-transaction information. 178 */ 179#define AHD_MAX_QUEUE AHD_SCB_MAX 180 181/* 182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 183 * in size and accommodate as many transactions as can be queued concurrently. 184 */ 185#define AHD_QIN_SIZE AHD_MAX_QUEUE 186#define AHD_QOUT_SIZE AHD_MAX_QUEUE 187 188#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 189/* 190 * The maximum amount of SCB storage we allocate in host memory. 191 */ 192#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 193 194/* 195 * Ring Buffer of incoming target commands. 196 * We allocate 256 to simplify the logic in the sequencer 197 * by using the natural wrap point of an 8bit counter. 198 */ 199#define AHD_TMODE_CMDS 256 200 201/* Reset line assertion time in us */ 202#define AHD_BUSRESET_DELAY 25 203 204/******************* Chip Characteristics/Operating Settings *****************/ 205/* 206 * Chip Type 207 * The chip order is from least sophisticated to most sophisticated. 208 */ 209typedef enum { 210 AHD_NONE = 0x0000, 211 AHD_CHIPID_MASK = 0x00FF, 212 AHD_AIC7901 = 0x0001, 213 AHD_AIC7902 = 0x0002, 214 AHD_AIC7901A = 0x0003, 215 AHD_PCI = 0x0100, /* Bus type PCI */ 216 AHD_PCIX = 0x0200, /* Bus type PCIX */ 217 AHD_BUS_MASK = 0x0F00 218} ahd_chip; 219 220/* 221 * Features available in each chip type. 222 */ 223typedef enum { 224 AHD_FENONE = 0x00000, 225 AHD_WIDE = 0x00001,/* Wide Channel */ 226 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 227 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 228 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 229 AHD_RTI = 0x04000,/* Retained Training Support */ 230 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 231 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 232 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */ 233 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 234 AHD_AIC7901_FE = AHD_FENONE, 235 AHD_AIC7901A_FE = AHD_FENONE, 236 AHD_AIC7902_FE = AHD_MULTI_FUNC 237} ahd_feature; 238 239/* 240 * Bugs in the silicon that we work around in software. 241 */ 242typedef enum { 243 AHD_BUGNONE = 0x0000, 244 /* 245 * Rev A hardware fails to update LAST/CURR/NEXTSCB 246 * correctly in certain packetized selection cases. 247 */ 248 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 249 /* The wrong SCB is accessed to check the abort pending bit. */ 250 AHD_ABORT_LQI_BUG = 0x0002, 251 /* Packetized bitbucket crosses packet boundaries. */ 252 AHD_PKT_BITBUCKET_BUG = 0x0004, 253 /* The selection timer runs twice as long as its setting. */ 254 AHD_LONG_SETIMO_BUG = 0x0008, 255 /* The Non-LQ CRC error status is delayed until phase change. */ 256 AHD_NLQICRC_DELAYED_BUG = 0x0010, 257 /* The chip must be reset for all outgoing bus resets. */ 258 AHD_SCSIRST_BUG = 0x0020, 259 /* Some PCIX fields must be saved and restored across chip reset. */ 260 AHD_PCIX_CHIPRST_BUG = 0x0040, 261 /* MMAPIO is not functional in PCI-X mode. */ 262 AHD_PCIX_MMAPIO_BUG = 0x0080, 263 /* Reads to SCBRAM fail to reset the discard timer. */ 264 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 265 /* Bug workarounds that can be disabled on non-PCIX busses. */ 266 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 267 | AHD_PCIX_MMAPIO_BUG 268 | AHD_PCIX_SCBRAM_RD_BUG, 269 /* 270 * LQOSTOP0 status set even for forced selections with ATN 271 * to perform non-packetized message delivery. 272 */ 273 AHD_LQO_ATNO_BUG = 0x0200, 274 /* FIFO auto-flush does not always trigger. */ 275 AHD_AUTOFLUSH_BUG = 0x0400, 276 /* The CLRLQO registers are not self-clearing. */ 277 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 278 /* The PACKETIZED status bit refers to the previous connection. */ 279 AHD_PKTIZED_STATUS_BUG = 0x1000, 280 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 281 AHD_PKT_LUN_BUG = 0x2000, 282 /* 283 * Only the FIFO allocated to the non-packetized connection may 284 * be in use during a non-packetzied connection. 285 */ 286 AHD_NONPACKFIFO_BUG = 0x4000, 287 /* 288 * Writing to a DFF SCBPTR register may fail if concurent with 289 * a hardware write to the other DFF SCBPTR register. This is 290 * not currently a concern in our sequencer since all chips with 291 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 292 * occur in non-packetized connections. 293 */ 294 AHD_MDFF_WSCBPTR_BUG = 0x8000, 295 /* SGHADDR updates are slow. */ 296 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 297 /* 298 * Changing the MODE_PTR coincident with an interrupt that 299 * switches to a different mode will cause the interrupt to 300 * be in the mode written outside of interrupt context. 301 */ 302 AHD_SET_MODE_BUG = 0x20000, 303 /* Non-packetized busfree revision does not work. */ 304 AHD_BUSFREEREV_BUG = 0x40000, 305 /* 306 * Paced transfers are indicated with a non-standard PPR 307 * option bit in the neg table, 160MHz is indicated by 308 * sync factor 0x7, and the offset if off by a factor of 2. 309 */ 310 AHD_PACED_NEGTABLE_BUG = 0x80000, 311 /* LQOOVERRUN false positives. */ 312 AHD_LQOOVERRUN_BUG = 0x100000, 313 /* 314 * Controller write to INTSTAT will lose to a host 315 * write to CLRINT. 316 */ 317 AHD_INTCOLLISION_BUG = 0x200000, 318 /* 319 * The GEM318 violates the SCSI spec by not waiting 320 * the mandated bus settle delay between phase changes 321 * in some situations. Some aic79xx chip revs. are more 322 * strict in this regard and will treat REQ assertions 323 * that fall within the bus settle delay window as 324 * glitches. This flag tells the firmware to tolerate 325 * early REQ assertions. 326 */ 327 AHD_EARLY_REQ_BUG = 0x400000, 328 /* 329 * The LED does not stay on long enough in packetized modes. 330 */ 331 AHD_FAINT_LED_BUG = 0x800000 332} ahd_bug; 333 334/* 335 * Configuration specific settings. 336 * The driver determines these settings by probing the 337 * chip/controller's configuration. 338 */ 339typedef enum { 340 AHD_FNONE = 0x00000, 341 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 342 AHD_USEDEFAULTS = 0x00004,/* 343 * For cards without an seeprom 344 * or a BIOS to initialize the chip's 345 * SRAM, we use the default target 346 * settings. 347 */ 348 AHD_SEQUENCER_DEBUG = 0x00008, 349 AHD_RESET_BUS_A = 0x00010, 350 AHD_EXTENDED_TRANS_A = 0x00020, 351 AHD_TERM_ENB_A = 0x00040, 352 AHD_SPCHK_ENB_A = 0x00080, 353 AHD_STPWLEVEL_A = 0x00100, 354 AHD_INITIATORROLE = 0x00200,/* 355 * Allow initiator operations on 356 * this controller. 357 */ 358 AHD_TARGETROLE = 0x00400,/* 359 * Allow target operations on this 360 * controller. 361 */ 362 AHD_RESOURCE_SHORTAGE = 0x00800, 363 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 364 AHD_INT50_SPEEDFLEX = 0x02000,/* 365 * Internal 50pin connector 366 * sits behind an aic3860 367 */ 368 AHD_BIOS_ENABLED = 0x04000, 369 AHD_ALL_INTERRUPTS = 0x08000, 370 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 371 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 372 AHD_CURRENT_SENSING = 0x40000, 373 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 374 AHD_HP_BOARD = 0x100000, 375 AHD_RESET_POLL_ACTIVE = 0x200000, 376 AHD_UPDATE_PEND_CMDS = 0x400000, 377 AHD_RUNNING_QOUTFIFO = 0x800000, 378 AHD_HAD_FIRST_SEL = 0x1000000, 379 AHD_SHUTDOWN_RECOVERY = 0x2000000 /* Terminate recovery thread. */ 380} ahd_flag; 381 382/************************* Hardware SCB Definition ***************************/ 383 384/* 385 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 386 * consists of a "hardware SCB" mirroring the fields available on the card 387 * and additional information the kernel stores for each transaction. 388 * 389 * To minimize space utilization, a portion of the hardware scb stores 390 * different data during different portions of a SCSI transaction. 391 * As initialized by the host driver for the initiator role, this area 392 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 393 * the cdb has been presented to the target, this area serves to store 394 * residual transfer information and the SCSI status byte. 395 * For the target role, the contents of this area do not change, but 396 * still serve a different purpose than for the initiator role. See 397 * struct target_data for details. 398 */ 399 400/* 401 * Status information embedded in the shared poriton of 402 * an SCB after passing the cdb to the target. The kernel 403 * driver will only read this data for transactions that 404 * complete abnormally. 405 */ 406struct initiator_status { 407 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 408 uint32_t residual_sgptr; /* The next S/G for this transfer */ 409 uint8_t scsi_status; /* Standard SCSI status byte */ 410}; 411 412struct target_status { 413 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 414 uint32_t residual_sgptr; /* The next S/G for this transfer */ 415 uint8_t scsi_status; /* SCSI status to give to initiator */ 416 uint8_t target_phases; /* Bitmap of phases to execute */ 417 uint8_t data_phase; /* Data-In or Data-Out */ 418 uint8_t initiator_tag; /* Initiator's transaction tag */ 419}; 420 421/* 422 * Initiator mode SCB shared data area. 423 * If the embedded CDB is 12 bytes or less, we embed 424 * the sense buffer address in the SCB. This allows 425 * us to retrieve sense information without interrupting 426 * the host in packetized mode. 427 */ 428typedef uint32_t sense_addr_t; 429#define MAX_CDB_LEN 16 430#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 431union initiator_data { 432 struct { 433 uint64_t cdbptr; 434 uint8_t cdblen; 435 } cdb_from_host; 436 uint8_t cdb[MAX_CDB_LEN]; 437 struct { 438 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 439 sense_addr_t sense_addr; 440 } cdb_plus_saddr; 441}; 442 443/* 444 * Target mode version of the shared data SCB segment. 445 */ 446struct target_data { 447 uint32_t spare[2]; 448 uint8_t scsi_status; /* SCSI status to give to initiator */ 449 uint8_t target_phases; /* Bitmap of phases to execute */ 450 uint8_t data_phase; /* Data-In or Data-Out */ 451 uint8_t initiator_tag; /* Initiator's transaction tag */ 452}; 453 454struct hardware_scb { 455/*0*/ union { 456 union initiator_data idata; 457 struct target_data tdata; 458 struct initiator_status istatus; 459 struct target_status tstatus; 460 } shared_data; 461/* 462 * A word about residuals. 463 * The scb is presented to the sequencer with the dataptr and datacnt 464 * fields initialized to the contents of the first S/G element to 465 * transfer. The sgptr field is initialized to the bus address for 466 * the S/G element that follows the first in the in core S/G array 467 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 468 * S/G entry for this transfer (single S/G element transfer with the 469 * first elements address and length preloaded in the dataptr/datacnt 470 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 471 * The SG_FULL_RESID flag ensures that the residual will be correctly 472 * noted even if no data transfers occur. Once the data phase is entered, 473 * the residual sgptr and datacnt are loaded from the sgptr and the 474 * datacnt fields. After each S/G element's dataptr and length are 475 * loaded into the hardware, the residual sgptr is advanced. After 476 * each S/G element is expired, its datacnt field is checked to see 477 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 478 * residual sg ptr and the transfer is considered complete. If the 479 * sequencer determines that there is a residual in the tranfer, or 480 * there is non-zero status, it will set the SG_STATUS_VALID flag in 481 * sgptr and dma the scb back into host memory. To sumarize: 482 * 483 * Sequencer: 484 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 485 * or residual_sgptr does not have SG_LIST_NULL set. 486 * 487 * o We are transfering the last segment if residual_datacnt has 488 * the SG_LAST_SEG flag set. 489 * 490 * Host: 491 * o A residual can only have occurred if a completed scb has the 492 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 493 * the residual_datacnt, and the residual_sgptr field will tell 494 * for sure. 495 * 496 * o residual_sgptr and sgptr refer to the "next" sg entry 497 * and so may point beyond the last valid sg entry for the 498 * transfer. 499 */ 500#define SG_PTR_MASK 0xFFFFFFF8 501/*16*/ uint16_t tag; /* Reused by Sequencer. */ 502/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 503/*19*/ uint8_t scsiid; /* 504 * Selection out Id 505 * Our Id (bits 0-3) Their ID (bits 4-7) 506 */ 507/*20*/ uint8_t lun; 508/*21*/ uint8_t task_attribute; 509/*22*/ uint8_t cdb_len; 510/*23*/ uint8_t task_management; 511/*24*/ uint64_t dataptr; 512/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 513/*36*/ uint32_t sgptr; 514/*40*/ uint32_t hscb_busaddr; 515/*44*/ uint32_t next_hscb_busaddr; 516/********** Long lun field only downloaded for full 8 byte lun support ********/ 517/*48*/ uint8_t pkt_long_lun[8]; 518/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 519/*56*/ uint8_t spare[8]; 520}; 521 522/************************ Kernel SCB Definitions ******************************/ 523/* 524 * Some fields of the SCB are OS dependent. Here we collect the 525 * definitions for elements that all OS platforms need to include 526 * in there SCB definition. 527 */ 528 529/* 530 * Definition of a scatter/gather element as transfered to the controller. 531 * The aic7xxx chips only support a 24bit length. We use the top byte of 532 * the length to store additional address bits and a flag to indicate 533 * that a given segment terminates the transfer. This gives us an 534 * addressable range of 512GB on machines with 64bit PCI or with chips 535 * that can support dual address cycles on 32bit PCI busses. 536 */ 537struct ahd_dma_seg { 538 uint32_t addr; 539 uint32_t len; 540#define AHD_DMA_LAST_SEG 0x80000000 541#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 542#define AHD_SG_LEN_MASK 0x00FFFFFF 543}; 544 545struct ahd_dma64_seg { 546 uint64_t addr; 547 uint32_t len; 548 uint32_t pad; 549}; 550 551struct map_node { 552 bus_dmamap_t dmamap; 553 bus_addr_t busaddr; 554 uint8_t *vaddr; 555 SLIST_ENTRY(map_node) links; 556}; 557 558/* 559 * The current state of this SCB. 560 */ 561typedef enum { 562 SCB_FLAG_NONE = 0x00000, 563 SCB_TRANSMISSION_ERROR = 0x00001,/* 564 * We detected a parity or CRC 565 * error that has effected the 566 * payload of the command. This 567 * flag is checked when normal 568 * status is returned to catch 569 * the case of a target not 570 * responding to our attempt 571 * to report the error. 572 */ 573 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 574 * Another device was active 575 * during the first timeout for 576 * this SCB so we gave ourselves 577 * an additional timeout period 578 * in case it was hogging the 579 * bus. 580 */ 581 SCB_DEVICE_RESET = 0x00004, 582 SCB_SENSE = 0x00008, 583 SCB_CDB32_PTR = 0x00010, 584 SCB_RECOVERY_SCB = 0x00020, 585 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 586 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 587 SCB_ABORT = 0x00100, 588 SCB_ACTIVE = 0x00200, 589 SCB_TARGET_IMMEDIATE = 0x00400, 590 SCB_PACKETIZED = 0x00800, 591 SCB_EXPECT_PPR_BUSFREE = 0x01000, 592 SCB_PKT_SENSE = 0x02000, 593 SCB_CMDPHASE_ABORT = 0x04000, 594 SCB_ON_COL_LIST = 0x08000, 595 SCB_SILENT = 0x10000,/* 596 * Be quiet about transmission type 597 * errors. They are expected and we 598 * don't want to upset the user. This 599 * flag is typically used during DV. 600 */ 601 SCB_TIMEDOUT = 0x20000/* 602 * SCB has timed out and is on the 603 * timedout list. 604 */ 605} scb_flag; 606 607struct scb { 608 struct hardware_scb *hscb; 609 union { 610 SLIST_ENTRY(scb) sle; 611 LIST_ENTRY(scb) le; 612 TAILQ_ENTRY(scb) tqe; 613 } links; 614 union { 615 SLIST_ENTRY(scb) sle; 616 LIST_ENTRY(scb) le; 617 TAILQ_ENTRY(scb) tqe; 618 } links2; 619#define pending_links links2.le 620#define collision_links links2.le 621 LIST_ENTRY(scb) timedout_links; 622 struct scb *col_scb; 623 aic_io_ctx_t io_ctx; 624 struct ahd_softc *ahd_softc; 625 scb_flag flags; 626#ifndef __linux__ 627 bus_dmamap_t dmamap; 628#endif 629 struct scb_platform_data *platform_data; 630 struct map_node *hscb_map; 631 struct map_node *sg_map; 632 struct map_node *sense_map; 633 void *sg_list; 634 uint8_t *sense_data; 635 bus_addr_t sg_list_busaddr; 636 bus_addr_t sense_busaddr; 637 u_int sg_count;/* How full ahd_dma_seg is */ 638#define AHD_MAX_LQ_CRC_ERRORS 5 639 u_int crc_retry_count; 640}; 641 642TAILQ_HEAD(scb_tailq, scb); 643LIST_HEAD(scb_list, scb); 644 645struct scb_data { 646 /* 647 * TAILQ of lists of free SCBs grouped by device 648 * collision domains. 649 */ 650 struct scb_tailq free_scbs; 651 652 /* 653 * Per-device lists of SCBs whose tag ID would collide 654 * with an already active tag on the device. 655 */ 656 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 657 658 /* 659 * SCBs that will not collide with any active device. 660 */ 661 struct scb_list any_dev_free_scb_list; 662 663 /* 664 * Mapping from tag to SCB. 665 */ 666 struct scb *scbindex[AHD_SCB_MAX]; 667 668 /* 669 * "Bus" addresses of our data structures. 670 */ 671 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 672 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 673 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 674 SLIST_HEAD(, map_node) hscb_maps; 675 SLIST_HEAD(, map_node) sg_maps; 676 SLIST_HEAD(, map_node) sense_maps; 677 int scbs_left; /* unallocated scbs in head map_node */ 678 int sgs_left; /* unallocated sgs in head map_node */ 679 int sense_left; /* unallocated sense in head map_node */ 680 uint16_t numscbs; 681 uint16_t maxhscbs; /* Number of SCBs on the card */ 682 uint8_t init_level; /* 683 * How far we've initialized 684 * this structure. 685 */ 686}; 687 688/************************ Target Mode Definitions *****************************/ 689 690/* 691 * Connection desciptor for select-in requests in target mode. 692 */ 693struct target_cmd { 694 uint8_t scsiid; /* Our ID and the initiator's ID */ 695 uint8_t identify; /* Identify message */ 696 uint8_t bytes[22]; /* 697 * Bytes contains any additional message 698 * bytes terminated by 0xFF. The remainder 699 * is the cdb to execute. 700 */ 701 uint8_t cmd_valid; /* 702 * When a command is complete, the firmware 703 * will set cmd_valid to all bits set. 704 * After the host has seen the command, 705 * the bits are cleared. This allows us 706 * to just peek at host memory to determine 707 * if more work is complete. cmd_valid is on 708 * an 8 byte boundary to simplify setting 709 * it on aic7880 hardware which only has 710 * limited direct access to the DMA FIFO. 711 */ 712 uint8_t pad[7]; 713}; 714 715/* 716 * Number of events we can buffer up if we run out 717 * of immediate notify ccbs. 718 */ 719#define AHD_TMODE_EVENT_BUFFER_SIZE 8 720struct ahd_tmode_event { 721 uint8_t initiator_id; 722 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 723#define EVENT_TYPE_BUS_RESET 0xFF 724 uint8_t event_arg; 725}; 726 727/* 728 * Per enabled lun target mode state. 729 * As this state is directly influenced by the host OS'es target mode 730 * environment, we let the OS module define it. Forward declare the 731 * structure here so we can store arrays of them, etc. in OS neutral 732 * data structures. 733 */ 734#ifdef AHD_TARGET_MODE 735struct ahd_tmode_lstate { 736 struct cam_path *path; 737 struct ccb_hdr_slist accept_tios; 738 struct ccb_hdr_slist immed_notifies; 739 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 740 uint8_t event_r_idx; 741 uint8_t event_w_idx; 742}; 743#else 744struct ahd_tmode_lstate; 745#endif 746 747/******************** Transfer Negotiation Datastructures *********************/ 748#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 749#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 750#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 751#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 752#define AHD_PERIOD_10MHz 0x19 753 754#define AHD_WIDTH_UNKNOWN 0xFF 755#define AHD_PERIOD_UNKNOWN 0xFF 756#define AHD_OFFSET_UNKNOWN 0xFF 757#define AHD_PPR_OPTS_UNKNOWN 0xFF 758 759/* 760 * Transfer Negotiation Information. 761 */ 762struct ahd_transinfo { 763 uint8_t protocol_version; /* SCSI Revision level */ 764 uint8_t transport_version; /* SPI Revision level */ 765 uint8_t width; /* Bus width */ 766 uint8_t period; /* Sync rate factor */ 767 uint8_t offset; /* Sync offset */ 768 uint8_t ppr_options; /* Parallel Protocol Request options */ 769}; 770 771/* 772 * Per-initiator current, goal and user transfer negotiation information. */ 773struct ahd_initiator_tinfo { 774 struct ahd_transinfo curr; 775 struct ahd_transinfo goal; 776 struct ahd_transinfo user; 777}; 778 779/* 780 * Per enabled target ID state. 781 * Pointers to lun target state as well as sync/wide negotiation information 782 * for each initiator<->target mapping. For the initiator role we pretend 783 * that we are the target and the targets are the initiators since the 784 * negotiation is the same regardless of role. 785 */ 786struct ahd_tmode_tstate { 787 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 788 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 789 790 /* 791 * Per initiator state bitmasks. 792 */ 793 uint16_t auto_negotiate;/* Auto Negotiation Required */ 794 uint16_t discenable; /* Disconnection allowed */ 795 uint16_t tagenable; /* Tagged Queuing allowed */ 796}; 797 798/* 799 * Points of interest along the negotiated transfer scale. 800 */ 801#define AHD_SYNCRATE_160 0x8 802#define AHD_SYNCRATE_PACED 0x8 803#define AHD_SYNCRATE_DT 0x9 804#define AHD_SYNCRATE_ULTRA2 0xa 805#define AHD_SYNCRATE_ULTRA 0xc 806#define AHD_SYNCRATE_FAST 0x19 807#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 808#define AHD_SYNCRATE_SYNC 0x32 809#define AHD_SYNCRATE_MIN 0x60 810#define AHD_SYNCRATE_ASYNC 0xFF 811#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 812 813/* Safe and valid period for async negotiations. */ 814#define AHD_ASYNC_XFER_PERIOD 0x44 815 816/* 817 * In RevA, the synctable uses a 120MHz rate for the period 818 * factor 8 and 160MHz for the period factor 7. The 120MHz 819 * rate never made it into the official SCSI spec, so we must 820 * compensate when setting the negotiation table for Rev A 821 * parts. 822 */ 823#define AHD_SYNCRATE_REVA_120 0x8 824#define AHD_SYNCRATE_REVA_160 0x7 825 826/***************************** Lookup Tables **********************************/ 827/* 828 * Phase -> name and message out response 829 * to parity errors in each phase table. 830 */ 831struct ahd_phase_table_entry { 832 uint8_t phase; 833 uint8_t mesg_out; /* Message response to parity errors */ 834 char *phasemsg; 835}; 836 837/************************** Serial EEPROM Format ******************************/ 838 839struct seeprom_config { 840/* 841 * Per SCSI ID Configuration Flags 842 */ 843 uint16_t device_flags[16]; /* words 0-15 */ 844#define CFXFER 0x003F /* synchronous transfer rate */ 845#define CFXFER_ASYNC 0x3F 846#define CFQAS 0x0040 /* Negotiate QAS */ 847#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 848#define CFSTART 0x0100 /* send start unit SCSI command */ 849#define CFINCBIOS 0x0200 /* include in BIOS scan */ 850#define CFDISC 0x0400 /* enable disconnection */ 851#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 852#define CFWIDEB 0x1000 /* wide bus device */ 853#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 854 855/* 856 * BIOS Control Bits 857 */ 858 uint16_t bios_control; /* word 16 */ 859#define CFSUPREM 0x0001 /* support all removeable drives */ 860#define CFSUPREMB 0x0002 /* support removeable boot drives */ 861#define CFBIOSSTATE 0x000C /* BIOS Action State */ 862#define CFBS_DISABLED 0x00 863#define CFBS_ENABLED 0x04 864#define CFBS_DISABLED_SCAN 0x08 865#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 866#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 867#define CFSPARITY 0x0040 /* SCSI parity */ 868#define CFEXTEND 0x0080 /* extended translation enabled */ 869#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 870#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 871#define CFMSG_VERBOSE 0x0000 872#define CFMSG_SILENT 0x0200 873#define CFMSG_DIAG 0x0400 874#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 875/* UNUSED 0xf000 */ 876 877/* 878 * Host Adapter Control Bits 879 */ 880 uint16_t adapter_control; /* word 17 */ 881#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 882#define CFSTERM 0x0002 /* SCSI low byte termination */ 883#define CFWSTERM 0x0004 /* SCSI high byte termination */ 884#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 885#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 886#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 887#define CFSTPWLEVEL 0x0040 /* Termination level control */ 888#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 889#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 890#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 891 892/* 893 * Bus Release Time, Host Adapter ID 894 */ 895 uint16_t brtime_id; /* word 18 */ 896#define CFSCSIID 0x000f /* host adapter SCSI ID */ 897/* UNUSED 0x00f0 */ 898#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 899 900/* 901 * Maximum targets 902 */ 903 uint16_t max_targets; /* word 19 */ 904#define CFMAXTARG 0x00ff /* maximum targets */ 905#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 906#define CFBOOTID 0xf000 /* Target to boot from */ 907 uint16_t res_1[10]; /* words 20-29 */ 908 uint16_t signature; /* BIOS Signature */ 909#define CFSIGNATURE 0x400 910 uint16_t checksum; /* word 31 */ 911}; 912 913/* 914 * Vital Product Data used during POST and by the BIOS. 915 */ 916struct vpd_config { 917 uint8_t bios_flags; 918#define VPDMASTERBIOS 0x0001 919#define VPDBOOTHOST 0x0002 920 uint8_t reserved_1[21]; 921 uint8_t resource_type; 922 uint8_t resource_len[2]; 923 uint8_t resource_data[8]; 924 uint8_t vpd_tag; 925 uint16_t vpd_len; 926 uint8_t vpd_keyword[2]; 927 uint8_t length; 928 uint8_t revision; 929 uint8_t device_flags; 930 uint8_t termnation_menus[2]; 931 uint8_t fifo_threshold; 932 uint8_t end_tag; 933 uint8_t vpd_checksum; 934 uint16_t default_target_flags; 935 uint16_t default_bios_flags; 936 uint16_t default_ctrl_flags; 937 uint8_t default_irq; 938 uint8_t pci_lattime; 939 uint8_t max_target; 940 uint8_t boot_lun; 941 uint16_t signature; 942 uint8_t reserved_2; 943 uint8_t checksum; 944 uint8_t reserved_3[4]; 945}; 946 947/****************************** Flexport Logic ********************************/ 948#define FLXADDR_TERMCTL 0x0 949#define FLX_TERMCTL_ENSECHIGH 0x8 950#define FLX_TERMCTL_ENSECLOW 0x4 951#define FLX_TERMCTL_ENPRIHIGH 0x2 952#define FLX_TERMCTL_ENPRILOW 0x1 953#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 954#define FLX_ROMSTAT_SEECFG 0xF0 955#define FLX_ROMSTAT_EECFG 0x0F 956#define FLX_ROMSTAT_SEE_93C66 0x00 957#define FLX_ROMSTAT_SEE_NONE 0xF0 958#define FLX_ROMSTAT_EE_512x8 0x0 959#define FLX_ROMSTAT_EE_1MBx8 0x1 960#define FLX_ROMSTAT_EE_2MBx8 0x2 961#define FLX_ROMSTAT_EE_4MBx8 0x3 962#define FLX_ROMSTAT_EE_16MBx8 0x4 963#define CURSENSE_ENB 0x1 964#define FLXADDR_FLEXSTAT 0x2 965#define FLX_FSTAT_BUSY 0x1 966#define FLXADDR_CURRENT_STAT 0x4 967#define FLX_CSTAT_SEC_HIGH 0xC0 968#define FLX_CSTAT_SEC_LOW 0x30 969#define FLX_CSTAT_PRI_HIGH 0x0C 970#define FLX_CSTAT_PRI_LOW 0x03 971#define FLX_CSTAT_MASK 0x03 972#define FLX_CSTAT_SHIFT 2 973#define FLX_CSTAT_OKAY 0x0 974#define FLX_CSTAT_OVER 0x1 975#define FLX_CSTAT_UNDER 0x2 976#define FLX_CSTAT_INVALID 0x3 977 978int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 979 u_int start_addr, u_int count, int bstream); 980 981int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 982 u_int start_addr, u_int count); 983int ahd_wait_seeprom(struct ahd_softc *ahd); 984int ahd_verify_vpd_cksum(struct vpd_config *vpd); 985int ahd_verify_cksum(struct seeprom_config *sc); 986int ahd_acquire_seeprom(struct ahd_softc *ahd); 987void ahd_release_seeprom(struct ahd_softc *ahd); 988 989/**************************** Message Buffer *********************************/ 990typedef enum { 991 MSG_FLAG_NONE = 0x00, 992 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 993 MSG_FLAG_IU_REQ_CHANGED = 0x02, 994 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 995 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 996 MSG_FLAG_PACKETIZED = 0x10 997} ahd_msg_flags; 998 999typedef enum { 1000 MSG_TYPE_NONE = 0x00, 1001 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 1002 MSG_TYPE_INITIATOR_MSGIN = 0x02, 1003 MSG_TYPE_TARGET_MSGOUT = 0x03, 1004 MSG_TYPE_TARGET_MSGIN = 0x04 1005} ahd_msg_type; 1006 1007typedef enum { 1008 MSGLOOP_IN_PROG, 1009 MSGLOOP_MSGCOMPLETE, 1010 MSGLOOP_TERMINATED 1011} msg_loop_stat; 1012 1013/*********************** Software Configuration Structure *********************/ 1014struct ahd_suspend_channel_state { 1015 uint8_t scsiseq; 1016 uint8_t sxfrctl0; 1017 uint8_t sxfrctl1; 1018 uint8_t simode0; 1019 uint8_t simode1; 1020 uint8_t seltimer; 1021 uint8_t seqctl; 1022}; 1023 1024struct ahd_suspend_state { 1025 struct ahd_suspend_channel_state channel[2]; 1026 uint8_t optionmode; 1027 uint8_t dscommand0; 1028 uint8_t dspcistatus; 1029 /* hsmailbox */ 1030 uint8_t crccontrol1; 1031 uint8_t scbbaddr; 1032 /* Host and sequencer SCB counts */ 1033 uint8_t dff_thrsh; 1034 uint8_t *scratch_ram; 1035 uint8_t *btt; 1036}; 1037 1038typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1039 1040typedef enum { 1041 AHD_MODE_DFF0, 1042 AHD_MODE_DFF1, 1043 AHD_MODE_CCHAN, 1044 AHD_MODE_SCSI, 1045 AHD_MODE_CFG, 1046 AHD_MODE_UNKNOWN 1047} ahd_mode; 1048 1049#define AHD_MK_MSK(x) (0x01 << (x)) 1050#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1051#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1052#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1053#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1054#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1055#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1056#define AHD_MODE_ANY_MSK (~0) 1057 1058typedef uint8_t ahd_mode_state; 1059 1060typedef void ahd_callback_t (void *); 1061 1062struct ahd_softc { 1063 bus_space_tag_t tags[2]; 1064 bus_space_handle_t bshs[2]; 1065#ifndef __linux__ 1066 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1067#endif 1068 struct scb_data scb_data; 1069 1070 struct hardware_scb *next_queued_hscb; 1071 struct map_node *next_queued_hscb_map; 1072 1073 /* 1074 * SCBs that have been sent to the controller 1075 */ 1076 LIST_HEAD(, scb) pending_scbs; 1077 1078 /* 1079 * SCBs whose timeout routine has been called. 1080 */ 1081 LIST_HEAD(, scb) timedout_scbs; 1082 1083 /* 1084 * Current register window mode information. 1085 */ 1086 ahd_mode dst_mode; 1087 ahd_mode src_mode; 1088 1089 /* 1090 * Saved register window mode information 1091 * used for restore on next unpause. 1092 */ 1093 ahd_mode saved_dst_mode; 1094 ahd_mode saved_src_mode; 1095 1096 /* 1097 * Platform specific data. 1098 */ 1099 struct ahd_platform_data *platform_data; 1100 1101 /* 1102 * Platform specific device information. 1103 */ 1104 aic_dev_softc_t dev_softc; 1105 1106 /* 1107 * Bus specific device information. 1108 */ 1109 ahd_bus_intr_t bus_intr; 1110 1111 /* 1112 * Target mode related state kept on a per enabled lun basis. 1113 * Targets that are not enabled will have null entries. 1114 * As an initiator, we keep one target entry for our initiator 1115 * ID to store our sync/wide transfer settings. 1116 */ 1117 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1118 1119 /* 1120 * The black hole device responsible for handling requests for 1121 * disabled luns on enabled targets. 1122 */ 1123 struct ahd_tmode_lstate *black_hole; 1124 1125 /* 1126 * Device instance currently on the bus awaiting a continue TIO 1127 * for a command that was not given the disconnect priveledge. 1128 */ 1129 struct ahd_tmode_lstate *pending_device; 1130 1131 /* 1132 * Timer handles for timer driven callbacks. 1133 */ 1134 aic_timer_t reset_timer; 1135 aic_timer_t stat_timer; 1136 1137 /* 1138 * Statistics. 1139 */ 1140#define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1141#define AHD_STAT_BUCKETS 4 1142 u_int cmdcmplt_bucket; 1143 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1144 uint32_t cmdcmplt_total; 1145 1146 /* 1147 * Card characteristics 1148 */ 1149 ahd_chip chip; 1150 ahd_feature features; 1151 ahd_bug bugs; 1152 ahd_flag flags; 1153 struct seeprom_config *seep_config; 1154 1155 /* Values to store in the SEQCTL register for pause and unpause */ 1156 uint8_t unpause; 1157 uint8_t pause; 1158 1159 /* Command Queues */ 1160 uint16_t qoutfifonext; 1161 uint16_t qoutfifonext_valid_tag; 1162 uint16_t qinfifonext; 1163 uint16_t qinfifo[AHD_SCB_MAX]; 1164 uint16_t *qoutfifo; 1165 1166 /* Critical Section Data */ 1167 struct cs *critical_sections; 1168 u_int num_critical_sections; 1169 1170 /* Buffer for handling packetized bitbucket. */ 1171 uint8_t *overrun_buf; 1172 1173 /* Links for chaining softcs */ 1174 TAILQ_ENTRY(ahd_softc) links; 1175 1176 /* Channel Names ('A', 'B', etc.) */ 1177 char channel; 1178 1179 /* Initiator Bus ID */ 1180 uint8_t our_id; 1181 1182 /* 1183 * Target incoming command FIFO. 1184 */ 1185 struct target_cmd *targetcmds; 1186 uint8_t tqinfifonext; 1187 1188 /* 1189 * Cached verson of the hs_mailbox so we can avoid 1190 * pausing the sequencer during mailbox updates. 1191 */ 1192 uint8_t hs_mailbox; 1193 1194 /* 1195 * Incoming and outgoing message handling. 1196 */ 1197 uint8_t send_msg_perror; 1198 ahd_msg_flags msg_flags; 1199 ahd_msg_type msg_type; 1200 uint8_t msgout_buf[12];/* Message we are sending */ 1201 uint8_t msgin_buf[12];/* Message we are receiving */ 1202 u_int msgout_len; /* Length of message to send */ 1203 u_int msgout_index; /* Current index in msgout */ 1204 u_int msgin_index; /* Current index in msgin */ 1205 1206 /* 1207 * Mapping information for data structures shared 1208 * between the sequencer and kernel. 1209 */ 1210 bus_dma_tag_t parent_dmat; 1211 bus_dma_tag_t shared_data_dmat; 1212 struct map_node shared_data_map; 1213 1214 /* Information saved through suspend/resume cycles */ 1215 struct ahd_suspend_state suspend_state; 1216 1217 /* Number of enabled target mode device on this card */ 1218 u_int enabled_luns; 1219 1220 /* Initialization level of this data structure */ 1221 u_int init_level; 1222 1223 /* PCI cacheline size. */ 1224 u_int pci_cachesize; 1225 1226 /* IO Cell Parameters */ 1227 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1228 1229 u_int stack_size; 1230 uint16_t *saved_stack; 1231 1232 /* Per-Unit descriptive information */ 1233 const char *description; 1234 const char *bus_description; 1235 char *name; 1236 int unit; 1237 1238 /* Selection Timer settings */ 1239 int seltime; 1240 1241 /* 1242 * Interrupt coalescing settings. 1243 */ 1244#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1245#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1246#define AHD_INT_COALESCING_MAXCMDS_MAX 127 1247#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1248#define AHD_INT_COALESCING_MINCMDS_MAX 127 1249#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1250#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1251 u_int int_coalescing_timer; 1252 u_int int_coalescing_maxcmds; 1253 u_int int_coalescing_mincmds; 1254 u_int int_coalescing_threshold; 1255 u_int int_coalescing_stop_threshold; 1256 1257 uint16_t user_discenable;/* Disconnection allowed */ 1258 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1259}; 1260 1261TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1262extern struct ahd_softc_tailq ahd_tailq; 1263 1264/*************************** IO Cell Configuration ****************************/ 1265#define AHD_PRECOMP_SLEW_INDEX \ 1266 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1267 1268#define AHD_AMPLITUDE_INDEX \ 1269 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1270 1271#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1272do { \ 1273 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1274 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1275 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1276} while (0) 1277 1278#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1279do { \ 1280 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1281 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1282 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1283} while (0) 1284 1285#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1286do { \ 1287 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1288 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1289 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1290} while (0) 1291 1292/************************ Active Device Information ***************************/ 1293typedef enum { 1294 ROLE_UNKNOWN, 1295 ROLE_INITIATOR, 1296 ROLE_TARGET 1297} role_t; 1298 1299struct ahd_devinfo { 1300 int our_scsiid; 1301 int target_offset; 1302 uint16_t target_mask; 1303 u_int target; 1304 u_int lun; 1305 char channel; 1306 role_t role; /* 1307 * Only guaranteed to be correct if not 1308 * in the busfree state. 1309 */ 1310}; 1311 1312/****************************** PCI Structures ********************************/ 1313#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ 1314#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ 1315#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ 1316 1317typedef int (ahd_device_setup_t)(struct ahd_softc *); 1318 1319struct ahd_pci_identity { 1320 uint64_t full_id; 1321 uint64_t id_mask; 1322 char *name; 1323 ahd_device_setup_t *setup; 1324}; 1325extern struct ahd_pci_identity ahd_pci_ident_table []; 1326extern const u_int ahd_num_pci_devs; 1327 1328/***************************** VL/EISA Declarations ***************************/ 1329struct aic7770_identity { 1330 uint32_t full_id; 1331 uint32_t id_mask; 1332 char *name; 1333 ahd_device_setup_t *setup; 1334}; 1335extern struct aic7770_identity aic7770_ident_table []; 1336extern const int ahd_num_aic7770_devs; 1337 1338#define AHD_EISA_SLOT_OFFSET 0xc00 1339#define AHD_EISA_IOSIZE 0x100 1340 1341/*************************** Function Declarations ****************************/ 1342/******************************************************************************/ 1343void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1344u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1345void ahd_busy_tcl(struct ahd_softc *ahd, 1346 u_int tcl, u_int busyid); 1347static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1348static __inline void 1349ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1350{ 1351 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1352} 1353 1354/***************************** PCI Front End *********************************/ 1355struct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t); 1356int ahd_pci_config(struct ahd_softc *, 1357 struct ahd_pci_identity *); 1358int ahd_pci_test_register_access(struct ahd_softc *); 1359 1360/************************** SCB and SCB queue management **********************/ 1361int ahd_probe_scbs(struct ahd_softc *); 1362void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1363 struct scb *scb); 1364int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1365 int target, char channel, int lun, 1366 u_int tag, role_t role); 1367 1368/****************************** Initialization ********************************/ 1369struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1370int ahd_softc_init(struct ahd_softc *); 1371void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1372int ahd_init(struct ahd_softc *ahd); 1373int ahd_default_config(struct ahd_softc *ahd); 1374int ahd_parse_vpddata(struct ahd_softc *ahd, 1375 struct vpd_config *vpd); 1376int ahd_parse_cfgdata(struct ahd_softc *ahd, 1377 struct seeprom_config *sc); 1378void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1379void ahd_update_coalescing_values(struct ahd_softc *ahd, 1380 u_int timer, 1381 u_int maxcmds, 1382 u_int mincmds); 1383void ahd_enable_coalescing(struct ahd_softc *ahd, 1384 int enable); 1385void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1386int ahd_suspend(struct ahd_softc *ahd); 1387int ahd_resume(struct ahd_softc *ahd); 1388void ahd_softc_insert(struct ahd_softc *); 1389struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1390void ahd_set_unit(struct ahd_softc *, int); 1391void ahd_set_name(struct ahd_softc *, char *); 1392struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1393void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1394void ahd_alloc_scbs(struct ahd_softc *ahd); 1395void ahd_free(struct ahd_softc *ahd); 1396int ahd_reset(struct ahd_softc *ahd, int reinit); 1397void ahd_shutdown(void *arg); 1398int ahd_write_flexport(struct ahd_softc *ahd, 1399 u_int addr, u_int value); 1400int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1401 uint8_t *value); 1402int ahd_wait_flexport(struct ahd_softc *ahd); 1403 1404/*************************** Interrupt Services *******************************/ 1405void ahd_pci_intr(struct ahd_softc *ahd); 1406void ahd_clear_intstat(struct ahd_softc *ahd); 1407void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1408void ahd_run_qoutfifo(struct ahd_softc *ahd); 1409#ifdef AHD_TARGET_MODE 1410void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1411#endif 1412void ahd_handle_hwerrint(struct ahd_softc *ahd); 1413void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1414void ahd_handle_scsiint(struct ahd_softc *ahd, 1415 u_int intstat); 1416void ahd_clear_critical_section(struct ahd_softc *ahd); 1417 1418/***************************** Error Recovery *********************************/ 1419typedef enum { 1420 SEARCH_COMPLETE, 1421 SEARCH_COUNT, 1422 SEARCH_REMOVE, 1423 SEARCH_PRINT 1424} ahd_search_action; 1425int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1426 char channel, int lun, u_int tag, 1427 role_t role, uint32_t status, 1428 ahd_search_action action); 1429int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1430 char channel, int lun, u_int tag, 1431 int stop_on_first, int remove, 1432 int save_state); 1433void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1434int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1435 int initiate_reset); 1436int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1437 char channel, int lun, u_int tag, 1438 role_t role, uint32_t status); 1439void ahd_restart(struct ahd_softc *ahd); 1440void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1441void ahd_handle_scb_status(struct ahd_softc *ahd, 1442 struct scb *scb); 1443void ahd_handle_scsi_status(struct ahd_softc *ahd, 1444 struct scb *scb); 1445void ahd_calc_residual(struct ahd_softc *ahd, 1446 struct scb *scb); 1447void ahd_timeout(struct scb *scb); 1448void ahd_recover_commands(struct ahd_softc *ahd); 1449/*************************** Utility Functions ********************************/ 1450struct ahd_phase_table_entry* 1451 ahd_lookup_phase_entry(int phase); 1452void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1453 u_int our_id, u_int target, 1454 u_int lun, char channel, 1455 role_t role); 1456/************************** Transfer Negotiation ******************************/ 1457void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1458 u_int *ppr_options, u_int maxsync); 1459void ahd_validate_offset(struct ahd_softc *ahd, 1460 struct ahd_initiator_tinfo *tinfo, 1461 u_int period, u_int *offset, 1462 int wide, role_t role); 1463void ahd_validate_width(struct ahd_softc *ahd, 1464 struct ahd_initiator_tinfo *tinfo, 1465 u_int *bus_width, 1466 role_t role); 1467/* 1468 * Negotiation types. These are used to qualify if we should renegotiate 1469 * even if our goal and current transport parameters are identical. 1470 */ 1471typedef enum { 1472 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1473 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1474 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1475} ahd_neg_type; 1476int ahd_update_neg_request(struct ahd_softc*, 1477 struct ahd_devinfo*, 1478 struct ahd_tmode_tstate*, 1479 struct ahd_initiator_tinfo*, 1480 ahd_neg_type); 1481void ahd_set_width(struct ahd_softc *ahd, 1482 struct ahd_devinfo *devinfo, 1483 u_int width, u_int type, int paused); 1484void ahd_set_syncrate(struct ahd_softc *ahd, 1485 struct ahd_devinfo *devinfo, 1486 u_int period, u_int offset, 1487 u_int ppr_options, 1488 u_int type, int paused); 1489typedef enum { 1490 AHD_QUEUE_NONE, 1491 AHD_QUEUE_BASIC, 1492 AHD_QUEUE_TAGGED 1493} ahd_queue_alg; 1494 1495void ahd_set_tags(struct ahd_softc *ahd, 1496 struct ahd_devinfo *devinfo, 1497 ahd_queue_alg alg); 1498 1499/**************************** Target Mode *************************************/ 1500#ifdef AHD_TARGET_MODE 1501void ahd_send_lstate_events(struct ahd_softc *, 1502 struct ahd_tmode_lstate *); 1503void ahd_handle_en_lun(struct ahd_softc *ahd, 1504 struct cam_sim *sim, union ccb *ccb); 1505cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1506 struct cam_sim *sim, union ccb *ccb, 1507 struct ahd_tmode_tstate **tstate, 1508 struct ahd_tmode_lstate **lstate, 1509 int notfound_failure); 1510#ifndef AHD_TMODE_ENABLE 1511#define AHD_TMODE_ENABLE 0 1512#endif 1513#endif 1514/******************************* Debug ***************************************/ 1515#ifdef AHD_DEBUG 1516extern uint32_t ahd_debug; 1517#define AHD_SHOW_MISC 0x00001 1518#define AHD_SHOW_SENSE 0x00002 1519#define AHD_SHOW_RECOVERY 0x00004 1520#define AHD_DUMP_SEEPROM 0x00008 1521#define AHD_SHOW_TERMCTL 0x00010 1522#define AHD_SHOW_MEMORY 0x00020 1523#define AHD_SHOW_MESSAGES 0x00040 1524#define AHD_SHOW_MODEPTR 0x00080 1525#define AHD_SHOW_SELTO 0x00100 1526#define AHD_SHOW_FIFOS 0x00200 1527#define AHD_SHOW_QFULL 0x00400 1528#define AHD_SHOW_DV 0x00800 1529#define AHD_SHOW_MASKED_ERRORS 0x01000 1530#define AHD_SHOW_QUEUE 0x02000 1531#define AHD_SHOW_TQIN 0x04000 1532#define AHD_SHOW_SG 0x08000 1533#define AHD_SHOW_INT_COALESCING 0x10000 1534#define AHD_DEBUG_SEQUENCER 0x20000 1535#endif 1536void ahd_print_scb(struct scb *scb); 1537void ahd_print_devinfo(struct ahd_softc *ahd, 1538 struct ahd_devinfo *devinfo); 1539void ahd_dump_sglist(struct scb *scb); 1540void ahd_dump_all_cards_state(void); 1541void ahd_dump_card_state(struct ahd_softc *ahd); 1542int ahd_print_register(ahd_reg_parse_entry_t *table, 1543 u_int num_entries, 1544 const char *name, 1545 u_int address, 1546 u_int value, 1547 u_int *cur_column, 1548 u_int wrap_point); 1549void ahd_dump_scbs(struct ahd_softc *ahd); 1550#endif /* _AIC79XX_H_ */ 1551