aic79xx.h revision 119690
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#94 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 119690 2003-09-02 17:30:40Z jhb $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x8000 79#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82#define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84#define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86#define SCSIID_CHANNEL(ahd, scsiid) ('A') 87#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88#define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90#define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92#define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94#define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98#define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100#ifdef AHD_DEBUG 101#define SCB_IS_SILENT(scb) \ 102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 103 && (((scb)->flags & SCB_SILENT) != 0)) 104#else 105#define SCB_IS_SILENT(scb) \ 106 (((scb)->flags & SCB_SILENT) != 0) 107#endif 108/* 109 * TCLs have the following format: TTTTLLLLLLLL 110 */ 111#define TCL_TARGET_OFFSET(tcl) \ 112 ((((tcl) >> 4) & TID) >> 4) 113#define TCL_LUN(tcl) \ 114 (tcl & (AHD_NUM_LUNS - 1)) 115#define BUILD_TCL(scsiid, lun) \ 116 ((lun) | (((scsiid) & TID) << 4)) 117#define BUILD_TCL_RAW(target, channel, lun) \ 118 ((lun) | ((target) << 8)) 119 120#define SCB_GET_TAG(scb) \ 121 ahd_le16toh(scb->hscb->tag) 122 123#ifndef AHD_TARGET_MODE 124#undef AHD_TMODE_ENABLE 125#define AHD_TMODE_ENABLE 0 126#endif 127 128#define AHD_BUILD_COL_IDX(target, lun) \ 129 (((lun) << 4) | target) 130 131#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 133 134#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 135do { \ 136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 138} while (0) 139 140#define AHD_COPY_SCB_COL_IDX(dst, src) \ 141do { \ 142 dst->hscb->scsiid = src->hscb->scsiid; \ 143 dst->hscb->lun = src->hscb->lun; \ 144} while (0) 145 146#define AHD_NEVER_COL_IDX 0xFFFF 147 148/**************************** Driver Constants ********************************/ 149/* 150 * The maximum number of supported targets. 151 */ 152#define AHD_NUM_TARGETS 16 153 154/* 155 * The maximum number of supported luns. 156 * The identify message only supports 64 luns in non-packetized transfers. 157 * You can have 2^64 luns when information unit transfers are enabled, 158 * but until we see a need to support that many, we support 256. 159 */ 160#define AHD_NUM_LUNS_NONPKT 64 161#define AHD_NUM_LUNS 256 162 163/* 164 * The maximum transfer per S/G segment. 165 */ 166#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 167 168/* 169 * The maximum amount of SCB storage in hardware on a controller. 170 * This value represents an upper bound. Due to software design, 171 * we may not be able to use this number. 172 */ 173#define AHD_SCB_MAX 512 174 175/* 176 * The maximum number of concurrent transactions supported per driver instance. 177 * Sequencer Control Blocks (SCBs) store per-transaction information. 178 */ 179#define AHD_MAX_QUEUE AHD_SCB_MAX 180 181/* 182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 183 * in size and accommodate as many transactions as can be queued concurrently. 184 */ 185#define AHD_QIN_SIZE AHD_MAX_QUEUE 186#define AHD_QOUT_SIZE AHD_MAX_QUEUE 187 188#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 189/* 190 * The maximum amount of SCB storage we allocate in host memory. 191 */ 192#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 193 194/* 195 * Ring Buffer of incoming target commands. 196 * We allocate 256 to simplify the logic in the sequencer 197 * by using the natural wrap point of an 8bit counter. 198 */ 199#define AHD_TMODE_CMDS 256 200 201/* Reset line assertion time in us */ 202#define AHD_BUSRESET_DELAY 25 203 204/******************* Chip Characteristics/Operating Settings *****************/ 205/* 206 * Chip Type 207 * The chip order is from least sophisticated to most sophisticated. 208 */ 209typedef enum { 210 AHD_NONE = 0x0000, 211 AHD_CHIPID_MASK = 0x00FF, 212 AHD_AIC7901 = 0x0001, 213 AHD_AIC7902 = 0x0002, 214 AHD_AIC7901A = 0x0003, 215 AHD_PCI = 0x0100, /* Bus type PCI */ 216 AHD_PCIX = 0x0200, /* Bus type PCIX */ 217 AHD_BUS_MASK = 0x0F00 218} ahd_chip; 219 220/* 221 * Features available in each chip type. 222 */ 223typedef enum { 224 AHD_FENONE = 0x00000, 225 AHD_WIDE = 0x00001,/* Wide Channel */ 226 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 227 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 228 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 229 AHD_RTI = 0x04000,/* Retained Training Support */ 230 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 231 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 232 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 233 AHD_AIC7901_FE = AHD_FENONE, 234 AHD_AIC7901A_FE = AHD_FENONE, 235 AHD_AIC7902_FE = AHD_MULTI_FUNC 236} ahd_feature; 237 238/* 239 * Bugs in the silicon that we work around in software. 240 */ 241typedef enum { 242 AHD_BUGNONE = 0x0000, 243 /* 244 * Rev A hardware fails to update LAST/CURR/NEXTSCB 245 * correctly in certain packetized selection cases. 246 */ 247 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 248 /* The wrong SCB is accessed to check the abort pending bit. */ 249 AHD_ABORT_LQI_BUG = 0x0002, 250 /* Packetized bitbucket crosses packet boundaries. */ 251 AHD_PKT_BITBUCKET_BUG = 0x0004, 252 /* The selection timer runs twice as long as its setting. */ 253 AHD_LONG_SETIMO_BUG = 0x0008, 254 /* The Non-LQ CRC error status is delayed until phase change. */ 255 AHD_NLQICRC_DELAYED_BUG = 0x0010, 256 /* The chip must be reset for all outgoing bus resets. */ 257 AHD_SCSIRST_BUG = 0x0020, 258 /* Some PCIX fields must be saved and restored across chip reset. */ 259 AHD_PCIX_CHIPRST_BUG = 0x0040, 260 /* MMAPIO is not functional in PCI-X mode. */ 261 AHD_PCIX_MMAPIO_BUG = 0x0080, 262 /* Reads to SCBRAM fail to reset the discard timer. */ 263 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 264 /* Bug workarounds that can be disabled on non-PCIX busses. */ 265 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 266 | AHD_PCIX_MMAPIO_BUG 267 | AHD_PCIX_SCBRAM_RD_BUG, 268 /* 269 * LQOSTOP0 status set even for forced selections with ATN 270 * to perform non-packetized message delivery. 271 */ 272 AHD_LQO_ATNO_BUG = 0x0200, 273 /* FIFO auto-flush does not always trigger. */ 274 AHD_AUTOFLUSH_BUG = 0x0400, 275 /* The CLRLQO registers are not self-clearing. */ 276 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 277 /* The PACKETIZED status bit refers to the previous connection. */ 278 AHD_PKTIZED_STATUS_BUG = 0x1000, 279 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 280 AHD_PKT_LUN_BUG = 0x2000, 281 /* 282 * Only the FIFO allocated to the non-packetized connection may 283 * be in use during a non-packetzied connection. 284 */ 285 AHD_NONPACKFIFO_BUG = 0x4000, 286 /* 287 * Writing to a DFF SCBPTR register may fail if concurent with 288 * a hardware write to the other DFF SCBPTR register. This is 289 * not currently a concern in our sequencer since all chips with 290 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 291 * occur in non-packetized connections. 292 */ 293 AHD_MDFF_WSCBPTR_BUG = 0x8000, 294 /* SGHADDR updates are slow. */ 295 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 296 /* 297 * Changing the MODE_PTR coincident with an interrupt that 298 * switches to a different mode will cause the interrupt to 299 * be in the mode written outside of interrupt context. 300 */ 301 AHD_SET_MODE_BUG = 0x20000, 302 /* Non-packetized busfree revision does not work. */ 303 AHD_BUSFREEREV_BUG = 0x40000, 304 /* 305 * Paced transfers are indicated with a non-standard PPR 306 * option bit in the neg table, 160MHz is indicated by 307 * sync factor 0x7, and the offset if off by a factor of 2. 308 */ 309 AHD_PACED_NEGTABLE_BUG = 0x80000, 310 /* LQOOVERRUN false positives. */ 311 AHD_LQOOVERRUN_BUG = 0x100000, 312 /* 313 * Controller write to INTSTAT will lose to a host 314 * write to CLRINT. 315 */ 316 AHD_INTCOLLISION_BUG = 0x200000, 317 /* 318 * The GEM318 violates the SCSI spec by not waiting 319 * the mandated bus settle delay between phase changes 320 * in some situations. Some aic79xx chip revs. are more 321 * strict in this regard and will treat REQ assertions 322 * that fall within the bus settle delay window as 323 * glitches. This flag tells the firmware to tolerate 324 * early REQ assertions. 325 */ 326 AHD_EARLY_REQ_BUG = 0x400000, 327 /* 328 * The LED does not stay on long enough in packetized modes. 329 */ 330 AHD_FAINT_LED_BUG = 0x800000 331} ahd_bug; 332 333/* 334 * Configuration specific settings. 335 * The driver determines these settings by probing the 336 * chip/controller's configuration. 337 */ 338typedef enum { 339 AHD_FNONE = 0x00000, 340 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 341 AHD_USEDEFAULTS = 0x00004,/* 342 * For cards without an seeprom 343 * or a BIOS to initialize the chip's 344 * SRAM, we use the default target 345 * settings. 346 */ 347 AHD_SEQUENCER_DEBUG = 0x00008, 348 AHD_RESET_BUS_A = 0x00010, 349 AHD_EXTENDED_TRANS_A = 0x00020, 350 AHD_TERM_ENB_A = 0x00040, 351 AHD_SPCHK_ENB_A = 0x00080, 352 AHD_STPWLEVEL_A = 0x00100, 353 AHD_INITIATORROLE = 0x00200,/* 354 * Allow initiator operations on 355 * this controller. 356 */ 357 AHD_TARGETROLE = 0x00400,/* 358 * Allow target operations on this 359 * controller. 360 */ 361 AHD_RESOURCE_SHORTAGE = 0x00800, 362 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 363 AHD_INT50_SPEEDFLEX = 0x02000,/* 364 * Internal 50pin connector 365 * sits behind an aic3860 366 */ 367 AHD_BIOS_ENABLED = 0x04000, 368 AHD_ALL_INTERRUPTS = 0x08000, 369 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 370 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 371 AHD_CURRENT_SENSING = 0x40000, 372 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 373 AHD_HP_BOARD = 0x100000, 374 AHD_RESET_POLL_ACTIVE = 0x200000, 375 AHD_UPDATE_PEND_CMDS = 0x400000, 376 AHD_RUNNING_QOUTFIFO = 0x800000, 377 AHD_HAD_FIRST_SEL = 0x1000000 378} ahd_flag; 379 380/************************* Hardware SCB Definition ***************************/ 381 382/* 383 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 384 * consists of a "hardware SCB" mirroring the fields available on the card 385 * and additional information the kernel stores for each transaction. 386 * 387 * To minimize space utilization, a portion of the hardware scb stores 388 * different data during different portions of a SCSI transaction. 389 * As initialized by the host driver for the initiator role, this area 390 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 391 * the cdb has been presented to the target, this area serves to store 392 * residual transfer information and the SCSI status byte. 393 * For the target role, the contents of this area do not change, but 394 * still serve a different purpose than for the initiator role. See 395 * struct target_data for details. 396 */ 397 398/* 399 * Status information embedded in the shared poriton of 400 * an SCB after passing the cdb to the target. The kernel 401 * driver will only read this data for transactions that 402 * complete abnormally. 403 */ 404struct initiator_status { 405 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 406 uint32_t residual_sgptr; /* The next S/G for this transfer */ 407 uint8_t scsi_status; /* Standard SCSI status byte */ 408}; 409 410struct target_status { 411 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 412 uint32_t residual_sgptr; /* The next S/G for this transfer */ 413 uint8_t scsi_status; /* SCSI status to give to initiator */ 414 uint8_t target_phases; /* Bitmap of phases to execute */ 415 uint8_t data_phase; /* Data-In or Data-Out */ 416 uint8_t initiator_tag; /* Initiator's transaction tag */ 417}; 418 419/* 420 * Initiator mode SCB shared data area. 421 * If the embedded CDB is 12 bytes or less, we embed 422 * the sense buffer address in the SCB. This allows 423 * us to retrieve sense information without interrupting 424 * the host in packetized mode. 425 */ 426typedef uint32_t sense_addr_t; 427#define MAX_CDB_LEN 16 428#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 429union initiator_data { 430 struct { 431 uint64_t cdbptr; 432 uint8_t cdblen; 433 } cdb_from_host; 434 uint8_t cdb[MAX_CDB_LEN]; 435 struct { 436 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 437 sense_addr_t sense_addr; 438 } cdb_plus_saddr; 439}; 440 441/* 442 * Target mode version of the shared data SCB segment. 443 */ 444struct target_data { 445 uint32_t spare[2]; 446 uint8_t scsi_status; /* SCSI status to give to initiator */ 447 uint8_t target_phases; /* Bitmap of phases to execute */ 448 uint8_t data_phase; /* Data-In or Data-Out */ 449 uint8_t initiator_tag; /* Initiator's transaction tag */ 450}; 451 452struct hardware_scb { 453/*0*/ union { 454 union initiator_data idata; 455 struct target_data tdata; 456 struct initiator_status istatus; 457 struct target_status tstatus; 458 } shared_data; 459/* 460 * A word about residuals. 461 * The scb is presented to the sequencer with the dataptr and datacnt 462 * fields initialized to the contents of the first S/G element to 463 * transfer. The sgptr field is initialized to the bus address for 464 * the S/G element that follows the first in the in core S/G array 465 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 466 * S/G entry for this transfer (single S/G element transfer with the 467 * first elements address and length preloaded in the dataptr/datacnt 468 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 469 * The SG_FULL_RESID flag ensures that the residual will be correctly 470 * noted even if no data transfers occur. Once the data phase is entered, 471 * the residual sgptr and datacnt are loaded from the sgptr and the 472 * datacnt fields. After each S/G element's dataptr and length are 473 * loaded into the hardware, the residual sgptr is advanced. After 474 * each S/G element is expired, its datacnt field is checked to see 475 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 476 * residual sg ptr and the transfer is considered complete. If the 477 * sequencer determines that there is a residual in the tranfer, or 478 * there is non-zero status, it will set the SG_STATUS_VALID flag in 479 * sgptr and dma the scb back into host memory. To sumarize: 480 * 481 * Sequencer: 482 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 483 * or residual_sgptr does not have SG_LIST_NULL set. 484 * 485 * o We are transfering the last segment if residual_datacnt has 486 * the SG_LAST_SEG flag set. 487 * 488 * Host: 489 * o A residual can only have occurred if a completed scb has the 490 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 491 * the residual_datacnt, and the residual_sgptr field will tell 492 * for sure. 493 * 494 * o residual_sgptr and sgptr refer to the "next" sg entry 495 * and so may point beyond the last valid sg entry for the 496 * transfer. 497 */ 498#define SG_PTR_MASK 0xFFFFFFF8 499/*16*/ uint16_t tag; /* Reused by Sequencer. */ 500/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 501/*19*/ uint8_t scsiid; /* 502 * Selection out Id 503 * Our Id (bits 0-3) Their ID (bits 4-7) 504 */ 505/*20*/ uint8_t lun; 506/*21*/ uint8_t task_attribute; 507/*22*/ uint8_t cdb_len; 508/*23*/ uint8_t task_management; 509/*24*/ uint64_t dataptr; 510/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 511/*36*/ uint32_t sgptr; 512/*40*/ uint32_t hscb_busaddr; 513/*44*/ uint32_t next_hscb_busaddr; 514/********** Long lun field only downloaded for full 8 byte lun support ********/ 515/*48*/ uint8_t pkt_long_lun[8]; 516/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 517/*56*/ uint8_t spare[8]; 518}; 519 520/************************ Kernel SCB Definitions ******************************/ 521/* 522 * Some fields of the SCB are OS dependent. Here we collect the 523 * definitions for elements that all OS platforms need to include 524 * in there SCB definition. 525 */ 526 527/* 528 * Definition of a scatter/gather element as transfered to the controller. 529 * The aic7xxx chips only support a 24bit length. We use the top byte of 530 * the length to store additional address bits and a flag to indicate 531 * that a given segment terminates the transfer. This gives us an 532 * addressable range of 512GB on machines with 64bit PCI or with chips 533 * that can support dual address cycles on 32bit PCI busses. 534 */ 535struct ahd_dma_seg { 536 uint32_t addr; 537 uint32_t len; 538#define AHD_DMA_LAST_SEG 0x80000000 539#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 540#define AHD_SG_LEN_MASK 0x00FFFFFF 541}; 542 543struct ahd_dma64_seg { 544 uint64_t addr; 545 uint32_t len; 546 uint32_t pad; 547}; 548 549struct map_node { 550 bus_dmamap_t dmamap; 551 bus_addr_t physaddr; 552 uint8_t *vaddr; 553 SLIST_ENTRY(map_node) links; 554}; 555 556/* 557 * The current state of this SCB. 558 */ 559typedef enum { 560 SCB_FLAG_NONE = 0x00000, 561 SCB_TRANSMISSION_ERROR = 0x00001,/* 562 * We detected a parity or CRC 563 * error that has effected the 564 * payload of the command. This 565 * flag is checked when normal 566 * status is returned to catch 567 * the case of a target not 568 * responding to our attempt 569 * to report the error. 570 */ 571 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 572 * Another device was active 573 * during the first timeout for 574 * this SCB so we gave ourselves 575 * an additional timeout period 576 * in case it was hogging the 577 * bus. 578 */ 579 SCB_DEVICE_RESET = 0x00004, 580 SCB_SENSE = 0x00008, 581 SCB_CDB32_PTR = 0x00010, 582 SCB_RECOVERY_SCB = 0x00020, 583 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 584 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 585 SCB_ABORT = 0x00100, 586 SCB_ACTIVE = 0x00200, 587 SCB_TARGET_IMMEDIATE = 0x00400, 588 SCB_PACKETIZED = 0x00800, 589 SCB_EXPECT_PPR_BUSFREE = 0x01000, 590 SCB_PKT_SENSE = 0x02000, 591 SCB_CMDPHASE_ABORT = 0x04000, 592 SCB_ON_COL_LIST = 0x08000, 593 SCB_SILENT = 0x10000 /* 594 * Be quiet about transmission type 595 * errors. They are expected and we 596 * don't want to upset the user. This 597 * flag is typically used during DV. 598 */ 599} scb_flag; 600 601struct scb { 602 struct hardware_scb *hscb; 603 union { 604 SLIST_ENTRY(scb) sle; 605 LIST_ENTRY(scb) le; 606 TAILQ_ENTRY(scb) tqe; 607 } links; 608 union { 609 SLIST_ENTRY(scb) sle; 610 LIST_ENTRY(scb) le; 611 TAILQ_ENTRY(scb) tqe; 612 } links2; 613#define pending_links links2.le 614#define collision_links links2.le 615 struct scb *col_scb; 616 ahd_io_ctx_t io_ctx; 617 struct ahd_softc *ahd_softc; 618 scb_flag flags; 619#ifndef __linux__ 620 bus_dmamap_t dmamap; 621#endif 622 struct scb_platform_data *platform_data; 623 struct map_node *hscb_map; 624 struct map_node *sg_map; 625 struct map_node *sense_map; 626 void *sg_list; 627 uint8_t *sense_data; 628 bus_addr_t sg_list_busaddr; 629 bus_addr_t sense_busaddr; 630 u_int sg_count;/* How full ahd_dma_seg is */ 631#define AHD_MAX_LQ_CRC_ERRORS 5 632 u_int crc_retry_count; 633}; 634 635TAILQ_HEAD(scb_tailq, scb); 636LIST_HEAD(scb_list, scb); 637 638struct scb_data { 639 /* 640 * TAILQ of lists of free SCBs grouped by device 641 * collision domains. 642 */ 643 struct scb_tailq free_scbs; 644 645 /* 646 * Per-device lists of SCBs whose tag ID would collide 647 * with an already active tag on the device. 648 */ 649 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 650 651 /* 652 * SCBs that will not collide with any active device. 653 */ 654 struct scb_list any_dev_free_scb_list; 655 656 /* 657 * Mapping from tag to SCB. 658 */ 659 struct scb *scbindex[AHD_SCB_MAX]; 660 661 /* 662 * "Bus" addresses of our data structures. 663 */ 664 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 665 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 666 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 667 SLIST_HEAD(, map_node) hscb_maps; 668 SLIST_HEAD(, map_node) sg_maps; 669 SLIST_HEAD(, map_node) sense_maps; 670 int scbs_left; /* unallocated scbs in head map_node */ 671 int sgs_left; /* unallocated sgs in head map_node */ 672 int sense_left; /* unallocated sense in head map_node */ 673 uint16_t numscbs; 674 uint16_t maxhscbs; /* Number of SCBs on the card */ 675 uint8_t init_level; /* 676 * How far we've initialized 677 * this structure. 678 */ 679}; 680 681/************************ Target Mode Definitions *****************************/ 682 683/* 684 * Connection desciptor for select-in requests in target mode. 685 */ 686struct target_cmd { 687 uint8_t scsiid; /* Our ID and the initiator's ID */ 688 uint8_t identify; /* Identify message */ 689 uint8_t bytes[22]; /* 690 * Bytes contains any additional message 691 * bytes terminated by 0xFF. The remainder 692 * is the cdb to execute. 693 */ 694 uint8_t cmd_valid; /* 695 * When a command is complete, the firmware 696 * will set cmd_valid to all bits set. 697 * After the host has seen the command, 698 * the bits are cleared. This allows us 699 * to just peek at host memory to determine 700 * if more work is complete. cmd_valid is on 701 * an 8 byte boundary to simplify setting 702 * it on aic7880 hardware which only has 703 * limited direct access to the DMA FIFO. 704 */ 705 uint8_t pad[7]; 706}; 707 708/* 709 * Number of events we can buffer up if we run out 710 * of immediate notify ccbs. 711 */ 712#define AHD_TMODE_EVENT_BUFFER_SIZE 8 713struct ahd_tmode_event { 714 uint8_t initiator_id; 715 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 716#define EVENT_TYPE_BUS_RESET 0xFF 717 uint8_t event_arg; 718}; 719 720/* 721 * Per enabled lun target mode state. 722 * As this state is directly influenced by the host OS'es target mode 723 * environment, we let the OS module define it. Forward declare the 724 * structure here so we can store arrays of them, etc. in OS neutral 725 * data structures. 726 */ 727#ifdef AHD_TARGET_MODE 728struct ahd_tmode_lstate { 729 struct cam_path *path; 730 struct ccb_hdr_slist accept_tios; 731 struct ccb_hdr_slist immed_notifies; 732 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 733 uint8_t event_r_idx; 734 uint8_t event_w_idx; 735}; 736#else 737struct ahd_tmode_lstate; 738#endif 739 740/******************** Transfer Negotiation Datastructures *********************/ 741#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 742#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 743#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 744#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 745#define AHD_PERIOD_10MHz 0x19 746 747#define AHD_WIDTH_UNKNOWN 0xFF 748#define AHD_PERIOD_UNKNOWN 0xFF 749#define AHD_OFFSET_UNKNOWN 0xFF 750#define AHD_PPR_OPTS_UNKNOWN 0xFF 751 752/* 753 * Transfer Negotiation Information. 754 */ 755struct ahd_transinfo { 756 uint8_t protocol_version; /* SCSI Revision level */ 757 uint8_t transport_version; /* SPI Revision level */ 758 uint8_t width; /* Bus width */ 759 uint8_t period; /* Sync rate factor */ 760 uint8_t offset; /* Sync offset */ 761 uint8_t ppr_options; /* Parallel Protocol Request options */ 762}; 763 764/* 765 * Per-initiator current, goal and user transfer negotiation information. */ 766struct ahd_initiator_tinfo { 767 struct ahd_transinfo curr; 768 struct ahd_transinfo goal; 769 struct ahd_transinfo user; 770}; 771 772/* 773 * Per enabled target ID state. 774 * Pointers to lun target state as well as sync/wide negotiation information 775 * for each initiator<->target mapping. For the initiator role we pretend 776 * that we are the target and the targets are the initiators since the 777 * negotiation is the same regardless of role. 778 */ 779struct ahd_tmode_tstate { 780 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 781 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 782 783 /* 784 * Per initiator state bitmasks. 785 */ 786 uint16_t auto_negotiate;/* Auto Negotiation Required */ 787 uint16_t discenable; /* Disconnection allowed */ 788 uint16_t tagenable; /* Tagged Queuing allowed */ 789}; 790 791/* 792 * Points of interest along the negotiated transfer scale. 793 */ 794#define AHD_SYNCRATE_160 0x8 795#define AHD_SYNCRATE_PACED 0x8 796#define AHD_SYNCRATE_DT 0x9 797#define AHD_SYNCRATE_ULTRA2 0xa 798#define AHD_SYNCRATE_ULTRA 0xc 799#define AHD_SYNCRATE_FAST 0x19 800#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 801#define AHD_SYNCRATE_SYNC 0x32 802#define AHD_SYNCRATE_MIN 0x60 803#define AHD_SYNCRATE_ASYNC 0xFF 804#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 805 806/* Safe and valid period for async negotiations. */ 807#define AHD_ASYNC_XFER_PERIOD 0x44 808 809/* 810 * In RevA, the synctable uses a 120MHz rate for the period 811 * factor 8 and 160MHz for the period factor 7. The 120MHz 812 * rate never made it into the official SCSI spec, so we must 813 * compensate when setting the negotiation table for Rev A 814 * parts. 815 */ 816#define AHD_SYNCRATE_REVA_120 0x8 817#define AHD_SYNCRATE_REVA_160 0x7 818 819/***************************** Lookup Tables **********************************/ 820/* 821 * Phase -> name and message out response 822 * to parity errors in each phase table. 823 */ 824struct ahd_phase_table_entry { 825 uint8_t phase; 826 uint8_t mesg_out; /* Message response to parity errors */ 827 char *phasemsg; 828}; 829 830/************************** Serial EEPROM Format ******************************/ 831 832struct seeprom_config { 833/* 834 * Per SCSI ID Configuration Flags 835 */ 836 uint16_t device_flags[16]; /* words 0-15 */ 837#define CFXFER 0x003F /* synchronous transfer rate */ 838#define CFXFER_ASYNC 0x3F 839#define CFQAS 0x0040 /* Negotiate QAS */ 840#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 841#define CFSTART 0x0100 /* send start unit SCSI command */ 842#define CFINCBIOS 0x0200 /* include in BIOS scan */ 843#define CFDISC 0x0400 /* enable disconnection */ 844#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 845#define CFWIDEB 0x1000 /* wide bus device */ 846#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 847 848/* 849 * BIOS Control Bits 850 */ 851 uint16_t bios_control; /* word 16 */ 852#define CFSUPREM 0x0001 /* support all removeable drives */ 853#define CFSUPREMB 0x0002 /* support removeable boot drives */ 854#define CFBIOSSTATE 0x000C /* BIOS Action State */ 855#define CFBS_DISABLED 0x00 856#define CFBS_ENABLED 0x04 857#define CFBS_DISABLED_SCAN 0x08 858#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 859#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 860#define CFSPARITY 0x0040 /* SCSI parity */ 861#define CFEXTEND 0x0080 /* extended translation enabled */ 862#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 863#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 864#define CFMSG_VERBOSE 0x0000 865#define CFMSG_SILENT 0x0200 866#define CFMSG_DIAG 0x0400 867#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 868/* UNUSED 0xf000 */ 869 870/* 871 * Host Adapter Control Bits 872 */ 873 uint16_t adapter_control; /* word 17 */ 874#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 875#define CFSTERM 0x0002 /* SCSI low byte termination */ 876#define CFWSTERM 0x0004 /* SCSI high byte termination */ 877#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 878#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 879#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 880#define CFSTPWLEVEL 0x0040 /* Termination level control */ 881#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 882#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 883#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 884 885/* 886 * Bus Release Time, Host Adapter ID 887 */ 888 uint16_t brtime_id; /* word 18 */ 889#define CFSCSIID 0x000f /* host adapter SCSI ID */ 890/* UNUSED 0x00f0 */ 891#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 892 893/* 894 * Maximum targets 895 */ 896 uint16_t max_targets; /* word 19 */ 897#define CFMAXTARG 0x00ff /* maximum targets */ 898#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 899#define CFBOOTID 0xf000 /* Target to boot from */ 900 uint16_t res_1[10]; /* words 20-29 */ 901 uint16_t signature; /* BIOS Signature */ 902#define CFSIGNATURE 0x400 903 uint16_t checksum; /* word 31 */ 904}; 905 906/* 907 * Vital Product Data used during POST and by the BIOS. 908 */ 909struct vpd_config { 910 uint8_t bios_flags; 911#define VPDMASTERBIOS 0x0001 912#define VPDBOOTHOST 0x0002 913 uint8_t reserved_1[21]; 914 uint8_t resource_type; 915 uint8_t resource_len[2]; 916 uint8_t resource_data[8]; 917 uint8_t vpd_tag; 918 uint16_t vpd_len; 919 uint8_t vpd_keyword[2]; 920 uint8_t length; 921 uint8_t revision; 922 uint8_t device_flags; 923 uint8_t termnation_menus[2]; 924 uint8_t fifo_threshold; 925 uint8_t end_tag; 926 uint8_t vpd_checksum; 927 uint16_t default_target_flags; 928 uint16_t default_bios_flags; 929 uint16_t default_ctrl_flags; 930 uint8_t default_irq; 931 uint8_t pci_lattime; 932 uint8_t max_target; 933 uint8_t boot_lun; 934 uint16_t signature; 935 uint8_t reserved_2; 936 uint8_t checksum; 937 uint8_t reserved_3[4]; 938}; 939 940/****************************** Flexport Logic ********************************/ 941#define FLXADDR_TERMCTL 0x0 942#define FLX_TERMCTL_ENSECHIGH 0x8 943#define FLX_TERMCTL_ENSECLOW 0x4 944#define FLX_TERMCTL_ENPRIHIGH 0x2 945#define FLX_TERMCTL_ENPRILOW 0x1 946#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 947#define FLX_ROMSTAT_SEECFG 0xF0 948#define FLX_ROMSTAT_EECFG 0x0F 949#define FLX_ROMSTAT_SEE_93C66 0x00 950#define FLX_ROMSTAT_SEE_NONE 0xF0 951#define FLX_ROMSTAT_EE_512x8 0x0 952#define FLX_ROMSTAT_EE_1MBx8 0x1 953#define FLX_ROMSTAT_EE_2MBx8 0x2 954#define FLX_ROMSTAT_EE_4MBx8 0x3 955#define FLX_ROMSTAT_EE_16MBx8 0x4 956#define CURSENSE_ENB 0x1 957#define FLXADDR_FLEXSTAT 0x2 958#define FLX_FSTAT_BUSY 0x1 959#define FLXADDR_CURRENT_STAT 0x4 960#define FLX_CSTAT_SEC_HIGH 0xC0 961#define FLX_CSTAT_SEC_LOW 0x30 962#define FLX_CSTAT_PRI_HIGH 0x0C 963#define FLX_CSTAT_PRI_LOW 0x03 964#define FLX_CSTAT_MASK 0x03 965#define FLX_CSTAT_SHIFT 2 966#define FLX_CSTAT_OKAY 0x0 967#define FLX_CSTAT_OVER 0x1 968#define FLX_CSTAT_UNDER 0x2 969#define FLX_CSTAT_INVALID 0x3 970 971int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 972 u_int start_addr, u_int count, int bstream); 973 974int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 975 u_int start_addr, u_int count); 976int ahd_wait_seeprom(struct ahd_softc *ahd); 977int ahd_verify_vpd_cksum(struct vpd_config *vpd); 978int ahd_verify_cksum(struct seeprom_config *sc); 979int ahd_acquire_seeprom(struct ahd_softc *ahd); 980void ahd_release_seeprom(struct ahd_softc *ahd); 981 982/**************************** Message Buffer *********************************/ 983typedef enum { 984 MSG_FLAG_NONE = 0x00, 985 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 986 MSG_FLAG_IU_REQ_CHANGED = 0x02, 987 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 988 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 989 MSG_FLAG_PACKETIZED = 0x10 990} ahd_msg_flags; 991 992typedef enum { 993 MSG_TYPE_NONE = 0x00, 994 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 995 MSG_TYPE_INITIATOR_MSGIN = 0x02, 996 MSG_TYPE_TARGET_MSGOUT = 0x03, 997 MSG_TYPE_TARGET_MSGIN = 0x04 998} ahd_msg_type; 999 1000typedef enum { 1001 MSGLOOP_IN_PROG, 1002 MSGLOOP_MSGCOMPLETE, 1003 MSGLOOP_TERMINATED 1004} msg_loop_stat; 1005 1006/*********************** Software Configuration Structure *********************/ 1007struct ahd_suspend_channel_state { 1008 uint8_t scsiseq; 1009 uint8_t sxfrctl0; 1010 uint8_t sxfrctl1; 1011 uint8_t simode0; 1012 uint8_t simode1; 1013 uint8_t seltimer; 1014 uint8_t seqctl; 1015}; 1016 1017struct ahd_suspend_state { 1018 struct ahd_suspend_channel_state channel[2]; 1019 uint8_t optionmode; 1020 uint8_t dscommand0; 1021 uint8_t dspcistatus; 1022 /* hsmailbox */ 1023 uint8_t crccontrol1; 1024 uint8_t scbbaddr; 1025 /* Host and sequencer SCB counts */ 1026 uint8_t dff_thrsh; 1027 uint8_t *scratch_ram; 1028 uint8_t *btt; 1029}; 1030 1031typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1032 1033typedef enum { 1034 AHD_MODE_DFF0, 1035 AHD_MODE_DFF1, 1036 AHD_MODE_CCHAN, 1037 AHD_MODE_SCSI, 1038 AHD_MODE_CFG, 1039 AHD_MODE_UNKNOWN 1040} ahd_mode; 1041 1042#define AHD_MK_MSK(x) (0x01 << (x)) 1043#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1044#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1045#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1046#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1047#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1048#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1049#define AHD_MODE_ANY_MSK (~0) 1050 1051typedef uint8_t ahd_mode_state; 1052 1053typedef void ahd_callback_t (void *); 1054 1055struct ahd_softc { 1056 bus_space_tag_t tags[2]; 1057 bus_space_handle_t bshs[2]; 1058#ifndef __linux__ 1059 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1060#endif 1061 struct scb_data scb_data; 1062 1063 struct hardware_scb *next_queued_hscb; 1064 1065 /* 1066 * SCBs that have been sent to the controller 1067 */ 1068 LIST_HEAD(, scb) pending_scbs; 1069 1070 /* 1071 * Current register window mode information. 1072 */ 1073 ahd_mode dst_mode; 1074 ahd_mode src_mode; 1075 1076 /* 1077 * Saved register window mode information 1078 * used for restore on next unpause. 1079 */ 1080 ahd_mode saved_dst_mode; 1081 ahd_mode saved_src_mode; 1082 1083 /* 1084 * Platform specific data. 1085 */ 1086 struct ahd_platform_data *platform_data; 1087 1088 /* 1089 * Platform specific device information. 1090 */ 1091 ahd_dev_softc_t dev_softc; 1092 1093 /* 1094 * Bus specific device information. 1095 */ 1096 ahd_bus_intr_t bus_intr; 1097 1098 /* 1099 * Target mode related state kept on a per enabled lun basis. 1100 * Targets that are not enabled will have null entries. 1101 * As an initiator, we keep one target entry for our initiator 1102 * ID to store our sync/wide transfer settings. 1103 */ 1104 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1105 1106 /* 1107 * The black hole device responsible for handling requests for 1108 * disabled luns on enabled targets. 1109 */ 1110 struct ahd_tmode_lstate *black_hole; 1111 1112 /* 1113 * Device instance currently on the bus awaiting a continue TIO 1114 * for a command that was not given the disconnect priveledge. 1115 */ 1116 struct ahd_tmode_lstate *pending_device; 1117 1118 /* 1119 * Timer handles for timer driven callbacks. 1120 */ 1121 ahd_timer_t reset_timer; 1122 ahd_timer_t stat_timer; 1123 1124 /* 1125 * Statistics. 1126 */ 1127#define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1128#define AHD_STAT_BUCKETS 4 1129 u_int cmdcmplt_bucket; 1130 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1131 uint32_t cmdcmplt_total; 1132 1133 /* 1134 * Card characteristics 1135 */ 1136 ahd_chip chip; 1137 ahd_feature features; 1138 ahd_bug bugs; 1139 ahd_flag flags; 1140 struct seeprom_config *seep_config; 1141 1142 /* Values to store in the SEQCTL register for pause and unpause */ 1143 uint8_t unpause; 1144 uint8_t pause; 1145 1146 /* Command Queues */ 1147 uint16_t qoutfifonext; 1148 uint16_t qoutfifonext_valid_tag; 1149 uint16_t qinfifonext; 1150 uint16_t qinfifo[AHD_SCB_MAX]; 1151 uint16_t *qoutfifo; 1152 1153 /* Critical Section Data */ 1154 struct cs *critical_sections; 1155 u_int num_critical_sections; 1156 1157 /* Buffer for handling packetized bitbucket. */ 1158 uint8_t *overrun_buf; 1159 1160 /* Links for chaining softcs */ 1161 TAILQ_ENTRY(ahd_softc) links; 1162 1163 /* Channel Names ('A', 'B', etc.) */ 1164 char channel; 1165 1166 /* Initiator Bus ID */ 1167 uint8_t our_id; 1168 1169 /* 1170 * Target incoming command FIFO. 1171 */ 1172 struct target_cmd *targetcmds; 1173 uint8_t tqinfifonext; 1174 1175 /* 1176 * Cached verson of the hs_mailbox so we can avoid 1177 * pausing the sequencer during mailbox updates. 1178 */ 1179 uint8_t hs_mailbox; 1180 1181 /* 1182 * Incoming and outgoing message handling. 1183 */ 1184 uint8_t send_msg_perror; 1185 ahd_msg_flags msg_flags; 1186 ahd_msg_type msg_type; 1187 uint8_t msgout_buf[12];/* Message we are sending */ 1188 uint8_t msgin_buf[12];/* Message we are receiving */ 1189 u_int msgout_len; /* Length of message to send */ 1190 u_int msgout_index; /* Current index in msgout */ 1191 u_int msgin_index; /* Current index in msgin */ 1192 1193 /* 1194 * Mapping information for data structures shared 1195 * between the sequencer and kernel. 1196 */ 1197 bus_dma_tag_t parent_dmat; 1198 bus_dma_tag_t shared_data_dmat; 1199 bus_dmamap_t shared_data_dmamap; 1200 bus_addr_t shared_data_busaddr; 1201 1202 /* Information saved through suspend/resume cycles */ 1203 struct ahd_suspend_state suspend_state; 1204 1205 /* Number of enabled target mode device on this card */ 1206 u_int enabled_luns; 1207 1208 /* Initialization level of this data structure */ 1209 u_int init_level; 1210 1211 /* PCI cacheline size. */ 1212 u_int pci_cachesize; 1213 1214 /* IO Cell Parameters */ 1215 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1216 1217 u_int stack_size; 1218 uint16_t *saved_stack; 1219 1220 /* Per-Unit descriptive information */ 1221 const char *description; 1222 const char *bus_description; 1223 char *name; 1224 int unit; 1225 1226 /* Selection Timer settings */ 1227 int seltime; 1228 1229 /* 1230 * Interrupt coalescing settings. 1231 */ 1232#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1233#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1234#define AHD_INT_COALESCING_MAXCMDS_MAX 127 1235#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1236#define AHD_INT_COALESCING_MINCMDS_MAX 127 1237#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1238#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1239 u_int int_coalescing_timer; 1240 u_int int_coalescing_maxcmds; 1241 u_int int_coalescing_mincmds; 1242 u_int int_coalescing_threshold; 1243 u_int int_coalescing_stop_threshold; 1244 1245 uint16_t user_discenable;/* Disconnection allowed */ 1246 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1247}; 1248 1249TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1250extern struct ahd_softc_tailq ahd_tailq; 1251 1252/*************************** IO Cell Configuration ****************************/ 1253#define AHD_PRECOMP_SLEW_INDEX \ 1254 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1255 1256#define AHD_AMPLITUDE_INDEX \ 1257 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1258 1259#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1260do { \ 1261 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1262 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1263 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1264} while (0) 1265 1266#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1267do { \ 1268 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1269 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1270 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1271} while (0) 1272 1273#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1274do { \ 1275 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1276 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1277 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1278} while (0) 1279 1280/************************ Active Device Information ***************************/ 1281typedef enum { 1282 ROLE_UNKNOWN, 1283 ROLE_INITIATOR, 1284 ROLE_TARGET 1285} role_t; 1286 1287struct ahd_devinfo { 1288 int our_scsiid; 1289 int target_offset; 1290 uint16_t target_mask; 1291 u_int target; 1292 u_int lun; 1293 char channel; 1294 role_t role; /* 1295 * Only guaranteed to be correct if not 1296 * in the busfree state. 1297 */ 1298}; 1299 1300/****************************** PCI Structures ********************************/ 1301#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ 1302#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ 1303#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ 1304 1305typedef int (ahd_device_setup_t)(struct ahd_softc *); 1306 1307struct ahd_pci_identity { 1308 uint64_t full_id; 1309 uint64_t id_mask; 1310 char *name; 1311 ahd_device_setup_t *setup; 1312}; 1313extern struct ahd_pci_identity ahd_pci_ident_table []; 1314extern const u_int ahd_num_pci_devs; 1315 1316/***************************** VL/EISA Declarations ***************************/ 1317struct aic7770_identity { 1318 uint32_t full_id; 1319 uint32_t id_mask; 1320 char *name; 1321 ahd_device_setup_t *setup; 1322}; 1323extern struct aic7770_identity aic7770_ident_table []; 1324extern const int ahd_num_aic7770_devs; 1325 1326#define AHD_EISA_SLOT_OFFSET 0xc00 1327#define AHD_EISA_IOSIZE 0x100 1328 1329/*************************** Function Declarations ****************************/ 1330/******************************************************************************/ 1331void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1332u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1333void ahd_busy_tcl(struct ahd_softc *ahd, 1334 u_int tcl, u_int busyid); 1335static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1336static __inline void 1337ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1338{ 1339 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1340} 1341 1342/***************************** PCI Front End *********************************/ 1343struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1344int ahd_pci_config(struct ahd_softc *, 1345 struct ahd_pci_identity *); 1346int ahd_pci_test_register_access(struct ahd_softc *); 1347 1348/************************** SCB and SCB queue management **********************/ 1349int ahd_probe_scbs(struct ahd_softc *); 1350void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1351 struct scb *scb); 1352int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1353 int target, char channel, int lun, 1354 u_int tag, role_t role); 1355 1356/****************************** Initialization ********************************/ 1357struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1358int ahd_softc_init(struct ahd_softc *); 1359void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1360int ahd_init(struct ahd_softc *ahd); 1361int ahd_default_config(struct ahd_softc *ahd); 1362int ahd_parse_vpddata(struct ahd_softc *ahd, 1363 struct vpd_config *vpd); 1364int ahd_parse_cfgdata(struct ahd_softc *ahd, 1365 struct seeprom_config *sc); 1366void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1367void ahd_update_coalescing_values(struct ahd_softc *ahd, 1368 u_int timer, 1369 u_int maxcmds, 1370 u_int mincmds); 1371void ahd_enable_coalescing(struct ahd_softc *ahd, 1372 int enable); 1373void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1374int ahd_suspend(struct ahd_softc *ahd); 1375int ahd_resume(struct ahd_softc *ahd); 1376void ahd_softc_insert(struct ahd_softc *); 1377struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1378void ahd_set_unit(struct ahd_softc *, int); 1379void ahd_set_name(struct ahd_softc *, char *); 1380struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1381void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1382void ahd_alloc_scbs(struct ahd_softc *ahd); 1383void ahd_free(struct ahd_softc *ahd); 1384int ahd_reset(struct ahd_softc *ahd, int reinit); 1385void ahd_shutdown(void *arg); 1386int ahd_write_flexport(struct ahd_softc *ahd, 1387 u_int addr, u_int value); 1388int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1389 uint8_t *value); 1390int ahd_wait_flexport(struct ahd_softc *ahd); 1391 1392/*************************** Interrupt Services *******************************/ 1393void ahd_pci_intr(struct ahd_softc *ahd); 1394void ahd_clear_intstat(struct ahd_softc *ahd); 1395void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1396void ahd_run_qoutfifo(struct ahd_softc *ahd); 1397#ifdef AHD_TARGET_MODE 1398void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1399#endif 1400void ahd_handle_hwerrint(struct ahd_softc *ahd); 1401void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1402void ahd_handle_scsiint(struct ahd_softc *ahd, 1403 u_int intstat); 1404void ahd_clear_critical_section(struct ahd_softc *ahd); 1405 1406/***************************** Error Recovery *********************************/ 1407typedef enum { 1408 SEARCH_COMPLETE, 1409 SEARCH_COUNT, 1410 SEARCH_REMOVE, 1411 SEARCH_PRINT 1412} ahd_search_action; 1413int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1414 char channel, int lun, u_int tag, 1415 role_t role, uint32_t status, 1416 ahd_search_action action); 1417int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1418 char channel, int lun, u_int tag, 1419 int stop_on_first, int remove, 1420 int save_state); 1421void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1422int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1423 int initiate_reset); 1424int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1425 char channel, int lun, u_int tag, 1426 role_t role, uint32_t status); 1427void ahd_restart(struct ahd_softc *ahd); 1428void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1429void ahd_handle_scb_status(struct ahd_softc *ahd, 1430 struct scb *scb); 1431void ahd_handle_scsi_status(struct ahd_softc *ahd, 1432 struct scb *scb); 1433void ahd_calc_residual(struct ahd_softc *ahd, 1434 struct scb *scb); 1435/*************************** Utility Functions ********************************/ 1436struct ahd_phase_table_entry* 1437 ahd_lookup_phase_entry(int phase); 1438void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1439 u_int our_id, u_int target, 1440 u_int lun, char channel, 1441 role_t role); 1442/************************** Transfer Negotiation ******************************/ 1443void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1444 u_int *ppr_options, u_int maxsync); 1445void ahd_validate_offset(struct ahd_softc *ahd, 1446 struct ahd_initiator_tinfo *tinfo, 1447 u_int period, u_int *offset, 1448 int wide, role_t role); 1449void ahd_validate_width(struct ahd_softc *ahd, 1450 struct ahd_initiator_tinfo *tinfo, 1451 u_int *bus_width, 1452 role_t role); 1453/* 1454 * Negotiation types. These are used to qualify if we should renegotiate 1455 * even if our goal and current transport parameters are identical. 1456 */ 1457typedef enum { 1458 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1459 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1460 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1461} ahd_neg_type; 1462int ahd_update_neg_request(struct ahd_softc*, 1463 struct ahd_devinfo*, 1464 struct ahd_tmode_tstate*, 1465 struct ahd_initiator_tinfo*, 1466 ahd_neg_type); 1467void ahd_set_width(struct ahd_softc *ahd, 1468 struct ahd_devinfo *devinfo, 1469 u_int width, u_int type, int paused); 1470void ahd_set_syncrate(struct ahd_softc *ahd, 1471 struct ahd_devinfo *devinfo, 1472 u_int period, u_int offset, 1473 u_int ppr_options, 1474 u_int type, int paused); 1475typedef enum { 1476 AHD_QUEUE_NONE, 1477 AHD_QUEUE_BASIC, 1478 AHD_QUEUE_TAGGED 1479} ahd_queue_alg; 1480 1481void ahd_set_tags(struct ahd_softc *ahd, 1482 struct ahd_devinfo *devinfo, 1483 ahd_queue_alg alg); 1484 1485/**************************** Target Mode *************************************/ 1486#ifdef AHD_TARGET_MODE 1487void ahd_send_lstate_events(struct ahd_softc *, 1488 struct ahd_tmode_lstate *); 1489void ahd_handle_en_lun(struct ahd_softc *ahd, 1490 struct cam_sim *sim, union ccb *ccb); 1491cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1492 struct cam_sim *sim, union ccb *ccb, 1493 struct ahd_tmode_tstate **tstate, 1494 struct ahd_tmode_lstate **lstate, 1495 int notfound_failure); 1496#ifndef AHD_TMODE_ENABLE 1497#define AHD_TMODE_ENABLE 0 1498#endif 1499#endif 1500/******************************* Debug ***************************************/ 1501#ifdef AHD_DEBUG 1502extern uint32_t ahd_debug; 1503#define AHD_SHOW_MISC 0x00001 1504#define AHD_SHOW_SENSE 0x00002 1505#define AHD_SHOW_RECOVERY 0x00004 1506#define AHD_DUMP_SEEPROM 0x00008 1507#define AHD_SHOW_TERMCTL 0x00010 1508#define AHD_SHOW_MEMORY 0x00020 1509#define AHD_SHOW_MESSAGES 0x00040 1510#define AHD_SHOW_MODEPTR 0x00080 1511#define AHD_SHOW_SELTO 0x00100 1512#define AHD_SHOW_FIFOS 0x00200 1513#define AHD_SHOW_QFULL 0x00400 1514#define AHD_SHOW_DV 0x00800 1515#define AHD_SHOW_MASKED_ERRORS 0x01000 1516#define AHD_SHOW_QUEUE 0x02000 1517#define AHD_SHOW_TQIN 0x04000 1518#define AHD_SHOW_SG 0x08000 1519#define AHD_SHOW_INT_COALESCING 0x10000 1520#define AHD_DEBUG_SEQUENCER 0x20000 1521#endif 1522void ahd_print_scb(struct scb *scb); 1523void ahd_print_devinfo(struct ahd_softc *ahd, 1524 struct ahd_devinfo *devinfo); 1525void ahd_dump_sglist(struct scb *scb); 1526void ahd_dump_all_cards_state(void); 1527void ahd_dump_card_state(struct ahd_softc *ahd); 1528int ahd_print_register(ahd_reg_parse_entry_t *table, 1529 u_int num_entries, 1530 const char *name, 1531 u_int address, 1532 u_int value, 1533 u_int *cur_column, 1534 u_int wrap_point); 1535void ahd_dump_scbs(struct ahd_softc *ahd); 1536#endif /* _AIC79XX_H_ */ 1537