aic79xx.h revision 114623
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#89 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 114623 2003-05-04 00:20:07Z gibbs $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x8000 79#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82#define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84#define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86#define SCSIID_CHANNEL(ahd, scsiid) ('A') 87#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88#define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90#define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92#define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94#define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98#define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100#ifdef AHD_DEBUG 101#define SCB_IS_SILENT(scb) \ 102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 103 && (((scb)->flags & SCB_SILENT) != 0)) 104#else 105#define SCB_IS_SILENT(scb) \ 106 (((scb)->flags & SCB_SILENT) != 0) 107#endif 108/* 109 * TCLs have the following format: TTTTLLLLLLLL 110 */ 111#define TCL_TARGET_OFFSET(tcl) \ 112 ((((tcl) >> 4) & TID) >> 4) 113#define TCL_LUN(tcl) \ 114 (tcl & (AHD_NUM_LUNS - 1)) 115#define BUILD_TCL(scsiid, lun) \ 116 ((lun) | (((scsiid) & TID) << 4)) 117#define BUILD_TCL_RAW(target, channel, lun) \ 118 ((lun) | ((target) << 8)) 119 120#define SCB_GET_TAG(scb) \ 121 ahd_le16toh(scb->hscb->tag) 122 123#ifndef AHD_TARGET_MODE 124#undef AHD_TMODE_ENABLE 125#define AHD_TMODE_ENABLE 0 126#endif 127 128#define AHD_BUILD_COL_IDX(target, lun) \ 129 (((lun) << 4) | target) 130 131#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 133 134#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 135do { \ 136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 138} while (0) 139 140#define AHD_COPY_SCB_COL_IDX(dst, src) \ 141do { \ 142 dst->hscb->scsiid = src->hscb->scsiid; \ 143 dst->hscb->lun = src->hscb->lun; \ 144} while (0) 145 146#define AHD_NEVER_COL_IDX 0xFFFF 147 148/**************************** Driver Constants ********************************/ 149/* 150 * The maximum number of supported targets. 151 */ 152#define AHD_NUM_TARGETS 16 153 154/* 155 * The maximum number of supported luns. 156 * The identify message only supports 64 luns in non-packetized transfers. 157 * You can have 2^64 luns when information unit transfers are enabled, 158 * but until we see a need to support that many, we support 256. 159 */ 160#define AHD_NUM_LUNS_NONPKT 64 161#define AHD_NUM_LUNS 256 162 163/* 164 * The maximum transfer per S/G segment. 165 */ 166#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 167 168/* 169 * The maximum amount of SCB storage in hardware on a controller. 170 * This value represents an upper bound. Due to software design, 171 * we may not be able to use this number. 172 */ 173#define AHD_SCB_MAX 512 174 175/* 176 * The maximum number of concurrent transactions supported per driver instance. 177 * Sequencer Control Blocks (SCBs) store per-transaction information. 178 */ 179#define AHD_MAX_QUEUE AHD_SCB_MAX 180 181/* 182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 183 * in size and accommodate as many transactions as can be queued concurrently. 184 */ 185#define AHD_QIN_SIZE AHD_MAX_QUEUE 186#define AHD_QOUT_SIZE AHD_MAX_QUEUE 187 188#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 189/* 190 * The maximum amount of SCB storage we allocate in host memory. 191 */ 192#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 193 194/* 195 * Ring Buffer of incoming target commands. 196 * We allocate 256 to simplify the logic in the sequencer 197 * by using the natural wrap point of an 8bit counter. 198 */ 199#define AHD_TMODE_CMDS 256 200 201/* Reset line assertion time in us */ 202#define AHD_BUSRESET_DELAY 25 203 204/******************* Chip Characteristics/Operating Settings *****************/ 205/* 206 * Chip Type 207 * The chip order is from least sophisticated to most sophisticated. 208 */ 209typedef enum { 210 AHD_NONE = 0x0000, 211 AHD_CHIPID_MASK = 0x00FF, 212 AHD_AIC7901 = 0x0001, 213 AHD_AIC7902 = 0x0002, 214 AHD_AIC7901A = 0x0003, 215 AHD_PCI = 0x0100, /* Bus type PCI */ 216 AHD_PCIX = 0x0200, /* Bus type PCIX */ 217 AHD_BUS_MASK = 0x0F00 218} ahd_chip; 219 220/* 221 * Features available in each chip type. 222 */ 223typedef enum { 224 AHD_FENONE = 0x00000, 225 AHD_WIDE = 0x00001,/* Wide Channel */ 226 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 227 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 228 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 229 AHD_RTI = 0x04000,/* Retained Training Support */ 230 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 231 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 232 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 233 AHD_AIC7901_FE = AHD_FENONE, 234 AHD_AIC7902_FE = AHD_MULTI_FUNC 235} ahd_feature; 236 237/* 238 * Bugs in the silicon that we work around in software. 239 */ 240typedef enum { 241 AHD_BUGNONE = 0x0000, 242 /* 243 * Rev A hardware fails to update LAST/CURR/NEXTSCB 244 * correctly in certain packetized selection cases. 245 */ 246 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 247 /* The wrong SCB is accessed to check the abort pending bit. */ 248 AHD_ABORT_LQI_BUG = 0x0002, 249 /* Packetized bitbucket crosses packet boundaries. */ 250 AHD_PKT_BITBUCKET_BUG = 0x0004, 251 /* The selection timer runs twice as long as its setting. */ 252 AHD_LONG_SETIMO_BUG = 0x0008, 253 /* The Non-LQ CRC error status is delayed until phase change. */ 254 AHD_NLQICRC_DELAYED_BUG = 0x0010, 255 /* The chip must be reset for all outgoing bus resets. */ 256 AHD_SCSIRST_BUG = 0x0020, 257 /* Some PCIX fields must be saved and restored across chip reset. */ 258 AHD_PCIX_CHIPRST_BUG = 0x0040, 259 /* MMAPIO is not functional in PCI-X mode. */ 260 AHD_PCIX_MMAPIO_BUG = 0x0080, 261 /* Reads to SCBRAM fail to reset the discard timer. */ 262 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 263 /* Bug workarounds that can be disabled on non-PCIX busses. */ 264 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 265 | AHD_PCIX_MMAPIO_BUG 266 | AHD_PCIX_SCBRAM_RD_BUG, 267 /* 268 * LQOSTOP0 status set even for forced selections with ATN 269 * to perform non-packetized message delivery. 270 */ 271 AHD_LQO_ATNO_BUG = 0x0200, 272 /* FIFO auto-flush does not always trigger. */ 273 AHD_AUTOFLUSH_BUG = 0x0400, 274 /* The CLRLQO registers are not self-clearing. */ 275 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 276 /* The PACKETIZED status bit refers to the previous connection. */ 277 AHD_PKTIZED_STATUS_BUG = 0x1000, 278 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 279 AHD_PKT_LUN_BUG = 0x2000, 280 /* 281 * Only the FIFO allocated to the non-packetized connection may 282 * be in use during a non-packetzied connection. 283 */ 284 AHD_NONPACKFIFO_BUG = 0x4000, 285 /* 286 * Writing to a DFF SCBPTR register may fail if concurent with 287 * a hardware write to the other DFF SCBPTR register. This is 288 * not currently a concern in our sequencer since all chips with 289 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 290 * occur in non-packetized connections. 291 */ 292 AHD_MDFF_WSCBPTR_BUG = 0x8000, 293 /* SGHADDR updates are slow. */ 294 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 295 /* 296 * Changing the MODE_PTR coincident with an interrupt that 297 * switches to a different mode will cause the interrupt to 298 * be in the mode written outside of interrupt context. 299 */ 300 AHD_SET_MODE_BUG = 0x20000, 301 /* Non-packetized busfree revision does not work. */ 302 AHD_BUSFREEREV_BUG = 0x40000, 303 /* 304 * Paced transfers are indicated with a non-standard PPR 305 * option bit in the neg table, 160MHz is indicated by 306 * sync factor 0x7, and the offset if off by a factor of 2. 307 */ 308 AHD_PACED_NEGTABLE_BUG = 0x80000, 309 /* LQOOVERRUN false positives. */ 310 AHD_LQOOVERRUN_BUG = 0x100000, 311 /* 312 * Controller write to INTSTAT will lose to a host 313 * write to CLRINT. 314 */ 315 AHD_INTCOLLISION_BUG = 0x200000, 316 /* 317 * The GEM318 violates the SCSI spec by not waiting 318 * the mandated bus settle delay between phase changes 319 * in some situations. Some aic79xx chip revs. are more 320 * strict in this regard and will treat REQ assertions 321 * that fall within the bus settle delay window as 322 * glitches. This flag tells the firmware to tolerate 323 * early REQ assertions. 324 */ 325 AHD_EARLY_REQ_BUG = 0x400000, 326 /* 327 * The LED does not stay on long enough in packetized modes. 328 */ 329 AHD_FAINT_LED_BUG = 0x800000 330} ahd_bug; 331 332/* 333 * Configuration specific settings. 334 * The driver determines these settings by probing the 335 * chip/controller's configuration. 336 */ 337typedef enum { 338 AHD_FNONE = 0x00000, 339 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 340 AHD_USEDEFAULTS = 0x00004,/* 341 * For cards without an seeprom 342 * or a BIOS to initialize the chip's 343 * SRAM, we use the default target 344 * settings. 345 */ 346 AHD_SEQUENCER_DEBUG = 0x00008, 347 AHD_RESET_BUS_A = 0x00010, 348 AHD_EXTENDED_TRANS_A = 0x00020, 349 AHD_TERM_ENB_A = 0x00040, 350 AHD_SPCHK_ENB_A = 0x00080, 351 AHD_STPWLEVEL_A = 0x00100, 352 AHD_INITIATORROLE = 0x00200,/* 353 * Allow initiator operations on 354 * this controller. 355 */ 356 AHD_TARGETROLE = 0x00400,/* 357 * Allow target operations on this 358 * controller. 359 */ 360 AHD_RESOURCE_SHORTAGE = 0x00800, 361 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 362 AHD_INT50_SPEEDFLEX = 0x02000,/* 363 * Internal 50pin connector 364 * sits behind an aic3860 365 */ 366 AHD_BIOS_ENABLED = 0x04000, 367 AHD_ALL_INTERRUPTS = 0x08000, 368 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 369 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 370 AHD_CURRENT_SENSING = 0x40000, 371 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 372 AHD_HP_BOARD = 0x100000, 373 AHD_RESET_POLL_ACTIVE = 0x200000, 374 AHD_UPDATE_PEND_CMDS = 0x400000, 375 AHD_RUNNING_QOUTFIFO = 0x800000 376} ahd_flag; 377 378/************************* Hardware SCB Definition ***************************/ 379 380/* 381 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 382 * consists of a "hardware SCB" mirroring the fields available on the card 383 * and additional information the kernel stores for each transaction. 384 * 385 * To minimize space utilization, a portion of the hardware scb stores 386 * different data during different portions of a SCSI transaction. 387 * As initialized by the host driver for the initiator role, this area 388 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 389 * the cdb has been presented to the target, this area serves to store 390 * residual transfer information and the SCSI status byte. 391 * For the target role, the contents of this area do not change, but 392 * still serve a different purpose than for the initiator role. See 393 * struct target_data for details. 394 */ 395 396/* 397 * Status information embedded in the shared poriton of 398 * an SCB after passing the cdb to the target. The kernel 399 * driver will only read this data for transactions that 400 * complete abnormally. 401 */ 402struct initiator_status { 403 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 404 uint32_t residual_sgptr; /* The next S/G for this transfer */ 405 uint8_t scsi_status; /* Standard SCSI status byte */ 406}; 407 408struct target_status { 409 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 410 uint32_t residual_sgptr; /* The next S/G for this transfer */ 411 uint8_t scsi_status; /* SCSI status to give to initiator */ 412 uint8_t target_phases; /* Bitmap of phases to execute */ 413 uint8_t data_phase; /* Data-In or Data-Out */ 414 uint8_t initiator_tag; /* Initiator's transaction tag */ 415}; 416 417/* 418 * Initiator mode SCB shared data area. 419 * If the embedded CDB is 12 bytes or less, we embed 420 * the sense buffer address in the SCB. This allows 421 * us to retrieve sense information without interrupting 422 * the host in packetized mode. 423 */ 424typedef uint32_t sense_addr_t; 425#define MAX_CDB_LEN 16 426#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 427union initiator_data { 428 struct { 429 uint64_t cdbptr; 430 uint8_t cdblen; 431 } cdb_from_host; 432 uint8_t cdb[MAX_CDB_LEN]; 433 struct { 434 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 435 sense_addr_t sense_addr; 436 } cdb_plus_saddr; 437}; 438 439/* 440 * Target mode version of the shared data SCB segment. 441 */ 442struct target_data { 443 uint32_t spare[2]; 444 uint8_t scsi_status; /* SCSI status to give to initiator */ 445 uint8_t target_phases; /* Bitmap of phases to execute */ 446 uint8_t data_phase; /* Data-In or Data-Out */ 447 uint8_t initiator_tag; /* Initiator's transaction tag */ 448}; 449 450struct hardware_scb { 451/*0*/ union { 452 union initiator_data idata; 453 struct target_data tdata; 454 struct initiator_status istatus; 455 struct target_status tstatus; 456 } shared_data; 457/* 458 * A word about residuals. 459 * The scb is presented to the sequencer with the dataptr and datacnt 460 * fields initialized to the contents of the first S/G element to 461 * transfer. The sgptr field is initialized to the bus address for 462 * the S/G element that follows the first in the in core S/G array 463 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 464 * S/G entry for this transfer (single S/G element transfer with the 465 * first elements address and length preloaded in the dataptr/datacnt 466 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 467 * The SG_FULL_RESID flag ensures that the residual will be correctly 468 * noted even if no data transfers occur. Once the data phase is entered, 469 * the residual sgptr and datacnt are loaded from the sgptr and the 470 * datacnt fields. After each S/G element's dataptr and length are 471 * loaded into the hardware, the residual sgptr is advanced. After 472 * each S/G element is expired, its datacnt field is checked to see 473 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 474 * residual sg ptr and the transfer is considered complete. If the 475 * sequencer determines that there is a residual in the tranfer, or 476 * there is non-zero status, it will set the SG_STATUS_VALID flag in 477 * sgptr and dma the scb back into host memory. To sumarize: 478 * 479 * Sequencer: 480 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 481 * or residual_sgptr does not have SG_LIST_NULL set. 482 * 483 * o We are transfering the last segment if residual_datacnt has 484 * the SG_LAST_SEG flag set. 485 * 486 * Host: 487 * o A residual can only have occurred if a completed scb has the 488 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 489 * the residual_datacnt, and the residual_sgptr field will tell 490 * for sure. 491 * 492 * o residual_sgptr and sgptr refer to the "next" sg entry 493 * and so may point beyond the last valid sg entry for the 494 * transfer. 495 */ 496#define SG_PTR_MASK 0xFFFFFFF8 497/*16*/ uint64_t dataptr; 498/*24*/ uint32_t datacnt; /* Byte 3 is spare. */ 499/*28*/ uint32_t sgptr; 500/*32*/ uint32_t hscb_busaddr; 501/*36*/ uint32_t next_hscb_busaddr; 502/*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 503/*41*/ uint8_t scsiid; /* 504 * Selection out Id 505 * Our Id (bits 0-3) Their ID (bits 4-7) 506 */ 507/*42*/ uint8_t lun; 508/*43*/ uint8_t task_attribute; 509/*44*/ uint8_t cdb_len; 510/*45*/ uint8_t task_management; 511/*46*/ uint16_t tag; /* Reused by Sequencer. */ 512/********** Long lun field only downloaded for full 8 byte lun support ********/ 513/*48*/ uint8_t pkt_long_lun[8]; 514/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 515/*56*/ uint8_t spare[8]; 516}; 517 518/************************ Kernel SCB Definitions ******************************/ 519/* 520 * Some fields of the SCB are OS dependent. Here we collect the 521 * definitions for elements that all OS platforms need to include 522 * in there SCB definition. 523 */ 524 525/* 526 * Definition of a scatter/gather element as transfered to the controller. 527 * The aic7xxx chips only support a 24bit length. We use the top byte of 528 * the length to store additional address bits and a flag to indicate 529 * that a given segment terminates the transfer. This gives us an 530 * addressable range of 512GB on machines with 64bit PCI or with chips 531 * that can support dual address cycles on 32bit PCI busses. 532 */ 533struct ahd_dma_seg { 534 uint32_t addr; 535 uint32_t len; 536#define AHD_DMA_LAST_SEG 0x80000000 537#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 538#define AHD_SG_LEN_MASK 0x00FFFFFF 539}; 540 541struct ahd_dma64_seg { 542 uint64_t addr; 543 uint32_t len; 544 uint32_t pad; 545}; 546 547struct map_node { 548 bus_dmamap_t dmamap; 549 bus_addr_t physaddr; 550 uint8_t *vaddr; 551 SLIST_ENTRY(map_node) links; 552}; 553 554/* 555 * The current state of this SCB. 556 */ 557typedef enum { 558 SCB_FLAG_NONE = 0x00000, 559 SCB_TRANSMISSION_ERROR = 0x00001,/* 560 * We detected a parity or CRC 561 * error that has effected the 562 * payload of the command. This 563 * flag is checked when normal 564 * status is returned to catch 565 * the case of a target not 566 * responding to our attempt 567 * to report the error. 568 */ 569 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 570 * Another device was active 571 * during the first timeout for 572 * this SCB so we gave ourselves 573 * an additional timeout period 574 * in case it was hogging the 575 * bus. 576 */ 577 SCB_DEVICE_RESET = 0x00004, 578 SCB_SENSE = 0x00008, 579 SCB_CDB32_PTR = 0x00010, 580 SCB_RECOVERY_SCB = 0x00020, 581 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 582 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 583 SCB_ABORT = 0x00100, 584 SCB_ACTIVE = 0x00200, 585 SCB_TARGET_IMMEDIATE = 0x00400, 586 SCB_PACKETIZED = 0x00800, 587 SCB_EXPECT_PPR_BUSFREE = 0x01000, 588 SCB_PKT_SENSE = 0x02000, 589 SCB_CMDPHASE_ABORT = 0x04000, 590 SCB_ON_COL_LIST = 0x08000, 591 SCB_SILENT = 0x10000 /* 592 * Be quiet about transmission type 593 * errors. They are expected and we 594 * don't want to upset the user. This 595 * flag is typically used during DV. 596 */ 597} scb_flag; 598 599struct scb { 600 struct hardware_scb *hscb; 601 union { 602 SLIST_ENTRY(scb) sle; 603 LIST_ENTRY(scb) le; 604 TAILQ_ENTRY(scb) tqe; 605 } links; 606 union { 607 SLIST_ENTRY(scb) sle; 608 LIST_ENTRY(scb) le; 609 TAILQ_ENTRY(scb) tqe; 610 } links2; 611#define pending_links links2.le 612#define collision_links links2.le 613 struct scb *col_scb; 614 ahd_io_ctx_t io_ctx; 615 struct ahd_softc *ahd_softc; 616 scb_flag flags; 617#ifndef __linux__ 618 bus_dmamap_t dmamap; 619#endif 620 struct scb_platform_data *platform_data; 621 struct map_node *hscb_map; 622 struct map_node *sg_map; 623 struct map_node *sense_map; 624 void *sg_list; 625 uint8_t *sense_data; 626 bus_addr_t sg_list_busaddr; 627 bus_addr_t sense_busaddr; 628 u_int sg_count;/* How full ahd_dma_seg is */ 629#define AHD_MAX_LQ_CRC_ERRORS 5 630 u_int crc_retry_count; 631}; 632 633TAILQ_HEAD(scb_tailq, scb); 634LIST_HEAD(scb_list, scb); 635 636struct scb_data { 637 /* 638 * TAILQ of lists of free SCBs grouped by device 639 * collision domains. 640 */ 641 struct scb_tailq free_scbs; 642 643 /* 644 * Per-device lists of SCBs whose tag ID would collide 645 * with an already active tag on the device. 646 */ 647 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 648 649 /* 650 * SCBs that will not collide with any active device. 651 */ 652 struct scb_list any_dev_free_scb_list; 653 654 /* 655 * Mapping from tag to SCB. 656 */ 657 struct scb *scbindex[AHD_SCB_MAX]; 658 659 /* 660 * "Bus" addresses of our data structures. 661 */ 662 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 663 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 664 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 665 SLIST_HEAD(, map_node) hscb_maps; 666 SLIST_HEAD(, map_node) sg_maps; 667 SLIST_HEAD(, map_node) sense_maps; 668 int scbs_left; /* unallocated scbs in head map_node */ 669 int sgs_left; /* unallocated sgs in head map_node */ 670 int sense_left; /* unallocated sense in head map_node */ 671 uint16_t numscbs; 672 uint16_t maxhscbs; /* Number of SCBs on the card */ 673 uint8_t init_level; /* 674 * How far we've initialized 675 * this structure. 676 */ 677}; 678 679/************************ Target Mode Definitions *****************************/ 680 681/* 682 * Connection desciptor for select-in requests in target mode. 683 */ 684struct target_cmd { 685 uint8_t scsiid; /* Our ID and the initiator's ID */ 686 uint8_t identify; /* Identify message */ 687 uint8_t bytes[22]; /* 688 * Bytes contains any additional message 689 * bytes terminated by 0xFF. The remainder 690 * is the cdb to execute. 691 */ 692 uint8_t cmd_valid; /* 693 * When a command is complete, the firmware 694 * will set cmd_valid to all bits set. 695 * After the host has seen the command, 696 * the bits are cleared. This allows us 697 * to just peek at host memory to determine 698 * if more work is complete. cmd_valid is on 699 * an 8 byte boundary to simplify setting 700 * it on aic7880 hardware which only has 701 * limited direct access to the DMA FIFO. 702 */ 703 uint8_t pad[7]; 704}; 705 706/* 707 * Number of events we can buffer up if we run out 708 * of immediate notify ccbs. 709 */ 710#define AHD_TMODE_EVENT_BUFFER_SIZE 8 711struct ahd_tmode_event { 712 uint8_t initiator_id; 713 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 714#define EVENT_TYPE_BUS_RESET 0xFF 715 uint8_t event_arg; 716}; 717 718/* 719 * Per enabled lun target mode state. 720 * As this state is directly influenced by the host OS'es target mode 721 * environment, we let the OS module define it. Forward declare the 722 * structure here so we can store arrays of them, etc. in OS neutral 723 * data structures. 724 */ 725#ifdef AHD_TARGET_MODE 726struct ahd_tmode_lstate { 727 struct cam_path *path; 728 struct ccb_hdr_slist accept_tios; 729 struct ccb_hdr_slist immed_notifies; 730 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 731 uint8_t event_r_idx; 732 uint8_t event_w_idx; 733}; 734#else 735struct ahd_tmode_lstate; 736#endif 737 738/******************** Transfer Negotiation Datastructures *********************/ 739#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 740#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 741#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 742#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 743#define AHD_PERIOD_10MHz 0x19 744 745#define AHD_WIDTH_UNKNOWN 0xFF 746#define AHD_PERIOD_UNKNOWN 0xFF 747#define AHD_OFFSET_UNKNOWN 0xFF 748#define AHD_PPR_OPTS_UNKNOWN 0xFF 749 750/* 751 * Transfer Negotiation Information. 752 */ 753struct ahd_transinfo { 754 uint8_t protocol_version; /* SCSI Revision level */ 755 uint8_t transport_version; /* SPI Revision level */ 756 uint8_t width; /* Bus width */ 757 uint8_t period; /* Sync rate factor */ 758 uint8_t offset; /* Sync offset */ 759 uint8_t ppr_options; /* Parallel Protocol Request options */ 760}; 761 762/* 763 * Per-initiator current, goal and user transfer negotiation information. */ 764struct ahd_initiator_tinfo { 765 struct ahd_transinfo curr; 766 struct ahd_transinfo goal; 767 struct ahd_transinfo user; 768}; 769 770/* 771 * Per enabled target ID state. 772 * Pointers to lun target state as well as sync/wide negotiation information 773 * for each initiator<->target mapping. For the initiator role we pretend 774 * that we are the target and the targets are the initiators since the 775 * negotiation is the same regardless of role. 776 */ 777struct ahd_tmode_tstate { 778 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 779 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 780 781 /* 782 * Per initiator state bitmasks. 783 */ 784 uint16_t auto_negotiate;/* Auto Negotiation Required */ 785 uint16_t discenable; /* Disconnection allowed */ 786 uint16_t tagenable; /* Tagged Queuing allowed */ 787}; 788 789/* 790 * Points of interest along the negotiated transfer scale. 791 */ 792#define AHD_SYNCRATE_160 0x8 793#define AHD_SYNCRATE_PACED 0x8 794#define AHD_SYNCRATE_DT 0x9 795#define AHD_SYNCRATE_ULTRA2 0xa 796#define AHD_SYNCRATE_ULTRA 0xc 797#define AHD_SYNCRATE_FAST 0x19 798#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 799#define AHD_SYNCRATE_SYNC 0x32 800#define AHD_SYNCRATE_MIN 0x60 801#define AHD_SYNCRATE_ASYNC 0xFF 802#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 803 804/* Safe and valid period for async negotiations. */ 805#define AHD_ASYNC_XFER_PERIOD 0x44 806 807/* 808 * In RevA, the synctable uses a 120MHz rate for the period 809 * factor 8 and 160MHz for the period factor 7. The 120MHz 810 * rate never made it into the official SCSI spec, so we must 811 * compensate when setting the negotiation table for Rev A 812 * parts. 813 */ 814#define AHD_SYNCRATE_REVA_120 0x8 815#define AHD_SYNCRATE_REVA_160 0x7 816 817/***************************** Lookup Tables **********************************/ 818/* 819 * Phase -> name and message out response 820 * to parity errors in each phase table. 821 */ 822struct ahd_phase_table_entry { 823 uint8_t phase; 824 uint8_t mesg_out; /* Message response to parity errors */ 825 char *phasemsg; 826}; 827 828/************************** Serial EEPROM Format ******************************/ 829 830struct seeprom_config { 831/* 832 * Per SCSI ID Configuration Flags 833 */ 834 uint16_t device_flags[16]; /* words 0-15 */ 835#define CFXFER 0x003F /* synchronous transfer rate */ 836#define CFXFER_ASYNC 0x3F 837#define CFQAS 0x0040 /* Negotiate QAS */ 838#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 839#define CFSTART 0x0100 /* send start unit SCSI command */ 840#define CFINCBIOS 0x0200 /* include in BIOS scan */ 841#define CFDISC 0x0400 /* enable disconnection */ 842#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 843#define CFWIDEB 0x1000 /* wide bus device */ 844#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 845 846/* 847 * BIOS Control Bits 848 */ 849 uint16_t bios_control; /* word 16 */ 850#define CFSUPREM 0x0001 /* support all removeable drives */ 851#define CFSUPREMB 0x0002 /* support removeable boot drives */ 852#define CFBIOSSTATE 0x000C /* BIOS Action State */ 853#define CFBS_DISABLED 0x00 854#define CFBS_ENABLED 0x04 855#define CFBS_DISABLED_SCAN 0x08 856#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 857#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 858#define CFSPARITY 0x0040 /* SCSI parity */ 859#define CFEXTEND 0x0080 /* extended translation enabled */ 860#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 861#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 862#define CFMSG_VERBOSE 0x0000 863#define CFMSG_SILENT 0x0200 864#define CFMSG_DIAG 0x0400 865#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 866/* UNUSED 0xf000 */ 867 868/* 869 * Host Adapter Control Bits 870 */ 871 uint16_t adapter_control; /* word 17 */ 872#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 873#define CFSTERM 0x0002 /* SCSI low byte termination */ 874#define CFWSTERM 0x0004 /* SCSI high byte termination */ 875#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 876#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 877#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 878#define CFSTPWLEVEL 0x0040 /* Termination level control */ 879#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 880#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 881#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 882 883/* 884 * Bus Release Time, Host Adapter ID 885 */ 886 uint16_t brtime_id; /* word 18 */ 887#define CFSCSIID 0x000f /* host adapter SCSI ID */ 888/* UNUSED 0x00f0 */ 889#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 890 891/* 892 * Maximum targets 893 */ 894 uint16_t max_targets; /* word 19 */ 895#define CFMAXTARG 0x00ff /* maximum targets */ 896#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 897#define CFBOOTID 0xf000 /* Target to boot from */ 898 uint16_t res_1[10]; /* words 20-29 */ 899 uint16_t signature; /* BIOS Signature */ 900#define CFSIGNATURE 0x400 901 uint16_t checksum; /* word 31 */ 902}; 903 904/* 905 * Vital Product Data used during POST and by the BIOS. 906 */ 907struct vpd_config { 908 uint8_t bios_flags; 909#define VPDMASTERBIOS 0x0001 910#define VPDBOOTHOST 0x0002 911 uint8_t reserved_1[21]; 912 uint8_t resource_type; 913 uint8_t resource_len[2]; 914 uint8_t resource_data[8]; 915 uint8_t vpd_tag; 916 uint16_t vpd_len; 917 uint8_t vpd_keyword[2]; 918 uint8_t length; 919 uint8_t revision; 920 uint8_t device_flags; 921 uint8_t termnation_menus[2]; 922 uint8_t fifo_threshold; 923 uint8_t end_tag; 924 uint8_t vpd_checksum; 925 uint16_t default_target_flags; 926 uint16_t default_bios_flags; 927 uint16_t default_ctrl_flags; 928 uint8_t default_irq; 929 uint8_t pci_lattime; 930 uint8_t max_target; 931 uint8_t boot_lun; 932 uint16_t signature; 933 uint8_t reserved_2; 934 uint8_t checksum; 935 uint8_t reserved_3[4]; 936}; 937 938/****************************** Flexport Logic ********************************/ 939#define FLXADDR_TERMCTL 0x0 940#define FLX_TERMCTL_ENSECHIGH 0x8 941#define FLX_TERMCTL_ENSECLOW 0x4 942#define FLX_TERMCTL_ENPRIHIGH 0x2 943#define FLX_TERMCTL_ENPRILOW 0x1 944#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 945#define FLX_ROMSTAT_SEECFG 0xF0 946#define FLX_ROMSTAT_EECFG 0x0F 947#define FLX_ROMSTAT_SEE_93C66 0x00 948#define FLX_ROMSTAT_SEE_NONE 0xF0 949#define FLX_ROMSTAT_EE_512x8 0x0 950#define FLX_ROMSTAT_EE_1MBx8 0x1 951#define FLX_ROMSTAT_EE_2MBx8 0x2 952#define FLX_ROMSTAT_EE_4MBx8 0x3 953#define FLX_ROMSTAT_EE_16MBx8 0x4 954#define CURSENSE_ENB 0x1 955#define FLXADDR_FLEXSTAT 0x2 956#define FLX_FSTAT_BUSY 0x1 957#define FLXADDR_CURRENT_STAT 0x4 958#define FLX_CSTAT_SEC_HIGH 0xC0 959#define FLX_CSTAT_SEC_LOW 0x30 960#define FLX_CSTAT_PRI_HIGH 0x0C 961#define FLX_CSTAT_PRI_LOW 0x03 962#define FLX_CSTAT_MASK 0x03 963#define FLX_CSTAT_SHIFT 2 964#define FLX_CSTAT_OKAY 0x0 965#define FLX_CSTAT_OVER 0x1 966#define FLX_CSTAT_UNDER 0x2 967#define FLX_CSTAT_INVALID 0x3 968 969int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 970 u_int start_addr, u_int count, int bstream); 971 972int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 973 u_int start_addr, u_int count); 974int ahd_wait_seeprom(struct ahd_softc *ahd); 975int ahd_verify_vpd_cksum(struct vpd_config *vpd); 976int ahd_verify_cksum(struct seeprom_config *sc); 977int ahd_acquire_seeprom(struct ahd_softc *ahd); 978void ahd_release_seeprom(struct ahd_softc *ahd); 979 980/**************************** Message Buffer *********************************/ 981typedef enum { 982 MSG_FLAG_NONE = 0x00, 983 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 984 MSG_FLAG_IU_REQ_CHANGED = 0x02, 985 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 986 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 987 MSG_FLAG_PACKETIZED = 0x10 988} ahd_msg_flags; 989 990typedef enum { 991 MSG_TYPE_NONE = 0x00, 992 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 993 MSG_TYPE_INITIATOR_MSGIN = 0x02, 994 MSG_TYPE_TARGET_MSGOUT = 0x03, 995 MSG_TYPE_TARGET_MSGIN = 0x04 996} ahd_msg_type; 997 998typedef enum { 999 MSGLOOP_IN_PROG, 1000 MSGLOOP_MSGCOMPLETE, 1001 MSGLOOP_TERMINATED 1002} msg_loop_stat; 1003 1004/*********************** Software Configuration Structure *********************/ 1005struct ahd_suspend_channel_state { 1006 uint8_t scsiseq; 1007 uint8_t sxfrctl0; 1008 uint8_t sxfrctl1; 1009 uint8_t simode0; 1010 uint8_t simode1; 1011 uint8_t seltimer; 1012 uint8_t seqctl; 1013}; 1014 1015struct ahd_suspend_state { 1016 struct ahd_suspend_channel_state channel[2]; 1017 uint8_t optionmode; 1018 uint8_t dscommand0; 1019 uint8_t dspcistatus; 1020 /* hsmailbox */ 1021 uint8_t crccontrol1; 1022 uint8_t scbbaddr; 1023 /* Host and sequencer SCB counts */ 1024 uint8_t dff_thrsh; 1025 uint8_t *scratch_ram; 1026 uint8_t *btt; 1027}; 1028 1029typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1030 1031typedef enum { 1032 AHD_MODE_DFF0, 1033 AHD_MODE_DFF1, 1034 AHD_MODE_CCHAN, 1035 AHD_MODE_SCSI, 1036 AHD_MODE_CFG, 1037 AHD_MODE_UNKNOWN 1038} ahd_mode; 1039 1040#define AHD_MK_MSK(x) (0x01 << (x)) 1041#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1042#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1043#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1044#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1045#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1046#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1047#define AHD_MODE_ANY_MSK (~0) 1048 1049typedef uint8_t ahd_mode_state; 1050 1051typedef void ahd_callback_t (void *); 1052 1053struct ahd_softc { 1054 bus_space_tag_t tags[2]; 1055 bus_space_handle_t bshs[2]; 1056#ifndef __linux__ 1057 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1058#endif 1059 struct scb_data scb_data; 1060 1061 struct hardware_scb *next_queued_hscb; 1062 1063 /* 1064 * SCBs that have been sent to the controller 1065 */ 1066 LIST_HEAD(, scb) pending_scbs; 1067 1068 /* 1069 * Current register window mode information. 1070 */ 1071 ahd_mode dst_mode; 1072 ahd_mode src_mode; 1073 1074 /* 1075 * Saved register window mode information 1076 * used for restore on next unpause. 1077 */ 1078 ahd_mode saved_dst_mode; 1079 ahd_mode saved_src_mode; 1080 1081 /* 1082 * Platform specific data. 1083 */ 1084 struct ahd_platform_data *platform_data; 1085 1086 /* 1087 * Platform specific device information. 1088 */ 1089 ahd_dev_softc_t dev_softc; 1090 1091 /* 1092 * Bus specific device information. 1093 */ 1094 ahd_bus_intr_t bus_intr; 1095 1096 /* 1097 * Target mode related state kept on a per enabled lun basis. 1098 * Targets that are not enabled will have null entries. 1099 * As an initiator, we keep one target entry for our initiator 1100 * ID to store our sync/wide transfer settings. 1101 */ 1102 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1103 1104 /* 1105 * The black hole device responsible for handling requests for 1106 * disabled luns on enabled targets. 1107 */ 1108 struct ahd_tmode_lstate *black_hole; 1109 1110 /* 1111 * Device instance currently on the bus awaiting a continue TIO 1112 * for a command that was not given the disconnect priveledge. 1113 */ 1114 struct ahd_tmode_lstate *pending_device; 1115 1116 /* 1117 * Timer handles for timer driven callbacks. 1118 */ 1119 ahd_timer_t reset_timer; 1120 ahd_timer_t stat_timer; 1121 1122 /* 1123 * Statistics. 1124 */ 1125#define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1126#define AHD_STAT_BUCKETS 4 1127 u_int cmdcmplt_bucket; 1128 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1129 uint32_t cmdcmplt_total; 1130 1131 /* 1132 * Card characteristics 1133 */ 1134 ahd_chip chip; 1135 ahd_feature features; 1136 ahd_bug bugs; 1137 ahd_flag flags; 1138 struct seeprom_config *seep_config; 1139 1140 /* Values to store in the SEQCTL register for pause and unpause */ 1141 uint8_t unpause; 1142 uint8_t pause; 1143 1144 /* Command Queues */ 1145 uint16_t qoutfifonext; 1146 uint16_t qoutfifonext_valid_tag; 1147 uint16_t qinfifonext; 1148 uint16_t qinfifo[AHD_SCB_MAX]; 1149 uint16_t *qoutfifo; 1150 1151 /* Critical Section Data */ 1152 struct cs *critical_sections; 1153 u_int num_critical_sections; 1154 1155 /* Buffer for handling packetized bitbucket. */ 1156 uint8_t *overrun_buf; 1157 1158 /* Links for chaining softcs */ 1159 TAILQ_ENTRY(ahd_softc) links; 1160 1161 /* Channel Names ('A', 'B', etc.) */ 1162 char channel; 1163 1164 /* Initiator Bus ID */ 1165 uint8_t our_id; 1166 1167 /* 1168 * Target incoming command FIFO. 1169 */ 1170 struct target_cmd *targetcmds; 1171 uint8_t tqinfifonext; 1172 1173 /* 1174 * Cached verson of the hs_mailbox so we can avoid 1175 * pausing the sequencer during mailbox updates. 1176 */ 1177 uint8_t hs_mailbox; 1178 1179 /* 1180 * Incoming and outgoing message handling. 1181 */ 1182 uint8_t send_msg_perror; 1183 ahd_msg_flags msg_flags; 1184 ahd_msg_type msg_type; 1185 uint8_t msgout_buf[12];/* Message we are sending */ 1186 uint8_t msgin_buf[12];/* Message we are receiving */ 1187 u_int msgout_len; /* Length of message to send */ 1188 u_int msgout_index; /* Current index in msgout */ 1189 u_int msgin_index; /* Current index in msgin */ 1190 1191 /* 1192 * Mapping information for data structures shared 1193 * between the sequencer and kernel. 1194 */ 1195 bus_dma_tag_t parent_dmat; 1196 bus_dma_tag_t shared_data_dmat; 1197 bus_dmamap_t shared_data_dmamap; 1198 bus_addr_t shared_data_busaddr; 1199 1200 /* Information saved through suspend/resume cycles */ 1201 struct ahd_suspend_state suspend_state; 1202 1203 /* Number of enabled target mode device on this card */ 1204 u_int enabled_luns; 1205 1206 /* Initialization level of this data structure */ 1207 u_int init_level; 1208 1209 /* PCI cacheline size. */ 1210 u_int pci_cachesize; 1211 1212 /* IO Cell Parameters */ 1213 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1214 1215 u_int stack_size; 1216 uint16_t *saved_stack; 1217 1218 /* Per-Unit descriptive information */ 1219 const char *description; 1220 const char *bus_description; 1221 char *name; 1222 int unit; 1223 1224 /* Selection Timer settings */ 1225 int seltime; 1226 1227 /* 1228 * Interrupt coalessing settings. 1229 */ 1230#define AHD_INT_COALESSING_TIMER_DEFAULT 250 /*us*/ 1231#define AHD_INT_COALESSING_MAXCMDS_DEFAULT 10 1232#define AHD_INT_COALESSING_MAXCMDS_MAX 127 1233#define AHD_INT_COALESSING_MINCMDS_DEFAULT 5 1234#define AHD_INT_COALESSING_MINCMDS_MAX 127 1235#define AHD_INT_COALESSING_THRESHOLD_DEFAULT 2000 1236#define AHD_INT_COALESSING_STOP_THRESHOLD_DEFAULT 1000 1237 u_int int_coalessing_timer; 1238 u_int int_coalessing_maxcmds; 1239 u_int int_coalessing_mincmds; 1240 u_int int_coalessing_threshold; 1241 u_int int_coalessing_stop_threshold; 1242 1243 uint16_t user_discenable;/* Disconnection allowed */ 1244 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1245}; 1246 1247TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1248extern struct ahd_softc_tailq ahd_tailq; 1249 1250/*************************** IO Cell Configuration ****************************/ 1251#define AHD_PRECOMP_SLEW_INDEX \ 1252 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1253 1254#define AHD_AMPLITUDE_INDEX \ 1255 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1256 1257#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1258do { \ 1259 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1260 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1261 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1262} while (0) 1263 1264#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1265do { \ 1266 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1267 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1268 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1269} while (0) 1270 1271#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1272do { \ 1273 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1274 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1275 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1276} while (0) 1277 1278/************************ Active Device Information ***************************/ 1279typedef enum { 1280 ROLE_UNKNOWN, 1281 ROLE_INITIATOR, 1282 ROLE_TARGET 1283} role_t; 1284 1285struct ahd_devinfo { 1286 int our_scsiid; 1287 int target_offset; 1288 uint16_t target_mask; 1289 u_int target; 1290 u_int lun; 1291 char channel; 1292 role_t role; /* 1293 * Only guaranteed to be correct if not 1294 * in the busfree state. 1295 */ 1296}; 1297 1298/****************************** PCI Structures ********************************/ 1299#define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/ 1300#define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */ 1301#define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */ 1302 1303typedef int (ahd_device_setup_t)(struct ahd_softc *); 1304 1305struct ahd_pci_identity { 1306 uint64_t full_id; 1307 uint64_t id_mask; 1308 char *name; 1309 ahd_device_setup_t *setup; 1310}; 1311extern struct ahd_pci_identity ahd_pci_ident_table []; 1312extern const u_int ahd_num_pci_devs; 1313 1314/***************************** VL/EISA Declarations ***************************/ 1315struct aic7770_identity { 1316 uint32_t full_id; 1317 uint32_t id_mask; 1318 char *name; 1319 ahd_device_setup_t *setup; 1320}; 1321extern struct aic7770_identity aic7770_ident_table []; 1322extern const int ahd_num_aic7770_devs; 1323 1324#define AHD_EISA_SLOT_OFFSET 0xc00 1325#define AHD_EISA_IOSIZE 0x100 1326 1327/*************************** Function Declarations ****************************/ 1328/******************************************************************************/ 1329void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1330u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1331void ahd_busy_tcl(struct ahd_softc *ahd, 1332 u_int tcl, u_int busyid); 1333static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1334static __inline void 1335ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1336{ 1337 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1338} 1339 1340/***************************** PCI Front End *********************************/ 1341struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1342int ahd_pci_config(struct ahd_softc *, 1343 struct ahd_pci_identity *); 1344int ahd_pci_test_register_access(struct ahd_softc *); 1345 1346/************************** SCB and SCB queue management **********************/ 1347int ahd_probe_scbs(struct ahd_softc *); 1348void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1349 struct scb *scb); 1350int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1351 int target, char channel, int lun, 1352 u_int tag, role_t role); 1353 1354/****************************** Initialization ********************************/ 1355struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1356int ahd_softc_init(struct ahd_softc *); 1357void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1358int ahd_init(struct ahd_softc *ahd); 1359int ahd_default_config(struct ahd_softc *ahd); 1360int ahd_parse_vpddata(struct ahd_softc *ahd, 1361 struct vpd_config *vpd); 1362int ahd_parse_cfgdata(struct ahd_softc *ahd, 1363 struct seeprom_config *sc); 1364void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1365void ahd_update_coalessing_values(struct ahd_softc *ahd, 1366 u_int timer, 1367 u_int maxcmds, 1368 u_int mincmds); 1369void ahd_enable_coalessing(struct ahd_softc *ahd, 1370 int enable); 1371void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1372int ahd_suspend(struct ahd_softc *ahd); 1373int ahd_resume(struct ahd_softc *ahd); 1374void ahd_softc_insert(struct ahd_softc *); 1375struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1376void ahd_set_unit(struct ahd_softc *, int); 1377void ahd_set_name(struct ahd_softc *, char *); 1378struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1379void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1380void ahd_alloc_scbs(struct ahd_softc *ahd); 1381void ahd_free(struct ahd_softc *ahd); 1382int ahd_reset(struct ahd_softc *ahd); 1383void ahd_shutdown(void *arg); 1384int ahd_write_flexport(struct ahd_softc *ahd, 1385 u_int addr, u_int value); 1386int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1387 uint8_t *value); 1388int ahd_wait_flexport(struct ahd_softc *ahd); 1389 1390/*************************** Interrupt Services *******************************/ 1391void ahd_pci_intr(struct ahd_softc *ahd); 1392void ahd_clear_intstat(struct ahd_softc *ahd); 1393void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1394void ahd_run_qoutfifo(struct ahd_softc *ahd); 1395#ifdef AHD_TARGET_MODE 1396void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1397#endif 1398void ahd_handle_hwerrint(struct ahd_softc *ahd); 1399void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1400void ahd_handle_scsiint(struct ahd_softc *ahd, 1401 u_int intstat); 1402void ahd_clear_critical_section(struct ahd_softc *ahd); 1403 1404/***************************** Error Recovery *********************************/ 1405typedef enum { 1406 SEARCH_COMPLETE, 1407 SEARCH_COUNT, 1408 SEARCH_REMOVE, 1409 SEARCH_PRINT 1410} ahd_search_action; 1411int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1412 char channel, int lun, u_int tag, 1413 role_t role, uint32_t status, 1414 ahd_search_action action); 1415int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1416 char channel, int lun, u_int tag, 1417 int stop_on_first, int remove, 1418 int save_state); 1419void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1420int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1421 int initiate_reset); 1422int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1423 char channel, int lun, u_int tag, 1424 role_t role, uint32_t status); 1425void ahd_restart(struct ahd_softc *ahd); 1426void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1427void ahd_handle_scb_status(struct ahd_softc *ahd, 1428 struct scb *scb); 1429void ahd_handle_scsi_status(struct ahd_softc *ahd, 1430 struct scb *scb); 1431void ahd_calc_residual(struct ahd_softc *ahd, 1432 struct scb *scb); 1433/*************************** Utility Functions ********************************/ 1434struct ahd_phase_table_entry* 1435 ahd_lookup_phase_entry(int phase); 1436void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1437 u_int our_id, u_int target, 1438 u_int lun, char channel, 1439 role_t role); 1440/************************** Transfer Negotiation ******************************/ 1441void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1442 u_int *ppr_options, u_int maxsync); 1443void ahd_validate_offset(struct ahd_softc *ahd, 1444 struct ahd_initiator_tinfo *tinfo, 1445 u_int period, u_int *offset, 1446 int wide, role_t role); 1447void ahd_validate_width(struct ahd_softc *ahd, 1448 struct ahd_initiator_tinfo *tinfo, 1449 u_int *bus_width, 1450 role_t role); 1451/* 1452 * Negotiation types. These are used to qualify if we should renegotiate 1453 * even if our goal and current transport parameters are identical. 1454 */ 1455typedef enum { 1456 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1457 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1458 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1459} ahd_neg_type; 1460int ahd_update_neg_request(struct ahd_softc*, 1461 struct ahd_devinfo*, 1462 struct ahd_tmode_tstate*, 1463 struct ahd_initiator_tinfo*, 1464 ahd_neg_type); 1465void ahd_set_width(struct ahd_softc *ahd, 1466 struct ahd_devinfo *devinfo, 1467 u_int width, u_int type, int paused); 1468void ahd_set_syncrate(struct ahd_softc *ahd, 1469 struct ahd_devinfo *devinfo, 1470 u_int period, u_int offset, 1471 u_int ppr_options, 1472 u_int type, int paused); 1473typedef enum { 1474 AHD_QUEUE_NONE, 1475 AHD_QUEUE_BASIC, 1476 AHD_QUEUE_TAGGED 1477} ahd_queue_alg; 1478 1479void ahd_set_tags(struct ahd_softc *ahd, 1480 struct ahd_devinfo *devinfo, 1481 ahd_queue_alg alg); 1482 1483/**************************** Target Mode *************************************/ 1484#ifdef AHD_TARGET_MODE 1485void ahd_send_lstate_events(struct ahd_softc *, 1486 struct ahd_tmode_lstate *); 1487void ahd_handle_en_lun(struct ahd_softc *ahd, 1488 struct cam_sim *sim, union ccb *ccb); 1489cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1490 struct cam_sim *sim, union ccb *ccb, 1491 struct ahd_tmode_tstate **tstate, 1492 struct ahd_tmode_lstate **lstate, 1493 int notfound_failure); 1494#ifndef AHD_TMODE_ENABLE 1495#define AHD_TMODE_ENABLE 0 1496#endif 1497#endif 1498/******************************* Debug ***************************************/ 1499#ifdef AHD_DEBUG 1500extern uint32_t ahd_debug; 1501#define AHD_SHOW_MISC 0x00001 1502#define AHD_SHOW_SENSE 0x00002 1503#define AHD_SHOW_RECOVERY 0x00004 1504#define AHD_DUMP_SEEPROM 0x00008 1505#define AHD_SHOW_TERMCTL 0x00010 1506#define AHD_SHOW_MEMORY 0x00020 1507#define AHD_SHOW_MESSAGES 0x00040 1508#define AHD_SHOW_MODEPTR 0x00080 1509#define AHD_SHOW_SELTO 0x00100 1510#define AHD_SHOW_FIFOS 0x00200 1511#define AHD_SHOW_QFULL 0x00400 1512#define AHD_SHOW_DV 0x00800 1513#define AHD_SHOW_MASKED_ERRORS 0x01000 1514#define AHD_SHOW_QUEUE 0x02000 1515#define AHD_SHOW_TQIN 0x04000 1516#define AHD_SHOW_SG 0x08000 1517#define AHD_SHOW_INT_COALESSING 0x10000 1518#define AHD_DEBUG_SEQUENCER 0x20000 1519#endif 1520void ahd_print_scb(struct scb *scb); 1521void ahd_print_devinfo(struct ahd_softc *ahd, 1522 struct ahd_devinfo *devinfo); 1523void ahd_dump_sglist(struct scb *scb); 1524void ahd_dump_all_cards_state(void); 1525void ahd_dump_card_state(struct ahd_softc *ahd); 1526int ahd_print_register(ahd_reg_parse_entry_t *table, 1527 u_int num_entries, 1528 const char *name, 1529 u_int address, 1530 u_int value, 1531 u_int *cur_column, 1532 u_int wrap_point); 1533void ahd_dump_scbs(struct ahd_softc *ahd); 1534#endif /* _AIC79XX_H_ */ 1535