aic79xx.h revision 111954
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#85 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 111954 2003-03-06 23:58:34Z gibbs $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x8000 79#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82#define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84#define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86#define SCSIID_CHANNEL(ahd, scsiid) ('A') 87#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88#define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90#define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92#define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94#define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98#define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100#ifdef AHD_DEBUG 101#define SCB_IS_SILENT(scb) \ 102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 103 && (((scb)->flags & SCB_SILENT) != 0)) 104#else 105#define SCB_IS_SILENT(scb) \ 106 (((scb)->flags & SCB_SILENT) != 0) 107#endif 108/* 109 * TCLs have the following format: TTTTLLLLLLLL 110 */ 111#define TCL_TARGET_OFFSET(tcl) \ 112 ((((tcl) >> 4) & TID) >> 4) 113#define TCL_LUN(tcl) \ 114 (tcl & (AHD_NUM_LUNS - 1)) 115#define BUILD_TCL(scsiid, lun) \ 116 ((lun) | (((scsiid) & TID) << 4)) 117#define BUILD_TCL_RAW(target, channel, lun) \ 118 ((lun) | ((target) << 8)) 119 120#define SCB_GET_TAG(scb) \ 121 ahd_le16toh(scb->hscb->tag) 122 123#ifndef AHD_TARGET_MODE 124#undef AHD_TMODE_ENABLE 125#define AHD_TMODE_ENABLE 0 126#endif 127 128#define AHD_BUILD_COL_IDX(target, lun) \ 129 (((lun) << 4) | target) 130 131#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 133 134#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 135do { \ 136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 138} while (0) 139 140#define AHD_COPY_SCB_COL_IDX(dst, src) \ 141do { \ 142 dst->hscb->scsiid = src->hscb->scsiid; \ 143 dst->hscb->lun = src->hscb->lun; \ 144} while (0) 145 146#define AHD_NEVER_COL_IDX 0xFFFF 147 148/**************************** Driver Constants ********************************/ 149/* 150 * The maximum number of supported targets. 151 */ 152#define AHD_NUM_TARGETS 16 153 154/* 155 * The maximum number of supported luns. 156 * The identify message only supports 64 luns in non-packetized transfers. 157 * You can have 2^64 luns when information unit transfers are enabled, 158 * but until we see a need to support that many, we support 256. 159 */ 160#define AHD_NUM_LUNS_NONPKT 64 161#define AHD_NUM_LUNS 256 162 163/* 164 * The maximum transfer per S/G segment. 165 */ 166#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 167 168/* 169 * The maximum amount of SCB storage in hardware on a controller. 170 * This value represents an upper bound. Due to software design, 171 * we may not be able to use this number. 172 */ 173#define AHD_SCB_MAX 512 174 175/* 176 * The maximum number of concurrent transactions supported per driver instance. 177 * Sequencer Control Blocks (SCBs) store per-transaction information. 178 */ 179#define AHD_MAX_QUEUE AHD_SCB_MAX 180 181/* 182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 183 * in size and accomodate as many transactions as can be queued concurrently. 184 */ 185#define AHD_QIN_SIZE AHD_MAX_QUEUE 186#define AHD_QOUT_SIZE AHD_MAX_QUEUE 187 188#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 189/* 190 * The maximum amount of SCB storage we allocate in host memory. 191 */ 192#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 193 194/* 195 * Ring Buffer of incoming target commands. 196 * We allocate 256 to simplify the logic in the sequencer 197 * by using the natural wrap point of an 8bit counter. 198 */ 199#define AHD_TMODE_CMDS 256 200 201/* Reset line assertion time in us */ 202#define AHD_BUSRESET_DELAY 25 203 204/******************* Chip Characteristics/Operating Settings *****************/ 205/* 206 * Chip Type 207 * The chip order is from least sophisticated to most sophisticated. 208 */ 209typedef enum { 210 AHD_NONE = 0x0000, 211 AHD_CHIPID_MASK = 0x00FF, 212 AHD_AIC7901 = 0x0001, 213 AHD_AIC7902 = 0x0002, 214 AHD_AIC7901A = 0x0003, 215 AHD_PCI = 0x0100, /* Bus type PCI */ 216 AHD_PCIX = 0x0200, /* Bus type PCIX */ 217 AHD_BUS_MASK = 0x0F00 218} ahd_chip; 219 220/* 221 * Features available in each chip type. 222 */ 223typedef enum { 224 AHD_FENONE = 0x00000, 225 AHD_WIDE = 0x00001,/* Wide Channel */ 226 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 227 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 228 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 229 AHD_RTI = 0x04000,/* Retained Training Support */ 230 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 231 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 232 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 233 AHD_AIC7901_FE = AHD_FENONE, 234 AHD_AIC7902_FE = AHD_MULTI_FUNC 235} ahd_feature; 236 237/* 238 * Bugs in the silicon that we work around in software. 239 */ 240typedef enum { 241 AHD_BUGNONE = 0x0000, 242 /* 243 * Rev A hardware fails to update LAST/CURR/NEXTSCB 244 * correctly in certain packetized selection cases. 245 */ 246 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 247 /* The wrong SCB is accessed to check the abort pending bit. */ 248 AHD_ABORT_LQI_BUG = 0x0002, 249 /* Packetized bitbucket crosses packet boundaries. */ 250 AHD_PKT_BITBUCKET_BUG = 0x0004, 251 /* The selection timer runs twice as long as its setting. */ 252 AHD_LONG_SETIMO_BUG = 0x0008, 253 /* The Non-LQ CRC error status is delayed until phase change. */ 254 AHD_NLQICRC_DELAYED_BUG = 0x0010, 255 /* The chip must be reset for all outgoing bus resets. */ 256 AHD_SCSIRST_BUG = 0x0020, 257 /* Some PCIX fields must be saved and restored across chip reset. */ 258 AHD_PCIX_CHIPRST_BUG = 0x0040, 259 /* MMAPIO is not functional in PCI-X mode. */ 260 AHD_PCIX_MMAPIO_BUG = 0x0080, 261 /* Reads to SCBRAM fail to reset the discard timer. */ 262 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 263 /* Bug workarounds that can be disabled on non-PCIX busses. */ 264 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 265 | AHD_PCIX_MMAPIO_BUG 266 | AHD_PCIX_SCBRAM_RD_BUG, 267 /* 268 * LQOSTOP0 status set even for forced selections with ATN 269 * to perform non-packetized message delivery. 270 */ 271 AHD_LQO_ATNO_BUG = 0x0200, 272 /* FIFO auto-flush does not always trigger. */ 273 AHD_AUTOFLUSH_BUG = 0x0400, 274 /* The CLRLQO registers are not self-clearing. */ 275 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 276 /* The PACKETIZED status bit refers to the previous connection. */ 277 AHD_PKTIZED_STATUS_BUG = 0x1000, 278 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 279 AHD_PKT_LUN_BUG = 0x2000, 280 /* 281 * Only the FIFO allocated to the non-packetized connection may 282 * be in use during a non-packetzied connection. 283 */ 284 AHD_NONPACKFIFO_BUG = 0x4000, 285 /* 286 * Writing to a DFF SCBPTR register may fail if concurent with 287 * a hardware write to the other DFF SCBPTR register. This is 288 * not currently a concern in our sequencer since all chips with 289 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 290 * occur in non-packetized connections. 291 */ 292 AHD_MDFF_WSCBPTR_BUG = 0x8000, 293 /* SGHADDR updates are slow. */ 294 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 295 /* 296 * Changing the MODE_PTR coincident with an interrupt that 297 * switches to a different mode will cause the interrupt to 298 * be in the mode written outside of interrupt context. 299 */ 300 AHD_SET_MODE_BUG = 0x20000, 301 /* Non-packetized busfree revision does not work. */ 302 AHD_BUSFREEREV_BUG = 0x40000, 303 /* 304 * Paced transfers are indicated with a non-standard PPR 305 * option bit in the neg table, 160MHz is indicated by 306 * sync factor 0x7, and the offset if off by a factor of 2. 307 */ 308 AHD_PACED_NEGTABLE_BUG = 0x80000, 309 /* LQOOVERRUN false positives. */ 310 AHD_LQOOVERRUN_BUG = 0x100000, 311 /* 312 * Controller write to INTSTAT will lose to a host 313 * write to CLRINT. 314 */ 315 AHD_INTCOLLISION_BUG = 0x200000, 316 /* 317 * The GEM318 violates the SCSI spec by not waiting 318 * the mandated bus settle delay between phase changes 319 * in some situations. Some aic79xx chip revs. are more 320 * strict in this regard and will treat REQ assertions 321 * that fall within the bus settle delay window as 322 * glitches. This flag tells the firmware to tolerate 323 * early REQ assertions. 324 */ 325 AHD_EARLY_REQ_BUG = 0x400000 326} ahd_bug; 327 328/* 329 * Configuration specific settings. 330 * The driver determines these settings by probing the 331 * chip/controller's configuration. 332 */ 333typedef enum { 334 AHD_FNONE = 0x00000, 335 AHD_PRIMARY_CHANNEL = 0x00003,/* 336 * The channel that should 337 * be probed first. 338 */ 339 AHD_USEDEFAULTS = 0x00004,/* 340 * For cards without an seeprom 341 * or a BIOS to initialize the chip's 342 * SRAM, we use the default target 343 * settings. 344 */ 345 AHD_SEQUENCER_DEBUG = 0x00008, 346 AHD_RESET_BUS_A = 0x00010, 347 AHD_EXTENDED_TRANS_A = 0x00020, 348 AHD_TERM_ENB_A = 0x00040, 349 AHD_SPCHK_ENB_A = 0x00080, 350 AHD_STPWLEVEL_A = 0x00100, 351 AHD_INITIATORROLE = 0x00200,/* 352 * Allow initiator operations on 353 * this controller. 354 */ 355 AHD_TARGETROLE = 0x00400,/* 356 * Allow target operations on this 357 * controller. 358 */ 359 AHD_RESOURCE_SHORTAGE = 0x00800, 360 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 361 AHD_INT50_SPEEDFLEX = 0x02000,/* 362 * Internal 50pin connector 363 * sits behind an aic3860 364 */ 365 AHD_BIOS_ENABLED = 0x04000, 366 AHD_ALL_INTERRUPTS = 0x08000, 367 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 368 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 369 AHD_CURRENT_SENSING = 0x40000, 370 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 371 AHD_HP_BOARD = 0x100000, 372 AHD_RESET_POLL_ACTIVE = 0x200000, 373 AHD_UPDATE_PEND_CMDS = 0x400000, 374 AHD_RUNNING_QOUTFIFO = 0x800000 375} ahd_flag; 376 377/************************* Hardware SCB Definition ***************************/ 378 379/* 380 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 381 * consists of a "hardware SCB" mirroring the fields availible on the card 382 * and additional information the kernel stores for each transaction. 383 * 384 * To minimize space utilization, a portion of the hardware scb stores 385 * different data during different portions of a SCSI transaction. 386 * As initialized by the host driver for the initiator role, this area 387 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 388 * the cdb has been presented to the target, this area serves to store 389 * residual transfer information and the SCSI status byte. 390 * For the target role, the contents of this area do not change, but 391 * still serve a different purpose than for the initiator role. See 392 * struct target_data for details. 393 */ 394 395/* 396 * Status information embedded in the shared poriton of 397 * an SCB after passing the cdb to the target. The kernel 398 * driver will only read this data for transactions that 399 * complete abnormally. 400 */ 401struct initiator_status { 402 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 403 uint32_t residual_sgptr; /* The next S/G for this transfer */ 404 uint8_t scsi_status; /* Standard SCSI status byte */ 405}; 406 407struct target_status { 408 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 409 uint32_t residual_sgptr; /* The next S/G for this transfer */ 410 uint8_t scsi_status; /* SCSI status to give to initiator */ 411 uint8_t target_phases; /* Bitmap of phases to execute */ 412 uint8_t data_phase; /* Data-In or Data-Out */ 413 uint8_t initiator_tag; /* Initiator's transaction tag */ 414}; 415 416/* 417 * Initiator mode SCB shared data area. 418 * If the embedded CDB is 12 bytes or less, we embed 419 * the sense buffer address in the SCB. This allows 420 * us to retrieve sense information without interrupting 421 * the host in packetized mode. 422 */ 423typedef uint32_t sense_addr_t; 424#define MAX_CDB_LEN 16 425#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 426union initiator_data { 427 struct { 428 uint64_t cdbptr; 429 uint8_t cdblen; 430 } cdb_from_host; 431 uint8_t cdb[MAX_CDB_LEN]; 432 struct { 433 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 434 sense_addr_t sense_addr; 435 } cdb_plus_saddr; 436}; 437 438/* 439 * Target mode version of the shared data SCB segment. 440 */ 441struct target_data { 442 uint32_t spare[2]; 443 uint8_t scsi_status; /* SCSI status to give to initiator */ 444 uint8_t target_phases; /* Bitmap of phases to execute */ 445 uint8_t data_phase; /* Data-In or Data-Out */ 446 uint8_t initiator_tag; /* Initiator's transaction tag */ 447}; 448 449struct hardware_scb { 450/*0*/ union { 451 union initiator_data idata; 452 struct target_data tdata; 453 struct initiator_status istatus; 454 struct target_status tstatus; 455 } shared_data; 456/* 457 * A word about residuals. 458 * The scb is presented to the sequencer with the dataptr and datacnt 459 * fields initialized to the contents of the first S/G element to 460 * transfer. The sgptr field is initialized to the bus address for 461 * the S/G element that follows the first in the in core S/G array 462 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 463 * S/G entry for this transfer (single S/G element transfer with the 464 * first elements address and length preloaded in the dataptr/datacnt 465 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 466 * The SG_FULL_RESID flag ensures that the residual will be correctly 467 * noted even if no data transfers occur. Once the data phase is entered, 468 * the residual sgptr and datacnt are loaded from the sgptr and the 469 * datacnt fields. After each S/G element's dataptr and length are 470 * loaded into the hardware, the residual sgptr is advanced. After 471 * each S/G element is expired, its datacnt field is checked to see 472 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 473 * residual sg ptr and the transfer is considered complete. If the 474 * sequencer determines that there is a residual in the tranfer, or 475 * there is non-zero status, it will set the SG_STATUS_VALID flag in 476 * sgptr and dma the scb back into host memory. To sumarize: 477 * 478 * Sequencer: 479 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 480 * or residual_sgptr does not have SG_LIST_NULL set. 481 * 482 * o We are transfering the last segment if residual_datacnt has 483 * the SG_LAST_SEG flag set. 484 * 485 * Host: 486 * o A residual can only have occurred if a completed scb has the 487 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 488 * the residual_datacnt, and the residual_sgptr field will tell 489 * for sure. 490 * 491 * o residual_sgptr and sgptr refer to the "next" sg entry 492 * and so may point beyond the last valid sg entry for the 493 * transfer. 494 */ 495#define SG_PTR_MASK 0xFFFFFFF8 496/*16*/ uint16_t tag; 497/*18*/ uint8_t cdb_len; 498/*19*/ uint8_t task_management; 499/*20*/ uint32_t next_hscb_busaddr; 500/*24*/ uint64_t dataptr; 501/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 502/*36*/ uint32_t sgptr; 503/*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 504/*41*/ uint8_t scsiid; /* 505 * Selection out Id 506 * Our Id (bits 0-3) Their ID (bits 4-7) 507 */ 508/*42*/ uint8_t lun; 509/*43*/ uint8_t task_attribute; 510/*44*/ uint32_t hscb_busaddr; 511/******* Long lun field only downloaded for full 8 byte lun support *******/ 512/*48*/ uint8_t pkt_long_lun[8]; 513/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 514/*56*/ uint8_t spare[8]; 515}; 516 517/************************ Kernel SCB Definitions ******************************/ 518/* 519 * Some fields of the SCB are OS dependent. Here we collect the 520 * definitions for elements that all OS platforms need to include 521 * in there SCB definition. 522 */ 523 524/* 525 * Definition of a scatter/gather element as transfered to the controller. 526 * The aic7xxx chips only support a 24bit length. We use the top byte of 527 * the length to store additional address bits and a flag to indicate 528 * that a given segment terminates the transfer. This gives us an 529 * addressable range of 512GB on machines with 64bit PCI or with chips 530 * that can support dual address cycles on 32bit PCI busses. 531 */ 532struct ahd_dma_seg { 533 uint32_t addr; 534 uint32_t len; 535#define AHD_DMA_LAST_SEG 0x80000000 536#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 537#define AHD_SG_LEN_MASK 0x00FFFFFF 538}; 539 540struct ahd_dma64_seg { 541 uint64_t addr; 542 uint32_t len; 543 uint32_t pad; 544}; 545 546struct map_node { 547 bus_dmamap_t dmamap; 548 bus_addr_t physaddr; 549 uint8_t *vaddr; 550 SLIST_ENTRY(map_node) links; 551}; 552 553/* 554 * The current state of this SCB. 555 */ 556typedef enum { 557 SCB_FLAG_NONE = 0x00000, 558 SCB_TRANSMISSION_ERROR = 0x00001,/* 559 * We detected a parity or CRC 560 * error that has effected the 561 * payload of the command. This 562 * flag is checked when normal 563 * status is returned to catch 564 * the case of a target not 565 * responding to our attempt 566 * to report the error. 567 */ 568 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 569 * Another device was active 570 * during the first timeout for 571 * this SCB so we gave ourselves 572 * an additional timeout period 573 * in case it was hogging the 574 * bus. 575 */ 576 SCB_DEVICE_RESET = 0x00004, 577 SCB_SENSE = 0x00008, 578 SCB_CDB32_PTR = 0x00010, 579 SCB_RECOVERY_SCB = 0x00020, 580 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 581 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 582 SCB_ABORT = 0x00100, 583 SCB_ACTIVE = 0x00200, 584 SCB_TARGET_IMMEDIATE = 0x00400, 585 SCB_PACKETIZED = 0x00800, 586 SCB_EXPECT_PPR_BUSFREE = 0x01000, 587 SCB_PKT_SENSE = 0x02000, 588 SCB_CMDPHASE_ABORT = 0x04000, 589 SCB_ON_COL_LIST = 0x08000, 590 SCB_SILENT = 0x10000 /* 591 * Be quiet about transmission type 592 * errors. They are expected and we 593 * don't want to upset the user. This 594 * flag is typically used during DV. 595 */ 596} scb_flag; 597 598struct scb { 599 struct hardware_scb *hscb; 600 union { 601 SLIST_ENTRY(scb) sle; 602 LIST_ENTRY(scb) le; 603 TAILQ_ENTRY(scb) tqe; 604 } links; 605 union { 606 SLIST_ENTRY(scb) sle; 607 LIST_ENTRY(scb) le; 608 TAILQ_ENTRY(scb) tqe; 609 } links2; 610#define pending_links links2.le 611#define collision_links links2.le 612 struct scb *col_scb; 613 ahd_io_ctx_t io_ctx; 614 struct ahd_softc *ahd_softc; 615 scb_flag flags; 616#ifndef __linux__ 617 bus_dmamap_t dmamap; 618#endif 619 struct scb_platform_data *platform_data; 620 struct map_node *hscb_map; 621 struct map_node *sg_map; 622 struct map_node *sense_map; 623 void *sg_list; 624 uint8_t *sense_data; 625 bus_addr_t sg_list_busaddr; 626 bus_addr_t sense_busaddr; 627 u_int sg_count;/* How full ahd_dma_seg is */ 628#define AHD_MAX_LQ_CRC_ERRORS 5 629 u_int crc_retry_count; 630}; 631 632TAILQ_HEAD(scb_tailq, scb); 633LIST_HEAD(scb_list, scb); 634 635struct scb_data { 636 /* 637 * TAILQ of lists of free SCBs grouped by device 638 * collision domains. 639 */ 640 struct scb_tailq free_scbs; 641 642 /* 643 * Per-device lists of SCBs whose tag ID would collide 644 * with an already active tag on the device. 645 */ 646 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 647 648 /* 649 * SCBs that will not collide with any active device. 650 */ 651 struct scb_list any_dev_free_scb_list; 652 653 /* 654 * Mapping from tag to SCB. 655 */ 656 struct scb *scbindex[AHD_SCB_MAX]; 657 658 /* 659 * "Bus" addresses of our data structures. 660 */ 661 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 662 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 663 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 664 SLIST_HEAD(, map_node) hscb_maps; 665 SLIST_HEAD(, map_node) sg_maps; 666 SLIST_HEAD(, map_node) sense_maps; 667 int scbs_left; /* unallocated scbs in head map_node */ 668 int sgs_left; /* unallocated sgs in head map_node */ 669 int sense_left; /* unallocated sense in head map_node */ 670 uint16_t numscbs; 671 uint16_t maxhscbs; /* Number of SCBs on the card */ 672 uint8_t init_level; /* 673 * How far we've initialized 674 * this structure. 675 */ 676}; 677 678/************************ Target Mode Definitions *****************************/ 679 680/* 681 * Connection desciptor for select-in requests in target mode. 682 */ 683struct target_cmd { 684 uint8_t scsiid; /* Our ID and the initiator's ID */ 685 uint8_t identify; /* Identify message */ 686 uint8_t bytes[22]; /* 687 * Bytes contains any additional message 688 * bytes terminated by 0xFF. The remainder 689 * is the cdb to execute. 690 */ 691 uint8_t cmd_valid; /* 692 * When a command is complete, the firmware 693 * will set cmd_valid to all bits set. 694 * After the host has seen the command, 695 * the bits are cleared. This allows us 696 * to just peek at host memory to determine 697 * if more work is complete. cmd_valid is on 698 * an 8 byte boundary to simplify setting 699 * it on aic7880 hardware which only has 700 * limited direct access to the DMA FIFO. 701 */ 702 uint8_t pad[7]; 703}; 704 705/* 706 * Number of events we can buffer up if we run out 707 * of immediate notify ccbs. 708 */ 709#define AHD_TMODE_EVENT_BUFFER_SIZE 8 710struct ahd_tmode_event { 711 uint8_t initiator_id; 712 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 713#define EVENT_TYPE_BUS_RESET 0xFF 714 uint8_t event_arg; 715}; 716 717/* 718 * Per enabled lun target mode state. 719 * As this state is directly influenced by the host OS'es target mode 720 * environment, we let the OS module define it. Forward declare the 721 * structure here so we can store arrays of them, etc. in OS neutral 722 * data structures. 723 */ 724#ifdef AHD_TARGET_MODE 725struct ahd_tmode_lstate { 726 struct cam_path *path; 727 struct ccb_hdr_slist accept_tios; 728 struct ccb_hdr_slist immed_notifies; 729 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 730 uint8_t event_r_idx; 731 uint8_t event_w_idx; 732}; 733#else 734struct ahd_tmode_lstate; 735#endif 736 737/******************** Transfer Negotiation Datastructures *********************/ 738#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 739#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 740#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 741#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 742#define AHD_PERIOD_10MHz 0x19 743 744#define AHD_WIDTH_UNKNOWN 0xFF 745#define AHD_PERIOD_UNKNOWN 0xFF 746#define AHD_OFFSET_UNKNOWN 0xFF 747#define AHD_PPR_OPTS_UNKNOWN 0xFF 748 749/* 750 * Transfer Negotiation Information. 751 */ 752struct ahd_transinfo { 753 uint8_t protocol_version; /* SCSI Revision level */ 754 uint8_t transport_version; /* SPI Revision level */ 755 uint8_t width; /* Bus width */ 756 uint8_t period; /* Sync rate factor */ 757 uint8_t offset; /* Sync offset */ 758 uint8_t ppr_options; /* Parallel Protocol Request options */ 759}; 760 761/* 762 * Per-initiator current, goal and user transfer negotiation information. */ 763struct ahd_initiator_tinfo { 764 struct ahd_transinfo curr; 765 struct ahd_transinfo goal; 766 struct ahd_transinfo user; 767}; 768 769/* 770 * Per enabled target ID state. 771 * Pointers to lun target state as well as sync/wide negotiation information 772 * for each initiator<->target mapping. For the initiator role we pretend 773 * that we are the target and the targets are the initiators since the 774 * negotiation is the same regardless of role. 775 */ 776struct ahd_tmode_tstate { 777 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 778 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 779 780 /* 781 * Per initiator state bitmasks. 782 */ 783 uint16_t auto_negotiate;/* Auto Negotiation Required */ 784 uint16_t discenable; /* Disconnection allowed */ 785 uint16_t tagenable; /* Tagged Queuing allowed */ 786}; 787 788/* 789 * Points of interest along the negotiated transfer scale. 790 */ 791#define AHD_SYNCRATE_160 0x8 792#define AHD_SYNCRATE_PACED 0x8 793#define AHD_SYNCRATE_DT 0x9 794#define AHD_SYNCRATE_ULTRA2 0xa 795#define AHD_SYNCRATE_ULTRA 0xc 796#define AHD_SYNCRATE_FAST 0x19 797#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 798#define AHD_SYNCRATE_SYNC 0x32 799#define AHD_SYNCRATE_MIN 0x60 800#define AHD_SYNCRATE_ASYNC 0xFF 801#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 802 803/* Safe and valid period for async negotiations. */ 804#define AHD_ASYNC_XFER_PERIOD 0x44 805 806/* 807 * In RevA, the synctable uses a 120MHz rate for the period 808 * factor 8 and 160MHz for the period factor 7. The 120MHz 809 * rate never made it into the official SCSI spec, so we must 810 * compensate when setting the negotiation table for Rev A 811 * parts. 812 */ 813#define AHD_SYNCRATE_REVA_120 0x8 814#define AHD_SYNCRATE_REVA_160 0x7 815 816/***************************** Lookup Tables **********************************/ 817/* 818 * Phase -> name and message out response 819 * to parity errors in each phase table. 820 */ 821struct ahd_phase_table_entry { 822 uint8_t phase; 823 uint8_t mesg_out; /* Message response to parity errors */ 824 char *phasemsg; 825}; 826 827/************************** Serial EEPROM Format ******************************/ 828 829struct seeprom_config { 830/* 831 * Per SCSI ID Configuration Flags 832 */ 833 uint16_t device_flags[16]; /* words 0-15 */ 834#define CFXFER 0x003F /* synchronous transfer rate */ 835#define CFXFER_ASYNC 0x3F 836#define CFQAS 0x0040 /* Negotiate QAS */ 837#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 838#define CFSTART 0x0100 /* send start unit SCSI command */ 839#define CFINCBIOS 0x0200 /* include in BIOS scan */ 840#define CFDISC 0x0400 /* enable disconnection */ 841#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 842#define CFWIDEB 0x1000 /* wide bus device */ 843#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 844 845/* 846 * BIOS Control Bits 847 */ 848 uint16_t bios_control; /* word 16 */ 849#define CFSUPREM 0x0001 /* support all removeable drives */ 850#define CFSUPREMB 0x0002 /* support removeable boot drives */ 851#define CFBIOSSTATE 0x000C /* BIOS Action State */ 852#define CFBS_DISABLED 0x00 853#define CFBS_ENABLED 0x04 854#define CFBS_DISABLED_SCAN 0x08 855#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 856#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 857#define CFSPARITY 0x0040 /* SCSI parity */ 858#define CFEXTEND 0x0080 /* extended translation enabled */ 859#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 860#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 861#define CFMSG_VERBOSE 0x0000 862#define CFMSG_SILENT 0x0200 863#define CFMSG_DIAG 0x0400 864#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 865/* UNUSED 0xf000 */ 866 867/* 868 * Host Adapter Control Bits 869 */ 870 uint16_t adapter_control; /* word 17 */ 871#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 872#define CFSTERM 0x0002 /* SCSI low byte termination */ 873#define CFWSTERM 0x0004 /* SCSI high byte termination */ 874#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 875#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 876#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 877#define CFSTPWLEVEL 0x0040 /* Termination level control */ 878#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 879#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 880#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 881 882/* 883 * Bus Release Time, Host Adapter ID 884 */ 885 uint16_t brtime_id; /* word 18 */ 886#define CFSCSIID 0x000f /* host adapter SCSI ID */ 887/* UNUSED 0x00f0 */ 888#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 889 890/* 891 * Maximum targets 892 */ 893 uint16_t max_targets; /* word 19 */ 894#define CFMAXTARG 0x00ff /* maximum targets */ 895#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 896#define CFBOOTID 0xf000 /* Target to boot from */ 897 uint16_t res_1[10]; /* words 20-29 */ 898 uint16_t signature; /* BIOS Signature */ 899#define CFSIGNATURE 0x400 900 uint16_t checksum; /* word 31 */ 901}; 902 903/****************************** Flexport Logic ********************************/ 904#define FLXADDR_TERMCTL 0x0 905#define FLX_TERMCTL_ENSECHIGH 0x8 906#define FLX_TERMCTL_ENSECLOW 0x4 907#define FLX_TERMCTL_ENPRIHIGH 0x2 908#define FLX_TERMCTL_ENPRILOW 0x1 909#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 910#define FLX_ROMSTAT_SEECFG 0xF0 911#define FLX_ROMSTAT_EECFG 0x0F 912#define FLX_ROMSTAT_SEE_93C66 0x00 913#define FLX_ROMSTAT_SEE_NONE 0xF0 914#define FLX_ROMSTAT_EE_512x8 0x0 915#define FLX_ROMSTAT_EE_1MBx8 0x1 916#define FLX_ROMSTAT_EE_2MBx8 0x2 917#define FLX_ROMSTAT_EE_4MBx8 0x3 918#define FLX_ROMSTAT_EE_16MBx8 0x4 919#define CURSENSE_ENB 0x1 920#define FLXADDR_FLEXSTAT 0x2 921#define FLX_FSTAT_BUSY 0x1 922#define FLXADDR_CURRENT_STAT 0x4 923#define FLX_CSTAT_SEC_HIGH 0xC0 924#define FLX_CSTAT_SEC_LOW 0x30 925#define FLX_CSTAT_PRI_HIGH 0x0C 926#define FLX_CSTAT_PRI_LOW 0x03 927#define FLX_CSTAT_MASK 0x03 928#define FLX_CSTAT_SHIFT 2 929#define FLX_CSTAT_OKAY 0x0 930#define FLX_CSTAT_OVER 0x1 931#define FLX_CSTAT_UNDER 0x2 932#define FLX_CSTAT_INVALID 0x3 933 934int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 935 u_int start_addr, u_int count); 936 937int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 938 u_int start_addr, u_int count); 939int ahd_wait_seeprom(struct ahd_softc *ahd); 940int ahd_verify_cksum(struct seeprom_config *sc); 941int ahd_acquire_seeprom(struct ahd_softc *ahd); 942void ahd_release_seeprom(struct ahd_softc *ahd); 943 944/**************************** Message Buffer *********************************/ 945typedef enum { 946 MSG_FLAG_NONE = 0x00, 947 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 948 MSG_FLAG_IU_REQ_CHANGED = 0x02, 949 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 950 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 951 MSG_FLAG_PACKETIZED = 0x10 952} ahd_msg_flags; 953 954typedef enum { 955 MSG_TYPE_NONE = 0x00, 956 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 957 MSG_TYPE_INITIATOR_MSGIN = 0x02, 958 MSG_TYPE_TARGET_MSGOUT = 0x03, 959 MSG_TYPE_TARGET_MSGIN = 0x04 960} ahd_msg_type; 961 962typedef enum { 963 MSGLOOP_IN_PROG, 964 MSGLOOP_MSGCOMPLETE, 965 MSGLOOP_TERMINATED 966} msg_loop_stat; 967 968/*********************** Software Configuration Structure *********************/ 969struct ahd_suspend_channel_state { 970 uint8_t scsiseq; 971 uint8_t sxfrctl0; 972 uint8_t sxfrctl1; 973 uint8_t simode0; 974 uint8_t simode1; 975 uint8_t seltimer; 976 uint8_t seqctl; 977}; 978 979struct ahd_suspend_state { 980 struct ahd_suspend_channel_state channel[2]; 981 uint8_t optionmode; 982 uint8_t dscommand0; 983 uint8_t dspcistatus; 984 /* hsmailbox */ 985 uint8_t crccontrol1; 986 uint8_t scbbaddr; 987 /* Host and sequencer SCB counts */ 988 uint8_t dff_thrsh; 989 uint8_t *scratch_ram; 990 uint8_t *btt; 991}; 992 993typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 994 995typedef enum { 996 AHD_MODE_DFF0, 997 AHD_MODE_DFF1, 998 AHD_MODE_CCHAN, 999 AHD_MODE_SCSI, 1000 AHD_MODE_CFG, 1001 AHD_MODE_UNKNOWN 1002} ahd_mode; 1003 1004#define AHD_MK_MSK(x) (0x01 << (x)) 1005#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1006#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1007#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1008#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1009#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1010#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1011#define AHD_MODE_ANY_MSK (~0) 1012 1013typedef uint8_t ahd_mode_state; 1014 1015typedef void ahd_callback_t (void *); 1016 1017struct ahd_softc { 1018 bus_space_tag_t tags[2]; 1019 bus_space_handle_t bshs[2]; 1020#ifndef __linux__ 1021 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1022#endif 1023 struct scb_data scb_data; 1024 1025 struct hardware_scb *next_queued_hscb; 1026 1027 /* 1028 * SCBs that have been sent to the controller 1029 */ 1030 LIST_HEAD(, scb) pending_scbs; 1031 1032 /* 1033 * Current register window mode information. 1034 */ 1035 ahd_mode dst_mode; 1036 ahd_mode src_mode; 1037 1038 /* 1039 * Saved register window mode information 1040 * used for restore on next unpause. 1041 */ 1042 ahd_mode saved_dst_mode; 1043 ahd_mode saved_src_mode; 1044 1045 /* 1046 * Platform specific data. 1047 */ 1048 struct ahd_platform_data *platform_data; 1049 1050 /* 1051 * Platform specific device information. 1052 */ 1053 ahd_dev_softc_t dev_softc; 1054 1055 /* 1056 * Bus specific device information. 1057 */ 1058 ahd_bus_intr_t bus_intr; 1059 1060 /* 1061 * Target mode related state kept on a per enabled lun basis. 1062 * Targets that are not enabled will have null entries. 1063 * As an initiator, we keep one target entry for our initiator 1064 * ID to store our sync/wide transfer settings. 1065 */ 1066 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1067 1068 /* 1069 * The black hole device responsible for handling requests for 1070 * disabled luns on enabled targets. 1071 */ 1072 struct ahd_tmode_lstate *black_hole; 1073 1074 /* 1075 * Device instance currently on the bus awaiting a continue TIO 1076 * for a command that was not given the disconnect priveledge. 1077 */ 1078 struct ahd_tmode_lstate *pending_device; 1079 1080 /* 1081 * Timer handles for timer driven callbacks. 1082 */ 1083 ahd_timer_t reset_timer; 1084 ahd_timer_t stat_timer; 1085 1086 /* 1087 * Statistics. 1088 */ 1089#define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1090#define AHD_STAT_BUCKETS 4 1091 u_int cmdcmplt_bucket; 1092 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1093 uint32_t cmdcmplt_total; 1094 1095 /* 1096 * Card characteristics 1097 */ 1098 ahd_chip chip; 1099 ahd_feature features; 1100 ahd_bug bugs; 1101 ahd_flag flags; 1102 struct seeprom_config *seep_config; 1103 1104 /* Values to store in the SEQCTL register for pause and unpause */ 1105 uint8_t unpause; 1106 uint8_t pause; 1107 1108 /* Command Queues */ 1109 uint16_t qoutfifonext; 1110 uint16_t qoutfifonext_valid_tag; 1111 uint16_t qinfifonext; 1112 uint16_t qinfifo[AHD_SCB_MAX]; 1113 uint16_t *qoutfifo; 1114 1115 /* Critical Section Data */ 1116 struct cs *critical_sections; 1117 u_int num_critical_sections; 1118 1119 /* Buffer for handling packetized bitbucket. */ 1120 uint8_t *overrun_buf; 1121 1122 /* Links for chaining softcs */ 1123 TAILQ_ENTRY(ahd_softc) links; 1124 1125 /* Channel Names ('A', 'B', etc.) */ 1126 char channel; 1127 1128 /* Initiator Bus ID */ 1129 uint8_t our_id; 1130 1131 /* 1132 * Target incoming command FIFO. 1133 */ 1134 struct target_cmd *targetcmds; 1135 uint8_t tqinfifonext; 1136 1137 /* 1138 * Cached verson of the hs_mailbox so we can avoid 1139 * pausing the sequencer during mailbox updates. 1140 */ 1141 uint8_t hs_mailbox; 1142 1143 /* 1144 * Incoming and outgoing message handling. 1145 */ 1146 uint8_t send_msg_perror; 1147 ahd_msg_flags msg_flags; 1148 ahd_msg_type msg_type; 1149 uint8_t msgout_buf[12];/* Message we are sending */ 1150 uint8_t msgin_buf[12];/* Message we are receiving */ 1151 u_int msgout_len; /* Length of message to send */ 1152 u_int msgout_index; /* Current index in msgout */ 1153 u_int msgin_index; /* Current index in msgin */ 1154 1155 /* 1156 * Mapping information for data structures shared 1157 * between the sequencer and kernel. 1158 */ 1159 bus_dma_tag_t parent_dmat; 1160 bus_dma_tag_t shared_data_dmat; 1161 bus_dmamap_t shared_data_dmamap; 1162 bus_addr_t shared_data_busaddr; 1163 1164 /* Information saved through suspend/resume cycles */ 1165 struct ahd_suspend_state suspend_state; 1166 1167 /* Number of enabled target mode device on this card */ 1168 u_int enabled_luns; 1169 1170 /* Initialization level of this data structure */ 1171 u_int init_level; 1172 1173 /* PCI cacheline size. */ 1174 u_int pci_cachesize; 1175 1176 /* IO Cell Parameters */ 1177 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1178 1179 u_int stack_size; 1180 uint16_t *saved_stack; 1181 1182 /* Per-Unit descriptive information */ 1183 const char *description; 1184 const char *bus_description; 1185 char *name; 1186 int unit; 1187 1188 /* Selection Timer settings */ 1189 int seltime; 1190 1191 /* 1192 * Interrupt coalessing settings. 1193 */ 1194#define AHD_INT_COALESSING_TIMER_DEFAULT 250 /*us*/ 1195#define AHD_INT_COALESSING_MAXCMDS_DEFAULT 10 1196#define AHD_INT_COALESSING_MAXCMDS_MAX 127 1197#define AHD_INT_COALESSING_MINCMDS_DEFAULT 5 1198#define AHD_INT_COALESSING_MINCMDS_MAX 127 1199#define AHD_INT_COALESSING_THRESHOLD_DEFAULT 2000 1200#define AHD_INT_COALESSING_STOP_THRESHOLD_DEFAULT 1000 1201 u_int int_coalessing_timer; 1202 u_int int_coalessing_maxcmds; 1203 u_int int_coalessing_mincmds; 1204 u_int int_coalessing_threshold; 1205 u_int int_coalessing_stop_threshold; 1206 1207 uint16_t user_discenable;/* Disconnection allowed */ 1208 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1209}; 1210 1211TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1212extern struct ahd_softc_tailq ahd_tailq; 1213 1214/*************************** IO Cell Configuration ****************************/ 1215#define AHD_PRECOMP_SLEW_INDEX \ 1216 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1217 1218#define AHD_AMPLITUDE_INDEX \ 1219 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1220 1221#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1222do { \ 1223 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1224 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1225 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1226} while (0) 1227 1228#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1229do { \ 1230 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1231 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1232 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1233} while (0) 1234 1235#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1236do { \ 1237 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1238 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1239 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1240} while (0) 1241 1242/************************ Active Device Information ***************************/ 1243typedef enum { 1244 ROLE_UNKNOWN, 1245 ROLE_INITIATOR, 1246 ROLE_TARGET 1247} role_t; 1248 1249struct ahd_devinfo { 1250 int our_scsiid; 1251 int target_offset; 1252 uint16_t target_mask; 1253 u_int target; 1254 u_int lun; 1255 char channel; 1256 role_t role; /* 1257 * Only guaranteed to be correct if not 1258 * in the busfree state. 1259 */ 1260}; 1261 1262/****************************** PCI Structures ********************************/ 1263#define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/ 1264#define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */ 1265#define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */ 1266 1267typedef int (ahd_device_setup_t)(struct ahd_softc *); 1268 1269struct ahd_pci_identity { 1270 uint64_t full_id; 1271 uint64_t id_mask; 1272 char *name; 1273 ahd_device_setup_t *setup; 1274}; 1275extern struct ahd_pci_identity ahd_pci_ident_table []; 1276extern const u_int ahd_num_pci_devs; 1277 1278/***************************** VL/EISA Declarations ***************************/ 1279struct aic7770_identity { 1280 uint32_t full_id; 1281 uint32_t id_mask; 1282 char *name; 1283 ahd_device_setup_t *setup; 1284}; 1285extern struct aic7770_identity aic7770_ident_table []; 1286extern const int ahd_num_aic7770_devs; 1287 1288#define AHD_EISA_SLOT_OFFSET 0xc00 1289#define AHD_EISA_IOSIZE 0x100 1290 1291/*************************** Function Declarations ****************************/ 1292/******************************************************************************/ 1293void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1294u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1295void ahd_busy_tcl(struct ahd_softc *ahd, 1296 u_int tcl, u_int busyid); 1297static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1298static __inline void 1299ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1300{ 1301 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1302} 1303 1304/***************************** PCI Front End *********************************/ 1305struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1306int ahd_pci_config(struct ahd_softc *, 1307 struct ahd_pci_identity *); 1308int ahd_pci_test_register_access(struct ahd_softc *); 1309 1310/************************** SCB and SCB queue management **********************/ 1311int ahd_probe_scbs(struct ahd_softc *); 1312void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1313 struct scb *scb); 1314int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1315 int target, char channel, int lun, 1316 u_int tag, role_t role); 1317 1318/****************************** Initialization ********************************/ 1319struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1320int ahd_softc_init(struct ahd_softc *); 1321void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1322int ahd_init(struct ahd_softc *ahd); 1323int ahd_default_config(struct ahd_softc *ahd); 1324int ahd_parse_cfgdata(struct ahd_softc *ahd, 1325 struct seeprom_config *sc); 1326void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1327void ahd_update_coalessing_values(struct ahd_softc *ahd, 1328 u_int timer, 1329 u_int maxcmds, 1330 u_int mincmds); 1331void ahd_enable_coalessing(struct ahd_softc *ahd, 1332 int enable); 1333void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1334int ahd_suspend(struct ahd_softc *ahd); 1335int ahd_resume(struct ahd_softc *ahd); 1336void ahd_softc_insert(struct ahd_softc *); 1337struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1338void ahd_set_unit(struct ahd_softc *, int); 1339void ahd_set_name(struct ahd_softc *, char *); 1340struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1341void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1342void ahd_alloc_scbs(struct ahd_softc *ahd); 1343void ahd_free(struct ahd_softc *ahd); 1344int ahd_reset(struct ahd_softc *ahd); 1345void ahd_shutdown(void *arg); 1346int ahd_write_flexport(struct ahd_softc *ahd, 1347 u_int addr, u_int value); 1348int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1349 uint8_t *value); 1350int ahd_wait_flexport(struct ahd_softc *ahd); 1351 1352/*************************** Interrupt Services *******************************/ 1353void ahd_pci_intr(struct ahd_softc *ahd); 1354void ahd_clear_intstat(struct ahd_softc *ahd); 1355void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1356void ahd_run_qoutfifo(struct ahd_softc *ahd); 1357#ifdef AHD_TARGET_MODE 1358void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1359#endif 1360void ahd_handle_hwerrint(struct ahd_softc *ahd); 1361void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1362void ahd_handle_scsiint(struct ahd_softc *ahd, 1363 u_int intstat); 1364void ahd_clear_critical_section(struct ahd_softc *ahd); 1365 1366/***************************** Error Recovery *********************************/ 1367typedef enum { 1368 SEARCH_COMPLETE, 1369 SEARCH_COUNT, 1370 SEARCH_REMOVE, 1371 SEARCH_PRINT 1372} ahd_search_action; 1373int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1374 char channel, int lun, u_int tag, 1375 role_t role, uint32_t status, 1376 ahd_search_action action); 1377int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1378 char channel, int lun, u_int tag, 1379 int stop_on_first, int remove, 1380 int save_state); 1381void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1382int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1383 int initiate_reset); 1384int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1385 char channel, int lun, u_int tag, 1386 role_t role, uint32_t status); 1387void ahd_restart(struct ahd_softc *ahd); 1388void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1389void ahd_handle_scb_status(struct ahd_softc *ahd, 1390 struct scb *scb); 1391void ahd_handle_scsi_status(struct ahd_softc *ahd, 1392 struct scb *scb); 1393void ahd_calc_residual(struct ahd_softc *ahd, 1394 struct scb *scb); 1395/*************************** Utility Functions ********************************/ 1396struct ahd_phase_table_entry* 1397 ahd_lookup_phase_entry(int phase); 1398void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1399 u_int our_id, u_int target, 1400 u_int lun, char channel, 1401 role_t role); 1402/************************** Transfer Negotiation ******************************/ 1403void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1404 u_int *ppr_options, u_int maxsync); 1405void ahd_validate_offset(struct ahd_softc *ahd, 1406 struct ahd_initiator_tinfo *tinfo, 1407 u_int period, u_int *offset, 1408 int wide, role_t role); 1409void ahd_validate_width(struct ahd_softc *ahd, 1410 struct ahd_initiator_tinfo *tinfo, 1411 u_int *bus_width, 1412 role_t role); 1413/* 1414 * Negotiation types. These are used to qualify if we should renegotiate 1415 * even if our goal and current transport parameters are identical. 1416 */ 1417typedef enum { 1418 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1419 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1420 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1421} ahd_neg_type; 1422int ahd_update_neg_request(struct ahd_softc*, 1423 struct ahd_devinfo*, 1424 struct ahd_tmode_tstate*, 1425 struct ahd_initiator_tinfo*, 1426 ahd_neg_type); 1427void ahd_set_width(struct ahd_softc *ahd, 1428 struct ahd_devinfo *devinfo, 1429 u_int width, u_int type, int paused); 1430void ahd_set_syncrate(struct ahd_softc *ahd, 1431 struct ahd_devinfo *devinfo, 1432 u_int period, u_int offset, 1433 u_int ppr_options, 1434 u_int type, int paused); 1435typedef enum { 1436 AHD_QUEUE_NONE, 1437 AHD_QUEUE_BASIC, 1438 AHD_QUEUE_TAGGED 1439} ahd_queue_alg; 1440 1441void ahd_set_tags(struct ahd_softc *ahd, 1442 struct ahd_devinfo *devinfo, 1443 ahd_queue_alg alg); 1444 1445/**************************** Target Mode *************************************/ 1446#ifdef AHD_TARGET_MODE 1447void ahd_send_lstate_events(struct ahd_softc *, 1448 struct ahd_tmode_lstate *); 1449void ahd_handle_en_lun(struct ahd_softc *ahd, 1450 struct cam_sim *sim, union ccb *ccb); 1451cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1452 struct cam_sim *sim, union ccb *ccb, 1453 struct ahd_tmode_tstate **tstate, 1454 struct ahd_tmode_lstate **lstate, 1455 int notfound_failure); 1456#ifndef AHD_TMODE_ENABLE 1457#define AHD_TMODE_ENABLE 0 1458#endif 1459#endif 1460/******************************* Debug ***************************************/ 1461#ifdef AHD_DEBUG 1462extern uint32_t ahd_debug; 1463#define AHD_SHOW_MISC 0x00001 1464#define AHD_SHOW_SENSE 0x00002 1465#define AHD_SHOW_RECOVERY 0x00004 1466#define AHD_DUMP_SEEPROM 0x00008 1467#define AHD_SHOW_TERMCTL 0x00010 1468#define AHD_SHOW_MEMORY 0x00020 1469#define AHD_SHOW_MESSAGES 0x00040 1470#define AHD_SHOW_MODEPTR 0x00080 1471#define AHD_SHOW_SELTO 0x00100 1472#define AHD_SHOW_FIFOS 0x00200 1473#define AHD_SHOW_QFULL 0x00400 1474#define AHD_SHOW_DV 0x00800 1475#define AHD_SHOW_MASKED_ERRORS 0x01000 1476#define AHD_SHOW_QUEUE 0x02000 1477#define AHD_SHOW_TQIN 0x04000 1478#define AHD_SHOW_SG 0x08000 1479#define AHD_SHOW_INT_COALESSING 0x10000 1480#define AHD_DEBUG_SEQUENCER 0x20000 1481#endif 1482void ahd_print_scb(struct scb *scb); 1483void ahd_print_devinfo(struct ahd_softc *ahd, 1484 struct ahd_devinfo *devinfo); 1485void ahd_dump_sglist(struct scb *scb); 1486void ahd_dump_all_cards_state(void); 1487void ahd_dump_card_state(struct ahd_softc *ahd); 1488int ahd_print_register(ahd_reg_parse_entry_t *table, 1489 u_int num_entries, 1490 const char *name, 1491 u_int address, 1492 u_int value, 1493 u_int *cur_column, 1494 u_int wrap_point); 1495void ahd_dump_scbs(struct ahd_softc *ahd); 1496#endif /* _AIC79XX_H_ */ 1497