aic79xx.h revision 109588
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#78 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 109588 2003-01-20 20:17:35Z gibbs $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x8000 79#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82#define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84#define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86#define SCSIID_CHANNEL(ahd, scsiid) ('A') 87#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88#define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90#define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92#define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94#define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98#define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100#ifdef AHD_DEBUG 101#define SCB_IS_SILENT(scb) \ 102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 103 && (((scb)->flags & SCB_SILENT) != 0)) 104#else 105#define SCB_IS_SILENT(scb) \ 106 (((scb)->flags & SCB_SILENT) != 0) 107#endif 108/* 109 * TCLs have the following format: TTTTLLLLLLLL 110 */ 111#define TCL_TARGET_OFFSET(tcl) \ 112 ((((tcl) >> 4) & TID) >> 4) 113#define TCL_LUN(tcl) \ 114 (tcl & (AHD_NUM_LUNS - 1)) 115#define BUILD_TCL(scsiid, lun) \ 116 ((lun) | (((scsiid) & TID) << 4)) 117#define BUILD_TCL_RAW(target, channel, lun) \ 118 ((lun) | ((target) << 8)) 119 120#define SCB_GET_TAG(scb) \ 121 ahd_le16toh(scb->hscb->tag) 122 123#ifndef AHD_TARGET_MODE 124#undef AHD_TMODE_ENABLE 125#define AHD_TMODE_ENABLE 0 126#endif 127 128#define AHD_BUILD_COL_IDX(target, lun) \ 129 (((lun) << 4) | target) 130 131#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 133 134#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 135do { \ 136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 138} while (0) 139 140#define AHD_COPY_SCB_COL_IDX(dst, src) \ 141do { \ 142 dst->hscb->scsiid = src->hscb->scsiid; \ 143 dst->hscb->lun = src->hscb->lun; \ 144} while (0) 145 146#define AHD_NEVER_COL_IDX 0xFFFF 147 148/**************************** Driver Constants ********************************/ 149/* 150 * The maximum number of supported targets. 151 */ 152#define AHD_NUM_TARGETS 16 153 154/* 155 * The maximum number of supported luns. 156 * The identify message only supports 64 luns in non-packetized transfers. 157 * You can have 2^64 luns when information unit transfers are enabled, 158 * but until we see a need to support that many, we support 256. 159 */ 160#define AHD_NUM_LUNS_NONPKT 64 161#define AHD_NUM_LUNS 256 162 163/* 164 * The maximum transfer per S/G segment. 165 */ 166#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 167 168/* 169 * The maximum amount of SCB storage in hardware on a controller. 170 * This value represents an upper bound. Due to software design, 171 * we may not be able to use this number. 172 */ 173#define AHD_SCB_MAX 512 174 175/* 176 * The maximum number of concurrent transactions supported per driver instance. 177 * Sequencer Control Blocks (SCBs) store per-transaction information. 178 */ 179#define AHD_MAX_QUEUE AHD_SCB_MAX 180 181/* 182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 183 * in size and accomodate as many transactions as can be queued concurrently. 184 */ 185#define AHD_QIN_SIZE AHD_MAX_QUEUE 186#define AHD_QOUT_SIZE AHD_MAX_QUEUE 187 188#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 189/* 190 * The maximum amount of SCB storage we allocate in host memory. 191 */ 192#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 193 194/* 195 * Ring Buffer of incoming target commands. 196 * We allocate 256 to simplify the logic in the sequencer 197 * by using the natural wrap point of an 8bit counter. 198 */ 199#define AHD_TMODE_CMDS 256 200 201/* Reset line assertion time in us */ 202#define AHD_BUSRESET_DELAY 25 203 204/******************* Chip Characteristics/Operating Settings *****************/ 205/* 206 * Chip Type 207 * The chip order is from least sophisticated to most sophisticated. 208 */ 209typedef enum { 210 AHD_NONE = 0x0000, 211 AHD_CHIPID_MASK = 0x00FF, 212 AHD_AIC7901 = 0x0001, 213 AHD_AIC7902 = 0x0002, 214 AHD_AIC7901A = 0x0003, 215 AHD_PCI = 0x0100, /* Bus type PCI */ 216 AHD_PCIX = 0x0200, /* Bus type PCIX */ 217 AHD_BUS_MASK = 0x0F00 218} ahd_chip; 219 220/* 221 * Features available in each chip type. 222 */ 223typedef enum { 224 AHD_FENONE = 0x00000, 225 AHD_WIDE = 0x00001,/* Wide Channel */ 226 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 227 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 228 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 229 AHD_RTI = 0x04000,/* Retained Training Support */ 230 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 231 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 232 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 233 AHD_AIC7901_FE = AHD_FENONE, 234 AHD_AIC7902_FE = AHD_MULTI_FUNC 235} ahd_feature; 236 237/* 238 * Bugs in the silicon that we work around in software. 239 */ 240typedef enum { 241 AHD_BUGNONE = 0x0000, 242 /* 243 * Rev A hardware fails to update LAST/CURR/NEXTSCB 244 * correctly in certain packetized selection cases. 245 */ 246 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 247 /* The wrong SCB is accessed to check the abort pending bit. */ 248 AHD_ABORT_LQI_BUG = 0x0002, 249 /* Packetized bitbucket crosses packet boundaries. */ 250 AHD_PKT_BITBUCKET_BUG = 0x0004, 251 /* The selection timer runs twice as long as its setting. */ 252 AHD_LONG_SETIMO_BUG = 0x0008, 253 /* The Non-LQ CRC error status is delayed until phase change. */ 254 AHD_NLQICRC_DELAYED_BUG = 0x0010, 255 /* The chip must be reset for all outgoing bus resets. */ 256 AHD_SCSIRST_BUG = 0x0020, 257 /* Some PCIX fields must be saved and restored across chip reset. */ 258 AHD_PCIX_CHIPRST_BUG = 0x0040, 259 /* MMAPIO is not functional in PCI-X mode. */ 260 AHD_PCIX_MMAPIO_BUG = 0x0080, 261 /* Bug workarounds that can be disabled on non-PCIX busses. */ 262 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 263 | AHD_PCIX_MMAPIO_BUG, 264 /* 265 * LQOSTOP0 status set even for forced selections with ATN 266 * to perform non-packetized message delivery. 267 */ 268 AHD_LQO_ATNO_BUG = 0x0100, 269 /* FIFO auto-flush does not always trigger. */ 270 AHD_AUTOFLUSH_BUG = 0x0200, 271 /* The CLRLQO registers are not self-clearing. */ 272 AHD_CLRLQO_AUTOCLR_BUG = 0x0400, 273 /* The PACKETIZED status bit refers to the previous connection. */ 274 AHD_PKTIZED_STATUS_BUG = 0x0800, 275 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 276 AHD_PKT_LUN_BUG = 0x1000, 277 /* 278 * Only the FIFO allocated to the non-packetized connection may 279 * be in use during a non-packetzied connection. 280 */ 281 AHD_NONPACKFIFO_BUG = 0x2000, 282 /* 283 * Writing to a DFF SCBPTR register may fail if concurent with 284 * a hardware write to the other DFF SCBPTR register. This is 285 * not currently a concern in our sequencer since all chips with 286 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 287 * occur in non-packetized connections. 288 */ 289 AHD_MDFF_WSCBPTR_BUG = 0x4000, 290 /* SGHADDR updates are slow. */ 291 AHD_REG_SLOW_SETTLE_BUG = 0x8000, 292 /* 293 * Changing the MODE_PTR coincident with an interrupt that 294 * switches to a different mode will cause the interrupt to 295 * be in the mode written outside of interrupt context. 296 */ 297 AHD_SET_MODE_BUG = 0x10000, 298 /* Non-packetized busfree revision does not work. */ 299 AHD_BUSFREEREV_BUG = 0x20000, 300 /* 301 * Paced transfers are indicated with a non-standard PPR 302 * option bit in the neg table, 160MHz is indicated by 303 * sync factor 0x7, and the offset if off by a factor of 2. 304 */ 305 AHD_PACED_NEGTABLE_BUG = 0x40000, 306 /* LQOOVERRUN false positives. */ 307 AHD_LQOOVERRUN_BUG = 0x80000, 308 /* 309 * Controller write to INTSTAT will lose to a host 310 * write to CLRINT. 311 */ 312 AHD_INTCOLLISION_BUG = 0x100000 313} ahd_bug; 314 315/* 316 * Configuration specific settings. 317 * The driver determines these settings by probing the 318 * chip/controller's configuration. 319 */ 320typedef enum { 321 AHD_FNONE = 0x00000, 322 AHD_PRIMARY_CHANNEL = 0x00003,/* 323 * The channel that should 324 * be probed first. 325 */ 326 AHD_USEDEFAULTS = 0x00004,/* 327 * For cards without an seeprom 328 * or a BIOS to initialize the chip's 329 * SRAM, we use the default target 330 * settings. 331 */ 332 AHD_SEQUENCER_DEBUG = 0x00008, 333 AHD_RESET_BUS_A = 0x00010, 334 AHD_EXTENDED_TRANS_A = 0x00020, 335 AHD_TERM_ENB_A = 0x00040, 336 AHD_SPCHK_ENB_A = 0x00080, 337 AHD_STPWLEVEL_A = 0x00100, 338 AHD_INITIATORROLE = 0x00200,/* 339 * Allow initiator operations on 340 * this controller. 341 */ 342 AHD_TARGETROLE = 0x00400,/* 343 * Allow target operations on this 344 * controller. 345 */ 346 AHD_RESOURCE_SHORTAGE = 0x00800, 347 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 348 AHD_INT50_SPEEDFLEX = 0x02000,/* 349 * Internal 50pin connector 350 * sits behind an aic3860 351 */ 352 AHD_BIOS_ENABLED = 0x04000, 353 AHD_ALL_INTERRUPTS = 0x08000, 354 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 355 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 356 AHD_CURRENT_SENSING = 0x40000, 357 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 358 AHD_HP_BOARD = 0x100000, 359 AHD_RESET_POLL_ACTIVE = 0x200000, 360 AHD_UPDATE_PEND_CMDS = 0x400000, 361 AHD_RUNNING_QOUTFIFO = 0x800000 362} ahd_flag; 363 364/************************* Hardware SCB Definition ***************************/ 365 366/* 367 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 368 * consists of a "hardware SCB" mirroring the fields availible on the card 369 * and additional information the kernel stores for each transaction. 370 * 371 * To minimize space utilization, a portion of the hardware scb stores 372 * different data during different portions of a SCSI transaction. 373 * As initialized by the host driver for the initiator role, this area 374 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 375 * the cdb has been presented to the target, this area serves to store 376 * residual transfer information and the SCSI status byte. 377 * For the target role, the contents of this area do not change, but 378 * still serve a different purpose than for the initiator role. See 379 * struct target_data for details. 380 */ 381 382/* 383 * Status information embedded in the shared poriton of 384 * an SCB after passing the cdb to the target. The kernel 385 * driver will only read this data for transactions that 386 * complete abnormally. 387 */ 388struct initiator_status { 389 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 390 uint32_t residual_sgptr; /* The next S/G for this transfer */ 391 uint8_t scsi_status; /* Standard SCSI status byte */ 392}; 393 394struct target_status { 395 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 396 uint32_t residual_sgptr; /* The next S/G for this transfer */ 397 uint8_t scsi_status; /* SCSI status to give to initiator */ 398 uint8_t target_phases; /* Bitmap of phases to execute */ 399 uint8_t data_phase; /* Data-In or Data-Out */ 400 uint8_t initiator_tag; /* Initiator's transaction tag */ 401}; 402 403/* 404 * Initiator mode SCB shared data area. 405 * If the embedded CDB is 12 bytes or less, we embed 406 * the sense buffer address in the SCB. This allows 407 * us to retrieve sense information without interupting 408 * the host in packetized mode. 409 */ 410typedef uint32_t sense_addr_t; 411#define MAX_CDB_LEN 16 412#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 413union initiator_data { 414 uint64_t cdbptr; 415 uint8_t cdb[MAX_CDB_LEN]; 416 struct { 417 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 418 sense_addr_t sense_addr; 419 } cdb_plus_saddr; 420}; 421 422/* 423 * Target mode version of the shared data SCB segment. 424 */ 425struct target_data { 426 uint32_t spare[2]; 427 uint8_t scsi_status; /* SCSI status to give to initiator */ 428 uint8_t target_phases; /* Bitmap of phases to execute */ 429 uint8_t data_phase; /* Data-In or Data-Out */ 430 uint8_t initiator_tag; /* Initiator's transaction tag */ 431}; 432 433struct hardware_scb { 434/*0*/ union { 435 union initiator_data idata; 436 struct target_data tdata; 437 struct initiator_status istatus; 438 struct target_status tstatus; 439 } shared_data; 440/* 441 * A word about residuals. 442 * The scb is presented to the sequencer with the dataptr and datacnt 443 * fields initialized to the contents of the first S/G element to 444 * transfer. The sgptr field is initialized to the bus address for 445 * the S/G element that follows the first in the in core S/G array 446 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 447 * S/G entry for this transfer (single S/G element transfer with the 448 * first elements address and length preloaded in the dataptr/datacnt 449 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 450 * The SG_FULL_RESID flag ensures that the residual will be correctly 451 * noted even if no data transfers occur. Once the data phase is entered, 452 * the residual sgptr and datacnt are loaded from the sgptr and the 453 * datacnt fields. After each S/G element's dataptr and length are 454 * loaded into the hardware, the residual sgptr is advanced. After 455 * each S/G element is expired, its datacnt field is checked to see 456 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 457 * residual sg ptr and the transfer is considered complete. If the 458 * sequencer determines that there is a residual in the tranfer, or 459 * there is non-zero status, it will set the SG_STATUS_VALID flag in 460 * sgptr and dma the scb back into host memory. To sumarize: 461 * 462 * Sequencer: 463 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 464 * or residual_sgptr does not have SG_LIST_NULL set. 465 * 466 * o We are transfering the last segment if residual_datacnt has 467 * the SG_LAST_SEG flag set. 468 * 469 * Host: 470 * o A residual can only have occurred if a completed scb has the 471 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 472 * the residual_datacnt, and the residual_sgptr field will tell 473 * for sure. 474 * 475 * o residual_sgptr and sgptr refer to the "next" sg entry 476 * and so may point beyond the last valid sg entry for the 477 * transfer. 478 */ 479#define SG_PTR_MASK 0xFFFFFFF8 480/*16*/ uint16_t tag; 481/*18*/ uint8_t cdb_len; 482/*19*/ uint8_t task_management; 483/*20*/ uint32_t next_hscb_busaddr; 484/*24*/ uint64_t dataptr; 485/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 486/*36*/ uint32_t sgptr; 487/*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 488/*41*/ uint8_t scsiid; /* 489 * Selection out Id 490 * Our Id (bits 0-3) Their ID (bits 4-7) 491 */ 492/*42*/ uint8_t lun; 493/*43*/ uint8_t task_attribute; 494/*44*/ uint32_t hscb_busaddr; 495/******* Long lun field only downloaded for full 8 byte lun support *******/ 496/*48*/ uint8_t pkt_long_lun[8]; 497/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 498/*56*/ uint8_t spare[8]; 499}; 500 501/************************ Kernel SCB Definitions ******************************/ 502/* 503 * Some fields of the SCB are OS dependent. Here we collect the 504 * definitions for elements that all OS platforms need to include 505 * in there SCB definition. 506 */ 507 508/* 509 * Definition of a scatter/gather element as transfered to the controller. 510 * The aic7xxx chips only support a 24bit length. We use the top byte of 511 * the length to store additional address bits and a flag to indicate 512 * that a given segment terminates the transfer. This gives us an 513 * addressable range of 512GB on machines with 64bit PCI or with chips 514 * that can support dual address cycles on 32bit PCI busses. 515 */ 516struct ahd_dma_seg { 517 uint32_t addr; 518 uint32_t len; 519#define AHD_DMA_LAST_SEG 0x80000000 520#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 521#define AHD_SG_LEN_MASK 0x00FFFFFF 522}; 523 524struct ahd_dma64_seg { 525 uint64_t addr; 526 uint32_t len; 527 uint32_t pad; 528}; 529 530struct map_node { 531 bus_dmamap_t dmamap; 532 bus_addr_t physaddr; 533 uint8_t *vaddr; 534 SLIST_ENTRY(map_node) links; 535}; 536 537/* 538 * The current state of this SCB. 539 */ 540typedef enum { 541 SCB_FLAG_NONE = 0x00000, 542 SCB_TRANSMISSION_ERROR = 0x00001,/* 543 * We detected a parity or CRC 544 * error that has effected the 545 * payload of the command. This 546 * flag is checked when normal 547 * status is returned to catch 548 * the case of a target not 549 * responding to our attempt 550 * to report the error. 551 */ 552 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 553 * Another device was active 554 * during the first timeout for 555 * this SCB so we gave ourselves 556 * an additional timeout period 557 * in case it was hogging the 558 * bus. 559 */ 560 SCB_DEVICE_RESET = 0x00004, 561 SCB_SENSE = 0x00008, 562 SCB_CDB32_PTR = 0x00010, 563 SCB_RECOVERY_SCB = 0x00020, 564 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 565 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 566 SCB_ABORT = 0x00100, 567 SCB_ACTIVE = 0x00200, 568 SCB_TARGET_IMMEDIATE = 0x00400, 569 SCB_PACKETIZED = 0x00800, 570 SCB_EXPECT_PPR_BUSFREE = 0x01000, 571 SCB_PKT_SENSE = 0x02000, 572 SCB_CMDPHASE_ABORT = 0x04000, 573 SCB_ON_COL_LIST = 0x08000, 574 SCB_SILENT = 0x10000 /* 575 * Be quiet about transmission type 576 * errors. They are expected and we 577 * don't want to upset the user. This 578 * flag is typically used during DV. 579 */ 580} scb_flag; 581 582struct scb { 583 struct hardware_scb *hscb; 584 union { 585 SLIST_ENTRY(scb) sle; 586 LIST_ENTRY(scb) le; 587 TAILQ_ENTRY(scb) tqe; 588 } links; 589 union { 590 SLIST_ENTRY(scb) sle; 591 LIST_ENTRY(scb) le; 592 TAILQ_ENTRY(scb) tqe; 593 } links2; 594#define pending_links links2.le 595#define collision_links links2.le 596 struct scb *col_scb; 597 ahd_io_ctx_t io_ctx; 598 struct ahd_softc *ahd_softc; 599 scb_flag flags; 600#ifndef __linux__ 601 bus_dmamap_t dmamap; 602#endif 603 struct scb_platform_data *platform_data; 604 struct map_node *hscb_map; 605 struct map_node *sg_map; 606 struct map_node *sense_map; 607 void *sg_list; 608 uint8_t *sense_data; 609 bus_addr_t sg_list_busaddr; 610 bus_addr_t sense_busaddr; 611 u_int sg_count;/* How full ahd_dma_seg is */ 612#define AHD_MAX_LQ_CRC_ERRORS 5 613 u_int crc_retry_count; 614}; 615 616TAILQ_HEAD(scb_tailq, scb); 617LIST_HEAD(scb_list, scb); 618 619struct scb_data { 620 /* 621 * TAILQ of lists of free SCBs grouped by device 622 * collision domains. 623 */ 624 struct scb_tailq free_scbs; 625 626 /* 627 * Per-device lists of SCBs whose tag ID would collide 628 * with an already active tag on the device. 629 */ 630 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 631 632 /* 633 * SCBs that will not collide with any active device. 634 */ 635 struct scb_list any_dev_free_scb_list; 636 637 /* 638 * Mapping from tag to SCB. 639 */ 640 struct scb *scbindex[AHD_SCB_MAX]; 641 642 /* 643 * "Bus" addresses of our data structures. 644 */ 645 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 646 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 647 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 648 SLIST_HEAD(, map_node) hscb_maps; 649 SLIST_HEAD(, map_node) sg_maps; 650 SLIST_HEAD(, map_node) sense_maps; 651 int scbs_left; /* unallocated scbs in head map_node */ 652 int sgs_left; /* unallocated sgs in head map_node */ 653 int sense_left; /* unallocated sense in head map_node */ 654 uint16_t numscbs; 655 uint16_t maxhscbs; /* Number of SCBs on the card */ 656 uint8_t init_level; /* 657 * How far we've initialized 658 * this structure. 659 */ 660}; 661 662/************************ Target Mode Definitions *****************************/ 663 664/* 665 * Connection desciptor for select-in requests in target mode. 666 */ 667struct target_cmd { 668 uint8_t scsiid; /* Our ID and the initiator's ID */ 669 uint8_t identify; /* Identify message */ 670 uint8_t bytes[22]; /* 671 * Bytes contains any additional message 672 * bytes terminated by 0xFF. The remainder 673 * is the cdb to execute. 674 */ 675 uint8_t cmd_valid; /* 676 * When a command is complete, the firmware 677 * will set cmd_valid to all bits set. 678 * After the host has seen the command, 679 * the bits are cleared. This allows us 680 * to just peek at host memory to determine 681 * if more work is complete. cmd_valid is on 682 * an 8 byte boundary to simplify setting 683 * it on aic7880 hardware which only has 684 * limited direct access to the DMA FIFO. 685 */ 686 uint8_t pad[7]; 687}; 688 689/* 690 * Number of events we can buffer up if we run out 691 * of immediate notify ccbs. 692 */ 693#define AHD_TMODE_EVENT_BUFFER_SIZE 8 694struct ahd_tmode_event { 695 uint8_t initiator_id; 696 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 697#define EVENT_TYPE_BUS_RESET 0xFF 698 uint8_t event_arg; 699}; 700 701/* 702 * Per enabled lun target mode state. 703 * As this state is directly influenced by the host OS'es target mode 704 * environment, we let the OS module define it. Forward declare the 705 * structure here so we can store arrays of them, etc. in OS neutral 706 * data structures. 707 */ 708#ifdef AHD_TARGET_MODE 709struct ahd_tmode_lstate { 710 struct cam_path *path; 711 struct ccb_hdr_slist accept_tios; 712 struct ccb_hdr_slist immed_notifies; 713 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 714 uint8_t event_r_idx; 715 uint8_t event_w_idx; 716}; 717#else 718struct ahd_tmode_lstate; 719#endif 720 721/******************** Transfer Negotiation Datastructures *********************/ 722#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 723#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 724#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 725#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 726#define AHD_PERIOD_10MHz 0x19 727 728#define AHD_WIDTH_UNKNOWN 0xFF 729#define AHD_PERIOD_UNKNOWN 0xFF 730#define AHD_OFFSET_UNKNOWN 0x0 731#define AHD_PPR_OPTS_UNKNOWN 0xFF 732 733/* 734 * Transfer Negotiation Information. 735 */ 736struct ahd_transinfo { 737 uint8_t protocol_version; /* SCSI Revision level */ 738 uint8_t transport_version; /* SPI Revision level */ 739 uint8_t width; /* Bus width */ 740 uint8_t period; /* Sync rate factor */ 741 uint8_t offset; /* Sync offset */ 742 uint8_t ppr_options; /* Parallel Protocol Request options */ 743}; 744 745/* 746 * Per-initiator current, goal and user transfer negotiation information. */ 747struct ahd_initiator_tinfo { 748 struct ahd_transinfo curr; 749 struct ahd_transinfo goal; 750 struct ahd_transinfo user; 751}; 752 753/* 754 * Per enabled target ID state. 755 * Pointers to lun target state as well as sync/wide negotiation information 756 * for each initiator<->target mapping. For the initiator role we pretend 757 * that we are the target and the targets are the initiators since the 758 * negotiation is the same regardless of role. 759 */ 760struct ahd_tmode_tstate { 761 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 762 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 763 764 /* 765 * Per initiator state bitmasks. 766 */ 767 uint16_t auto_negotiate;/* Auto Negotiation Required */ 768 uint16_t discenable; /* Disconnection allowed */ 769 uint16_t tagenable; /* Tagged Queuing allowed */ 770}; 771 772/* 773 * Points of interest along the negotiated transfer scale. 774 */ 775#define AHD_SYNCRATE_160 0x8 776#define AHD_SYNCRATE_PACED 0x8 777#define AHD_SYNCRATE_DT 0x9 778#define AHD_SYNCRATE_ULTRA2 0xa 779#define AHD_SYNCRATE_ULTRA 0xc 780#define AHD_SYNCRATE_FAST 0x19 781#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 782#define AHD_SYNCRATE_SYNC 0x32 783#define AHD_SYNCRATE_MIN 0x60 784#define AHD_SYNCRATE_ASYNC 0xFF 785#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 786 787/* Safe and valid period for async negotiations. */ 788#define AHD_ASYNC_XFER_PERIOD 0x44 789 790/* 791 * In RevA, the synctable uses a 120MHz rate for the period 792 * factor 8 and 160MHz for the period factor 7. The 120MHz 793 * rate never made it into the official SCSI spec, so we must 794 * compensate when setting the negotiation table for Rev A 795 * parts. 796 */ 797#define AHD_SYNCRATE_REVA_120 0x8 798#define AHD_SYNCRATE_REVA_160 0x7 799 800/***************************** Lookup Tables **********************************/ 801/* 802 * Phase -> name and message out response 803 * to parity errors in each phase table. 804 */ 805struct ahd_phase_table_entry { 806 uint8_t phase; 807 uint8_t mesg_out; /* Message response to parity errors */ 808 char *phasemsg; 809}; 810 811/************************** Serial EEPROM Format ******************************/ 812 813struct seeprom_config { 814/* 815 * Per SCSI ID Configuration Flags 816 */ 817 uint16_t device_flags[16]; /* words 0-15 */ 818#define CFXFER 0x003F /* synchronous transfer rate */ 819#define CFXFER_ASYNC 0x3F 820#define CFQAS 0x0040 /* Negotiate QAS */ 821#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 822#define CFSTART 0x0100 /* send start unit SCSI command */ 823#define CFINCBIOS 0x0200 /* include in BIOS scan */ 824#define CFDISC 0x0400 /* enable disconnection */ 825#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 826#define CFWIDEB 0x1000 /* wide bus device */ 827#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 828 829/* 830 * BIOS Control Bits 831 */ 832 uint16_t bios_control; /* word 16 */ 833#define CFSUPREM 0x0001 /* support all removeable drives */ 834#define CFSUPREMB 0x0002 /* support removeable boot drives */ 835#define CFBIOSSTATE 0x000C /* BIOS Action State */ 836#define CFBS_DISABLED 0x00 837#define CFBS_ENABLED 0x04 838#define CFBS_DISABLED_SCAN 0x08 839#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 840#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 841#define CFSPARITY 0x0040 /* SCSI parity */ 842#define CFEXTEND 0x0080 /* extended translation enabled */ 843#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 844#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 845#define CFMSG_VERBOSE 0x0000 846#define CFMSG_SILENT 0x0200 847#define CFMSG_DIAG 0x0400 848#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 849/* UNUSED 0xf000 */ 850 851/* 852 * Host Adapter Control Bits 853 */ 854 uint16_t adapter_control; /* word 17 */ 855#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 856#define CFSTERM 0x0002 /* SCSI low byte termination */ 857#define CFWSTERM 0x0004 /* SCSI high byte termination */ 858#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 859#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 860#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 861#define CFSTPWLEVEL 0x0040 /* Termination level control */ 862#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 863#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 864#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 865 866/* 867 * Bus Release Time, Host Adapter ID 868 */ 869 uint16_t brtime_id; /* word 18 */ 870#define CFSCSIID 0x000f /* host adapter SCSI ID */ 871/* UNUSED 0x00f0 */ 872#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 873 874/* 875 * Maximum targets 876 */ 877 uint16_t max_targets; /* word 19 */ 878#define CFMAXTARG 0x00ff /* maximum targets */ 879#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 880#define CFBOOTID 0xf000 /* Target to boot from */ 881 uint16_t res_1[10]; /* words 20-29 */ 882 uint16_t signature; /* BIOS Signature */ 883#define CFSIGNATURE 0x400 884 uint16_t checksum; /* word 31 */ 885}; 886 887/****************************** Flexport Logic ********************************/ 888#define FLXADDR_TERMCTL 0x0 889#define FLX_TERMCTL_ENSECHIGH 0x8 890#define FLX_TERMCTL_ENSECLOW 0x4 891#define FLX_TERMCTL_ENPRIHIGH 0x2 892#define FLX_TERMCTL_ENPRILOW 0x1 893#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 894#define FLX_ROMSTAT_SEECFG 0xF0 895#define FLX_ROMSTAT_EECFG 0x0F 896#define FLX_ROMSTAT_SEE_93C66 0x00 897#define FLX_ROMSTAT_SEE_NONE 0xF0 898#define FLX_ROMSTAT_EE_512x8 0x0 899#define FLX_ROMSTAT_EE_1MBx8 0x1 900#define FLX_ROMSTAT_EE_2MBx8 0x2 901#define FLX_ROMSTAT_EE_4MBx8 0x3 902#define FLX_ROMSTAT_EE_16MBx8 0x4 903#define CURSENSE_ENB 0x1 904#define FLXADDR_FLEXSTAT 0x2 905#define FLX_FSTAT_BUSY 0x1 906#define FLXADDR_CURRENT_STAT 0x4 907#define FLX_CSTAT_SEC_HIGH 0xC0 908#define FLX_CSTAT_SEC_LOW 0x30 909#define FLX_CSTAT_PRI_HIGH 0x0C 910#define FLX_CSTAT_PRI_LOW 0x03 911#define FLX_CSTAT_MASK 0x03 912#define FLX_CSTAT_SHIFT 2 913#define FLX_CSTAT_OKAY 0x0 914#define FLX_CSTAT_OVER 0x1 915#define FLX_CSTAT_UNDER 0x2 916#define FLX_CSTAT_INVALID 0x3 917 918int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 919 u_int start_addr, u_int count); 920 921int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 922 u_int start_addr, u_int count); 923int ahd_wait_seeprom(struct ahd_softc *ahd); 924int ahd_verify_cksum(struct seeprom_config *sc); 925int ahd_acquire_seeprom(struct ahd_softc *ahd); 926void ahd_release_seeprom(struct ahd_softc *ahd); 927 928/**************************** Message Buffer *********************************/ 929typedef enum { 930 MSG_FLAG_NONE = 0x00, 931 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 932 MSG_FLAG_IU_REQ_CHANGED = 0x02, 933 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 934 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 935 MSG_FLAG_PACKETIZED = 0x10 936} ahd_msg_flags; 937 938typedef enum { 939 MSG_TYPE_NONE = 0x00, 940 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 941 MSG_TYPE_INITIATOR_MSGIN = 0x02, 942 MSG_TYPE_TARGET_MSGOUT = 0x03, 943 MSG_TYPE_TARGET_MSGIN = 0x04 944} ahd_msg_type; 945 946typedef enum { 947 MSGLOOP_IN_PROG, 948 MSGLOOP_MSGCOMPLETE, 949 MSGLOOP_TERMINATED 950} msg_loop_stat; 951 952/*********************** Software Configuration Structure *********************/ 953struct ahd_suspend_channel_state { 954 uint8_t scsiseq; 955 uint8_t sxfrctl0; 956 uint8_t sxfrctl1; 957 uint8_t simode0; 958 uint8_t simode1; 959 uint8_t seltimer; 960 uint8_t seqctl; 961}; 962 963struct ahd_suspend_state { 964 struct ahd_suspend_channel_state channel[2]; 965 uint8_t optionmode; 966 uint8_t dscommand0; 967 uint8_t dspcistatus; 968 /* hsmailbox */ 969 uint8_t crccontrol1; 970 uint8_t scbbaddr; 971 /* Host and sequencer SCB counts */ 972 uint8_t dff_thrsh; 973 uint8_t *scratch_ram; 974 uint8_t *btt; 975}; 976 977typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 978 979typedef enum { 980 AHD_MODE_DFF0, 981 AHD_MODE_DFF1, 982 AHD_MODE_CCHAN, 983 AHD_MODE_SCSI, 984 AHD_MODE_CFG, 985 AHD_MODE_UNKNOWN 986} ahd_mode; 987 988#define AHD_MK_MSK(x) (0x01 << (x)) 989#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 990#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 991#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 992#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 993#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 994#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 995#define AHD_MODE_ANY_MSK (~0) 996 997typedef uint8_t ahd_mode_state; 998 999typedef void ahd_callback_t (void *); 1000 1001struct ahd_softc { 1002 bus_space_tag_t tags[2]; 1003 bus_space_handle_t bshs[2]; 1004#ifndef __linux__ 1005 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1006#endif 1007 struct scb_data scb_data; 1008 1009 struct hardware_scb *next_queued_hscb; 1010 1011 /* 1012 * SCBs that have been sent to the controller 1013 */ 1014 LIST_HEAD(, scb) pending_scbs; 1015 1016 /* 1017 * Current register window mode information. 1018 */ 1019 ahd_mode dst_mode; 1020 ahd_mode src_mode; 1021 1022 /* 1023 * Saved register window mode information 1024 * used for restore on next unpause. 1025 */ 1026 ahd_mode saved_dst_mode; 1027 ahd_mode saved_src_mode; 1028 1029 /* 1030 * Platform specific data. 1031 */ 1032 struct ahd_platform_data *platform_data; 1033 1034 /* 1035 * Platform specific device information. 1036 */ 1037 ahd_dev_softc_t dev_softc; 1038 1039 /* 1040 * Bus specific device information. 1041 */ 1042 ahd_bus_intr_t bus_intr; 1043 1044 /* 1045 * Target mode related state kept on a per enabled lun basis. 1046 * Targets that are not enabled will have null entries. 1047 * As an initiator, we keep one target entry for our initiator 1048 * ID to store our sync/wide transfer settings. 1049 */ 1050 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1051 1052 /* 1053 * The black hole device responsible for handling requests for 1054 * disabled luns on enabled targets. 1055 */ 1056 struct ahd_tmode_lstate *black_hole; 1057 1058 /* 1059 * Device instance currently on the bus awaiting a continue TIO 1060 * for a command that was not given the disconnect priveledge. 1061 */ 1062 struct ahd_tmode_lstate *pending_device; 1063 1064 /* 1065 * Timer handles for timer driven callbacks. 1066 */ 1067 ahd_timer_t reset_timer; 1068 ahd_timer_t stat_timer; 1069 1070 /* 1071 * Statistics. 1072 */ 1073#define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1074#define AHD_STAT_BUCKETS 4 1075 u_int cmdcmplt_bucket; 1076 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1077 uint32_t cmdcmplt_total; 1078 1079 /* 1080 * Card characteristics 1081 */ 1082 ahd_chip chip; 1083 ahd_feature features; 1084 ahd_bug bugs; 1085 ahd_flag flags; 1086 struct seeprom_config *seep_config; 1087 1088 /* Values to store in the SEQCTL register for pause and unpause */ 1089 uint8_t unpause; 1090 uint8_t pause; 1091 1092 /* Command Queues */ 1093 uint16_t qoutfifonext; 1094 uint16_t qoutfifonext_valid_tag; 1095 uint16_t qinfifonext; 1096 uint16_t qinfifo[AHD_SCB_MAX]; 1097 uint16_t *qoutfifo; 1098 1099 /* Critical Section Data */ 1100 struct cs *critical_sections; 1101 u_int num_critical_sections; 1102 1103 /* Buffer for handling packetized bitbucket. */ 1104 uint8_t *overrun_buf; 1105 1106 /* Links for chaining softcs */ 1107 TAILQ_ENTRY(ahd_softc) links; 1108 1109 /* Channel Names ('A', 'B', etc.) */ 1110 char channel; 1111 1112 /* Initiator Bus ID */ 1113 uint8_t our_id; 1114 1115 /* 1116 * Target incoming command FIFO. 1117 */ 1118 struct target_cmd *targetcmds; 1119 uint8_t tqinfifonext; 1120 1121 /* 1122 * Cached verson of the hs_mailbox so we can avoid 1123 * pausing the sequencer during mailbox updates. 1124 */ 1125 uint8_t hs_mailbox; 1126 1127 /* 1128 * Incoming and outgoing message handling. 1129 */ 1130 uint8_t send_msg_perror; 1131 ahd_msg_flags msg_flags; 1132 ahd_msg_type msg_type; 1133 uint8_t msgout_buf[12];/* Message we are sending */ 1134 uint8_t msgin_buf[12];/* Message we are receiving */ 1135 u_int msgout_len; /* Length of message to send */ 1136 u_int msgout_index; /* Current index in msgout */ 1137 u_int msgin_index; /* Current index in msgin */ 1138 1139 /* 1140 * Mapping information for data structures shared 1141 * between the sequencer and kernel. 1142 */ 1143 bus_dma_tag_t parent_dmat; 1144 bus_dma_tag_t shared_data_dmat; 1145 bus_dmamap_t shared_data_dmamap; 1146 bus_addr_t shared_data_busaddr; 1147 1148 /* Information saved through suspend/resume cycles */ 1149 struct ahd_suspend_state suspend_state; 1150 1151 /* Number of enabled target mode device on this card */ 1152 u_int enabled_luns; 1153 1154 /* Initialization level of this data structure */ 1155 u_int init_level; 1156 1157 /* PCI cacheline size. */ 1158 u_int pci_cachesize; 1159 1160 /* IO Cell Parameters */ 1161 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1162 1163 u_int stack_size; 1164 uint16_t *saved_stack; 1165 1166 /* Per-Unit descriptive information */ 1167 const char *description; 1168 const char *bus_description; 1169 char *name; 1170 int unit; 1171 1172 /* Selection Timer settings */ 1173 int seltime; 1174 1175 /* 1176 * Interrupt coalessing settings. 1177 */ 1178#define AHD_INT_COALESSING_TIMER_DEFAULT 250 /*us*/ 1179#define AHD_INT_COALESSING_MAXCMDS_DEFAULT 10 1180#define AHD_INT_COALESSING_MAXCMDS_MAX 127 1181#define AHD_INT_COALESSING_MINCMDS_DEFAULT 5 1182#define AHD_INT_COALESSING_MINCMDS_MAX 127 1183#define AHD_INT_COALESSING_THRESHOLD_DEFAULT 2000 1184#define AHD_INT_COALESSING_STOP_THRESHOLD_DEFAULT 1000 1185 u_int int_coalessing_timer; 1186 u_int int_coalessing_maxcmds; 1187 u_int int_coalessing_mincmds; 1188 u_int int_coalessing_threshold; 1189 u_int int_coalessing_stop_threshold; 1190 1191 uint16_t user_discenable;/* Disconnection allowed */ 1192 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1193}; 1194 1195TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1196extern struct ahd_softc_tailq ahd_tailq; 1197 1198/*************************** IO Cell Configuration ****************************/ 1199#define AHD_PRECOMP_SLEW_INDEX \ 1200 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1201 1202#define AHD_AMPLITUDE_INDEX \ 1203 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1204 1205#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1206do { \ 1207 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1208 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1209 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1210} while (0) 1211 1212#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1213do { \ 1214 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1215 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1216 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1217} while (0) 1218 1219#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1220do { \ 1221 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1222 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1223 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1224} while (0) 1225 1226/************************ Active Device Information ***************************/ 1227typedef enum { 1228 ROLE_UNKNOWN, 1229 ROLE_INITIATOR, 1230 ROLE_TARGET 1231} role_t; 1232 1233struct ahd_devinfo { 1234 int our_scsiid; 1235 int target_offset; 1236 uint16_t target_mask; 1237 u_int target; 1238 u_int lun; 1239 char channel; 1240 role_t role; /* 1241 * Only guaranteed to be correct if not 1242 * in the busfree state. 1243 */ 1244}; 1245 1246/****************************** PCI Structures ********************************/ 1247#define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/ 1248#define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */ 1249#define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */ 1250 1251typedef int (ahd_device_setup_t)(struct ahd_softc *); 1252 1253struct ahd_pci_identity { 1254 uint64_t full_id; 1255 uint64_t id_mask; 1256 char *name; 1257 ahd_device_setup_t *setup; 1258}; 1259extern struct ahd_pci_identity ahd_pci_ident_table []; 1260extern const u_int ahd_num_pci_devs; 1261 1262/***************************** VL/EISA Declarations ***************************/ 1263struct aic7770_identity { 1264 uint32_t full_id; 1265 uint32_t id_mask; 1266 char *name; 1267 ahd_device_setup_t *setup; 1268}; 1269extern struct aic7770_identity aic7770_ident_table []; 1270extern const int ahd_num_aic7770_devs; 1271 1272#define AHD_EISA_SLOT_OFFSET 0xc00 1273#define AHD_EISA_IOSIZE 0x100 1274 1275/*************************** Function Declarations ****************************/ 1276/******************************************************************************/ 1277void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1278u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1279void ahd_busy_tcl(struct ahd_softc *ahd, 1280 u_int tcl, u_int busyid); 1281static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1282static __inline void 1283ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1284{ 1285 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1286} 1287 1288/***************************** PCI Front End *********************************/ 1289struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1290int ahd_pci_config(struct ahd_softc *, 1291 struct ahd_pci_identity *); 1292int ahd_pci_test_register_access(struct ahd_softc *); 1293 1294/************************** SCB and SCB queue management **********************/ 1295int ahd_probe_scbs(struct ahd_softc *); 1296void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1297 struct scb *scb); 1298int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1299 int target, char channel, int lun, 1300 u_int tag, role_t role); 1301 1302/****************************** Initialization ********************************/ 1303struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1304int ahd_softc_init(struct ahd_softc *); 1305void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1306int ahd_init(struct ahd_softc *ahd); 1307int ahd_default_config(struct ahd_softc *ahd); 1308int ahd_parse_cfgdata(struct ahd_softc *ahd, 1309 struct seeprom_config *sc); 1310void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1311void ahd_update_coalessing_values(struct ahd_softc *ahd, 1312 u_int timer, 1313 u_int maxcmds, 1314 u_int mincmds); 1315void ahd_enable_coalessing(struct ahd_softc *ahd, 1316 int enable); 1317void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1318int ahd_suspend(struct ahd_softc *ahd); 1319int ahd_resume(struct ahd_softc *ahd); 1320void ahd_softc_insert(struct ahd_softc *); 1321struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1322void ahd_set_unit(struct ahd_softc *, int); 1323void ahd_set_name(struct ahd_softc *, char *); 1324struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1325void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1326void ahd_alloc_scbs(struct ahd_softc *ahd); 1327void ahd_free(struct ahd_softc *ahd); 1328int ahd_reset(struct ahd_softc *ahd); 1329void ahd_shutdown(void *arg); 1330int ahd_write_flexport(struct ahd_softc *ahd, 1331 u_int addr, u_int value); 1332int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1333 uint8_t *value); 1334int ahd_wait_flexport(struct ahd_softc *ahd); 1335 1336/*************************** Interrupt Services *******************************/ 1337void ahd_pci_intr(struct ahd_softc *ahd); 1338void ahd_clear_intstat(struct ahd_softc *ahd); 1339void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1340void ahd_run_qoutfifo(struct ahd_softc *ahd); 1341#ifdef AHD_TARGET_MODE 1342void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1343#endif 1344void ahd_handle_hwerrint(struct ahd_softc *ahd); 1345void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1346void ahd_handle_scsiint(struct ahd_softc *ahd, 1347 u_int intstat); 1348void ahd_clear_critical_section(struct ahd_softc *ahd); 1349 1350/***************************** Error Recovery *********************************/ 1351typedef enum { 1352 SEARCH_COMPLETE, 1353 SEARCH_COUNT, 1354 SEARCH_REMOVE, 1355 SEARCH_PRINT 1356} ahd_search_action; 1357int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1358 char channel, int lun, u_int tag, 1359 role_t role, uint32_t status, 1360 ahd_search_action action); 1361int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1362 char channel, int lun, u_int tag, 1363 int stop_on_first, int remove, 1364 int save_state); 1365void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1366int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1367 int initiate_reset); 1368int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1369 char channel, int lun, u_int tag, 1370 role_t role, uint32_t status); 1371void ahd_restart(struct ahd_softc *ahd); 1372void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1373void ahd_handle_scb_status(struct ahd_softc *ahd, 1374 struct scb *scb); 1375void ahd_handle_scsi_status(struct ahd_softc *ahd, 1376 struct scb *scb); 1377void ahd_calc_residual(struct ahd_softc *ahd, 1378 struct scb *scb); 1379/*************************** Utility Functions ********************************/ 1380struct ahd_phase_table_entry* 1381 ahd_lookup_phase_entry(int phase); 1382void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1383 u_int our_id, u_int target, 1384 u_int lun, char channel, 1385 role_t role); 1386/************************** Transfer Negotiation ******************************/ 1387void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1388 u_int *ppr_options, u_int maxsync); 1389void ahd_validate_offset(struct ahd_softc *ahd, 1390 struct ahd_initiator_tinfo *tinfo, 1391 u_int period, u_int *offset, 1392 int wide, role_t role); 1393void ahd_validate_width(struct ahd_softc *ahd, 1394 struct ahd_initiator_tinfo *tinfo, 1395 u_int *bus_width, 1396 role_t role); 1397/* 1398 * Negotiation types. These are used to qualify if we should renegotiate 1399 * even if our goal and current transport parameters are identical. 1400 */ 1401typedef enum { 1402 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1403 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1404 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1405} ahd_neg_type; 1406int ahd_update_neg_request(struct ahd_softc*, 1407 struct ahd_devinfo*, 1408 struct ahd_tmode_tstate*, 1409 struct ahd_initiator_tinfo*, 1410 ahd_neg_type); 1411void ahd_set_width(struct ahd_softc *ahd, 1412 struct ahd_devinfo *devinfo, 1413 u_int width, u_int type, int paused); 1414void ahd_set_syncrate(struct ahd_softc *ahd, 1415 struct ahd_devinfo *devinfo, 1416 u_int period, u_int offset, 1417 u_int ppr_options, 1418 u_int type, int paused); 1419typedef enum { 1420 AHD_QUEUE_NONE, 1421 AHD_QUEUE_BASIC, 1422 AHD_QUEUE_TAGGED 1423} ahd_queue_alg; 1424 1425void ahd_set_tags(struct ahd_softc *ahd, 1426 struct ahd_devinfo *devinfo, 1427 ahd_queue_alg alg); 1428 1429/**************************** Target Mode *************************************/ 1430#ifdef AHD_TARGET_MODE 1431void ahd_send_lstate_events(struct ahd_softc *, 1432 struct ahd_tmode_lstate *); 1433void ahd_handle_en_lun(struct ahd_softc *ahd, 1434 struct cam_sim *sim, union ccb *ccb); 1435cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1436 struct cam_sim *sim, union ccb *ccb, 1437 struct ahd_tmode_tstate **tstate, 1438 struct ahd_tmode_lstate **lstate, 1439 int notfound_failure); 1440#ifndef AHD_TMODE_ENABLE 1441#define AHD_TMODE_ENABLE 0 1442#endif 1443#endif 1444/******************************* Debug ***************************************/ 1445#ifdef AHD_DEBUG 1446extern uint32_t ahd_debug; 1447#define AHD_SHOW_MISC 0x00001 1448#define AHD_SHOW_SENSE 0x00002 1449#define AHD_SHOW_RECOVERY 0x00004 1450#define AHD_DUMP_SEEPROM 0x00008 1451#define AHD_SHOW_TERMCTL 0x00010 1452#define AHD_SHOW_MEMORY 0x00020 1453#define AHD_SHOW_MESSAGES 0x00040 1454#define AHD_SHOW_MODEPTR 0x00080 1455#define AHD_SHOW_SELTO 0x00100 1456#define AHD_SHOW_FIFOS 0x00200 1457#define AHD_SHOW_QFULL 0x00400 1458#define AHD_SHOW_DV 0x00800 1459#define AHD_SHOW_MASKED_ERRORS 0x01000 1460#define AHD_SHOW_QUEUE 0x02000 1461#define AHD_SHOW_TQIN 0x04000 1462#define AHD_SHOW_SG 0x08000 1463#define AHD_SHOW_INT_COALESSING 0x10000 1464#define AHD_DEBUG_SEQUENCER 0x20000 1465#endif 1466void ahd_print_scb(struct scb *scb); 1467void ahd_print_devinfo(struct ahd_softc *ahd, 1468 struct ahd_devinfo *devinfo); 1469void ahd_dump_sglist(struct scb *scb); 1470void ahd_dump_all_cards_state(void); 1471void ahd_dump_card_state(struct ahd_softc *ahd); 1472int ahd_print_register(ahd_reg_parse_entry_t *table, 1473 u_int num_entries, 1474 const char *name, 1475 u_int address, 1476 u_int value, 1477 u_int *cur_column, 1478 u_int wrap_point); 1479void ahd_dump_scbs(struct ahd_softc *ahd); 1480#endif /* _AIC79XX_H_ */ 1481