aic79xx.h revision 102680
1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#56 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic79xx.h 102680 2002-08-31 06:48:42Z gibbs $ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef MAX 57#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58#endif 59 60#ifndef MIN 61#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62#endif 63 64#ifndef TRUE 65#define TRUE 1 66#endif 67#ifndef FALSE 68#define FALSE 0 69#endif 70 71#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73#define ALL_CHANNELS '\0' 74#define ALL_TARGETS_MASK 0xFFFF 75#define INITIATOR_WILDCARD (~0) 76#define SCB_LIST_NULL 0xFF00 77#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78#define QOUTFIFO_ENTRY_VALID 0x8000 79#define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 80#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82#define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84#define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86#define SCSIID_CHANNEL(ahd, scsiid) ('A') 87#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88#define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90#define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92#define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94#define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98#define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100/* 101 * TCLs have the following format: TTTTLLLLLLLL 102 */ 103#define TCL_TARGET_OFFSET(tcl) \ 104 ((((tcl) >> 4) & TID) >> 4) 105#define TCL_LUN(tcl) \ 106 (tcl & (AHD_NUM_LUNS - 1)) 107#define BUILD_TCL(scsiid, lun) \ 108 ((lun) | (((scsiid) & TID) << 4)) 109#define BUILD_TCL_RAW(target, channel, lun) \ 110 ((lun) | ((target) << 8)) 111 112#define SCB_GET_TAG(scb) \ 113 ahd_le16toh(scb->hscb->tag) 114 115#ifndef AHD_TARGET_MODE 116#undef AHD_TMODE_ENABLE 117#define AHD_TMODE_ENABLE 0 118#endif 119 120#define AHD_BUILD_COL_IDX(target, lun) \ 121 (((lun) << 4) | target) 122 123#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 124 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 125 126#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 127do { \ 128 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 129 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 130} while (0) 131 132#define AHD_COPY_SCB_COL_IDX(dst, src) \ 133do { \ 134 dst->hscb->scsiid = src->hscb->scsiid; \ 135 dst->hscb->lun = src->hscb->lun; \ 136} while (0) 137 138#define AHD_NEVER_COL_IDX 0xFFFF 139 140/**************************** Driver Constants ********************************/ 141/* 142 * The maximum number of supported targets. 143 */ 144#define AHD_NUM_TARGETS 16 145 146/* 147 * The maximum number of supported luns. 148 * The identify message only supports 64 luns in non-packetized transfers. 149 * You can have 2^64 luns when information unit transfers are enabled, 150 * but until we see a need to support that many, we support 256. 151 */ 152#define AHD_NUM_LUNS_NONPKT 64 153#define AHD_NUM_LUNS 256 154 155/* 156 * The maximum transfer per S/G segment. 157 */ 158#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 159 160/* 161 * The maximum amount of SCB storage in hardware on a controller. 162 * This value represents an upper bound. Due to software design, 163 * we may not be able to use this number. 164 */ 165#define AHD_SCB_MAX 512 166 167/* 168 * The maximum number of concurrent transactions supported per driver instance. 169 * Sequencer Control Blocks (SCBs) store per-transaction information. 170 */ 171#define AHD_MAX_QUEUE AHD_SCB_MAX 172 173/* 174 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 175 * in size and accomodate as many transactions as can be queued concurrently. 176 */ 177#define AHD_QIN_SIZE AHD_MAX_QUEUE 178#define AHD_QOUT_SIZE AHD_MAX_QUEUE 179 180#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 181/* 182 * The maximum amount of SCB storage we allocate in host memory. 183 */ 184#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 185 186/* 187 * Ring Buffer of incoming target commands. 188 * We allocate 256 to simplify the logic in the sequencer 189 * by using the natural wrap point of an 8bit counter. 190 */ 191#define AHD_TMODE_CMDS 256 192 193/* Reset line assertion time in us */ 194#define AHD_BUSRESET_DELAY 25 195 196/******************* Chip Characteristics/Operating Settings *****************/ 197/* 198 * Chip Type 199 * The chip order is from least sophisticated to most sophisticated. 200 */ 201typedef enum { 202 AHD_NONE = 0x0000, 203 AHD_CHIPID_MASK = 0x00FF, 204 AHD_AIC7901 = 0x0001, 205 AHD_AIC7902 = 0x0002, 206 AHD_AIC7901A = 0x0003, 207 AHD_PCI = 0x0100, /* Bus type PCI */ 208 AHD_PCIX = 0x0200, /* Bus type PCIX */ 209 AHD_BUS_MASK = 0x0F00 210} ahd_chip; 211 212/* 213 * Features available in each chip type. 214 */ 215typedef enum { 216 AHD_FENONE = 0x00000, 217 AHD_WIDE = 0x00001, /* Wide Channel */ 218 AHD_MULTI_FUNC = 0x00100, /* Multi-Function Twin Channel Device */ 219 AHD_TARGETMODE = 0x01000, /* Has tested target mode support */ 220 AHD_MULTIROLE = 0x02000, /* Space for two roles at a time */ 221 AHD_REMOVABLE = 0x00000, /* Hot-Swap supported - None so far*/ 222 AHD_AIC7901_FE = AHD_FENONE, 223 AHD_AIC7902_FE = AHD_MULTI_FUNC 224} ahd_feature; 225 226/* 227 * Bugs in the silicon that we work around in software. 228 */ 229typedef enum { 230 AHD_BUGNONE = 0x0000, 231 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 232 AHD_ABORT_LQI_BUG = 0x0002, 233 AHD_PKT_BITBUCKET_BUG = 0x0004, 234 AHD_LONG_SETIMO_BUG = 0x0008, 235 AHD_NLQICRC_DELAYED_BUG = 0x0010, 236 AHD_SCSIRST_BUG = 0x0020, 237 AHD_PCIX_CHIPRST_BUG = 0x0040, 238 AHD_PCIX_MMAPIO_BUG = 0x0080, 239 /* Bug workarounds that can be disabled on non-PCIX busses. */ 240 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 241 | AHD_PCIX_MMAPIO_BUG, 242 AHD_LQO_ATNO_BUG = 0x0100, 243 AHD_AUTOFLUSH_BUG = 0x0200, 244 AHD_CLRLQO_AUTOCLR_BUG = 0x0400, 245 AHD_PKTIZED_STATUS_BUG = 0x0800, 246 AHD_PKT_LUN_BUG = 0x1000 247} ahd_bug; 248 249/* 250 * Configuration specific settings. 251 * The driver determines these settings by probing the 252 * chip/controller's configuration. 253 */ 254typedef enum { 255 AHD_FNONE = 0x00000, 256 AHD_PRIMARY_CHANNEL = 0x00003,/* 257 * The channel that should 258 * be probed first. 259 */ 260 AHD_USEDEFAULTS = 0x00004,/* 261 * For cards without an seeprom 262 * or a BIOS to initialize the chip's 263 * SRAM, we use the default target 264 * settings. 265 */ 266 AHD_SEQUENCER_DEBUG = 0x00008, 267 AHD_RESET_BUS_A = 0x00010, 268 AHD_EXTENDED_TRANS_A = 0x00020, 269 AHD_TERM_ENB_A = 0x00040, 270 AHD_SPCHK_ENB_A = 0x00080, 271 AHD_STPWLEVEL_A = 0x00100, 272 AHD_INITIATORROLE = 0x00200,/* 273 * Allow initiator operations on 274 * this controller. 275 */ 276 AHD_TARGETROLE = 0x00400,/* 277 * Allow target operations on this 278 * controller. 279 */ 280 AHD_RESOURCE_SHORTAGE = 0x00800, 281 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 282 AHD_INT50_SPEEDFLEX = 0x02000,/* 283 * Internal 50pin connector 284 * sits behind an aic3860 285 */ 286 AHD_BIOS_ENABLED = 0x04000, 287 AHD_ALL_INTERRUPTS = 0x08000, 288 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 289 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 290 AHD_CURRENT_SENSING = 0x40000, 291 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 292 AHD_CPQ_BOARD = 0x100000, 293 AHD_RESET_POLL_ACTIVE = 0x200000 294} ahd_flag; 295 296/************************* Hardware SCB Definition ***************************/ 297 298/* 299 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 300 * consists of a "hardware SCB" mirroring the fields availible on the card 301 * and additional information the kernel stores for each transaction. 302 * 303 * To minimize space utilization, a portion of the hardware scb stores 304 * different data during different portions of a SCSI transaction. 305 * As initialized by the host driver for the initiator role, this area 306 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 307 * the cdb has been presented to the target, this area serves to store 308 * residual transfer information and the SCSI status byte. 309 * For the target role, the contents of this area do not change, but 310 * still serve a different purpose than for the initiator role. See 311 * struct target_data for details. 312 */ 313 314/* 315 * Status information embedded in the shared poriton of 316 * an SCB after passing the cdb to the target. The kernel 317 * driver will only read this data for transactions that 318 * complete abnormally. 319 */ 320struct initiator_status { 321 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 322 uint32_t residual_sgptr; /* The next S/G for this transfer */ 323 uint8_t scsi_status; /* Standard SCSI status byte */ 324}; 325 326struct target_status { 327 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 328 uint32_t residual_sgptr; /* The next S/G for this transfer */ 329 uint8_t scsi_status; /* SCSI status to give to initiator */ 330 uint8_t target_phases; /* Bitmap of phases to execute */ 331 uint8_t data_phase; /* Data-In or Data-Out */ 332 uint8_t initiator_tag; /* Initiator's transaction tag */ 333}; 334 335/* 336 * Initiator mode SCB shared data area. 337 * If the embedded CDB is 12 bytes or less, we embed 338 * the sense buffer address in the SCB. This allows 339 * us to retrieve sense information without interupting 340 * the host in packetized mode. 341 */ 342typedef uint32_t sense_addr_t; 343#define MAX_CDB_LEN 16 344#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 345union initiator_data { 346 uint64_t cdbptr; 347 uint8_t cdb[MAX_CDB_LEN]; 348 struct { 349 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 350 sense_addr_t sense_addr; 351 } cdb_plus_saddr; 352}; 353 354/* 355 * Target mode version of the shared data SCB segment. 356 */ 357struct target_data { 358 uint32_t spare[2]; 359 uint8_t scsi_status; /* SCSI status to give to initiator */ 360 uint8_t target_phases; /* Bitmap of phases to execute */ 361 uint8_t data_phase; /* Data-In or Data-Out */ 362 uint8_t initiator_tag; /* Initiator's transaction tag */ 363}; 364 365struct hardware_scb { 366/*0*/ union { 367 union initiator_data idata; 368 struct target_data tdata; 369 struct initiator_status istatus; 370 struct target_status tstatus; 371 } shared_data; 372/* 373 * A word about residuals. 374 * The scb is presented to the sequencer with the dataptr and datacnt 375 * fields initialized to the contents of the first S/G element to 376 * transfer. The sgptr field is initialized to the bus address for 377 * the S/G element that follows the first in the in core S/G array 378 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 379 * S/G entry for this transfer (single S/G element transfer with the 380 * first elements address and length preloaded in the dataptr/datacnt 381 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 382 * The SG_FULL_RESID flag ensures that the residual will be correctly 383 * noted even if no data transfers occur. Once the data phase is entered, 384 * the residual sgptr and datacnt are loaded from the sgptr and the 385 * datacnt fields. After each S/G element's dataptr and length are 386 * loaded into the hardware, the residual sgptr is advanced. After 387 * each S/G element is expired, its datacnt field is checked to see 388 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 389 * residual sg ptr and the transfer is considered complete. If the 390 * sequencer determines that there is a residual in the tranfer, or 391 * there is non-zero status, it will set the SG_STATUS_VALID flag in 392 * sgptr and dma the scb back into host memory. To sumarize: 393 * 394 * Sequencer: 395 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 396 * or residual_sgptr does not have SG_LIST_NULL set. 397 * 398 * o We are transfering the last segment if residual_datacnt has 399 * the SG_LAST_SEG flag set. 400 * 401 * Host: 402 * o A residual can only have occurred if a completed scb has the 403 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 404 * the residual_datacnt, and the residual_sgptr field will tell 405 * for sure. 406 * 407 * o residual_sgptr and sgptr refer to the "next" sg entry 408 * and so may point beyond the last valid sg entry for the 409 * transfer. 410 */ 411#define SG_PTR_MASK 0xFFFFFFF8 412/*16*/ uint8_t cdb_len; 413/*17*/ uint8_t task_management; 414/*18*/ uint16_t tag; 415/*20*/ uint32_t next_hscb_busaddr; 416/*24*/ uint64_t dataptr; 417/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 418/*36*/ uint32_t sgptr; 419/*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 420/*41*/ uint8_t scsiid; /* 421 * Selection out Id 422 * Our Id (bits 0-3) Their ID (bits 4-7) 423 */ 424/*42*/ uint8_t lun; 425/*43*/ uint8_t task_attribute_nonpkt_tag; 426/*44*/ uint32_t hscb_busaddr; 427/******* Long lun field only downloaded for full 8 byte lun support *******/ 428/*48*/ uint8_t pkt_long_lun[8]; 429/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 430/*56*/ uint8_t spare[8]; 431}; 432 433/************************ Kernel SCB Definitions ******************************/ 434/* 435 * Some fields of the SCB are OS dependent. Here we collect the 436 * definitions for elements that all OS platforms need to include 437 * in there SCB definition. 438 */ 439 440/* 441 * Definition of a scatter/gather element as transfered to the controller. 442 * The aic7xxx chips only support a 24bit length. We use the top byte of 443 * the length to store additional address bits and a flag to indicate 444 * that a given segment terminates the transfer. This gives us an 445 * addressable range of 512GB on machines with 64bit PCI or with chips 446 * that can support dual address cycles on 32bit PCI busses. 447 */ 448struct ahd_dma_seg { 449 uint32_t addr; 450 uint32_t len; 451#define AHD_DMA_LAST_SEG 0x80000000 452#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 453#define AHD_SG_LEN_MASK 0x00FFFFFF 454}; 455 456struct ahd_dma64_seg { 457 uint64_t addr; 458 uint32_t len; 459 uint32_t pad; 460}; 461 462struct map_node { 463 bus_dmamap_t dmamap; 464 bus_addr_t physaddr; 465 uint8_t *vaddr; 466 SLIST_ENTRY(map_node) links; 467}; 468 469/* 470 * The current state of this SCB. 471 */ 472typedef enum { 473 SCB_FLAG_NONE = 0x00000, 474 SCB_TRANSMISSION_ERROR = 0x00001,/* 475 * We detected a parity or CRC 476 * error that has effected the 477 * payload of the command. This 478 * flag is checked when normal 479 * status is returned to catch 480 * the case of a target not 481 * responding to our attempt 482 * to report the error. 483 */ 484 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 485 * Another device was active 486 * during the first timeout for 487 * this SCB so we gave ourselves 488 * an additional timeout period 489 * in case it was hogging the 490 * bus. 491 */ 492 SCB_DEVICE_RESET = 0x00004, 493 SCB_SENSE = 0x00008, 494 SCB_CDB32_PTR = 0x00010, 495 SCB_RECOVERY_SCB = 0x00020, 496 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 497 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 498 SCB_ABORT = 0x00100, 499 SCB_ACTIVE = 0x00400, 500 SCB_TARGET_IMMEDIATE = 0x00800, 501 SCB_PACKETIZED = 0x01000, 502 SCB_EXPECT_PPR_BUSFREE = 0x02000, 503 SCB_PKT_SENSE = 0x04000, 504 SCB_CMDPHASE_ABORT = 0x08000, 505 SCB_ON_COL_LIST = 0x10000 506} scb_flag; 507 508struct scb { 509 struct hardware_scb *hscb; 510 union { 511 SLIST_ENTRY(scb) sle; 512 LIST_ENTRY(scb) le; 513 TAILQ_ENTRY(scb) tqe; 514 } links; 515 union { 516 SLIST_ENTRY(scb) sle; 517 LIST_ENTRY(scb) le; 518 TAILQ_ENTRY(scb) tqe; 519 } links2; 520#define pending_links links2.le 521#define collision_links links2.le 522 struct scb *col_scb; 523 ahd_io_ctx_t io_ctx; 524 struct ahd_softc *ahd_softc; 525 scb_flag flags; 526#ifndef __linux__ 527 bus_dmamap_t dmamap; 528#endif 529 struct scb_platform_data *platform_data; 530 struct map_node *hscb_map; 531 struct map_node *sg_map; 532 struct map_node *sense_map; 533 void *sg_list; 534 uint8_t *sense_data; 535 bus_addr_t sg_list_busaddr; 536 bus_addr_t sense_busaddr; 537 u_int sg_count;/* How full ahd_dma_seg is */ 538}; 539 540TAILQ_HEAD(scb_tailq, scb); 541LIST_HEAD(scb_list, scb); 542 543struct scb_data { 544 /* 545 * TAILQ of lists of free SCBs grouped by device 546 * collision domains. 547 */ 548 struct scb_tailq free_scbs; 549 550 /* 551 * Per-device lists of SCBs whose tag ID would collide 552 * with an already active tag on the device. 553 */ 554 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 555 556 /* 557 * SCBs that will not collide with any active device. 558 */ 559 struct scb_list any_dev_free_scb_list; 560 561 /* 562 * Mapping from tag to SCB. 563 */ 564 struct scb *scbindex[AHD_SCB_MAX]; 565 566 /* 567 * "Bus" addresses of our data structures. 568 */ 569 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 570 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 571 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 572 SLIST_HEAD(, map_node) hscb_maps; 573 SLIST_HEAD(, map_node) sg_maps; 574 SLIST_HEAD(, map_node) sense_maps; 575 int scbs_left; /* unallocated scbs in head map_node */ 576 int sgs_left; /* unallocated sgs in head map_node */ 577 int sense_left; /* unallocated sense in head map_node */ 578 uint16_t numscbs; 579 uint16_t maxhscbs; /* Number of SCBs on the card */ 580 uint8_t init_level; /* 581 * How far we've initialized 582 * this structure. 583 */ 584}; 585 586/************************ Target Mode Definitions *****************************/ 587 588/* 589 * Connection desciptor for select-in requests in target mode. 590 */ 591struct target_cmd { 592 uint8_t scsiid; /* Our ID and the initiator's ID */ 593 uint8_t identify; /* Identify message */ 594 uint8_t bytes[22]; /* 595 * Bytes contains any additional message 596 * bytes terminated by 0xFF. The remainder 597 * is the cdb to execute. 598 */ 599 uint8_t cmd_valid; /* 600 * When a command is complete, the firmware 601 * will set cmd_valid to all bits set. 602 * After the host has seen the command, 603 * the bits are cleared. This allows us 604 * to just peek at host memory to determine 605 * if more work is complete. cmd_valid is on 606 * an 8 byte boundary to simplify setting 607 * it on aic7880 hardware which only has 608 * limited direct access to the DMA FIFO. 609 */ 610 uint8_t pad[7]; 611}; 612 613/* 614 * Number of events we can buffer up if we run out 615 * of immediate notify ccbs. 616 */ 617#define AHD_TMODE_EVENT_BUFFER_SIZE 8 618struct ahd_tmode_event { 619 uint8_t initiator_id; 620 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 621#define EVENT_TYPE_BUS_RESET 0xFF 622 uint8_t event_arg; 623}; 624 625/* 626 * Per enabled lun target mode state. 627 * As this state is directly influenced by the host OS'es target mode 628 * environment, we let the OS module define it. Forward declare the 629 * structure here so we can store arrays of them, etc. in OS neutral 630 * data structures. 631 */ 632#ifdef AHD_TARGET_MODE 633struct ahd_tmode_lstate { 634 struct cam_path *path; 635 struct ccb_hdr_slist accept_tios; 636 struct ccb_hdr_slist immed_notifies; 637 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 638 uint8_t event_r_idx; 639 uint8_t event_w_idx; 640}; 641#else 642struct ahd_tmode_lstate; 643#endif 644 645/******************** Transfer Negotiation Datastructures *********************/ 646#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 647#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 648#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 649#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 650#define AHD_PERIOD_ASYNC 0xFF 651#define AHD_PERIOD_10MHz 0x19 652 653/* 654 * Transfer Negotiation Information. 655 */ 656struct ahd_transinfo { 657 uint8_t protocol_version; /* SCSI Revision level */ 658 uint8_t transport_version; /* SPI Revision level */ 659 uint8_t width; /* Bus width */ 660 uint8_t period; /* Sync rate factor */ 661 uint8_t offset; /* Sync offset */ 662 uint8_t ppr_options; /* Parallel Protocol Request options */ 663}; 664 665/* 666 * Per-initiator current, goal and user transfer negotiation information. */ 667struct ahd_initiator_tinfo { 668 struct ahd_transinfo curr; 669 struct ahd_transinfo goal; 670 struct ahd_transinfo user; 671}; 672 673/* 674 * Per enabled target ID state. 675 * Pointers to lun target state as well as sync/wide negotiation information 676 * for each initiator<->target mapping. For the initiator role we pretend 677 * that we are the target and the targets are the initiators since the 678 * negotiation is the same regardless of role. 679 */ 680struct ahd_tmode_tstate { 681 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 682 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 683 684 /* 685 * Per initiator state bitmasks. 686 */ 687 uint16_t auto_negotiate;/* Auto Negotiation Required */ 688 uint16_t discenable; /* Disconnection allowed */ 689 uint16_t tagenable; /* Tagged Queuing allowed */ 690}; 691 692/* 693 * Points of interest along the negotiated transfer scale. 694 */ 695#define AHD_SYNCRATE_MAX 0x8 696#define AHD_SYNCRATE_160 0x8 697#define AHD_SYNCRATE_PACED 0x8 698#define AHD_SYNCRATE_DT 0x9 699#define AHD_SYNCRATE_ULTRA2 0xa 700#define AHD_SYNCRATE_ULTRA 0xc 701#define AHD_SYNCRATE_FAST 0x19 702#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 703#define AHD_SYNCRATE_SYNC 0x32 704#define AHD_SYNCRATE_MIN 0x60 705#define AHD_SYNCRATE_ASYNC 0xFF 706 707/* 708 * In RevA, the synctable uses a 120MHz rate for the period 709 * factor 8 and 160MHz for the period factor 7. The 120MHz 710 * rate never made it into the official SCSI spec, so we must 711 * compensate when setting the negotiation table for Rev A 712 * parts. 713 */ 714#define AHD_SYNCRATE_REVA_120 0x8 715#define AHD_SYNCRATE_REVA_160 0x7 716 717/***************************** Lookup Tables **********************************/ 718/* 719 * Phase -> name and message out response 720 * to parity errors in each phase table. 721 */ 722struct ahd_phase_table_entry { 723 uint8_t phase; 724 uint8_t mesg_out; /* Message response to parity errors */ 725 char *phasemsg; 726}; 727 728/************************** Serial EEPROM Format ******************************/ 729 730struct seeprom_config { 731/* 732 * Per SCSI ID Configuration Flags 733 */ 734 uint16_t device_flags[16]; /* words 0-15 */ 735#define CFXFER 0x003F /* synchronous transfer rate */ 736#define CFXFER_ASYNC 0x3F 737#define CFQAS 0x0040 /* Negotiate QAS */ 738#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 739#define CFSTART 0x0100 /* send start unit SCSI command */ 740#define CFINCBIOS 0x0200 /* include in BIOS scan */ 741#define CFDISC 0x0400 /* enable disconnection */ 742#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 743#define CFWIDEB 0x1000 /* wide bus device */ 744#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 745 746/* 747 * BIOS Control Bits 748 */ 749 uint16_t bios_control; /* word 16 */ 750#define CFSUPREM 0x0001 /* support all removeable drives */ 751#define CFSUPREMB 0x0002 /* support removeable boot drives */ 752#define CFBIOSSTATE 0x000C /* BIOS Action State */ 753#define CFBS_DISABLED 0x00 754#define CFBS_ENABLED 0x04 755#define CFBS_DISABLED_SCAN 0x08 756#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 757#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 758#define CFSPARITY 0x0040 /* SCSI parity */ 759#define CFEXTEND 0x0080 /* extended translation enabled */ 760#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 761#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 762#define CFMSG_VERBOSE 0x0000 763#define CFMSG_SILENT 0x0200 764#define CFMSG_DIAG 0x0400 765#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 766/* UNUSED 0xf000 */ 767 768/* 769 * Host Adapter Control Bits 770 */ 771 uint16_t adapter_control; /* word 17 */ 772#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 773#define CFSTERM 0x0002 /* SCSI low byte termination */ 774#define CFWSTERM 0x0004 /* SCSI high byte termination */ 775#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 776#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 777#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 778#define CFSTPWLEVEL 0x0040 /* Termination level control */ 779#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 780#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 781#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 782 783/* 784 * Bus Release Time, Host Adapter ID 785 */ 786 uint16_t brtime_id; /* word 18 */ 787#define CFSCSIID 0x000f /* host adapter SCSI ID */ 788/* UNUSED 0x00f0 */ 789#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 790 791/* 792 * Maximum targets 793 */ 794 uint16_t max_targets; /* word 19 */ 795#define CFMAXTARG 0x00ff /* maximum targets */ 796#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 797#define CFBOOTID 0xf000 /* Target to boot from */ 798 uint16_t res_1[10]; /* words 20-29 */ 799 uint16_t signature; /* BIOS Signature */ 800#define CFSIGNATURE 0x400 801 uint16_t checksum; /* word 31 */ 802}; 803 804/****************************** Flexport Logic ********************************/ 805#define FLXADDR_TERMCTL 0x0 806#define FLX_TERMCTL_ENSECHIGH 0x8 807#define FLX_TERMCTL_ENSECLOW 0x4 808#define FLX_TERMCTL_ENPRIHIGH 0x2 809#define FLX_TERMCTL_ENPRILOW 0x1 810#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 811#define FLX_ROMSTAT_SEECFG 0xF0 812#define FLX_ROMSTAT_EECFG 0x0F 813#define FLX_ROMSTAT_SEE_93C66 0x00 814#define FLX_ROMSTAT_SEE_NONE 0xF0 815#define FLX_ROMSTAT_EE_512x8 0x0 816#define FLX_ROMSTAT_EE_1MBx8 0x1 817#define FLX_ROMSTAT_EE_2MBx8 0x2 818#define FLX_ROMSTAT_EE_4MBx8 0x3 819#define FLX_ROMSTAT_EE_16MBx8 0x4 820#define CURSENSE_ENB 0x1 821#define FLXADDR_FLEXSTAT 0x2 822#define FLX_FSTAT_BUSY 0x1 823#define FLXADDR_CURRENT_STAT 0x4 824#define FLX_CSTAT_SEC_HIGH 0xC0 825#define FLX_CSTAT_SEC_LOW 0x30 826#define FLX_CSTAT_PRI_HIGH 0x0C 827#define FLX_CSTAT_PRI_LOW 0x03 828#define FLX_CSTAT_MASK 0x03 829#define FLX_CSTAT_SHIFT 2 830#define FLX_CSTAT_OKAY 0x0 831#define FLX_CSTAT_OVER 0x1 832#define FLX_CSTAT_UNDER 0x2 833#define FLX_CSTAT_INVALID 0x3 834 835int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 836 u_int start_addr, u_int count); 837 838int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 839 u_int start_addr, u_int count); 840int ahd_wait_seeprom(struct ahd_softc *ahd); 841int ahd_verify_cksum(struct seeprom_config *sc); 842int ahd_acquire_seeprom(struct ahd_softc *ahd); 843void ahd_release_seeprom(struct ahd_softc *ahd); 844 845/**************************** Message Buffer *********************************/ 846typedef enum { 847 MSG_FLAG_NONE = 0x00, 848 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 849 MSG_FLAG_IU_REQ_CHANGED = 0x02, 850 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 851 MSG_FLAG_PACKETIZED = 0x08 852} ahd_msg_flags; 853 854typedef enum { 855 MSG_TYPE_NONE = 0x00, 856 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 857 MSG_TYPE_INITIATOR_MSGIN = 0x02, 858 MSG_TYPE_TARGET_MSGOUT = 0x03, 859 MSG_TYPE_TARGET_MSGIN = 0x04 860} ahd_msg_type; 861 862typedef enum { 863 MSGLOOP_IN_PROG, 864 MSGLOOP_MSGCOMPLETE, 865 MSGLOOP_TERMINATED 866} msg_loop_stat; 867 868/*********************** Software Configuration Structure *********************/ 869struct ahd_suspend_channel_state { 870 uint8_t scsiseq; 871 uint8_t sxfrctl0; 872 uint8_t sxfrctl1; 873 uint8_t simode0; 874 uint8_t simode1; 875 uint8_t seltimer; 876 uint8_t seqctl; 877}; 878 879struct ahd_suspend_state { 880 struct ahd_suspend_channel_state channel[2]; 881 uint8_t optionmode; 882 uint8_t dscommand0; 883 uint8_t dspcistatus; 884 /* hsmailbox */ 885 uint8_t crccontrol1; 886 uint8_t scbbaddr; 887 /* Host and sequencer SCB counts */ 888 uint8_t dff_thrsh; 889 uint8_t *scratch_ram; 890 uint8_t *btt; 891}; 892 893typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 894 895typedef enum { 896 AHD_MODE_DFF0, 897 AHD_MODE_DFF1, 898 AHD_MODE_CCHAN, 899 AHD_MODE_SCSI, 900 AHD_MODE_CFG, 901 AHD_MODE_UNKNOWN 902} ahd_mode; 903 904#define AHD_MK_MSK(x) (0x01 << (x)) 905#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 906#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 907#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 908#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 909#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 910#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 911#define AHD_MODE_ANY_MSK (~0) 912 913typedef uint8_t ahd_mode_state; 914 915typedef void ahd_callback_t (void *); 916 917struct ahd_softc { 918 bus_space_tag_t tags[2]; 919 bus_space_handle_t bshs[2]; 920#ifndef __linux__ 921 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 922#endif 923 struct scb_data scb_data; 924 925 struct hardware_scb *next_queued_hscb; 926 927 /* 928 * SCBs that have been sent to the controller 929 */ 930 LIST_HEAD(, scb) pending_scbs; 931 932 /* 933 * Current register window mode information. 934 */ 935 ahd_mode dst_mode; 936 ahd_mode src_mode; 937 938 /* 939 * Saved register window mode information 940 * used for restore on next unpause. 941 */ 942 ahd_mode saved_dst_mode; 943 ahd_mode saved_src_mode; 944 945 /* 946 * Platform specific data. 947 */ 948 struct ahd_platform_data *platform_data; 949 950 /* 951 * Platform specific device information. 952 */ 953 ahd_dev_softc_t dev_softc; 954 955 /* 956 * Bus specific device information. 957 */ 958 ahd_bus_intr_t bus_intr; 959 960 /* 961 * Target mode related state kept on a per enabled lun basis. 962 * Targets that are not enabled will have null entries. 963 * As an initiator, we keep one target entry for our initiator 964 * ID to store our sync/wide transfer settings. 965 */ 966 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 967 968 /* 969 * The black hole device responsible for handling requests for 970 * disabled luns on enabled targets. 971 */ 972 struct ahd_tmode_lstate *black_hole; 973 974 /* 975 * Device instance currently on the bus awaiting a continue TIO 976 * for a command that was not given the disconnect priveledge. 977 */ 978 struct ahd_tmode_lstate *pending_device; 979 980 /* 981 * Timer handles for timer driven callbacks. 982 */ 983 ahd_timer_t reset_timer; 984 985 /* 986 * Card characteristics 987 */ 988 ahd_chip chip; 989 ahd_feature features; 990 ahd_bug bugs; 991 ahd_flag flags; 992 struct seeprom_config *seep_config; 993 994 /* Values to store in the SEQCTL register for pause and unpause */ 995 uint8_t unpause; 996 uint8_t pause; 997 998 /* Command Queues */ 999 uint16_t qoutfifonext; 1000 uint16_t qoutfifonext_valid_tag; 1001 uint16_t qinfifonext; 1002 uint16_t qinfifo[AHD_SCB_MAX]; 1003 uint16_t *qoutfifo; 1004 1005 /* Critical Section Data */ 1006 struct cs *critical_sections; 1007 u_int num_critical_sections; 1008 1009 /* Buffer for handling packetized bitbucket. */ 1010 uint8_t *overrun_buf; 1011 1012 /* Links for chaining softcs */ 1013 TAILQ_ENTRY(ahd_softc) links; 1014 1015 /* Channel Names ('A', 'B', etc.) */ 1016 char channel; 1017 1018 /* Initiator Bus ID */ 1019 uint8_t our_id; 1020 1021 /* 1022 * PCI error detection. 1023 */ 1024 int unsolicited_ints; 1025 1026 /* 1027 * Target incoming command FIFO. 1028 */ 1029 struct target_cmd *targetcmds; 1030 uint8_t tqinfifonext; 1031 1032 /* 1033 * Incoming and outgoing message handling. 1034 */ 1035 uint8_t send_msg_perror; 1036 ahd_msg_flags msg_flags; 1037 ahd_msg_type msg_type; 1038 uint8_t msgout_buf[12];/* Message we are sending */ 1039 uint8_t msgin_buf[12];/* Message we are receiving */ 1040 u_int msgout_len; /* Length of message to send */ 1041 u_int msgout_index; /* Current index in msgout */ 1042 u_int msgin_index; /* Current index in msgin */ 1043 1044 /* 1045 * Mapping information for data structures shared 1046 * between the sequencer and kernel. 1047 */ 1048 bus_dma_tag_t parent_dmat; 1049 bus_dma_tag_t shared_data_dmat; 1050 bus_dmamap_t shared_data_dmamap; 1051 bus_addr_t shared_data_busaddr; 1052 1053 /* Information saved through suspend/resume cycles */ 1054 struct ahd_suspend_state suspend_state; 1055 1056 /* Number of enabled target mode device on this card */ 1057 u_int enabled_luns; 1058 1059 /* Initialization level of this data structure */ 1060 u_int init_level; 1061 1062 /* PCI cacheline size. */ 1063 u_int pci_cachesize; 1064 1065 /* Per-Unit descriptive information */ 1066 const char *description; 1067 const char *bus_description; 1068 char *name; 1069 int unit; 1070 1071 /* Selection Timer settings */ 1072 int seltime; 1073 1074 uint16_t user_discenable;/* Disconnection allowed */ 1075 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1076}; 1077 1078TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1079extern struct ahd_softc_tailq ahd_tailq; 1080 1081/************************ Active Device Information ***************************/ 1082typedef enum { 1083 ROLE_UNKNOWN, 1084 ROLE_INITIATOR, 1085 ROLE_TARGET 1086} role_t; 1087 1088struct ahd_devinfo { 1089 int our_scsiid; 1090 int target_offset; 1091 uint16_t target_mask; 1092 u_int target; 1093 u_int lun; 1094 char channel; 1095 role_t role; /* 1096 * Only guaranteed to be correct if not 1097 * in the busfree state. 1098 */ 1099}; 1100 1101/****************************** PCI Structures ********************************/ 1102#define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/ 1103#define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */ 1104#define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */ 1105 1106typedef int (ahd_device_setup_t)(struct ahd_softc *); 1107 1108struct ahd_pci_identity { 1109 uint64_t full_id; 1110 uint64_t id_mask; 1111 char *name; 1112 ahd_device_setup_t *setup; 1113}; 1114extern struct ahd_pci_identity ahd_pci_ident_table []; 1115extern const u_int ahd_num_pci_devs; 1116 1117/***************************** VL/EISA Declarations ***************************/ 1118struct aic7770_identity { 1119 uint32_t full_id; 1120 uint32_t id_mask; 1121 char *name; 1122 ahd_device_setup_t *setup; 1123}; 1124extern struct aic7770_identity aic7770_ident_table []; 1125extern const int ahd_num_aic7770_devs; 1126 1127#define AHD_EISA_SLOT_OFFSET 0xc00 1128#define AHD_EISA_IOSIZE 0x100 1129 1130/*************************** Function Declarations ****************************/ 1131/******************************************************************************/ 1132u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1133void ahd_busy_tcl(struct ahd_softc *ahd, 1134 u_int tcl, u_int busyid); 1135static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1136static __inline void 1137ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1138{ 1139 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1140} 1141 1142/***************************** PCI Front End *********************************/ 1143struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1144int ahd_pci_config(struct ahd_softc *, 1145 struct ahd_pci_identity *); 1146 1147/*************************** EISA/VL Front End ********************************/ 1148struct aic7770_identity *aic7770_find_device(uint32_t); 1149int aic7770_config(struct ahd_softc *ahd, 1150 struct aic7770_identity *); 1151 1152/************************** SCB and SCB queue management **********************/ 1153int ahd_probe_scbs(struct ahd_softc *); 1154void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1155 struct scb *scb); 1156int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1157 int target, char channel, int lun, 1158 u_int tag, role_t role); 1159 1160/****************************** Initialization ********************************/ 1161struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1162int ahd_softc_init(struct ahd_softc *); 1163void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1164int ahd_init(struct ahd_softc *ahd); 1165int ahd_default_config(struct ahd_softc *ahd); 1166int ahd_parse_cfgdata(struct ahd_softc *ahd, 1167 struct seeprom_config *sc); 1168void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1169void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1170int ahd_suspend(struct ahd_softc *ahd); 1171int ahd_resume(struct ahd_softc *ahd); 1172void ahd_softc_insert(struct ahd_softc *); 1173struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1174void ahd_set_unit(struct ahd_softc *, int); 1175void ahd_set_name(struct ahd_softc *, char *); 1176struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1177void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1178void ahd_alloc_scbs(struct ahd_softc *ahd); 1179void ahd_free(struct ahd_softc *ahd); 1180int ahd_reset(struct ahd_softc *ahd); 1181void ahd_shutdown(void *arg); 1182int ahd_write_flexport(struct ahd_softc *ahd, 1183 u_int addr, u_int value); 1184int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1185 uint8_t *value); 1186int ahd_wait_flexport(struct ahd_softc *ahd); 1187 1188/*************************** Interrupt Services *******************************/ 1189void ahd_pci_intr(struct ahd_softc *ahd); 1190void ahd_clear_intstat(struct ahd_softc *ahd); 1191void ahd_run_qoutfifo(struct ahd_softc *ahd); 1192#ifdef AHD_TARGET_MODE 1193void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1194#endif 1195void ahd_handle_hwerrint(struct ahd_softc *ahd); 1196void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1197void ahd_handle_scsiint(struct ahd_softc *ahd, 1198 u_int intstat); 1199void ahd_clear_critical_section(struct ahd_softc *ahd); 1200 1201/***************************** Error Recovery *********************************/ 1202typedef enum { 1203 SEARCH_COMPLETE, 1204 SEARCH_COUNT, 1205 SEARCH_REMOVE, 1206 SEARCH_PRINT 1207} ahd_search_action; 1208int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1209 char channel, int lun, u_int tag, 1210 role_t role, uint32_t status, 1211 ahd_search_action action); 1212int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1213 char channel, int lun, u_int tag, 1214 int stop_on_first, int remove, 1215 int save_state); 1216void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1217int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1218 int initiate_reset); 1219int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1220 char channel, int lun, u_int tag, 1221 role_t role, uint32_t status); 1222void ahd_restart(struct ahd_softc *ahd); 1223void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1224void ahd_handle_scb_status(struct ahd_softc *ahd, 1225 struct scb *scb); 1226void ahd_handle_scsi_status(struct ahd_softc *ahd, 1227 struct scb *scb); 1228void ahd_calc_residual(struct ahd_softc *ahd, 1229 struct scb *scb); 1230/*************************** Utility Functions ********************************/ 1231struct ahd_phase_table_entry* 1232 ahd_lookup_phase_entry(int phase); 1233void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1234 u_int our_id, u_int target, 1235 u_int lun, char channel, 1236 role_t role); 1237/************************** Transfer Negotiation ******************************/ 1238void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1239 u_int *ppr_options, u_int maxsync); 1240void ahd_validate_offset(struct ahd_softc *ahd, 1241 struct ahd_initiator_tinfo *tinfo, 1242 u_int period, u_int *offset, 1243 int wide, role_t role); 1244void ahd_validate_width(struct ahd_softc *ahd, 1245 struct ahd_initiator_tinfo *tinfo, 1246 u_int *bus_width, 1247 role_t role); 1248int ahd_update_neg_request(struct ahd_softc*, 1249 struct ahd_devinfo*, 1250 struct ahd_tmode_tstate*, 1251 struct ahd_initiator_tinfo*, 1252 int /*force*/); 1253void ahd_set_width(struct ahd_softc *ahd, 1254 struct ahd_devinfo *devinfo, 1255 u_int width, u_int type, int paused); 1256void ahd_set_syncrate(struct ahd_softc *ahd, 1257 struct ahd_devinfo *devinfo, 1258 u_int period, u_int offset, 1259 u_int ppr_options, 1260 u_int type, int paused); 1261typedef enum { 1262 AHD_QUEUE_NONE, 1263 AHD_QUEUE_BASIC, 1264 AHD_QUEUE_TAGGED 1265} ahd_queue_alg; 1266 1267void ahd_set_tags(struct ahd_softc *ahd, 1268 struct ahd_devinfo *devinfo, 1269 ahd_queue_alg alg); 1270 1271/**************************** Target Mode *************************************/ 1272#ifdef AHD_TARGET_MODE 1273void ahd_send_lstate_events(struct ahd_softc *, 1274 struct ahd_tmode_lstate *); 1275void ahd_handle_en_lun(struct ahd_softc *ahd, 1276 struct cam_sim *sim, union ccb *ccb); 1277cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1278 struct cam_sim *sim, union ccb *ccb, 1279 struct ahd_tmode_tstate **tstate, 1280 struct ahd_tmode_lstate **lstate, 1281 int notfound_failure); 1282#ifndef AHD_TMODE_ENABLE 1283#define AHD_TMODE_ENABLE 0 1284#endif 1285#endif 1286/******************************* Debug ***************************************/ 1287#ifdef AHD_DEBUG 1288extern uint32_t ahd_debug; 1289#define AHD_SHOW_MISC 0x0001 1290#define AHD_SHOW_SENSE 0x0002 1291#define AHD_DUMP_SEEPROM 0x0004 1292#define AHD_SHOW_TERMCTL 0x0008 1293#define AHD_SHOW_MEMORY 0x0010 1294#define AHD_SHOW_MESSAGES 0x0020 1295#define AHD_SHOW_MODEPTR 0x0040 1296#define AHD_SHOW_SELTO 0x0080 1297#define AHD_SHOW_FIFOS 0x0100 1298#define AHD_SHOW_QFULL 0x0200 1299#define AHD_SHOW_QUEUE 0x0400 1300#define AHD_SHOW_TQIN 0x0800 1301#define AHD_SHOW_SG 0x0800 1302#define AHD_DEBUG_SEQUENCER 0x2000 1303#endif 1304void ahd_print_scb(struct scb *scb); 1305void ahd_dump_sglist(struct scb *scb); 1306void ahd_dump_all_cards_state(void); 1307void ahd_dump_card_state(struct ahd_softc *ahd); 1308int ahd_print_register(ahd_reg_parse_entry_t *table, 1309 u_int num_entries, 1310 const char *name, 1311 u_int address, 1312 u_int value, 1313 u_int *cur_column, 1314 u_int wrap_point); 1315void ahd_dump_scbs(struct ahd_softc *ahd); 1316#endif /* _AIC79XX_H_ */ 1317