ahc_pci.c revision 64248
1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/ahc_pci.c 64248 2000-08-04 18:17:45Z wpaul $ 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41 42#include <pci/pcireg.h> 43#include <pci/pcivar.h> 44 45#include <machine/bus_memio.h> 46#include <machine/bus_pio.h> 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <machine/clock.h> 50#include <sys/rman.h> 51 52#include <cam/cam.h> 53#include <cam/cam_ccb.h> 54#include <cam/cam_sim.h> 55#include <cam/cam_xpt_sim.h> 56 57#include <cam/scsi/scsi_all.h> 58 59#include <dev/aic7xxx/aic7xxx.h> 60#include <dev/aic7xxx/93cx6.h> 61 62#include <aic7xxx_reg.h> 63 64#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 65#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 66 67static __inline uint64_t 68ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 69{ 70 uint64_t id; 71 72 id = subvendor 73 | (subdevice << 16) 74 | ((uint64_t)vendor << 32) 75 | ((uint64_t)device << 48); 76 77 return (id); 78} 79 80#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 81#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 82#define ID_AIC7850 0x5078900400000000ull 83#define ID_AHA_2910_15_20_30C 0x5078900478509004ull 84#define ID_AIC7855 0x5578900400000000ull 85#define ID_AIC7859 0x3860900400000000ull 86#define ID_AHA_2930CU 0x3860900438699004ull 87#define ID_AIC7860 0x6078900400000000ull 88#define ID_AIC7860C 0x6078900478609004ull 89#define ID_AHA_2940AU_0 0x6178900400000000ull 90#define ID_AHA_2940AU_1 0x6178900478619004ull 91#define ID_AHA_2940AU_CN 0x2178900478219004ull 92#define ID_AHA_2930C_VAR 0x6038900438689004ull 93 94#define ID_AIC7870 0x7078900400000000ull 95#define ID_AHA_2940 0x7178900400000000ull 96#define ID_AHA_3940 0x7278900400000000ull 97#define ID_AHA_398X 0x7378900400000000ull 98#define ID_AHA_2944 0x7478900400000000ull 99#define ID_AHA_3944 0x7578900400000000ull 100#define ID_AHA_4944 0x7678900400000000ull 101 102#define ID_AIC7880 0x8078900400000000ull 103#define ID_AIC7880_B 0x8078900478809004ull 104#define ID_AHA_2940U 0x8178900400000000ull 105#define ID_AHA_3940U 0x8278900400000000ull 106#define ID_AHA_2944U 0x8478900400000000ull 107#define ID_AHA_3944U 0x8578900400000000ull 108#define ID_AHA_398XU 0x8378900400000000ull 109#define ID_AHA_4944U 0x8678900400000000ull 110#define ID_AHA_2940UB 0x8178900478819004ull 111#define ID_AHA_2930U 0x8878900478889004ull 112#define ID_AHA_2940U_PRO 0x8778900478879004ull 113#define ID_AHA_2940U_CN 0x0078900478009004ull 114 115#define ID_AIC7895 0x7895900478959004ull 116#define ID_AIC7895_RAID_PORT 0x7893900478939004ull 117#define ID_AHA_2940U_DUAL 0x7895900478919004ull 118#define ID_AHA_3940AU 0x7895900478929004ull 119#define ID_AHA_3944AU 0x7895900478949004ull 120 121#define ID_AIC7890 0x001F9005000F9005ull 122#define ID_AAA_131U2 0x0013900500039005ull 123#define ID_AHA_2930U2 0x0011900501819005ull 124#define ID_AHA_2940U2B 0x00109005A1009005ull 125#define ID_AHA_2940U2_OEM 0x0010900521809005ull 126#define ID_AHA_2940U2 0x00109005A1809005ull 127#define ID_AHA_2950U2B 0x00109005E1009005ull 128 129#define ID_AIC7892 0x008F9005FFFF9005ull 130#define ID_AHA_29160 0x00809005E2A09005ull 131#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 132#define ID_AHA_29160N 0x0080900562A09005ull 133#define ID_AHA_29160B 0x00809005E2209005ull 134#define ID_AHA_19160B 0x0081900562A19005ull 135 136#define ID_AIC7896 0x005F9005FFFF9005ull 137#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 138#define ID_AHA_3950U2B_1 0x00509005F5009005ull 139#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 140#define ID_AHA_3950U2D_1 0x00519005B5009005ull 141 142#define ID_AIC7899 0x00CF9005FFFF9005ull 143#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 144#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 145 146#define ID_AIC7810 0x1078900400000000ull 147#define ID_AIC7815 0x7815900400000000ull 148 149typedef int (ahc_device_setup_t)(device_t, struct ahc_probe_config *); 150 151static ahc_device_setup_t ahc_aic7850_setup; 152static ahc_device_setup_t ahc_aic7855_setup; 153static ahc_device_setup_t ahc_aic7859_setup; 154static ahc_device_setup_t ahc_aic7860_setup; 155static ahc_device_setup_t ahc_aic7870_setup; 156static ahc_device_setup_t ahc_aha394X_setup; 157static ahc_device_setup_t ahc_aha494X_setup; 158static ahc_device_setup_t ahc_aha398X_setup; 159static ahc_device_setup_t ahc_aic7880_setup; 160static ahc_device_setup_t ahc_2940Pro_setup; 161static ahc_device_setup_t ahc_aha394XU_setup; 162static ahc_device_setup_t ahc_aha398XU_setup; 163static ahc_device_setup_t ahc_aic7890_setup; 164static ahc_device_setup_t ahc_aic7892_setup; 165static ahc_device_setup_t ahc_aic7895_setup; 166static ahc_device_setup_t ahc_aic7896_setup; 167static ahc_device_setup_t ahc_aic7899_setup; 168static ahc_device_setup_t ahc_raid_setup; 169static ahc_device_setup_t ahc_aha394XX_setup; 170static ahc_device_setup_t ahc_aha494XX_setup; 171static ahc_device_setup_t ahc_aha398XX_setup; 172 173struct ahc_pci_identity { 174 uint64_t full_id; 175 uint64_t id_mask; 176 char *name; 177 ahc_device_setup_t *setup; 178}; 179 180struct ahc_pci_identity ahc_pci_ident_table [] = 181{ 182 /* aic7850 based controllers */ 183 { 184 ID_AHA_2910_15_20_30C, 185 ID_ALL_MASK, 186 "Adaptec 2910/15/20/30C SCSI adapter", 187 ahc_aic7850_setup 188 }, 189 /* aic7859 based controllers */ 190 { 191 ID_AHA_2930CU, 192 ID_ALL_MASK, 193 "Adaptec 2930CU SCSI adapter", 194 ahc_aic7859_setup 195 }, 196 /* aic7860 based controllers */ 197 { 198 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 199 ID_DEV_VENDOR_MASK, 200 "Adaptec 2940A Ultra SCSI adapter", 201 ahc_aic7860_setup 202 }, 203 { 204 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 205 ID_DEV_VENDOR_MASK, 206 "Adaptec 2940A/CN Ultra SCSI adapter", 207 ahc_aic7860_setup 208 }, 209 { 210 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 211 ID_DEV_VENDOR_MASK, 212 "Adaptec 2930C SCSI adapter (VAR)", 213 ahc_aic7860_setup 214 }, 215 /* aic7870 based controllers */ 216 { 217 ID_AHA_2940, 218 ID_ALL_MASK, 219 "Adaptec 2940 SCSI adapter", 220 ahc_aic7870_setup 221 }, 222 { 223 ID_AHA_3940, 224 ID_ALL_MASK, 225 "Adaptec 3940 SCSI adapter", 226 ahc_aha394X_setup 227 }, 228 { 229 ID_AHA_398X, 230 ID_ALL_MASK, 231 "Adaptec 398X SCSI RAID adapter", 232 ahc_aha398X_setup 233 }, 234 { 235 ID_AHA_2944, 236 ID_ALL_MASK, 237 "Adaptec 2944 SCSI adapter", 238 ahc_aic7870_setup 239 }, 240 { 241 ID_AHA_3944, 242 ID_ALL_MASK, 243 "Adaptec 3944 SCSI adapter", 244 ahc_aha394X_setup 245 }, 246 { 247 ID_AHA_4944, 248 ID_ALL_MASK, 249 "Adaptec 4944 SCSI adapter", 250 ahc_aha494X_setup 251 }, 252 /* aic7880 based controllers */ 253 { 254 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 255 ID_DEV_VENDOR_MASK, 256 "Adaptec 2940 Ultra SCSI adapter", 257 ahc_aic7880_setup 258 }, 259 { 260 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 261 ID_DEV_VENDOR_MASK, 262 "Adaptec 3940 Ultra SCSI adapter", 263 ahc_aha394XU_setup 264 }, 265 { 266 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 267 ID_DEV_VENDOR_MASK, 268 "Adaptec 2944 Ultra SCSI adapter", 269 ahc_aic7880_setup 270 }, 271 { 272 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 273 ID_DEV_VENDOR_MASK, 274 "Adaptec 3944 Ultra SCSI adapter", 275 ahc_aha394XU_setup 276 }, 277 { 278 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 279 ID_DEV_VENDOR_MASK, 280 "Adaptec 398X Ultra SCSI RAID adapter", 281 ahc_aha398XU_setup 282 }, 283 { 284 /* 285 * XXX Don't know the slot numbers 286 * so we can't identify channels 287 */ 288 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 289 ID_DEV_VENDOR_MASK, 290 "Adaptec 4944 Ultra SCSI adapter", 291 ahc_aic7880_setup 292 }, 293 { 294 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 295 ID_DEV_VENDOR_MASK, 296 "Adaptec 2930 Ultra SCSI adapter", 297 ahc_aic7880_setup 298 }, 299 { 300 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 301 ID_DEV_VENDOR_MASK, 302 "Adaptec 2940 Pro Ultra SCSI adapter", 303 ahc_2940Pro_setup 304 }, 305 { 306 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 307 ID_DEV_VENDOR_MASK, 308 "Adaptec 2940/CN Ultra SCSI adapter", 309 ahc_aic7880_setup 310 }, 311 /* aic7890 based controllers */ 312 { 313 ID_AHA_2930U2, 314 ID_ALL_MASK, 315 "Adaptec 2930 Ultra2 SCSI adapter", 316 ahc_aic7890_setup 317 }, 318 { 319 ID_AHA_2940U2B, 320 ID_ALL_MASK, 321 "Adaptec 2940B Ultra2 SCSI adapter", 322 ahc_aic7890_setup 323 }, 324 { 325 ID_AHA_2940U2_OEM, 326 ID_ALL_MASK, 327 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 328 ahc_aic7890_setup 329 }, 330 { 331 ID_AHA_2940U2, 332 ID_ALL_MASK, 333 "Adaptec 2940 Ultra2 SCSI adapter", 334 ahc_aic7890_setup 335 }, 336 { 337 ID_AHA_2950U2B, 338 ID_ALL_MASK, 339 "Adaptec 2950 Ultra2 SCSI adapter", 340 ahc_aic7890_setup 341 }, 342 { 343 ID_AAA_131U2, 344 ID_ALL_MASK, 345 "Adaptec AAA-131 Ultra2 RAID adapter", 346 ahc_aic7890_setup 347 }, 348 /* aic7892 based controllers */ 349 { 350 ID_AHA_29160, 351 ID_ALL_MASK, 352 "Adaptec 29160 Ultra160 SCSI adapter", 353 ahc_aic7892_setup 354 }, 355 { 356 ID_AHA_29160_CPQ, 357 ID_ALL_MASK, 358 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 359 ahc_aic7892_setup 360 }, 361 { 362 ID_AHA_29160N, 363 ID_ALL_MASK, 364 "Adaptec 29160N Ultra160 SCSI adapter", 365 ahc_aic7892_setup 366 }, 367 { 368 ID_AHA_29160B, 369 ID_ALL_MASK, 370 "Adaptec 29160B Ultra160 SCSI adapter", 371 ahc_aic7892_setup 372 }, 373 { 374 ID_AHA_19160B, 375 ID_ALL_MASK, 376 "Adaptec 19160B Ultra160 SCSI adapter", 377 ahc_aic7892_setup 378 }, 379 /* aic7895 based controllers */ 380 { 381 ID_AHA_2940U_DUAL, 382 ID_ALL_MASK, 383 "Adaptec 2940/DUAL Ultra SCSI adapter", 384 ahc_aic7895_setup 385 }, 386 { 387 ID_AHA_3940AU, 388 ID_ALL_MASK, 389 "Adaptec 3940A Ultra SCSI adapter", 390 ahc_aic7895_setup 391 }, 392 { 393 ID_AHA_3944AU, 394 ID_ALL_MASK, 395 "Adaptec 3944A Ultra SCSI adapter", 396 ahc_aic7895_setup 397 }, 398 /* aic7896/97 based controllers */ 399 { 400 ID_AHA_3950U2B_0, 401 ID_ALL_MASK, 402 "Adaptec 3950B Ultra2 SCSI adapter", 403 ahc_aic7896_setup 404 }, 405 { 406 ID_AHA_3950U2B_1, 407 ID_ALL_MASK, 408 "Adaptec 3950B Ultra2 SCSI adapter", 409 ahc_aic7896_setup 410 }, 411 { 412 ID_AHA_3950U2D_0, 413 ID_ALL_MASK, 414 "Adaptec 3950D Ultra2 SCSI adapter", 415 ahc_aic7896_setup 416 }, 417 { 418 ID_AHA_3950U2D_1, 419 ID_ALL_MASK, 420 "Adaptec 3950D Ultra2 SCSI adapter", 421 ahc_aic7896_setup 422 }, 423 /* aic7899 based controllers */ 424 { 425 ID_AHA_3960D, 426 ID_ALL_MASK, 427 "Adaptec 3960D Ultra160 SCSI adapter", 428 ahc_aic7899_setup 429 }, 430 { 431 ID_AHA_3960D_CPQ, 432 ID_ALL_MASK, 433 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 434 ahc_aic7899_setup 435 }, 436 /* Generic chip probes for devices we don't know 'exactly' */ 437 { 438 ID_AIC7850 & ID_DEV_VENDOR_MASK, 439 ID_DEV_VENDOR_MASK, 440 "Adaptec aic7850 SCSI adapter", 441 ahc_aic7850_setup 442 }, 443 { 444 ID_AIC7855 & ID_DEV_VENDOR_MASK, 445 ID_DEV_VENDOR_MASK, 446 "Adaptec aic7855 SCSI adapter", 447 ahc_aic7855_setup 448 }, 449 { 450 ID_AIC7859 & ID_DEV_VENDOR_MASK, 451 ID_DEV_VENDOR_MASK, 452 "Adaptec aic7859 SCSI adapter", 453 ahc_aic7859_setup 454 }, 455 { 456 ID_AIC7860 & ID_DEV_VENDOR_MASK, 457 ID_DEV_VENDOR_MASK, 458 "Adaptec aic7860 SCSI adapter", 459 ahc_aic7860_setup 460 }, 461 { 462 ID_AIC7870 & ID_DEV_VENDOR_MASK, 463 ID_DEV_VENDOR_MASK, 464 "Adaptec aic7870 SCSI adapter", 465 ahc_aic7870_setup 466 }, 467 { 468 ID_AIC7880 & ID_DEV_VENDOR_MASK, 469 ID_DEV_VENDOR_MASK, 470 "Adaptec aic7880 Ultra SCSI adapter", 471 ahc_aic7880_setup 472 }, 473 { 474 ID_AIC7890 & ID_DEV_VENDOR_MASK, 475 ID_DEV_VENDOR_MASK, 476 "Adaptec aic7890/91 Ultra2 SCSI adapter", 477 ahc_aic7890_setup 478 }, 479 { 480 ID_AIC7892 & ID_DEV_VENDOR_MASK, 481 ID_DEV_VENDOR_MASK, 482 "Adaptec aic7892 Ultra160 SCSI adapter", 483 ahc_aic7892_setup 484 }, 485 { 486 ID_AIC7895 & ID_DEV_VENDOR_MASK, 487 ID_DEV_VENDOR_MASK, 488 "Adaptec aic7895 Ultra SCSI adapter", 489 ahc_aic7895_setup 490 }, 491 { 492 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 493 ID_DEV_VENDOR_MASK, 494 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 495 ahc_aic7895_setup 496 }, 497 { 498 ID_AIC7896 & ID_DEV_VENDOR_MASK, 499 ID_DEV_VENDOR_MASK, 500 "Adaptec aic7896/97 Ultra2 SCSI adapter", 501 ahc_aic7896_setup 502 }, 503 { 504 ID_AIC7899 & ID_DEV_VENDOR_MASK, 505 ID_DEV_VENDOR_MASK, 506 "Adaptec aic7899 Ultra160 SCSI adapter", 507 ahc_aic7899_setup 508 }, 509 { 510 ID_AIC7810 & ID_DEV_VENDOR_MASK, 511 ID_DEV_VENDOR_MASK, 512 "Adaptec aic7810 RAID memory controller", 513 ahc_raid_setup 514 }, 515 { 516 ID_AIC7815 & ID_DEV_VENDOR_MASK, 517 ID_DEV_VENDOR_MASK, 518 "Adaptec aic7815 RAID memory controller", 519 ahc_raid_setup 520 } 521}; 522 523static const int ahc_num_pci_devs = 524 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 525 526#define AHC_394X_SLOT_CHANNEL_A 4 527#define AHC_394X_SLOT_CHANNEL_B 5 528 529#define AHC_398X_SLOT_CHANNEL_A 4 530#define AHC_398X_SLOT_CHANNEL_B 8 531#define AHC_398X_SLOT_CHANNEL_C 12 532 533#define AHC_494X_SLOT_CHANNEL_A 4 534#define AHC_494X_SLOT_CHANNEL_B 5 535#define AHC_494X_SLOT_CHANNEL_C 6 536#define AHC_494X_SLOT_CHANNEL_D 7 537 538#define DEVCONFIG 0x40 539#define SCBSIZE32 0x00010000ul /* aic789X only */ 540#define MPORTMODE 0x00000400ul /* aic7870 only */ 541#define RAMPSM 0x00000200ul /* aic7870 only */ 542#define VOLSENSE 0x00000100ul 543#define SCBRAMSEL 0x00000080ul 544#define MRDCEN 0x00000040ul 545#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 546#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 547#define BERREN 0x00000008ul 548#define DACEN 0x00000004ul 549#define STPWLEVEL 0x00000002ul 550#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 551 552#define CSIZE_LATTIME 0x0c 553#define CACHESIZE 0x0000003ful /* only 5 bits */ 554#define LATTIME 0x0000ff00ul 555 556static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 557static int ahc_ext_scbram_present(struct ahc_softc *ahc); 558static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 559 int pcheck, int fast, int large); 560static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 561static int verify_cksum(struct seeprom_config *sc); 562static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 563static void configure_termination(struct ahc_softc *ahc, 564 struct seeprom_descriptor *sd, 565 u_int adapter_control, 566 u_int *sxfrctl1); 567 568static void ahc_new_term_detect(struct ahc_softc *ahc, 569 int *enableSEC_low, 570 int *enableSEC_high, 571 int *enablePRI_low, 572 int *enablePRI_high, 573 int *eeprom_present); 574static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 575 int *internal68_present, 576 int *externalcable_present, 577 int *eeprom_present); 578static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 579 int *externalcable_present, 580 int *eeprom_present); 581static int acquire_seeprom(struct ahc_softc *ahc, 582 struct seeprom_descriptor *sd); 583static void release_seeprom(struct seeprom_descriptor *sd); 584static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 585static uint8_t read_brdctl(struct ahc_softc *ahc); 586 587static struct ahc_softc *first_398X; 588 589static int ahc_pci_probe(device_t dev); 590static int ahc_pci_attach(device_t dev); 591 592/* Exported for use in the ahc_intr routine */ 593void ahc_pci_intr(struct ahc_softc *ahc); 594 595static device_method_t ahc_pci_methods[] = { 596 /* Device interface */ 597 DEVMETHOD(device_probe, ahc_pci_probe), 598 DEVMETHOD(device_attach, ahc_pci_attach), 599 { 0, 0 } 600}; 601 602static driver_t ahc_pci_driver = { 603 "ahc", 604 ahc_pci_methods, 605 sizeof(struct ahc_softc) 606}; 607 608static devclass_t ahc_devclass; 609 610DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 611 612static struct ahc_pci_identity * 613ahc_find_pci_device(device_t dev) 614{ 615 uint64_t full_id; 616 struct ahc_pci_identity *entry; 617 u_int i; 618 619 full_id = ahc_compose_id(pci_get_device(dev), 620 pci_get_vendor(dev), 621 pci_get_subdevice(dev), 622 pci_get_subvendor(dev)); 623 624 for (i = 0; i < ahc_num_pci_devs; i++) { 625 entry = &ahc_pci_ident_table[i]; 626 if (entry->full_id == (full_id & entry->id_mask)) 627 return (entry); 628 } 629 return (NULL); 630} 631 632static int 633ahc_pci_probe(device_t dev) 634{ 635 struct ahc_pci_identity *entry; 636 637 entry = ahc_find_pci_device(dev); 638 if (entry != NULL) { 639 device_set_desc(dev, entry->name); 640 return (0); 641 } 642 return (ENXIO); 643} 644 645static int 646ahc_pci_attach(device_t dev) 647{ 648 struct ahc_probe_config probe_config; 649 bus_dma_tag_t parent_dmat; 650 struct ahc_pci_identity *entry; 651 struct resource *regs; 652 struct ahc_softc *ahc; 653 struct scb_data *shared_scb_data; 654 u_int command; 655 int regs_type; 656 int regs_id; 657 u_int our_id = 0; 658 u_int sxfrctl1; 659 u_int scsiseq; 660 u_int dscommand0; 661 int error; 662 int zero; 663 uint8_t sblkctl; 664 665 shared_scb_data = NULL; 666 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 667 entry = ahc_find_pci_device(dev); 668 if (entry == NULL) 669 return (ENXIO); 670 ahc_init_probe_config(&probe_config); 671 error = entry->setup(dev, &probe_config); 672 probe_config.chip |= AHC_PCI; 673 probe_config.description = entry->name; 674 if (error != 0) 675 return (error); 676 677 regs = NULL; 678 regs_type = 0; 679 regs_id = 0; 680#ifdef AHC_ALLOW_MEMIO 681 if ((command & PCIM_CMD_MEMEN) != 0) { 682 regs_type = SYS_RES_MEMORY; 683 regs_id = AHC_PCI_MEMADDR; 684 regs = bus_alloc_resource(dev, regs_type, 685 ®s_id, 0, ~0, 1, RF_ACTIVE); 686 } 687#endif 688 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 689 regs_type = SYS_RES_IOPORT; 690 regs_id = AHC_PCI_IOADDR; 691 regs = bus_alloc_resource(dev, regs_type, 692 ®s_id, 0, ~0, 1, RF_ACTIVE); 693 } 694 695 if (regs == NULL) { 696 device_printf(dev, "can't allocate register resources\n"); 697 return (ENOMEM); 698 } 699 700 /* Ensure busmastering is enabled */ 701 command |= PCIM_CMD_BUSMASTEREN; 702 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 703 704 /* Allocate a dmatag for our SCB DMA maps */ 705 /* XXX Should be a child of the PCI bus dma tag */ 706 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 707 /*boundary*/0, 708 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 709 /*highaddr*/BUS_SPACE_MAXADDR, 710 /*filter*/NULL, /*filterarg*/NULL, 711 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 712 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 713 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 714 715 if (error != 0) { 716 printf("ahc_pci_attach: Could not allocate DMA tag " 717 "- error %d\n", error); 718 return (ENOMEM); 719 } 720 721 /* On all PCI adapters, we allow SCB paging */ 722 probe_config.flags |= AHC_PAGESCBS; 723 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 724 &probe_config, shared_scb_data)) == NULL) 725 return (ENOMEM); 726 727 /* Store our PCI bus information for use in our PCI error handler */ 728 ahc->device = dev; 729 730 /* Remeber how the card was setup in case there is no SEEPROM */ 731 pause_sequencer(ahc); 732 if ((ahc->features & AHC_ULTRA2) != 0) 733 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 734 else 735 our_id = ahc_inb(ahc, SCSIID) & OID; 736 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 737 scsiseq = ahc_inb(ahc, SCSISEQ); 738 739 if (ahc_reset(ahc) != 0) { 740 /* Failed */ 741 ahc_free(ahc); 742 return (ENXIO); 743 } 744 745 if ((ahc->features & AHC_DT) != 0) { 746 u_int sfunct; 747 748 /* Perform ALT-Mode Setup */ 749 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 750 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 751 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 752 /* Send CRC info in target mode every 4K */ 753 ahc_outb(ahc, TARGCRCCNT, 0); 754 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 755 ahc_outb(ahc, SFUNCT, sfunct); 756 757 /* Normal mode setup */ 758 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 759 |TARGCRCENDEN|TARGCRCCNTEN); 760 } 761 zero = 0; 762 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 763 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 764 if (ahc->irq == NULL) { 765 ahc_free(ahc); 766 return (ENOMEM); 767 } 768 769 ahc->irq_res_type = SYS_RES_IRQ; 770 771 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 772 dscommand0 |= MPARCKEN; 773 if ((ahc->features & AHC_ULTRA2) != 0) { 774 775 /* 776 * DPARCKEN doesn't work correctly on 777 * some MBs so don't use it. 778 */ 779 dscommand0 &= ~DPARCKEN; 780 /* 781 * We default to using 32byte SCBs 782 * and using cacheline streaming. 783 * If external SCB ram is detected, 784 * we'll switch to using 64 byte SCBs. 785 */ 786 dscommand0 |= CACHETHEN|USCBSIZE32; 787 } 788 /* 789 * Handle chips that must have cache line 790 * streaming (dis/en)abled. 791 */ 792 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 793 dscommand0 |= CACHETHEN; 794 795 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 796 dscommand0 &= ~CACHETHEN; 797 798 ahc_outb(ahc, DSCOMMAND0, dscommand0); 799 800 /* See if we have a SEEPROM and perform auto-term */ 801 check_extport(ahc, &sxfrctl1); 802 803 /* 804 * Take the LED out of diagnostic mode 805 */ 806 sblkctl = ahc_inb(ahc, SBLKCTL); 807 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 808 809 /* 810 * I don't know where this is set in the SEEPROM or by the 811 * BIOS, so we default to 100% on Ultra or slower controllers 812 * and 75% on ULTRA2 controllers. 813 */ 814 if ((ahc->features & AHC_ULTRA2) != 0) { 815 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 816 } else { 817 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 818 } 819 820 if (ahc->flags & AHC_USEDEFAULTS) { 821 /* 822 * PCI Adapter default setup 823 * Should only be used if the adapter does not have 824 * an SEEPROM. 825 */ 826 /* See if someone else set us up already */ 827 if (scsiseq != 0) { 828 printf("%s: Using left over BIOS settings\n", 829 ahc_name(ahc)); 830 ahc->flags &= ~AHC_USEDEFAULTS; 831 } else { 832 /* 833 * Assume only one connector and always turn 834 * on termination. 835 */ 836 our_id = 0x07; 837 sxfrctl1 = STPWEN; 838 } 839 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 840 841 ahc->our_id = our_id; 842 } 843 844 /* 845 * Take a look to see if we have external SRAM. 846 * We currently do not attempt to use SRAM that is 847 * shared among multiple controllers. 848 */ 849 ahc_probe_ext_scbram(ahc); 850 851 printf("%s: %s ", ahc_name(ahc), 852 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 853 854 /* 855 * Record our termination setting for the 856 * generic initialization routine. 857 */ 858 if ((sxfrctl1 & STPWEN) != 0) 859 ahc->flags |= AHC_TERM_ENB_A; 860 861 if (ahc_init(ahc)) { 862 ahc_free(ahc); 863 return (ENOMEM); 864 } 865 866 /* XXX Crude hack - fix sometime */ 867 if (ahc->flags & AHC_SHARED_SRAM) { 868 /* Only set this once we've successfully probed */ 869 if (shared_scb_data == NULL) 870 first_398X = ahc; 871 } 872 873 ahc_attach(ahc); 874 return (0); 875} 876 877/* 878 * Test for the presense of external sram in an 879 * "unshared" configuration. 880 */ 881static int 882ahc_ext_scbram_present(struct ahc_softc *ahc) 883{ 884 int ramps; 885 int single_user; 886 uint32_t devconfig; 887 888 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 889 single_user = (devconfig & MPORTMODE) != 0; 890 891 if ((ahc->features & AHC_ULTRA2) != 0) 892 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 893 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 894 ramps = (devconfig & RAMPSM) != 0; 895 else 896 ramps = 0; 897 898 if (ramps && single_user) 899 return (1); 900 return (0); 901} 902 903/* 904 * Enable external scbram. 905 */ 906static void 907ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 908 int fast, int large) 909{ 910 uint32_t devconfig; 911 912 if (ahc->features & AHC_MULTI_FUNC) { 913 /* 914 * Set the SCB Base addr (highest address bit) 915 * depending on which channel we are. 916 */ 917 ahc_outb(ahc, SCBBADDR, pci_get_function(ahc->device)); 918 } 919 920 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 921 if ((ahc->features & AHC_ULTRA2) != 0) { 922 u_int dscommand0; 923 924 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 925 if (enable) 926 dscommand0 &= ~INTSCBRAMSEL; 927 else 928 dscommand0 |= INTSCBRAMSEL; 929 if (large) 930 dscommand0 |= USCBSIZE32; 931 else 932 dscommand0 &= ~USCBSIZE32; 933 ahc_outb(ahc, DSCOMMAND0, dscommand0); 934 } else { 935 if (fast) 936 devconfig &= ~EXTSCBTIME; 937 else 938 devconfig |= EXTSCBTIME; 939 if (enable) 940 devconfig &= ~SCBRAMSEL; 941 else 942 devconfig |= SCBRAMSEL; 943 if (large) 944 devconfig &= ~SCBSIZE32; 945 else 946 devconfig |= SCBSIZE32; 947 } 948 if (pcheck) 949 devconfig |= EXTSCBPEN; 950 else 951 devconfig &= ~EXTSCBPEN; 952 953 pci_write_config(ahc->device, DEVCONFIG, devconfig, /*bytes*/4); 954} 955 956/* 957 * Take a look to see if we have external SRAM. 958 * We currently do not attempt to use SRAM that is 959 * shared among multiple controllers. 960 */ 961static void 962ahc_probe_ext_scbram(struct ahc_softc *ahc) 963{ 964 int num_scbs; 965 int test_num_scbs; 966 int enable; 967 int pcheck; 968 int fast; 969 int large; 970 971 enable = FALSE; 972 pcheck = FALSE; 973 fast = FALSE; 974 large = FALSE; 975 num_scbs = 0; 976 977 if (ahc_ext_scbram_present(ahc) == 0) 978 return; 979 980 /* 981 * Probe for the best parameters to use. 982 */ 983 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 984 num_scbs = ahc_probe_scbs(ahc); 985 if (num_scbs == 0) { 986 /* The SRAM wasn't really present. */ 987 goto done; 988 } 989 enable = TRUE; 990 991 /* 992 * Clear any outstanding parity error 993 * and ensure that parity error reporting 994 * is enabled. 995 */ 996 ahc_outb(ahc, SEQCTL, 0); 997 ahc_outb(ahc, CLRINT, CLRPARERR); 998 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 999 1000 /* Now see if we can do parity */ 1001 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1002 num_scbs = ahc_probe_scbs(ahc); 1003 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1004 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1005 pcheck = TRUE; 1006 1007 /* Clear any resulting parity error */ 1008 ahc_outb(ahc, CLRINT, CLRPARERR); 1009 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1010 1011 /* Now see if we can do fast timing */ 1012 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1013 test_num_scbs = ahc_probe_scbs(ahc); 1014 if (test_num_scbs == num_scbs 1015 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1016 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1017 fast = TRUE; 1018 1019 /* 1020 * See if we can use large SCBs and still maintain 1021 * the same overall count of SCBs. 1022 */ 1023 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1024 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1025 test_num_scbs = ahc_probe_scbs(ahc); 1026 if (test_num_scbs >= num_scbs) { 1027 large = TRUE; 1028 num_scbs = test_num_scbs; 1029 } 1030 if (num_scbs >= 64) 1031 /* 1032 * We have enough space to move the "busy targets 1033 * table" into SCB space and make it qualify all 1034 * the way to the lun level. 1035 */ 1036 ahc->flags |= AHC_SCB_BTT; 1037 } 1038done: 1039 /* 1040 * Disable parity error reporting until we 1041 * can load instruction ram. 1042 */ 1043 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1044 /* Clear any latched parity error */ 1045 ahc_outb(ahc, CLRINT, CLRPARERR); 1046 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1047 if (bootverbose && enable) { 1048 printf("%s: External SRAM, %s access%s\n", 1049 ahc_name(ahc), fast ? "fast" : "slow", 1050 pcheck ? ", parity checking enabled" : ""); 1051 1052 } 1053 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1054} 1055 1056static int 1057verify_cksum(struct seeprom_config *sc) 1058{ 1059 int i; 1060 int maxaddr; 1061 uint32_t checksum; 1062 uint16_t *scarray; 1063 1064 maxaddr = (sizeof(*sc)/2) - 1; 1065 checksum = 0; 1066 scarray = (uint16_t *)sc; 1067 1068 for (i = 0; i < maxaddr; i++) 1069 checksum = checksum + scarray[i]; 1070 if (checksum == 0 1071 || (checksum & 0xFFFF) != sc->checksum) { 1072 return (0); 1073 } else { 1074 return(1); 1075 } 1076} 1077 1078/* 1079 * Check the external port logic for a serial eeprom 1080 * and termination/cable detection contrls. 1081 */ 1082static void 1083check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1084{ 1085 struct seeprom_descriptor sd; 1086 struct seeprom_config sc; 1087 u_int scsi_conf; 1088 u_int adapter_control; 1089 int have_seeprom; 1090 int have_autoterm; 1091 1092 sd.sd_tag = ahc->tag; 1093 sd.sd_bsh = ahc->bsh; 1094 sd.sd_control_offset = SEECTL; 1095 sd.sd_status_offset = SEECTL; 1096 sd.sd_dataout_offset = SEECTL; 1097 1098 /* 1099 * For some multi-channel devices, the c46 is simply too 1100 * small to work. For the other controller types, we can 1101 * get our information from either SEEPROM type. Set the 1102 * type to start our probe with accordingly. 1103 */ 1104 if (ahc->flags & AHC_LARGE_SEEPROM) 1105 sd.sd_chip = C56_66; 1106 else 1107 sd.sd_chip = C46; 1108 1109 sd.sd_MS = SEEMS; 1110 sd.sd_RDY = SEERDY; 1111 sd.sd_CS = SEECS; 1112 sd.sd_CK = SEECK; 1113 sd.sd_DO = SEEDO; 1114 sd.sd_DI = SEEDI; 1115 1116 have_seeprom = acquire_seeprom(ahc, &sd); 1117 if (have_seeprom) { 1118 1119 if (bootverbose) 1120 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1121 1122 for (;;) { 1123 bus_size_t start_addr; 1124 1125 start_addr = 32 * (ahc->channel - 'A'); 1126 1127 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 1128 start_addr, sizeof(sc)/2); 1129 1130 if (have_seeprom) 1131 have_seeprom = verify_cksum(&sc); 1132 1133 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1134 if (bootverbose) { 1135 if (have_seeprom == 0) 1136 printf ("checksum error\n"); 1137 else 1138 printf ("done.\n"); 1139 } 1140 break; 1141 } 1142 sd.sd_chip = C56_66; 1143 } 1144 } 1145 1146#if 0 1147 /* 1148 * This code causes a machine with an aic7880 chipset 1149 * to reboot spontaneously. Whatever it's supposed to do, 1150 * it's doing it wrong. -wpaul 1151 */ 1152 if (!have_seeprom) { 1153 /* 1154 * Pull scratch ram settings and treat them as 1155 * if they are the contents of an seeprom if 1156 * the 'ADPT' signature is found in SCB2. 1157 */ 1158 ahc_outb(ahc, SCBPTR, 2); 1159 if (ahc_inb(ahc, SCB_CONTROL) == 'A' 1160 && ahc_inb(ahc, SCB_CONTROL + 1) == 'D' 1161 && ahc_inb(ahc, SCB_CONTROL + 2) == 'P' 1162 && ahc_inb(ahc, SCB_CONTROL + 3) == 'T') { 1163 uint8_t *sc_bytes; 1164 int i; 1165 1166 printf("Got Here!\n"); 1167 sc_bytes = (uint8_t *)≻ 1168 for (i = 0; i < 64; i++) 1169 sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i); 1170 /* Byte 0x1c is stored in byte 4 of SCB2 */ 1171 sc_bytes[0x1c] = ahc_inb(ahc, SCB_CONTROL + 4); 1172 have_seeprom = verify_cksum(&sc); 1173 if (have_seeprom) 1174 printf("And it even worked!\n"); 1175 } 1176 } 1177#endif 1178 1179 if (!have_seeprom) { 1180 if (bootverbose) 1181 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1182 ahc->flags |= AHC_USEDEFAULTS; 1183 } else { 1184 /* 1185 * Put the data we've collected down into SRAM 1186 * where ahc_init will find it. 1187 */ 1188 int i; 1189 int max_targ = sc.max_targets & CFMAXTARG; 1190 uint16_t discenable; 1191 uint16_t ultraenb; 1192 1193 discenable = 0; 1194 ultraenb = 0; 1195 if ((sc.adapter_control & CFULTRAEN) != 0) { 1196 /* 1197 * Determine if this adapter has a "newstyle" 1198 * SEEPROM format. 1199 */ 1200 for (i = 0; i < max_targ; i++) { 1201 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1202 ahc->flags |= AHC_NEWEEPROM_FMT; 1203 break; 1204 } 1205 } 1206 } 1207 1208 for (i = 0; i < max_targ; i++) { 1209 u_int scsirate; 1210 uint16_t target_mask; 1211 1212 target_mask = 0x01 << i; 1213 if (sc.device_flags[i] & CFDISC) 1214 discenable |= target_mask; 1215 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1216 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1217 ultraenb |= target_mask; 1218 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1219 ultraenb |= target_mask; 1220 } 1221 if ((sc.device_flags[i] & CFXFER) == 0x04 1222 && (ultraenb & target_mask) != 0) { 1223 /* Treat 10MHz as a non-ultra speed */ 1224 sc.device_flags[i] &= ~CFXFER; 1225 ultraenb &= ~target_mask; 1226 } 1227 if ((ahc->features & AHC_ULTRA2) != 0) { 1228 u_int offset; 1229 1230 if (sc.device_flags[i] & CFSYNCH) 1231 offset = MAX_OFFSET_ULTRA2; 1232 else 1233 offset = 0; 1234 ahc_outb(ahc, TARG_OFFSET + i, offset); 1235 1236 /* 1237 * The ultra enable bits contain the 1238 * high bit of the ultra2 sync rate 1239 * field. 1240 */ 1241 scsirate = (sc.device_flags[i] & CFXFER) 1242 | ((ultraenb & target_mask) 1243 ? 0x8 : 0x0); 1244 if (sc.device_flags[i] & CFWIDEB) 1245 scsirate |= WIDEXFER; 1246 } else { 1247 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1248 if (sc.device_flags[i] & CFSYNCH) 1249 scsirate |= SOFS; 1250 if (sc.device_flags[i] & CFWIDEB) 1251 scsirate |= WIDEXFER; 1252 } 1253 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1254 } 1255 ahc->our_id = sc.brtime_id & CFSCSIID; 1256 1257 scsi_conf = (ahc->our_id & 0x7); 1258 if (sc.adapter_control & CFSPARITY) 1259 scsi_conf |= ENSPCHK; 1260 if (sc.adapter_control & CFRESETB) 1261 scsi_conf |= RESET_SCSI; 1262 1263 if (sc.bios_control & CFEXTEND) 1264 ahc->flags |= AHC_EXTENDED_TRANS_A; 1265 if (ahc->features & AHC_ULTRA 1266 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1267 /* Should we enable Ultra mode? */ 1268 if (!(sc.adapter_control & CFULTRAEN)) 1269 /* Treat us as a non-ultra card */ 1270 ultraenb = 0; 1271 } 1272 1273 if (sc.signature == CFSIGNATURE) { 1274 uint32_t devconfig; 1275 1276 /* Honor the STPWLEVEL settings */ 1277 devconfig = pci_read_config(ahc->device, DEVCONFIG, 1278 /*bytes*/4); 1279 devconfig &= ~STPWLEVEL; 1280 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1281 devconfig |= STPWLEVEL; 1282 pci_write_config(ahc->device, DEVCONFIG, 1283 devconfig, /*bytes*/4); 1284 } 1285 /* Set SCSICONF info */ 1286 ahc_outb(ahc, SCSICONF, scsi_conf); 1287 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1288 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1289 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1290 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1291 } 1292 1293 /* 1294 * Cards that have the external logic necessary to talk to 1295 * a SEEPROM, are almost certain to have the remaining logic 1296 * necessary for auto-termination control. This assumption 1297 * hasn't failed yet... 1298 */ 1299 have_autoterm = have_seeprom; 1300 if (have_seeprom) 1301 adapter_control = sc.adapter_control; 1302 else 1303 adapter_control = CFAUTOTERM; 1304 1305 /* 1306 * Some low-cost chips have SEEPROM and auto-term control built 1307 * in, instead of using a GAL. They can tell us directly 1308 * if the termination logic is enabled. 1309 */ 1310 if ((ahc->features & AHC_SPIOCAP) != 0) { 1311 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1312 have_autoterm = TRUE; 1313 else 1314 have_autoterm = FALSE; 1315 } 1316 1317 if (have_autoterm) 1318 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1319 1320 release_seeprom(&sd); 1321} 1322 1323static void 1324configure_termination(struct ahc_softc *ahc, 1325 struct seeprom_descriptor *sd, 1326 u_int adapter_control, 1327 u_int *sxfrctl1) 1328{ 1329 uint8_t brddat; 1330 1331 brddat = 0; 1332 1333 /* 1334 * Update the settings in sxfrctl1 to match the 1335 * termination settings 1336 */ 1337 *sxfrctl1 = 0; 1338 1339 /* 1340 * SEECS must be on for the GALS to latch 1341 * the data properly. Be sure to leave MS 1342 * on or we will release the seeprom. 1343 */ 1344 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1345 if ((adapter_control & CFAUTOTERM) != 0 1346 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1347 int internal50_present; 1348 int internal68_present; 1349 int externalcable_present; 1350 int eeprom_present; 1351 int enableSEC_low; 1352 int enableSEC_high; 1353 int enablePRI_low; 1354 int enablePRI_high; 1355 1356 enableSEC_low = 0; 1357 enableSEC_high = 0; 1358 enablePRI_low = 0; 1359 enablePRI_high = 0; 1360 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1361 ahc_new_term_detect(ahc, &enableSEC_low, 1362 &enableSEC_high, 1363 &enablePRI_low, 1364 &enablePRI_high, 1365 &eeprom_present); 1366 if ((adapter_control & CFSEAUTOTERM) == 0) { 1367 if (bootverbose) 1368 printf("%s: Manual SE Termination\n", 1369 ahc_name(ahc)); 1370 enableSEC_low = (adapter_control & CFSELOWTERM); 1371 enableSEC_high = 1372 (adapter_control & CFSEHIGHTERM); 1373 } 1374 if ((adapter_control & CFAUTOTERM) == 0) { 1375 if (bootverbose) 1376 printf("%s: Manual LVD Termination\n", 1377 ahc_name(ahc)); 1378 enablePRI_low = (adapter_control & CFSTERM); 1379 enablePRI_high = (adapter_control & CFWSTERM); 1380 } 1381 /* Make the table calculations below happy */ 1382 internal50_present = 0; 1383 internal68_present = 1; 1384 externalcable_present = 1; 1385 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1386 aic785X_cable_detect(ahc, &internal50_present, 1387 &externalcable_present, 1388 &eeprom_present); 1389 } else { 1390 aic787X_cable_detect(ahc, &internal50_present, 1391 &internal68_present, 1392 &externalcable_present, 1393 &eeprom_present); 1394 } 1395 1396 if ((ahc->features & AHC_WIDE) == 0) 1397 internal68_present = 0; 1398 1399 if (bootverbose) { 1400 if ((ahc->features & AHC_ULTRA2) == 0) { 1401 printf("%s: internal 50 cable %s present, " 1402 "internal 68 cable %s present\n", 1403 ahc_name(ahc), 1404 internal50_present ? "is":"not", 1405 internal68_present ? "is":"not"); 1406 1407 printf("%s: external cable %s present\n", 1408 ahc_name(ahc), 1409 externalcable_present ? "is":"not"); 1410 } 1411 printf("%s: BIOS eeprom %s present\n", 1412 ahc_name(ahc), eeprom_present ? "is" : "not"); 1413 } 1414 1415 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1416 /* 1417 * The 50 pin connector is a separate bus, 1418 * so force it to always be terminated. 1419 * In the future, perform current sensing 1420 * to determine if we are in the middle of 1421 * a properly terminated bus. 1422 */ 1423 internal50_present = 0; 1424 } 1425 1426 /* 1427 * Now set the termination based on what 1428 * we found. 1429 * Flash Enable = BRDDAT7 1430 * Secondary High Term Enable = BRDDAT6 1431 * Secondary Low Term Enable = BRDDAT5 (7890) 1432 * Primary High Term Enable = BRDDAT4 (7890) 1433 */ 1434 if ((ahc->features & AHC_ULTRA2) == 0 1435 && (internal50_present != 0) 1436 && (internal68_present != 0) 1437 && (externalcable_present != 0)) { 1438 printf("%s: Illegal cable configuration!!. " 1439 "Only two connectors on the " 1440 "adapter may be used at a " 1441 "time!\n", ahc_name(ahc)); 1442 } 1443 1444 if ((ahc->features & AHC_WIDE) != 0 1445 && ((externalcable_present == 0) 1446 || (internal68_present == 0) 1447 || (enableSEC_high != 0))) { 1448 brddat |= BRDDAT6; 1449 if (bootverbose) { 1450 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1451 printf("%s: 68 pin termination " 1452 "Enabled\n", ahc_name(ahc)); 1453 else 1454 printf("%s: %sHigh byte termination " 1455 "Enabled\n", ahc_name(ahc), 1456 enableSEC_high ? "Secondary " 1457 : ""); 1458 } 1459 } 1460 1461 if (((internal50_present ? 1 : 0) 1462 + (internal68_present ? 1 : 0) 1463 + (externalcable_present ? 1 : 0)) <= 1 1464 || (enableSEC_low != 0)) { 1465 if ((ahc->features & AHC_ULTRA2) != 0) 1466 brddat |= BRDDAT5; 1467 else 1468 *sxfrctl1 |= STPWEN; 1469 if (bootverbose) { 1470 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1471 printf("%s: 50 pin termination " 1472 "Enabled\n", ahc_name(ahc)); 1473 else 1474 printf("%s: %sLow byte termination " 1475 "Enabled\n", ahc_name(ahc), 1476 enableSEC_low ? "Secondary " 1477 : ""); 1478 } 1479 } 1480 1481 if (enablePRI_low != 0) { 1482 *sxfrctl1 |= STPWEN; 1483 if (bootverbose) 1484 printf("%s: Primary Low Byte termination " 1485 "Enabled\n", ahc_name(ahc)); 1486 } 1487 1488 /* 1489 * Setup STPWEN before setting up the rest of 1490 * the termination per the tech note on the U160 cards. 1491 */ 1492 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1493 1494 if (enablePRI_high != 0) { 1495 brddat |= BRDDAT4; 1496 if (bootverbose) 1497 printf("%s: Primary High Byte " 1498 "termination Enabled\n", 1499 ahc_name(ahc)); 1500 } 1501 1502 write_brdctl(ahc, brddat); 1503 1504 } else { 1505 if ((adapter_control & CFSTERM) != 0) { 1506 *sxfrctl1 |= STPWEN; 1507 1508 if (bootverbose) 1509 printf("%s: %sLow byte termination Enabled\n", 1510 ahc_name(ahc), 1511 (ahc->features & AHC_ULTRA2) ? "Primary " 1512 : ""); 1513 } 1514 1515 if ((adapter_control & CFWSTERM) != 0) { 1516 brddat |= BRDDAT6; 1517 if (bootverbose) 1518 printf("%s: %sHigh byte termination Enabled\n", 1519 ahc_name(ahc), 1520 (ahc->features & AHC_ULTRA2) 1521 ? "Secondary " : ""); 1522 } 1523 1524 /* 1525 * Setup STPWEN before setting up the rest of 1526 * the termination per the tech note on the U160 cards. 1527 */ 1528 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1529 1530 write_brdctl(ahc, brddat); 1531 } 1532 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1533} 1534 1535static void 1536ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1537 int *enableSEC_high, int *enablePRI_low, 1538 int *enablePRI_high, int *eeprom_present) 1539{ 1540 uint8_t brdctl; 1541 1542 /* 1543 * BRDDAT7 = Eeprom 1544 * BRDDAT6 = Enable Secondary High Byte termination 1545 * BRDDAT5 = Enable Secondary Low Byte termination 1546 * BRDDAT4 = Enable Primary high byte termination 1547 * BRDDAT3 = Enable Primary low byte termination 1548 */ 1549 brdctl = read_brdctl(ahc); 1550 *eeprom_present = brdctl & BRDDAT7; 1551 *enableSEC_high = (brdctl & BRDDAT6); 1552 *enableSEC_low = (brdctl & BRDDAT5); 1553 *enablePRI_high = (brdctl & BRDDAT4); 1554 *enablePRI_low = (brdctl & BRDDAT3); 1555} 1556 1557static void 1558aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1559 int *internal68_present, int *externalcable_present, 1560 int *eeprom_present) 1561{ 1562 uint8_t brdctl; 1563 1564 /* 1565 * First read the status of our cables. 1566 * Set the rom bank to 0 since the 1567 * bank setting serves as a multiplexor 1568 * for the cable detection logic. 1569 * BRDDAT5 controls the bank switch. 1570 */ 1571 write_brdctl(ahc, 0); 1572 1573 /* 1574 * Now read the state of the internal 1575 * connectors. BRDDAT6 is INT50 and 1576 * BRDDAT7 is INT68. 1577 */ 1578 brdctl = read_brdctl(ahc); 1579 *internal50_present = !(brdctl & BRDDAT6); 1580 *internal68_present = !(brdctl & BRDDAT7); 1581 1582 /* 1583 * Set the rom bank to 1 and determine 1584 * the other signals. 1585 */ 1586 write_brdctl(ahc, BRDDAT5); 1587 1588 /* 1589 * Now read the state of the external 1590 * connectors. BRDDAT6 is EXT68 and 1591 * BRDDAT7 is EPROMPS. 1592 */ 1593 brdctl = read_brdctl(ahc); 1594 *externalcable_present = !(brdctl & BRDDAT6); 1595 *eeprom_present = brdctl & BRDDAT7; 1596} 1597 1598static void 1599aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1600 int *externalcable_present, int *eeprom_present) 1601{ 1602 uint8_t brdctl; 1603 1604 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1605 ahc_outb(ahc, BRDCTL, 0); 1606 brdctl = ahc_inb(ahc, BRDCTL); 1607 *internal50_present = !(brdctl & BRDDAT5); 1608 *externalcable_present = !(brdctl & BRDDAT6); 1609 1610 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1611} 1612 1613static int 1614acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1615{ 1616 int wait; 1617 1618 if ((ahc->features & AHC_SPIOCAP) != 0 1619 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1620 return (0); 1621 1622 /* 1623 * Request access of the memory port. When access is 1624 * granted, SEERDY will go high. We use a 1 second 1625 * timeout which should be near 1 second more than 1626 * is needed. Reason: after the chip reset, there 1627 * should be no contention. 1628 */ 1629 SEEPROM_OUTB(sd, sd->sd_MS); 1630 wait = 1000; /* 1 second timeout in msec */ 1631 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1632 DELAY(1000); /* delay 1 msec */ 1633 } 1634 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1635 SEEPROM_OUTB(sd, 0); 1636 return (0); 1637 } 1638 return(1); 1639} 1640 1641static void 1642release_seeprom(struct seeprom_descriptor *sd) 1643{ 1644 /* Release access to the memory port and the serial EEPROM. */ 1645 SEEPROM_OUTB(sd, 0); 1646} 1647 1648static void 1649write_brdctl(struct ahc_softc *ahc, uint8_t value) 1650{ 1651 uint8_t brdctl; 1652 1653 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1654 brdctl = BRDSTB; 1655 if (ahc->channel == 'B') 1656 brdctl |= BRDCS; 1657 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1658 brdctl = 0; 1659 } else { 1660 brdctl = BRDSTB|BRDCS; 1661 } 1662 ahc_outb(ahc, BRDCTL, brdctl); 1663 DELAY(20); 1664 brdctl |= value; 1665 ahc_outb(ahc, BRDCTL, brdctl); 1666 DELAY(20); 1667 if ((ahc->features & AHC_ULTRA2) != 0) 1668 brdctl |= BRDSTB_ULTRA2; 1669 else 1670 brdctl &= ~BRDSTB; 1671 ahc_outb(ahc, BRDCTL, brdctl); 1672 DELAY(20); 1673 if ((ahc->features & AHC_ULTRA2) != 0) 1674 brdctl = 0; 1675 else 1676 brdctl &= ~BRDCS; 1677 ahc_outb(ahc, BRDCTL, brdctl); 1678} 1679 1680static uint8_t 1681read_brdctl(ahc) 1682 struct ahc_softc *ahc; 1683{ 1684 uint8_t brdctl; 1685 uint8_t value; 1686 1687 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1688 brdctl = BRDRW; 1689 if (ahc->channel == 'B') 1690 brdctl |= BRDCS; 1691 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1692 brdctl = BRDRW_ULTRA2; 1693 } else { 1694 brdctl = BRDRW|BRDCS; 1695 } 1696 ahc_outb(ahc, BRDCTL, brdctl); 1697 DELAY(20); 1698 value = ahc_inb(ahc, BRDCTL); 1699 ahc_outb(ahc, BRDCTL, 0); 1700 return (value); 1701} 1702 1703#define DPE 0x80 1704#define SSE 0x40 1705#define RMA 0x20 1706#define RTA 0x10 1707#define STA 0x08 1708#define DPR 0x01 1709 1710void 1711ahc_pci_intr(struct ahc_softc *ahc) 1712{ 1713 uint8_t status1; 1714 1715 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1716 1717 if (status1 & DPE) { 1718 printf("%s: Data Parity Error Detected during address " 1719 "or write data phase\n", ahc_name(ahc)); 1720 } 1721 if (status1 & SSE) { 1722 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1723 } 1724 if (status1 & RMA) { 1725 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1726 } 1727 if (status1 & RTA) { 1728 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1729 } 1730 if (status1 & STA) { 1731 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1732 } 1733 if (status1 & DPR) { 1734 printf("%s: Data Parity Error has been reported via PERR#\n", 1735 ahc_name(ahc)); 1736 } 1737 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1738 printf("%s: Latched PCIERR interrupt with " 1739 "no status bits set\n", ahc_name(ahc)); 1740 } 1741 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1742 1743 if (status1 & (DPR|RMA|RTA)) { 1744 ahc_outb(ahc, CLRINT, CLRPARERR); 1745 } 1746} 1747 1748static int 1749ahc_aic7850_setup(device_t dev, struct ahc_probe_config *probe_config) 1750{ 1751 probe_config->channel = 'A'; 1752 probe_config->chip = AHC_AIC7850; 1753 probe_config->features = AHC_AIC7850_FE; 1754 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1755 return (0); 1756} 1757 1758static int 1759ahc_aic7855_setup(device_t dev, struct ahc_probe_config *probe_config) 1760{ 1761 probe_config->channel = 'A'; 1762 probe_config->chip = AHC_AIC7855; 1763 probe_config->features = AHC_AIC7855_FE; 1764 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1765 return (0); 1766} 1767 1768static int 1769ahc_aic7859_setup(device_t dev, struct ahc_probe_config *probe_config) 1770{ 1771 probe_config->channel = 'A'; 1772 probe_config->chip = AHC_AIC7859; 1773 probe_config->features = AHC_AIC7859_FE; 1774 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1775 return (0); 1776} 1777 1778static int 1779ahc_aic7860_setup(device_t dev, struct ahc_probe_config *probe_config) 1780{ 1781 probe_config->channel = 'A'; 1782 probe_config->chip = AHC_AIC7860; 1783 probe_config->features = AHC_AIC7860_FE; 1784 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1785 return (0); 1786} 1787 1788static int 1789ahc_aic7870_setup(device_t dev, struct ahc_probe_config *probe_config) 1790{ 1791 probe_config->channel = 'A'; 1792 probe_config->chip = AHC_AIC7870; 1793 probe_config->features = AHC_AIC7870_FE; 1794 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1795 return (0); 1796} 1797 1798static int 1799ahc_aha394X_setup(device_t dev, struct ahc_probe_config *probe_config) 1800{ 1801 int error; 1802 1803 error = ahc_aic7870_setup(dev, probe_config); 1804 if (error == 0) 1805 error = ahc_aha394XX_setup(dev, probe_config); 1806 return (error); 1807} 1808 1809static int 1810ahc_aha398X_setup(device_t dev, struct ahc_probe_config *probe_config) 1811{ 1812 int error; 1813 1814 error = ahc_aic7870_setup(dev, probe_config); 1815 if (error == 0) 1816 error = ahc_aha398XX_setup(dev, probe_config); 1817 return (error); 1818} 1819 1820static int 1821ahc_aha494X_setup(device_t dev, struct ahc_probe_config *probe_config) 1822{ 1823 int error; 1824 1825 error = ahc_aic7870_setup(dev, probe_config); 1826 if (error == 0) 1827 error = ahc_aha494XX_setup(dev, probe_config); 1828 return (error); 1829} 1830 1831static int 1832ahc_aic7880_setup(device_t dev, struct ahc_probe_config *probe_config) 1833{ 1834 probe_config->channel = 'A'; 1835 probe_config->chip = AHC_AIC7880; 1836 probe_config->features = AHC_AIC7880_FE; 1837 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1838 return (0); 1839} 1840 1841static int 1842ahc_2940Pro_setup(device_t dev, struct ahc_probe_config *probe_config) 1843{ 1844 int error; 1845 1846 probe_config->flags |= AHC_INT50_SPEEDFLEX; 1847 error = ahc_aic7880_setup(dev, probe_config); 1848 return (0); 1849} 1850 1851static int 1852ahc_aha394XU_setup(device_t dev, struct ahc_probe_config *probe_config) 1853{ 1854 int error; 1855 1856 error = ahc_aic7880_setup(dev, probe_config); 1857 if (error == 0) 1858 error = ahc_aha394XX_setup(dev, probe_config); 1859 return (error); 1860} 1861 1862static int 1863ahc_aha398XU_setup(device_t dev, struct ahc_probe_config *probe_config) 1864{ 1865 int error; 1866 1867 error = ahc_aic7880_setup(dev, probe_config); 1868 if (error == 0) 1869 error = ahc_aha398XX_setup(dev, probe_config); 1870 return (error); 1871} 1872 1873static int 1874ahc_aic7890_setup(device_t dev, struct ahc_probe_config *probe_config) 1875{ 1876 probe_config->channel = 'A'; 1877 probe_config->chip = AHC_AIC7890; 1878 probe_config->features = AHC_AIC7890_FE; 1879 probe_config->flags |= AHC_NEWEEPROM_FMT; 1880 if (pci_get_revid(dev) == 0) 1881 probe_config->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1882 return (0); 1883} 1884 1885static int 1886ahc_aic7892_setup(device_t dev, struct ahc_probe_config *probe_config) 1887{ 1888 probe_config->channel = 'A'; 1889 probe_config->chip = AHC_AIC7892; 1890 probe_config->features = AHC_AIC7892_FE; 1891 probe_config->flags |= AHC_NEWEEPROM_FMT; 1892 return (0); 1893} 1894 1895static int 1896ahc_aic7895_setup(device_t dev, struct ahc_probe_config *probe_config) 1897{ 1898 uint32_t devconfig; 1899 1900 probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1901 probe_config->chip = AHC_AIC7895; 1902 /* The 'C' revision of the aic7895 has a few additional features */ 1903 if (pci_get_revid(dev) >= 4) 1904 probe_config->features = AHC_AIC7895C_FE; 1905 else 1906 probe_config->features = AHC_AIC7895_FE; 1907 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1908 probe_config->flags |= AHC_NEWEEPROM_FMT; 1909 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1910 devconfig |= SCBSIZE32; 1911 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1912 return (0); 1913} 1914 1915static int 1916ahc_aic7896_setup(device_t dev, struct ahc_probe_config *probe_config) 1917{ 1918 probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1919 probe_config->chip = AHC_AIC7896; 1920 probe_config->features = AHC_AIC7896_FE; 1921 probe_config->flags |= AHC_NEWEEPROM_FMT; 1922 probe_config->bugs |= AHC_CACHETHEN_DIS_BUG; 1923 return (0); 1924} 1925 1926static int 1927ahc_aic7899_setup(device_t dev, struct ahc_probe_config *probe_config) 1928{ 1929 probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1930 probe_config->chip = AHC_AIC7899; 1931 probe_config->features = AHC_AIC7899_FE; 1932 probe_config->flags |= AHC_NEWEEPROM_FMT; 1933 return (0); 1934} 1935 1936static int 1937ahc_raid_setup(device_t dev, struct ahc_probe_config *probe_config) 1938{ 1939 printf("RAID functionality unsupported\n"); 1940 return (ENXIO); 1941} 1942 1943static int 1944ahc_aha394XX_setup(device_t dev, struct ahc_probe_config *probe_config) 1945{ 1946 switch (pci_get_slot(dev)) { 1947 case AHC_394X_SLOT_CHANNEL_A: 1948 probe_config->channel = 'A'; 1949 break; 1950 case AHC_394X_SLOT_CHANNEL_B: 1951 probe_config->channel = 'B'; 1952 break; 1953 default: 1954 printf("adapter at unexpected slot %d\n" 1955 "unable to map to a channel\n", 1956 pci_get_slot(dev)); 1957 probe_config->channel = 'A'; 1958 } 1959 return (0); 1960} 1961 1962static int 1963ahc_aha398XX_setup(device_t dev, struct ahc_probe_config *probe_config) 1964{ 1965 switch (pci_get_slot(dev)) { 1966 case AHC_398X_SLOT_CHANNEL_A: 1967 probe_config->channel = 'A'; 1968 break; 1969 case AHC_398X_SLOT_CHANNEL_B: 1970 probe_config->channel = 'B'; 1971 break; 1972 case AHC_398X_SLOT_CHANNEL_C: 1973 probe_config->channel = 'C'; 1974 break; 1975 default: 1976 printf("adapter at unexpected slot %d\n" 1977 "unable to map to a channel\n", 1978 pci_get_slot(dev)); 1979 probe_config->channel = 'A'; 1980 break; 1981 } 1982 probe_config->flags |= AHC_LARGE_SEEPROM; 1983 return (0); 1984} 1985 1986static int 1987ahc_aha494XX_setup(device_t dev, struct ahc_probe_config *probe_config) 1988{ 1989 switch (pci_get_slot(dev)) { 1990 case AHC_494X_SLOT_CHANNEL_A: 1991 probe_config->channel = 'A'; 1992 break; 1993 case AHC_494X_SLOT_CHANNEL_B: 1994 probe_config->channel = 'B'; 1995 break; 1996 case AHC_494X_SLOT_CHANNEL_C: 1997 probe_config->channel = 'C'; 1998 break; 1999 case AHC_494X_SLOT_CHANNEL_D: 2000 probe_config->channel = 'D'; 2001 break; 2002 default: 2003 printf("adapter at unexpected slot %d\n" 2004 "unable to map to a channel\n", 2005 pci_get_slot(dev)); 2006 probe_config->channel = 'A'; 2007 } 2008 probe_config->flags |= AHC_LARGE_SEEPROM; 2009 return (0); 2010} 2011