ahc_pci.c revision 63457
1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU Public License ("GPL"). 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/ahc_pci.c 63457 2000-07-18 20:12:14Z gibbs $ 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41 42#include <pci/pcireg.h> 43#include <pci/pcivar.h> 44 45#include <machine/bus_memio.h> 46#include <machine/bus_pio.h> 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <machine/clock.h> 50#include <sys/rman.h> 51 52#include <cam/cam.h> 53#include <cam/cam_ccb.h> 54#include <cam/cam_sim.h> 55#include <cam/cam_xpt_sim.h> 56 57#include <cam/scsi/scsi_all.h> 58 59#include <dev/aic7xxx/aic7xxx.h> 60#include <dev/aic7xxx/93cx6.h> 61 62#include <aic7xxx_reg.h> 63 64#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 65#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 66 67static __inline uint64_t 68ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 69{ 70 uint64_t id; 71 72 id = subvendor 73 | (subdevice << 16) 74 | ((uint64_t)vendor << 32) 75 | ((uint64_t)device << 48); 76 77 return (id); 78} 79 80#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 81#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 82#define ID_AIC7850 0x5078900400000000ull 83#define ID_AHA_2910_15_20_30C 0x5078900478509004ull 84#define ID_AIC7855 0x5578900400000000ull 85#define ID_AIC7859 0x3860900400000000ull 86#define ID_AHA_2930CU 0x3860900438699004ull 87#define ID_AIC7860 0x6078900400000000ull 88#define ID_AIC7860C 0x6078900478609004ull 89#define ID_AHA_2940AU_0 0x6178900400000000ull 90#define ID_AHA_2940AU_1 0x6178900478619004ull 91#define ID_AHA_2940AU_CN 0x2178900478219004ull 92#define ID_AHA_2930C_VAR 0x6038900438689004ull 93 94#define ID_AIC7870 0x7078900400000000ull 95#define ID_AHA_2940 0x7178900400000000ull 96#define ID_AHA_3940 0x7278900400000000ull 97#define ID_AHA_398X 0x7378900400000000ull 98#define ID_AHA_2944 0x7478900400000000ull 99#define ID_AHA_3944 0x7578900400000000ull 100#define ID_AHA_4944 0x7678900400000000ull 101 102#define ID_AIC7880 0x8078900400000000ull 103#define ID_AIC7880_B 0x8078900478809004ull 104#define ID_AHA_2940U 0x8178900400000000ull 105#define ID_AHA_3940U 0x8278900400000000ull 106#define ID_AHA_2944U 0x8478900400000000ull 107#define ID_AHA_3944U 0x8578900400000000ull 108#define ID_AHA_398XU 0x8378900400000000ull 109#define ID_AHA_4944U 0x8678900400000000ull 110#define ID_AHA_2940UB 0x8178900478819004ull 111#define ID_AHA_2930U 0x8878900478889004ull 112#define ID_AHA_2940U_PRO 0x8778900478879004ull 113#define ID_AHA_2940U_CN 0x0078900478009004ull 114 115#define ID_AIC7895 0x7895900478959004ull 116#define ID_AIC7895_RAID_PORT 0x7893900478939004ull 117#define ID_AHA_2940U_DUAL 0x7895900478919004ull 118#define ID_AHA_3940AU 0x7895900478929004ull 119#define ID_AHA_3944AU 0x7895900478949004ull 120 121#define ID_AIC7890 0x001F9005000F9005ull 122#define ID_AAA_131U2 0x0013900500039005ull 123#define ID_AHA_2930U2 0x0011900501819005ull 124#define ID_AHA_2940U2B 0x00109005A1009005ull 125#define ID_AHA_2940U2_OEM 0x0010900521809005ull 126#define ID_AHA_2940U2 0x00109005A1809005ull 127#define ID_AHA_2950U2B 0x00109005E1009005ull 128 129#define ID_AIC7892 0x008F9005FFFF9005ull 130#define ID_AHA_29160 0x00809005E2A09005ull 131#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 132#define ID_AHA_29160N 0x0080900562A09005ull 133#define ID_AHA_29160B 0x00809005E2209005ull 134#define ID_AHA_19160B 0x0081900562A19005ull 135 136#define ID_AIC7896 0x005F9005FFFF9005ull 137#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 138#define ID_AHA_3950U2B_1 0x00509005F5009005ull 139#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 140#define ID_AHA_3950U2D_1 0x00519005B5009005ull 141 142#define ID_AIC7899 0x00CF9005FFFF9005ull 143#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 144#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 145 146#define ID_AIC7810 0x1078900400000000ull 147#define ID_AIC7815 0x7815900400000000ull 148 149typedef int (ahc_device_setup_t)(device_t, struct ahc_probe_config *); 150 151static ahc_device_setup_t ahc_aic7850_setup; 152static ahc_device_setup_t ahc_aic7855_setup; 153static ahc_device_setup_t ahc_aic7859_setup; 154static ahc_device_setup_t ahc_aic7860_setup; 155static ahc_device_setup_t ahc_aic7870_setup; 156static ahc_device_setup_t ahc_aha394X_setup; 157static ahc_device_setup_t ahc_aha494X_setup; 158static ahc_device_setup_t ahc_aha398X_setup; 159static ahc_device_setup_t ahc_aic7880_setup; 160static ahc_device_setup_t ahc_2940Pro_setup; 161static ahc_device_setup_t ahc_aha394XU_setup; 162static ahc_device_setup_t ahc_aha398XU_setup; 163static ahc_device_setup_t ahc_aic7890_setup; 164static ahc_device_setup_t ahc_aic7892_setup; 165static ahc_device_setup_t ahc_aic7895_setup; 166static ahc_device_setup_t ahc_aic7896_setup; 167static ahc_device_setup_t ahc_aic7899_setup; 168static ahc_device_setup_t ahc_raid_setup; 169static ahc_device_setup_t ahc_aha394XX_setup; 170static ahc_device_setup_t ahc_aha494XX_setup; 171static ahc_device_setup_t ahc_aha398XX_setup; 172 173struct ahc_pci_identity { 174 uint64_t full_id; 175 uint64_t id_mask; 176 char *name; 177 ahc_device_setup_t *setup; 178}; 179 180struct ahc_pci_identity ahc_pci_ident_table [] = 181{ 182 /* aic7850 based controllers */ 183 { 184 ID_AHA_2910_15_20_30C, 185 ID_ALL_MASK, 186 "Adaptec 2910/15/20/30C SCSI adapter", 187 ahc_aic7850_setup 188 }, 189 /* aic7859 based controllers */ 190 { 191 ID_AHA_2930CU, 192 ID_ALL_MASK, 193 "Adaptec 2930CU SCSI adapter", 194 ahc_aic7859_setup 195 }, 196 /* aic7860 based controllers */ 197 { 198 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 199 ID_DEV_VENDOR_MASK, 200 "Adaptec 2940A Ultra SCSI adapter", 201 ahc_aic7860_setup 202 }, 203 { 204 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 205 ID_DEV_VENDOR_MASK, 206 "Adaptec 2940A/CN Ultra SCSI adapter", 207 ahc_aic7860_setup 208 }, 209 { 210 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 211 ID_DEV_VENDOR_MASK, 212 "Adaptec 2930C SCSI adapter (VAR)", 213 ahc_aic7860_setup 214 }, 215 /* aic7870 based controllers */ 216 { 217 ID_AHA_2940, 218 ID_ALL_MASK, 219 "Adaptec 2940 SCSI adapter", 220 ahc_aic7870_setup 221 }, 222 { 223 ID_AHA_3940, 224 ID_ALL_MASK, 225 "Adaptec 3940 SCSI adapter", 226 ahc_aha394X_setup 227 }, 228 { 229 ID_AHA_398X, 230 ID_ALL_MASK, 231 "Adaptec 398X SCSI RAID adapter", 232 ahc_aha398X_setup 233 }, 234 { 235 ID_AHA_2944, 236 ID_ALL_MASK, 237 "Adaptec 2944 SCSI adapter", 238 ahc_aic7870_setup 239 }, 240 { 241 ID_AHA_3944, 242 ID_ALL_MASK, 243 "Adaptec 3944 SCSI adapter", 244 ahc_aha394X_setup 245 }, 246 { 247 ID_AHA_4944, 248 ID_ALL_MASK, 249 "Adaptec 4944 SCSI adapter", 250 ahc_aha494X_setup 251 }, 252 /* aic7880 based controllers */ 253 { 254 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 255 ID_DEV_VENDOR_MASK, 256 "Adaptec 2940 Ultra SCSI adapter", 257 ahc_aic7880_setup 258 }, 259 { 260 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 261 ID_DEV_VENDOR_MASK, 262 "Adaptec 3940 Ultra SCSI adapter", 263 ahc_aha394XU_setup 264 }, 265 { 266 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 267 ID_DEV_VENDOR_MASK, 268 "Adaptec 2944 Ultra SCSI adapter", 269 ahc_aic7880_setup 270 }, 271 { 272 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 273 ID_DEV_VENDOR_MASK, 274 "Adaptec 3944 Ultra SCSI adapter", 275 ahc_aha394XU_setup 276 }, 277 { 278 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 279 ID_DEV_VENDOR_MASK, 280 "Adaptec 398X Ultra SCSI RAID adapter", 281 ahc_aha398XU_setup 282 }, 283 { 284 /* 285 * XXX Don't know the slot numbers 286 * so we can't identify channels 287 */ 288 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 289 ID_DEV_VENDOR_MASK, 290 "Adaptec 4944 Ultra SCSI adapter", 291 ahc_aic7880_setup 292 }, 293 { 294 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 295 ID_DEV_VENDOR_MASK, 296 "Adaptec 2930 Ultra SCSI adapter", 297 ahc_aic7880_setup 298 }, 299 { 300 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 301 ID_DEV_VENDOR_MASK, 302 "Adaptec 2940 Pro Ultra SCSI adapter", 303 ahc_2940Pro_setup 304 }, 305 { 306 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 307 ID_DEV_VENDOR_MASK, 308 "Adaptec 2940/CN Ultra SCSI adapter", 309 ahc_aic7880_setup 310 }, 311 /* aic7890 based controllers */ 312 { 313 ID_AHA_2930U2, 314 ID_ALL_MASK, 315 "Adaptec 2930 Ultra2 SCSI adapter", 316 ahc_aic7890_setup 317 }, 318 { 319 ID_AHA_2940U2B, 320 ID_ALL_MASK, 321 "Adaptec 2940B Ultra2 SCSI adapter", 322 ahc_aic7890_setup 323 }, 324 { 325 ID_AHA_2940U2_OEM, 326 ID_ALL_MASK, 327 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 328 ahc_aic7890_setup 329 }, 330 { 331 ID_AHA_2940U2, 332 ID_ALL_MASK, 333 "Adaptec 2940 Ultra2 SCSI adapter", 334 ahc_aic7890_setup 335 }, 336 { 337 ID_AHA_2950U2B, 338 ID_ALL_MASK, 339 "Adaptec 2950 Ultra2 SCSI adapter", 340 ahc_aic7890_setup 341 }, 342 { 343 ID_AAA_131U2, 344 ID_ALL_MASK, 345 "Adaptec AAA-131 Ultra2 RAID adapter", 346 ahc_aic7890_setup 347 }, 348 /* aic7892 based controllers */ 349 { 350 ID_AHA_29160, 351 ID_ALL_MASK, 352 "Adaptec 29160 Ultra160 SCSI adapter", 353 ahc_aic7892_setup 354 }, 355 { 356 ID_AHA_29160_CPQ, 357 ID_ALL_MASK, 358 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 359 ahc_aic7892_setup 360 }, 361 { 362 ID_AHA_29160N, 363 ID_ALL_MASK, 364 "Adaptec 29160N Ultra160 SCSI adapter", 365 ahc_aic7892_setup 366 }, 367 { 368 ID_AHA_29160B, 369 ID_ALL_MASK, 370 "Adaptec 29160B Ultra160 SCSI adapter", 371 ahc_aic7892_setup 372 }, 373 { 374 ID_AHA_19160B, 375 ID_ALL_MASK, 376 "Adaptec 19160B Ultra160 SCSI adapter", 377 ahc_aic7892_setup 378 }, 379 /* aic7895 based controllers */ 380 { 381 ID_AHA_2940U_DUAL, 382 ID_ALL_MASK, 383 "Adaptec 2940/DUAL Ultra SCSI adapter", 384 ahc_aic7895_setup 385 }, 386 { 387 ID_AHA_3940AU, 388 ID_ALL_MASK, 389 "Adaptec 3940A Ultra SCSI adapter", 390 ahc_aic7895_setup 391 }, 392 { 393 ID_AHA_3944AU, 394 ID_ALL_MASK, 395 "Adaptec 3944A Ultra SCSI adapter", 396 ahc_aic7895_setup 397 }, 398 /* aic7896/97 based controllers */ 399 { 400 ID_AHA_3950U2B_0, 401 ID_ALL_MASK, 402 "Adaptec 3950B Ultra2 SCSI adapter", 403 ahc_aic7896_setup 404 }, 405 { 406 ID_AHA_3950U2B_1, 407 ID_ALL_MASK, 408 "Adaptec 3950B Ultra2 SCSI adapter", 409 ahc_aic7896_setup 410 }, 411 { 412 ID_AHA_3950U2D_0, 413 ID_ALL_MASK, 414 "Adaptec 3950D Ultra2 SCSI adapter", 415 ahc_aic7896_setup 416 }, 417 { 418 ID_AHA_3950U2D_1, 419 ID_ALL_MASK, 420 "Adaptec 3950D Ultra2 SCSI adapter", 421 ahc_aic7896_setup 422 }, 423 /* aic7899 based controllers */ 424 { 425 ID_AHA_3960D, 426 ID_ALL_MASK, 427 "Adaptec 3960D Ultra160 SCSI adapter", 428 ahc_aic7899_setup 429 }, 430 { 431 ID_AHA_3960D_CPQ, 432 ID_ALL_MASK, 433 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 434 ahc_aic7899_setup 435 }, 436 /* Generic chip probes for devices we don't know 'exactly' */ 437 { 438 ID_AIC7850 & ID_DEV_VENDOR_MASK, 439 ID_DEV_VENDOR_MASK, 440 "Adaptec aic7850 SCSI adapter", 441 ahc_aic7850_setup 442 }, 443 { 444 ID_AIC7855 & ID_DEV_VENDOR_MASK, 445 ID_DEV_VENDOR_MASK, 446 "Adaptec aic7855 SCSI adapter", 447 ahc_aic7855_setup 448 }, 449 { 450 ID_AIC7859 & ID_DEV_VENDOR_MASK, 451 ID_DEV_VENDOR_MASK, 452 "Adaptec aic7859 SCSI adapter", 453 ahc_aic7859_setup 454 }, 455 { 456 ID_AIC7860 & ID_DEV_VENDOR_MASK, 457 ID_DEV_VENDOR_MASK, 458 "Adaptec aic7860 SCSI adapter", 459 ahc_aic7860_setup 460 }, 461 { 462 ID_AIC7870 & ID_DEV_VENDOR_MASK, 463 ID_DEV_VENDOR_MASK, 464 "Adaptec aic7870 SCSI adapter", 465 ahc_aic7870_setup 466 }, 467 { 468 ID_AIC7880 & ID_DEV_VENDOR_MASK, 469 ID_DEV_VENDOR_MASK, 470 "Adaptec aic7880 Ultra SCSI adapter", 471 ahc_aic7880_setup 472 }, 473 { 474 ID_AIC7890 & ID_DEV_VENDOR_MASK, 475 ID_DEV_VENDOR_MASK, 476 "Adaptec aic7890/91 Ultra2 SCSI adapter", 477 ahc_aic7890_setup 478 }, 479 { 480 ID_AIC7892 & ID_DEV_VENDOR_MASK, 481 ID_DEV_VENDOR_MASK, 482 "Adaptec aic7892 Ultra160 SCSI adapter", 483 ahc_aic7892_setup 484 }, 485 { 486 ID_AIC7895 & ID_DEV_VENDOR_MASK, 487 ID_DEV_VENDOR_MASK, 488 "Adaptec aic7895 Ultra SCSI adapter", 489 ahc_aic7895_setup 490 }, 491 { 492 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 493 ID_DEV_VENDOR_MASK, 494 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 495 ahc_aic7895_setup 496 }, 497 { 498 ID_AIC7896 & ID_DEV_VENDOR_MASK, 499 ID_DEV_VENDOR_MASK, 500 "Adaptec aic7896/97 Ultra2 SCSI adapter", 501 ahc_aic7896_setup 502 }, 503 { 504 ID_AIC7899 & ID_DEV_VENDOR_MASK, 505 ID_DEV_VENDOR_MASK, 506 "Adaptec aic7899 Ultra160 SCSI adapter", 507 ahc_aic7899_setup 508 }, 509 { 510 ID_AIC7810 & ID_DEV_VENDOR_MASK, 511 ID_DEV_VENDOR_MASK, 512 "Adaptec aic7810 RAID memory controller", 513 ahc_raid_setup 514 }, 515 { 516 ID_AIC7815 & ID_DEV_VENDOR_MASK, 517 ID_DEV_VENDOR_MASK, 518 "Adaptec aic7815 RAID memory controller", 519 ahc_raid_setup 520 } 521}; 522 523static const int ahc_num_pci_devs = 524 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 525 526#define AHC_394X_SLOT_CHANNEL_A 4 527#define AHC_394X_SLOT_CHANNEL_B 5 528 529#define AHC_398X_SLOT_CHANNEL_A 4 530#define AHC_398X_SLOT_CHANNEL_B 8 531#define AHC_398X_SLOT_CHANNEL_C 12 532 533#define AHC_494X_SLOT_CHANNEL_A 4 534#define AHC_494X_SLOT_CHANNEL_B 5 535#define AHC_494X_SLOT_CHANNEL_C 6 536#define AHC_494X_SLOT_CHANNEL_D 7 537 538#define DEVCONFIG 0x40 539#define SCBSIZE32 0x00010000ul /* aic789X only */ 540#define MPORTMODE 0x00000400ul /* aic7870 only */ 541#define RAMPSM 0x00000200ul /* aic7870 only */ 542#define VOLSENSE 0x00000100ul 543#define SCBRAMSEL 0x00000080ul 544#define MRDCEN 0x00000040ul 545#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 546#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 547#define BERREN 0x00000008ul 548#define DACEN 0x00000004ul 549#define STPWLEVEL 0x00000002ul 550#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 551 552#define CSIZE_LATTIME 0x0c 553#define CACHESIZE 0x0000003ful /* only 5 bits */ 554#define LATTIME 0x0000ff00ul 555 556static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 557static int ahc_ext_scbram_present(struct ahc_softc *ahc); 558static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 559 int pcheck, int fast, int large); 560static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 561static int verify_cksum(struct seeprom_config *sc); 562static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 563static void configure_termination(struct ahc_softc *ahc, 564 struct seeprom_descriptor *sd, 565 u_int adapter_control, 566 u_int *sxfrctl1); 567 568static void ahc_new_term_detect(struct ahc_softc *ahc, 569 int *enableSEC_low, 570 int *enableSEC_high, 571 int *enablePRI_low, 572 int *enablePRI_high, 573 int *eeprom_present); 574static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 575 int *internal68_present, 576 int *externalcable_present, 577 int *eeprom_present); 578static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 579 int *externalcable_present, 580 int *eeprom_present); 581static int acquire_seeprom(struct ahc_softc *ahc, 582 struct seeprom_descriptor *sd); 583static void release_seeprom(struct seeprom_descriptor *sd); 584static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 585static uint8_t read_brdctl(struct ahc_softc *ahc); 586 587static struct ahc_softc *first_398X; 588 589static int ahc_pci_probe(device_t dev); 590static int ahc_pci_attach(device_t dev); 591 592/* Exported for use in the ahc_intr routine */ 593void ahc_pci_intr(struct ahc_softc *ahc); 594 595static device_method_t ahc_pci_methods[] = { 596 /* Device interface */ 597 DEVMETHOD(device_probe, ahc_pci_probe), 598 DEVMETHOD(device_attach, ahc_pci_attach), 599 { 0, 0 } 600}; 601 602static driver_t ahc_pci_driver = { 603 "ahc", 604 ahc_pci_methods, 605 sizeof(struct ahc_softc) 606}; 607 608static devclass_t ahc_devclass; 609 610DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 611 612static struct ahc_pci_identity * 613ahc_find_pci_device(device_t dev) 614{ 615 uint64_t full_id; 616 struct ahc_pci_identity *entry; 617 u_int i; 618 619 full_id = ahc_compose_id(pci_get_device(dev), 620 pci_get_vendor(dev), 621 pci_get_subdevice(dev), 622 pci_get_subvendor(dev)); 623 624 for (i = 0; i < ahc_num_pci_devs; i++) { 625 entry = &ahc_pci_ident_table[i]; 626 if (entry->full_id == (full_id & entry->id_mask)) 627 return (entry); 628 } 629 return (NULL); 630} 631 632static int 633ahc_pci_probe(device_t dev) 634{ 635 struct ahc_pci_identity *entry; 636 637 entry = ahc_find_pci_device(dev); 638 if (entry != NULL) { 639 device_set_desc(dev, entry->name); 640 return (0); 641 } 642 return (ENXIO); 643} 644 645static int 646ahc_pci_attach(device_t dev) 647{ 648 struct ahc_probe_config probe_config; 649 bus_dma_tag_t parent_dmat; 650 struct ahc_pci_identity *entry; 651 struct resource *regs; 652 struct ahc_softc *ahc; 653 struct scb_data *shared_scb_data; 654 u_int command; 655 int regs_type; 656 int regs_id; 657 u_int our_id = 0; 658 u_int sxfrctl1; 659 u_int scsiseq; 660 u_int dscommand0; 661 int error; 662 int zero; 663 uint8_t sblkctl; 664 665 shared_scb_data = NULL; 666 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 667 entry = ahc_find_pci_device(dev); 668 if (entry == NULL) 669 return (ENXIO); 670 ahc_init_probe_config(&probe_config); 671 error = entry->setup(dev, &probe_config); 672 probe_config.chip |= AHC_PCI; 673 probe_config.description = entry->name; 674 if (error != 0) 675 return (error); 676 677 regs = NULL; 678 regs_type = 0; 679 regs_id = 0; 680#ifdef AHC_ALLOW_MEMIO 681 if ((command & PCIM_CMD_MEMEN) != 0) { 682 regs_type = SYS_RES_MEMORY; 683 regs_id = AHC_PCI_MEMADDR; 684 regs = bus_alloc_resource(dev, regs_type, 685 ®s_id, 0, ~0, 1, RF_ACTIVE); 686 } 687#endif 688 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 689 regs_type = SYS_RES_IOPORT; 690 regs_id = AHC_PCI_IOADDR; 691 regs = bus_alloc_resource(dev, regs_type, 692 ®s_id, 0, ~0, 1, RF_ACTIVE); 693 } 694 695 if (regs == NULL) { 696 device_printf(dev, "can't allocate register resources\n"); 697 return (ENOMEM); 698 } 699 700 /* Ensure busmastering is enabled */ 701 command |= PCIM_CMD_BUSMASTEREN; 702 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 703 704 /* Allocate a dmatag for our SCB DMA maps */ 705 /* XXX Should be a child of the PCI bus dma tag */ 706 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 707 /*boundary*/0, 708 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 709 /*highaddr*/BUS_SPACE_MAXADDR, 710 /*filter*/NULL, /*filterarg*/NULL, 711 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 712 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 713 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 714 715 if (error != 0) { 716 printf("ahc_pci_attach: Could not allocate DMA tag " 717 "- error %d\n", error); 718 return (ENOMEM); 719 } 720 721 /* On all PCI adapters, we allow SCB paging */ 722 probe_config.flags |= AHC_PAGESCBS; 723 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 724 &probe_config, shared_scb_data)) == NULL) 725 return (ENOMEM); 726 727 /* Store our PCI bus information for use in our PCI error handler */ 728 ahc->device = dev; 729 730 /* Remeber how the card was setup in case there is no SEEPROM */ 731 pause_sequencer(ahc); 732 if ((ahc->features & AHC_ULTRA2) != 0) 733 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 734 else 735 our_id = ahc_inb(ahc, SCSIID) & OID; 736 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 737 scsiseq = ahc_inb(ahc, SCSISEQ); 738 739 if (ahc_reset(ahc) != 0) { 740 /* Failed */ 741 ahc_free(ahc); 742 return (ENXIO); 743 } 744 745 if ((ahc->features & AHC_DT) != 0) { 746 u_int sfunct; 747 748 /* Perform ALT-Mode Setup */ 749 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 750 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 751 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 752 /* Send CRC info in target mode every 4K */ 753 ahc_outb(ahc, TARGCRCCNT, 0); 754 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 755 ahc_outb(ahc, SFUNCT, sfunct); 756 757 /* Normal mode setup */ 758 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 759 |TARGCRCENDEN|TARGCRCCNTEN); 760 } 761 zero = 0; 762 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 763 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 764 if (ahc->irq == NULL) { 765 ahc_free(ahc); 766 return (ENOMEM); 767 } 768 769 ahc->irq_res_type = SYS_RES_IRQ; 770 771 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 772 dscommand0 |= MPARCKEN; 773 if ((ahc->features & AHC_ULTRA2) != 0) { 774 775 /* 776 * DPARCKEN doesn't work correctly on 777 * some MBs so don't use it. 778 */ 779 dscommand0 &= ~DPARCKEN; 780 dscommand0 |= CACHETHEN|USCBSIZE32; 781 } 782 783 ahc_outb(ahc, DSCOMMAND0, dscommand0); 784 785 /* See if we have a SEEPROM and perform auto-term */ 786 check_extport(ahc, &sxfrctl1); 787 788 /* 789 * Take the LED out of diagnostic mode 790 */ 791 sblkctl = ahc_inb(ahc, SBLKCTL); 792 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 793 794 /* 795 * I don't know where this is set in the SEEPROM or by the 796 * BIOS, so we default to 100% on Ultra or slower controllers 797 * and 75% on ULTRA2 controllers. 798 */ 799 if ((ahc->features & AHC_ULTRA2) != 0) { 800 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 801 } else { 802 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 803 } 804 805 if (ahc->flags & AHC_USEDEFAULTS) { 806 /* 807 * PCI Adapter default setup 808 * Should only be used if the adapter does not have 809 * an SEEPROM. 810 */ 811 /* See if someone else set us up already */ 812 if (scsiseq != 0) { 813 printf("%s: Using left over BIOS settings\n", 814 ahc_name(ahc)); 815 ahc->flags &= ~AHC_USEDEFAULTS; 816 } else { 817 /* 818 * Assume only one connector and always turn 819 * on termination. 820 */ 821 our_id = 0x07; 822 sxfrctl1 = STPWEN; 823 } 824 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 825 826 ahc->our_id = our_id; 827 } 828 829 /* 830 * Take a look to see if we have external SRAM. 831 * We currently do not attempt to use SRAM that is 832 * shared among multiple controllers. 833 */ 834 ahc_probe_ext_scbram(ahc); 835 836 printf("%s: %s ", ahc_name(ahc), 837 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 838 839 /* 840 * Record our termination setting for the 841 * generic initialization routine. 842 */ 843 if ((sxfrctl1 & STPWEN) != 0) 844 ahc->flags |= AHC_TERM_ENB_A; 845 846 if (ahc_init(ahc)) { 847 ahc_free(ahc); 848 return (ENOMEM); 849 } 850 851 /* XXX Crude hack - fix sometime */ 852 if (ahc->flags & AHC_SHARED_SRAM) { 853 /* Only set this once we've successfully probed */ 854 if (shared_scb_data == NULL) 855 first_398X = ahc; 856 } 857 858 ahc_attach(ahc); 859 return (0); 860} 861 862/* 863 * Test for the presense of external sram in an 864 * "unshared" configuration. 865 */ 866static int 867ahc_ext_scbram_present(struct ahc_softc *ahc) 868{ 869 int ramps; 870 int single_user; 871 uint32_t devconfig; 872 873 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 874 single_user = (devconfig & MPORTMODE) != 0; 875 876 if ((ahc->features & AHC_ULTRA2) != 0) 877 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 878 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 879 ramps = (devconfig & RAMPSM) != 0; 880 else 881 ramps = 0; 882 883 if (ramps && single_user) 884 return (1); 885 return (0); 886} 887 888/* 889 * Enable external scbram. 890 */ 891static void 892ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 893 int fast, int large) 894{ 895 uint32_t devconfig; 896 897 if (ahc->features & AHC_MULTI_FUNC) { 898 /* 899 * Set the SCB Base addr (highest address bit) 900 * depending on which channel we are. 901 */ 902 ahc_outb(ahc, SCBBADDR, pci_get_function(ahc->device)); 903 } 904 905 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 906 if ((ahc->features & AHC_ULTRA2) != 0) { 907 u_int dscommand0; 908 909 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 910 if (enable) 911 dscommand0 &= ~INTSCBRAMSEL; 912 else 913 dscommand0 |= INTSCBRAMSEL; 914 if (large) 915 dscommand0 |= USCBSIZE32; 916 else 917 dscommand0 &= ~USCBSIZE32; 918 ahc_outb(ahc, DSCOMMAND0, dscommand0); 919 } else { 920 if (fast) 921 devconfig &= ~EXTSCBTIME; 922 else 923 devconfig |= EXTSCBTIME; 924 if (enable) 925 devconfig &= ~SCBRAMSEL; 926 else 927 devconfig |= SCBRAMSEL; 928 if (large) 929 devconfig &= ~SCBSIZE32; 930 else 931 devconfig |= SCBSIZE32; 932 } 933 if (pcheck) 934 devconfig |= EXTSCBPEN; 935 else 936 devconfig &= ~EXTSCBPEN; 937 938 pci_write_config(ahc->device, DEVCONFIG, devconfig, /*bytes*/4); 939} 940 941/* 942 * Take a look to see if we have external SRAM. 943 * We currently do not attempt to use SRAM that is 944 * shared among multiple controllers. 945 */ 946static void 947ahc_probe_ext_scbram(struct ahc_softc *ahc) 948{ 949 int num_scbs; 950 int test_num_scbs; 951 int enable; 952 int pcheck; 953 int fast; 954 int large; 955 956 enable = FALSE; 957 pcheck = FALSE; 958 fast = FALSE; 959 large = FALSE; 960 num_scbs = 0; 961 962 if (ahc_ext_scbram_present(ahc) == 0) 963 return; 964 965 /* 966 * Probe for the best parameters to use. 967 */ 968 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 969 num_scbs = ahc_probe_scbs(ahc); 970 if (num_scbs == 0) { 971 /* The SRAM wasn't really present. */ 972 goto done; 973 } 974 enable = TRUE; 975 976 /* 977 * Clear any outstanding parity error 978 * and ensure that parity error reporting 979 * is enabled. 980 */ 981 ahc_outb(ahc, SEQCTL, 0); 982 ahc_outb(ahc, CLRINT, CLRPARERR); 983 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 984 985 /* Now see if we can do parity */ 986 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 987 num_scbs = ahc_probe_scbs(ahc); 988 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 989 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 990 pcheck = TRUE; 991 992 /* Clear any resulting parity error */ 993 ahc_outb(ahc, CLRINT, CLRPARERR); 994 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 995 996 /* Now see if we can do fast timing */ 997 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 998 test_num_scbs = ahc_probe_scbs(ahc); 999 if (test_num_scbs == num_scbs 1000 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1001 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1002 fast = TRUE; 1003 1004 /* 1005 * See if we can use large SCBs and still maintain 1006 * the same overall count of SCBs. 1007 */ 1008 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1009 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1010 test_num_scbs = ahc_probe_scbs(ahc); 1011 if (test_num_scbs >= num_scbs) { 1012 large = TRUE; 1013 num_scbs = test_num_scbs; 1014 } 1015 if (num_scbs >= 64) 1016 /* 1017 * We have enough space to move the "busy targets 1018 * table" into SCB space and make it qualify all 1019 * the way to the lun level. 1020 */ 1021 ahc->flags |= AHC_SCB_BTT; 1022 } 1023done: 1024 /* 1025 * Disable parity error reporting until we 1026 * can load instruction ram. 1027 */ 1028 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1029 /* Clear any latched parity error */ 1030 ahc_outb(ahc, CLRINT, CLRPARERR); 1031 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1032 if (bootverbose && enable) { 1033 printf("%s: External SRAM, %s access%s\n", 1034 ahc_name(ahc), fast ? "fast" : "slow", 1035 pcheck ? ", parity checking enabled" : ""); 1036 1037 } 1038 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1039} 1040 1041static int 1042verify_cksum(struct seeprom_config *sc) 1043{ 1044 int i; 1045 int maxaddr; 1046 uint32_t checksum; 1047 uint16_t *scarray; 1048 1049 maxaddr = (sizeof(*sc)/2) - 1; 1050 checksum = 0; 1051 scarray = (uint16_t *)sc; 1052 1053 for (i = 0; i < maxaddr; i++) 1054 checksum = checksum + scarray[i]; 1055 if (checksum == 0 1056 || (checksum & 0xFFFF) != sc->checksum) { 1057 return (0); 1058 } else { 1059 return(1); 1060 } 1061} 1062 1063/* 1064 * Check the external port logic for a serial eeprom 1065 * and termination/cable detection contrls. 1066 */ 1067static void 1068check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1069{ 1070 struct seeprom_descriptor sd; 1071 struct seeprom_config sc; 1072 u_int scsi_conf; 1073 u_int adapter_control; 1074 int have_seeprom; 1075 int have_autoterm; 1076 1077 sd.sd_tag = ahc->tag; 1078 sd.sd_bsh = ahc->bsh; 1079 sd.sd_control_offset = SEECTL; 1080 sd.sd_status_offset = SEECTL; 1081 sd.sd_dataout_offset = SEECTL; 1082 1083 /* 1084 * For some multi-channel devices, the c46 is simply too 1085 * small to work. For the other controller types, we can 1086 * get our information from either SEEPROM type. Set the 1087 * type to start our probe with accordingly. 1088 */ 1089 if (ahc->flags & AHC_LARGE_SEEPROM) 1090 sd.sd_chip = C56_66; 1091 else 1092 sd.sd_chip = C46; 1093 1094 sd.sd_MS = SEEMS; 1095 sd.sd_RDY = SEERDY; 1096 sd.sd_CS = SEECS; 1097 sd.sd_CK = SEECK; 1098 sd.sd_DO = SEEDO; 1099 sd.sd_DI = SEEDI; 1100 1101 have_seeprom = acquire_seeprom(ahc, &sd); 1102 if (have_seeprom) { 1103 1104 if (bootverbose) 1105 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1106 1107 for (;;) { 1108 bus_size_t start_addr; 1109 1110 start_addr = 32 * (ahc->channel - 'A'); 1111 1112 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 1113 start_addr, sizeof(sc)/2); 1114 1115 if (have_seeprom) 1116 have_seeprom = verify_cksum(&sc); 1117 1118 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1119 if (bootverbose) { 1120 if (have_seeprom == 0) 1121 printf ("checksum error\n"); 1122 else 1123 printf ("done.\n"); 1124 } 1125 break; 1126 } 1127 sd.sd_chip = C56_66; 1128 } 1129 } 1130 1131 if (!have_seeprom) { 1132 /* 1133 * Pull scratch ram settings and treat them as 1134 * if they are the contents of an seeprom if 1135 * the 'ADPT' signature is found in SCB2. 1136 */ 1137 ahc_outb(ahc, SCBPTR, 2); 1138 if (ahc_inb(ahc, SCB_CONTROL) == 'A' 1139 && ahc_inb(ahc, SCB_CONTROL + 1) == 'D' 1140 && ahc_inb(ahc, SCB_CONTROL + 2) == 'P' 1141 && ahc_inb(ahc, SCB_CONTROL + 3) == 'T') { 1142 uint8_t *sc_bytes; 1143 int i; 1144 1145 printf("Got Here!\n"); 1146 sc_bytes = (uint8_t *)≻ 1147 for (i = 0; i < 64; i++) 1148 sc_bytes[i] = ahc_inb(ahc, TARG_SCSIRATE + i); 1149 /* Byte 0x1c is stored in byte 4 of SCB2 */ 1150 sc_bytes[0x1c] = ahc_inb(ahc, SCB_CONTROL + 4); 1151 have_seeprom = verify_cksum(&sc); 1152 if (have_seeprom) 1153 printf("And it even worked!\n"); 1154 } 1155 } 1156 1157 if (!have_seeprom) { 1158 if (bootverbose) 1159 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1160 ahc->flags |= AHC_USEDEFAULTS; 1161 } else { 1162 /* 1163 * Put the data we've collected down into SRAM 1164 * where ahc_init will find it. 1165 */ 1166 int i; 1167 int max_targ = sc.max_targets & CFMAXTARG; 1168 uint16_t discenable; 1169 uint16_t ultraenb; 1170 1171 discenable = 0; 1172 ultraenb = 0; 1173 if ((sc.adapter_control & CFULTRAEN) != 0) { 1174 /* 1175 * Determine if this adapter has a "newstyle" 1176 * SEEPROM format. 1177 */ 1178 for (i = 0; i < max_targ; i++) { 1179 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1180 ahc->flags |= AHC_NEWEEPROM_FMT; 1181 break; 1182 } 1183 } 1184 } 1185 1186 for (i = 0; i < max_targ; i++) { 1187 u_int scsirate; 1188 uint16_t target_mask; 1189 1190 target_mask = 0x01 << i; 1191 if (sc.device_flags[i] & CFDISC) 1192 discenable |= target_mask; 1193 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1194 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1195 ultraenb |= target_mask; 1196 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1197 ultraenb |= target_mask; 1198 } 1199 if ((sc.device_flags[i] & CFXFER) == 0x04 1200 && (ultraenb & target_mask) != 0) { 1201 /* Treat 10MHz as a non-ultra speed */ 1202 sc.device_flags[i] &= ~CFXFER; 1203 ultraenb &= ~target_mask; 1204 } 1205 if ((ahc->features & AHC_ULTRA2) != 0) { 1206 u_int offset; 1207 1208 if (sc.device_flags[i] & CFSYNCH) 1209 offset = MAX_OFFSET_ULTRA2; 1210 else 1211 offset = 0; 1212 ahc_outb(ahc, TARG_OFFSET + i, offset); 1213 1214 /* 1215 * The ultra enable bits contain the 1216 * high bit of the ultra2 sync rate 1217 * field. 1218 */ 1219 scsirate = (sc.device_flags[i] & CFXFER) 1220 | ((ultraenb & target_mask) 1221 ? 0x8 : 0x0); 1222 if (sc.device_flags[i] & CFWIDEB) 1223 scsirate |= WIDEXFER; 1224 } else { 1225 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1226 if (sc.device_flags[i] & CFSYNCH) 1227 scsirate |= SOFS; 1228 if (sc.device_flags[i] & CFWIDEB) 1229 scsirate |= WIDEXFER; 1230 } 1231 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1232 } 1233 ahc->our_id = sc.brtime_id & CFSCSIID; 1234 1235 scsi_conf = (ahc->our_id & 0x7); 1236 if (sc.adapter_control & CFSPARITY) 1237 scsi_conf |= ENSPCHK; 1238 if (sc.adapter_control & CFRESETB) 1239 scsi_conf |= RESET_SCSI; 1240 1241 if (sc.bios_control & CFEXTEND) 1242 ahc->flags |= AHC_EXTENDED_TRANS_A; 1243 if (ahc->features & AHC_ULTRA 1244 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1245 /* Should we enable Ultra mode? */ 1246 if (!(sc.adapter_control & CFULTRAEN)) 1247 /* Treat us as a non-ultra card */ 1248 ultraenb = 0; 1249 } 1250 1251 if (sc.signature == CFSIGNATURE) { 1252 uint32_t devconfig; 1253 1254 /* Honor the STPWLEVEL settings */ 1255 devconfig = pci_read_config(ahc->device, DEVCONFIG, 1256 /*bytes*/4); 1257 devconfig &= ~STPWLEVEL; 1258 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1259 devconfig |= STPWLEVEL; 1260 pci_write_config(ahc->device, DEVCONFIG, 1261 devconfig, /*bytes*/4); 1262 } 1263 /* Set SCSICONF info */ 1264 ahc_outb(ahc, SCSICONF, scsi_conf); 1265 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1266 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1267 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1268 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1269 } 1270 1271 /* 1272 * Cards that have the external logic necessary to talk to 1273 * a SEEPROM, are almost certain to have the remaining logic 1274 * necessary for auto-termination control. This assumption 1275 * hasn't failed yet... 1276 */ 1277 have_autoterm = have_seeprom; 1278 if (have_seeprom) 1279 adapter_control = sc.adapter_control; 1280 else 1281 adapter_control = CFAUTOTERM; 1282 1283 /* 1284 * Some low-cost chips have SEEPROM and auto-term control built 1285 * in, instead of using a GAL. They can tell us directly 1286 * if the termination logic is enabled. 1287 */ 1288 if ((ahc->features & AHC_SPIOCAP) != 0) { 1289 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1290 have_autoterm = TRUE; 1291 else 1292 have_autoterm = FALSE; 1293 } 1294 1295 if (have_autoterm) 1296 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1297 1298 release_seeprom(&sd); 1299} 1300 1301static void 1302configure_termination(struct ahc_softc *ahc, 1303 struct seeprom_descriptor *sd, 1304 u_int adapter_control, 1305 u_int *sxfrctl1) 1306{ 1307 uint8_t brddat; 1308 1309 brddat = 0; 1310 1311 /* 1312 * Update the settings in sxfrctl1 to match the 1313 * termination settings 1314 */ 1315 *sxfrctl1 = 0; 1316 1317 /* 1318 * SEECS must be on for the GALS to latch 1319 * the data properly. Be sure to leave MS 1320 * on or we will release the seeprom. 1321 */ 1322 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1323 if ((adapter_control & CFAUTOTERM) != 0 1324 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1325 int internal50_present; 1326 int internal68_present; 1327 int externalcable_present; 1328 int eeprom_present; 1329 int enableSEC_low; 1330 int enableSEC_high; 1331 int enablePRI_low; 1332 int enablePRI_high; 1333 1334 enableSEC_low = 0; 1335 enableSEC_high = 0; 1336 enablePRI_low = 0; 1337 enablePRI_high = 0; 1338 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1339 ahc_new_term_detect(ahc, &enableSEC_low, 1340 &enableSEC_high, 1341 &enablePRI_low, 1342 &enablePRI_high, 1343 &eeprom_present); 1344 if ((adapter_control & CFSEAUTOTERM) == 0) { 1345 if (bootverbose) 1346 printf("%s: Manual SE Termination\n", 1347 ahc_name(ahc)); 1348 enableSEC_low = (adapter_control & CFSELOWTERM); 1349 enableSEC_high = 1350 (adapter_control & CFSEHIGHTERM); 1351 } 1352 if ((adapter_control & CFAUTOTERM) == 0) { 1353 if (bootverbose) 1354 printf("%s: Manual LVD Termination\n", 1355 ahc_name(ahc)); 1356 enablePRI_low = (adapter_control & CFSTERM); 1357 enablePRI_high = (adapter_control & CFWSTERM); 1358 } 1359 /* Make the table calculations below happy */ 1360 internal50_present = 0; 1361 internal68_present = 1; 1362 externalcable_present = 1; 1363 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1364 aic785X_cable_detect(ahc, &internal50_present, 1365 &externalcable_present, 1366 &eeprom_present); 1367 } else { 1368 aic787X_cable_detect(ahc, &internal50_present, 1369 &internal68_present, 1370 &externalcable_present, 1371 &eeprom_present); 1372 } 1373 1374 if ((ahc->features & AHC_WIDE) == 0) 1375 internal68_present = 0; 1376 1377 if (bootverbose) { 1378 if ((ahc->features & AHC_ULTRA2) == 0) { 1379 printf("%s: internal 50 cable %s present, " 1380 "internal 68 cable %s present\n", 1381 ahc_name(ahc), 1382 internal50_present ? "is":"not", 1383 internal68_present ? "is":"not"); 1384 1385 printf("%s: external cable %s present\n", 1386 ahc_name(ahc), 1387 externalcable_present ? "is":"not"); 1388 } 1389 printf("%s: BIOS eeprom %s present\n", 1390 ahc_name(ahc), eeprom_present ? "is" : "not"); 1391 } 1392 1393 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1394 /* 1395 * The 50 pin connector is a separate bus, 1396 * so force it to always be terminated. 1397 * In the future, perform current sensing 1398 * to determine if we are in the middle of 1399 * a properly terminated bus. 1400 */ 1401 internal50_present = 0; 1402 } 1403 1404 /* 1405 * Now set the termination based on what 1406 * we found. 1407 * Flash Enable = BRDDAT7 1408 * Secondary High Term Enable = BRDDAT6 1409 * Secondary Low Term Enable = BRDDAT5 (7890) 1410 * Primary High Term Enable = BRDDAT4 (7890) 1411 */ 1412 if ((ahc->features & AHC_ULTRA2) == 0 1413 && (internal50_present != 0) 1414 && (internal68_present != 0) 1415 && (externalcable_present != 0)) { 1416 printf("%s: Illegal cable configuration!!. " 1417 "Only two connectors on the " 1418 "adapter may be used at a " 1419 "time!\n", ahc_name(ahc)); 1420 } 1421 1422 if ((ahc->features & AHC_WIDE) != 0 1423 && ((externalcable_present == 0) 1424 || (internal68_present == 0) 1425 || (enableSEC_high != 0))) { 1426 brddat |= BRDDAT6; 1427 if (bootverbose) { 1428 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1429 printf("%s: 68 pin termination " 1430 "Enabled\n", ahc_name(ahc)); 1431 else 1432 printf("%s: %sHigh byte termination " 1433 "Enabled\n", ahc_name(ahc), 1434 enableSEC_high ? "Secondary " 1435 : ""); 1436 } 1437 } 1438 1439 if (((internal50_present ? 1 : 0) 1440 + (internal68_present ? 1 : 0) 1441 + (externalcable_present ? 1 : 0)) <= 1 1442 || (enableSEC_low != 0)) { 1443 if ((ahc->features & AHC_ULTRA2) != 0) 1444 brddat |= BRDDAT5; 1445 else 1446 *sxfrctl1 |= STPWEN; 1447 if (bootverbose) { 1448 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1449 printf("%s: 50 pin termination " 1450 "Enabled\n", ahc_name(ahc)); 1451 else 1452 printf("%s: %sLow byte termination " 1453 "Enabled\n", ahc_name(ahc), 1454 enableSEC_low ? "Secondary " 1455 : ""); 1456 } 1457 } 1458 1459 if (enablePRI_low != 0) { 1460 *sxfrctl1 |= STPWEN; 1461 if (bootverbose) 1462 printf("%s: Primary Low Byte termination " 1463 "Enabled\n", ahc_name(ahc)); 1464 } 1465 1466 /* 1467 * Setup STPWEN before setting up the rest of 1468 * the termination per the tech note on the U160 cards. 1469 */ 1470 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1471 1472 if (enablePRI_high != 0) { 1473 brddat |= BRDDAT4; 1474 if (bootverbose) 1475 printf("%s: Primary High Byte " 1476 "termination Enabled\n", 1477 ahc_name(ahc)); 1478 } 1479 1480 write_brdctl(ahc, brddat); 1481 1482 } else { 1483 if ((adapter_control & CFSTERM) != 0) { 1484 *sxfrctl1 |= STPWEN; 1485 1486 if (bootverbose) 1487 printf("%s: %sLow byte termination Enabled\n", 1488 ahc_name(ahc), 1489 (ahc->features & AHC_ULTRA2) ? "Primary " 1490 : ""); 1491 } 1492 1493 if ((adapter_control & CFWSTERM) != 0) { 1494 brddat |= BRDDAT6; 1495 if (bootverbose) 1496 printf("%s: %sHigh byte termination Enabled\n", 1497 ahc_name(ahc), 1498 (ahc->features & AHC_ULTRA2) 1499 ? "Secondary " : ""); 1500 } 1501 1502 /* 1503 * Setup STPWEN before setting up the rest of 1504 * the termination per the tech note on the U160 cards. 1505 */ 1506 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1507 1508 write_brdctl(ahc, brddat); 1509 } 1510 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1511} 1512 1513static void 1514ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1515 int *enableSEC_high, int *enablePRI_low, 1516 int *enablePRI_high, int *eeprom_present) 1517{ 1518 uint8_t brdctl; 1519 1520 /* 1521 * BRDDAT7 = Eeprom 1522 * BRDDAT6 = Enable Secondary High Byte termination 1523 * BRDDAT5 = Enable Secondary Low Byte termination 1524 * BRDDAT4 = Enable Primary high byte termination 1525 * BRDDAT3 = Enable Primary low byte termination 1526 */ 1527 brdctl = read_brdctl(ahc); 1528 *eeprom_present = brdctl & BRDDAT7; 1529 *enableSEC_high = (brdctl & BRDDAT6); 1530 *enableSEC_low = (brdctl & BRDDAT5); 1531 *enablePRI_high = (brdctl & BRDDAT4); 1532 *enablePRI_low = (brdctl & BRDDAT3); 1533} 1534 1535static void 1536aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1537 int *internal68_present, int *externalcable_present, 1538 int *eeprom_present) 1539{ 1540 uint8_t brdctl; 1541 1542 /* 1543 * First read the status of our cables. 1544 * Set the rom bank to 0 since the 1545 * bank setting serves as a multiplexor 1546 * for the cable detection logic. 1547 * BRDDAT5 controls the bank switch. 1548 */ 1549 write_brdctl(ahc, 0); 1550 1551 /* 1552 * Now read the state of the internal 1553 * connectors. BRDDAT6 is INT50 and 1554 * BRDDAT7 is INT68. 1555 */ 1556 brdctl = read_brdctl(ahc); 1557 *internal50_present = !(brdctl & BRDDAT6); 1558 *internal68_present = !(brdctl & BRDDAT7); 1559 1560 /* 1561 * Set the rom bank to 1 and determine 1562 * the other signals. 1563 */ 1564 write_brdctl(ahc, BRDDAT5); 1565 1566 /* 1567 * Now read the state of the external 1568 * connectors. BRDDAT6 is EXT68 and 1569 * BRDDAT7 is EPROMPS. 1570 */ 1571 brdctl = read_brdctl(ahc); 1572 *externalcable_present = !(brdctl & BRDDAT6); 1573 *eeprom_present = brdctl & BRDDAT7; 1574} 1575 1576static void 1577aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1578 int *externalcable_present, int *eeprom_present) 1579{ 1580 uint8_t brdctl; 1581 1582 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1583 ahc_outb(ahc, BRDCTL, 0); 1584 brdctl = ahc_inb(ahc, BRDCTL); 1585 *internal50_present = !(brdctl & BRDDAT5); 1586 *externalcable_present = !(brdctl & BRDDAT6); 1587 1588 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1589} 1590 1591static int 1592acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1593{ 1594 int wait; 1595 1596 if ((ahc->features & AHC_SPIOCAP) != 0 1597 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1598 return (0); 1599 1600 /* 1601 * Request access of the memory port. When access is 1602 * granted, SEERDY will go high. We use a 1 second 1603 * timeout which should be near 1 second more than 1604 * is needed. Reason: after the chip reset, there 1605 * should be no contention. 1606 */ 1607 SEEPROM_OUTB(sd, sd->sd_MS); 1608 wait = 1000; /* 1 second timeout in msec */ 1609 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1610 DELAY(1000); /* delay 1 msec */ 1611 } 1612 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1613 SEEPROM_OUTB(sd, 0); 1614 return (0); 1615 } 1616 return(1); 1617} 1618 1619static void 1620release_seeprom(struct seeprom_descriptor *sd) 1621{ 1622 /* Release access to the memory port and the serial EEPROM. */ 1623 SEEPROM_OUTB(sd, 0); 1624} 1625 1626static void 1627write_brdctl(struct ahc_softc *ahc, uint8_t value) 1628{ 1629 uint8_t brdctl; 1630 1631 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1632 brdctl = BRDSTB; 1633 if (ahc->channel == 'B') 1634 brdctl |= BRDCS; 1635 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1636 brdctl = 0; 1637 } else { 1638 brdctl = BRDSTB|BRDCS; 1639 } 1640 ahc_outb(ahc, BRDCTL, brdctl); 1641 DELAY(20); 1642 brdctl |= value; 1643 ahc_outb(ahc, BRDCTL, brdctl); 1644 DELAY(20); 1645 if ((ahc->features & AHC_ULTRA2) != 0) 1646 brdctl |= BRDSTB_ULTRA2; 1647 else 1648 brdctl &= ~BRDSTB; 1649 ahc_outb(ahc, BRDCTL, brdctl); 1650 DELAY(20); 1651 if ((ahc->features & AHC_ULTRA2) != 0) 1652 brdctl = 0; 1653 else 1654 brdctl &= ~BRDCS; 1655 ahc_outb(ahc, BRDCTL, brdctl); 1656} 1657 1658static uint8_t 1659read_brdctl(ahc) 1660 struct ahc_softc *ahc; 1661{ 1662 uint8_t brdctl; 1663 uint8_t value; 1664 1665 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1666 brdctl = BRDRW; 1667 if (ahc->channel == 'B') 1668 brdctl |= BRDCS; 1669 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1670 brdctl = BRDRW_ULTRA2; 1671 } else { 1672 brdctl = BRDRW|BRDCS; 1673 } 1674 ahc_outb(ahc, BRDCTL, brdctl); 1675 DELAY(20); 1676 value = ahc_inb(ahc, BRDCTL); 1677 ahc_outb(ahc, BRDCTL, 0); 1678 return (value); 1679} 1680 1681#define DPE 0x80 1682#define SSE 0x40 1683#define RMA 0x20 1684#define RTA 0x10 1685#define STA 0x08 1686#define DPR 0x01 1687 1688void 1689ahc_pci_intr(struct ahc_softc *ahc) 1690{ 1691 uint8_t status1; 1692 1693 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1694 1695 if (status1 & DPE) { 1696 printf("%s: Data Parity Error Detected during address " 1697 "or write data phase\n", ahc_name(ahc)); 1698 } 1699 if (status1 & SSE) { 1700 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1701 } 1702 if (status1 & RMA) { 1703 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1704 } 1705 if (status1 & RTA) { 1706 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1707 } 1708 if (status1 & STA) { 1709 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1710 } 1711 if (status1 & DPR) { 1712 printf("%s: Data Parity Error has been reported via PERR#\n", 1713 ahc_name(ahc)); 1714 } 1715 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1716 printf("%s: Latched PCIERR interrupt with " 1717 "no status bits set\n", ahc_name(ahc)); 1718 } 1719 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1720 1721 if (status1 & (DPR|RMA|RTA)) { 1722 ahc_outb(ahc, CLRINT, CLRPARERR); 1723 } 1724} 1725 1726static int 1727ahc_aic7850_setup(device_t dev, struct ahc_probe_config *probe_config) 1728{ 1729 probe_config->channel = 'A'; 1730 probe_config->chip = AHC_AIC7850; 1731 probe_config->features = AHC_AIC7850_FE; 1732 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1733 return (0); 1734} 1735 1736static int 1737ahc_aic7855_setup(device_t dev, struct ahc_probe_config *probe_config) 1738{ 1739 probe_config->channel = 'A'; 1740 probe_config->chip = AHC_AIC7855; 1741 probe_config->features = AHC_AIC7855_FE; 1742 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1743 return (0); 1744} 1745 1746static int 1747ahc_aic7859_setup(device_t dev, struct ahc_probe_config *probe_config) 1748{ 1749 probe_config->channel = 'A'; 1750 probe_config->chip = AHC_AIC7859; 1751 probe_config->features = AHC_AIC7859_FE; 1752 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1753 return (0); 1754} 1755 1756static int 1757ahc_aic7860_setup(device_t dev, struct ahc_probe_config *probe_config) 1758{ 1759 probe_config->channel = 'A'; 1760 probe_config->chip = AHC_AIC7860; 1761 probe_config->features = AHC_AIC7860_FE; 1762 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1763 return (0); 1764} 1765 1766static int 1767ahc_aic7870_setup(device_t dev, struct ahc_probe_config *probe_config) 1768{ 1769 probe_config->channel = 'A'; 1770 probe_config->chip = AHC_AIC7870; 1771 probe_config->features = AHC_AIC7870_FE; 1772 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1773 return (0); 1774} 1775 1776static int 1777ahc_aha394X_setup(device_t dev, struct ahc_probe_config *probe_config) 1778{ 1779 int error; 1780 1781 error = ahc_aic7870_setup(dev, probe_config); 1782 if (error == 0) 1783 error = ahc_aha394XX_setup(dev, probe_config); 1784 return (error); 1785} 1786 1787static int 1788ahc_aha398X_setup(device_t dev, struct ahc_probe_config *probe_config) 1789{ 1790 int error; 1791 1792 error = ahc_aic7870_setup(dev, probe_config); 1793 if (error == 0) 1794 error = ahc_aha398XX_setup(dev, probe_config); 1795 return (error); 1796} 1797 1798static int 1799ahc_aha494X_setup(device_t dev, struct ahc_probe_config *probe_config) 1800{ 1801 int error; 1802 1803 error = ahc_aic7870_setup(dev, probe_config); 1804 if (error == 0) 1805 error = ahc_aha494XX_setup(dev, probe_config); 1806 return (error); 1807} 1808 1809static int 1810ahc_aic7880_setup(device_t dev, struct ahc_probe_config *probe_config) 1811{ 1812 probe_config->channel = 'A'; 1813 probe_config->chip = AHC_AIC7880; 1814 probe_config->features = AHC_AIC7880_FE; 1815 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1816 return (0); 1817} 1818 1819static int 1820ahc_2940Pro_setup(device_t dev, struct ahc_probe_config *probe_config) 1821{ 1822 int error; 1823 1824 probe_config->flags |= AHC_INT50_SPEEDFLEX; 1825 error = ahc_aic7880_setup(dev, probe_config); 1826 return (0); 1827} 1828 1829static int 1830ahc_aha394XU_setup(device_t dev, struct ahc_probe_config *probe_config) 1831{ 1832 int error; 1833 1834 error = ahc_aic7880_setup(dev, probe_config); 1835 if (error == 0) 1836 error = ahc_aha394XX_setup(dev, probe_config); 1837 return (error); 1838} 1839 1840static int 1841ahc_aha398XU_setup(device_t dev, struct ahc_probe_config *probe_config) 1842{ 1843 int error; 1844 1845 error = ahc_aic7880_setup(dev, probe_config); 1846 if (error == 0) 1847 error = ahc_aha398XX_setup(dev, probe_config); 1848 return (error); 1849} 1850 1851static int 1852ahc_aic7890_setup(device_t dev, struct ahc_probe_config *probe_config) 1853{ 1854 probe_config->channel = 'A'; 1855 probe_config->chip = AHC_AIC7890; 1856 probe_config->features = AHC_AIC7890_FE; 1857 probe_config->flags |= AHC_NEWEEPROM_FMT; 1858 if (pci_get_revid(dev) == 0) 1859 probe_config->bugs |= AHC_AUTOFLUSH_BUG; 1860 return (0); 1861} 1862 1863static int 1864ahc_aic7892_setup(device_t dev, struct ahc_probe_config *probe_config) 1865{ 1866 probe_config->channel = 'A'; 1867 probe_config->chip = AHC_AIC7892; 1868 probe_config->features = AHC_AIC7892_FE; 1869 probe_config->flags |= AHC_NEWEEPROM_FMT; 1870 return (0); 1871} 1872 1873static int 1874ahc_aic7895_setup(device_t dev, struct ahc_probe_config *probe_config) 1875{ 1876 uint32_t devconfig; 1877 1878 probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1879 probe_config->chip = AHC_AIC7895; 1880 /* The 'C' revision of the aic7895 has a few additional features */ 1881 if (pci_get_revid(dev) >= 4) 1882 probe_config->features = AHC_AIC7895C_FE; 1883 else 1884 probe_config->features = AHC_AIC7895_FE; 1885 probe_config->bugs |= AHC_TMODE_WIDEODD_BUG; 1886 probe_config->flags |= AHC_NEWEEPROM_FMT; 1887 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1888 devconfig |= SCBSIZE32; 1889 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1890 return (0); 1891} 1892 1893static int 1894ahc_aic7896_setup(device_t dev, struct ahc_probe_config *probe_config) 1895{ 1896 probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1897 probe_config->chip = AHC_AIC7896; 1898 probe_config->features = AHC_AIC7896_FE; 1899 probe_config->flags |= AHC_NEWEEPROM_FMT; 1900 return (0); 1901} 1902 1903static int 1904ahc_aic7899_setup(device_t dev, struct ahc_probe_config *probe_config) 1905{ 1906 probe_config->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1907 probe_config->chip = AHC_AIC7899; 1908 probe_config->features = AHC_AIC7899_FE; 1909 probe_config->flags |= AHC_NEWEEPROM_FMT; 1910 return (0); 1911} 1912 1913static int 1914ahc_raid_setup(device_t dev, struct ahc_probe_config *probe_config) 1915{ 1916 printf("RAID functionality unsupported\n"); 1917 return (ENXIO); 1918} 1919 1920static int 1921ahc_aha394XX_setup(device_t dev, struct ahc_probe_config *probe_config) 1922{ 1923 switch (pci_get_slot(dev)) { 1924 case AHC_394X_SLOT_CHANNEL_A: 1925 probe_config->channel = 'A'; 1926 break; 1927 case AHC_394X_SLOT_CHANNEL_B: 1928 probe_config->channel = 'B'; 1929 break; 1930 default: 1931 printf("adapter at unexpected slot %d\n" 1932 "unable to map to a channel\n", 1933 pci_get_slot(dev)); 1934 probe_config->channel = 'A'; 1935 } 1936 return (0); 1937} 1938 1939static int 1940ahc_aha398XX_setup(device_t dev, struct ahc_probe_config *probe_config) 1941{ 1942 switch (pci_get_slot(dev)) { 1943 case AHC_398X_SLOT_CHANNEL_A: 1944 probe_config->channel = 'A'; 1945 break; 1946 case AHC_398X_SLOT_CHANNEL_B: 1947 probe_config->channel = 'B'; 1948 break; 1949 case AHC_398X_SLOT_CHANNEL_C: 1950 probe_config->channel = 'C'; 1951 break; 1952 default: 1953 printf("adapter at unexpected slot %d\n" 1954 "unable to map to a channel\n", 1955 pci_get_slot(dev)); 1956 probe_config->channel = 'A'; 1957 break; 1958 } 1959 probe_config->flags |= AHC_LARGE_SEEPROM; 1960 return (0); 1961} 1962 1963static int 1964ahc_aha494XX_setup(device_t dev, struct ahc_probe_config *probe_config) 1965{ 1966 switch (pci_get_slot(dev)) { 1967 case AHC_494X_SLOT_CHANNEL_A: 1968 probe_config->channel = 'A'; 1969 break; 1970 case AHC_494X_SLOT_CHANNEL_B: 1971 probe_config->channel = 'B'; 1972 break; 1973 case AHC_494X_SLOT_CHANNEL_C: 1974 probe_config->channel = 'C'; 1975 break; 1976 case AHC_494X_SLOT_CHANNEL_D: 1977 probe_config->channel = 'D'; 1978 break; 1979 default: 1980 printf("adapter at unexpected slot %d\n" 1981 "unable to map to a channel\n", 1982 pci_get_slot(dev)); 1983 probe_config->channel = 'A'; 1984 } 1985 probe_config->flags |= AHC_LARGE_SEEPROM; 1986 return (0); 1987} 1988