ahc_pci.c revision 55699
1/* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD: head/sys/dev/aic7xxx/ahc_pci.c 55699 2000-01-10 01:47:51Z gibbs $ 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/bus.h> 45 46#include <pci/pcireg.h> 47#include <pci/pcivar.h> 48 49#include <machine/bus_memio.h> 50#include <machine/bus_pio.h> 51#include <machine/bus.h> 52#include <machine/resource.h> 53#include <machine/clock.h> 54#include <sys/rman.h> 55 56#include <cam/cam.h> 57#include <cam/cam_ccb.h> 58#include <cam/cam_sim.h> 59#include <cam/cam_xpt_sim.h> 60 61#include <cam/scsi/scsi_all.h> 62 63#include <dev/aic7xxx/aic7xxx.h> 64#include <dev/aic7xxx/93cx6.h> 65 66#include <aic7xxx_reg.h> 67 68#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 69#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 70 71static __inline u_int64_t 72ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 73{ 74 u_int64_t id; 75 76 id = subvendor 77 | (subdevice << 16) 78 | ((u_int64_t)vendor << 32) 79 | ((u_int64_t)device << 48); 80 81 return (id); 82} 83 84#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 85#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 86#define ID_AIC7850 0x5078900400000000ull 87#define ID_AHA_2910_15_20_30C 0x5078900478509004ull 88#define ID_AIC7855 0x5578900400000000ull 89#define ID_AIC7859 0x3860900400000000ull 90#define ID_AHA_2930CU 0x3860900438699004ull 91#define ID_AIC7860 0x6078900400000000ull 92#define ID_AIC7860C 0x6078900478609004ull 93#define ID_AHA_2940AU_0 0x6178900400000000ull 94#define ID_AHA_2940AU_1 0x6178900478619004ull 95#define ID_AHA_2940AU_CN 0x2178900478219004ull 96#define ID_AHA_2930C_VAR 0x6038900438689004ull 97 98#define ID_AIC7870 0x7078900400000000ull 99#define ID_AHA_2940 0x7178900400000000ull 100#define ID_AHA_3940 0x7278900400000000ull 101#define ID_AHA_398X 0x7378900400000000ull 102#define ID_AHA_2944 0x7478900400000000ull 103#define ID_AHA_3944 0x7578900400000000ull 104 105#define ID_AIC7880 0x8078900400000000ull 106#define ID_AIC7880_B 0x8078900478809004ull 107#define ID_AHA_2940U 0x8178900400000000ull 108#define ID_AHA_3940U 0x8278900400000000ull 109#define ID_AHA_2944U 0x8478900400000000ull 110#define ID_AHA_3944U 0x8578900400000000ull 111#define ID_AHA_398XU 0x8378900400000000ull 112#define ID_AHA_4944U 0x8678900400000000ull 113#define ID_AHA_2940UB 0x8178900478819004ull 114#define ID_AHA_2930U 0x8878900478889004ull 115#define ID_AHA_2940U_PRO 0x8778900478879004ull 116#define ID_AHA_2940U_CN 0x0078900478009004ull 117 118#define ID_AIC7895 0x7895900478959004ull 119#define ID_AIC7895_RAID_PORT 0x7893900478939004ull 120#define ID_AHA_2940U_DUAL 0x7895900478919004ull 121#define ID_AHA_3940AU 0x7895900478929004ull 122#define ID_AHA_3944AU 0x7895900478949004ull 123 124#define ID_AIC7890 0x001F9005000F9005ull 125#define ID_AHA_2930U2 0x0011900501819005ull 126#define ID_AHA_2940U2B 0x00109005A1009005ull 127#define ID_AHA_2940U2_OEM 0x0010900521809005ull 128#define ID_AHA_2940U2 0x00109005A1809005ull 129#define ID_AHA_2950U2B 0x00109005E1009005ull 130 131#define ID_AIC7892 0x008F9005FFFF9005ull 132#define ID_AHA_29160 0x00809005E2A09005ull 133#define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 134#define ID_AHA_29160N 0x0080900562A09005ull 135#define ID_AHA_29160B 0x00809005E2209005ull 136#define ID_AHA_19160B 0x0081900562A19005ull 137 138#define ID_AIC7896 0x005F9005FFFF9005ull 139#define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140#define ID_AHA_3950U2B_1 0x00509005F5009005ull 141#define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142#define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144#define ID_AIC7899 0x00CF9005FFFF9005ull 145#define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 146#define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 147 148#define ID_AIC7810 0x1078900400000000ull 149#define ID_AIC7815 0x1578900400000000ull 150 151typedef int (ahc_device_setup_t)(device_t, char *, ahc_chip *, 152 ahc_feature *, ahc_flag *); 153 154static ahc_device_setup_t ahc_aic7850_setup; 155static ahc_device_setup_t ahc_aic7855_setup; 156static ahc_device_setup_t ahc_aic7859_setup; 157static ahc_device_setup_t ahc_aic7860_setup; 158static ahc_device_setup_t ahc_aic7870_setup; 159static ahc_device_setup_t ahc_aha394X_setup; 160static ahc_device_setup_t ahc_aha398X_setup; 161static ahc_device_setup_t ahc_aic7880_setup; 162static ahc_device_setup_t ahc_2940Pro_setup; 163static ahc_device_setup_t ahc_aha394XU_setup; 164static ahc_device_setup_t ahc_aha398XU_setup; 165static ahc_device_setup_t ahc_aic7890_setup; 166static ahc_device_setup_t ahc_aic7892_setup; 167static ahc_device_setup_t ahc_aic7895_setup; 168static ahc_device_setup_t ahc_aic7896_setup; 169static ahc_device_setup_t ahc_aic7899_setup; 170static ahc_device_setup_t ahc_raid_setup; 171static ahc_device_setup_t ahc_aha394XX_setup; 172static ahc_device_setup_t ahc_aha398XX_setup; 173 174struct ahc_pci_identity { 175 u_int64_t full_id; 176 u_int64_t id_mask; 177 char *name; 178 ahc_device_setup_t *setup; 179}; 180 181struct ahc_pci_identity ahc_pci_ident_table [] = 182{ 183 /* aic7850 based controllers */ 184 { 185 ID_AHA_2910_15_20_30C, 186 ID_ALL_MASK, 187 "Adaptec 2910/15/20/30C SCSI adapter", 188 ahc_aic7850_setup 189 }, 190 /* aic7859 based controllers */ 191 { 192 ID_AHA_2930CU, 193 ID_ALL_MASK, 194 "Adaptec 2930CU SCSI adapter", 195 ahc_aic7859_setup 196 }, 197 /* aic7860 based controllers */ 198 { 199 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 200 ID_DEV_VENDOR_MASK, 201 "Adaptec 2940A Ultra SCSI adapter", 202 ahc_aic7860_setup 203 }, 204 { 205 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 206 ID_DEV_VENDOR_MASK, 207 "Adaptec 2940A/CN Ultra SCSI adapter", 208 ahc_aic7860_setup 209 }, 210 { 211 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 212 ID_DEV_VENDOR_MASK, 213 "Adaptec 2930C SCSI adapter (VAR)", 214 ahc_aic7860_setup 215 }, 216 /* aic7870 based controllers */ 217 { 218 ID_AHA_2940, 219 ID_ALL_MASK, 220 "Adaptec 2940 SCSI adapter", 221 ahc_aic7870_setup 222 }, 223 { 224 ID_AHA_3940, 225 ID_ALL_MASK, 226 "Adaptec 3940 SCSI adapter", 227 ahc_aha394X_setup 228 }, 229 { 230 ID_AHA_398X, 231 ID_ALL_MASK, 232 "Adaptec 398X SCSI RAID adapter", 233 ahc_aha398X_setup 234 }, 235 { 236 ID_AHA_2944, 237 ID_ALL_MASK, 238 "Adaptec 2944 SCSI adapter", 239 ahc_aic7870_setup 240 }, 241 { 242 ID_AHA_3944, 243 ID_ALL_MASK, 244 "Adaptec 3944 SCSI adapter", 245 ahc_aha394X_setup 246 }, 247 /* aic7880 based controllers */ 248 { 249 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 250 ID_DEV_VENDOR_MASK, 251 "Adaptec 2940 Ultra SCSI adapter", 252 ahc_aic7880_setup 253 }, 254 { 255 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 256 ID_DEV_VENDOR_MASK, 257 "Adaptec 3940 Ultra SCSI adapter", 258 ahc_aha394XU_setup 259 }, 260 { 261 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 2944 Ultra SCSI adapter", 264 ahc_aic7880_setup 265 }, 266 { 267 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 3944 Ultra SCSI adapter", 270 ahc_aha394XU_setup 271 }, 272 { 273 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 398X Ultra SCSI RAID adapter", 276 ahc_aha398XU_setup 277 }, 278 { 279 /* 280 * XXX Don't know the slot numbers 281 * so we can't identify channels 282 */ 283 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 284 ID_DEV_VENDOR_MASK, 285 "Adaptec 4944 Ultra SCSI adapter", 286 ahc_aic7880_setup 287 }, 288 { 289 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 290 ID_DEV_VENDOR_MASK, 291 "Adaptec 2930 Ultra SCSI adapter", 292 ahc_aic7880_setup 293 }, 294 { 295 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 296 ID_DEV_VENDOR_MASK, 297 "Adaptec 2940 Pro Ultra SCSI adapter", 298 ahc_2940Pro_setup 299 }, 300 { 301 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 302 ID_DEV_VENDOR_MASK, 303 "Adaptec 2940/CN Ultra SCSI adapter", 304 ahc_aic7880_setup 305 }, 306 /* aic7890 based controllers */ 307 { 308 ID_AHA_2930U2, 309 ID_ALL_MASK, 310 "Adaptec 2930 Ultra2 SCSI adapter", 311 ahc_aic7890_setup 312 }, 313 { 314 ID_AHA_2940U2B, 315 ID_ALL_MASK, 316 "Adaptec 2940B Ultra2 SCSI adapter", 317 ahc_aic7890_setup 318 }, 319 { 320 ID_AHA_2940U2_OEM, 321 ID_ALL_MASK, 322 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 323 ahc_aic7890_setup 324 }, 325 { 326 ID_AHA_2940U2, 327 ID_ALL_MASK, 328 "Adaptec 2940 Ultra2 SCSI adapter", 329 ahc_aic7890_setup 330 }, 331 { 332 ID_AHA_2950U2B, 333 ID_ALL_MASK, 334 "Adaptec 2950 Ultra2 SCSI adapter", 335 ahc_aic7890_setup 336 }, 337 /* aic7892 based controllers */ 338 { 339 ID_AHA_29160, 340 ID_ALL_MASK, 341 "Adaptec 29160 Ultra160 SCSI adapter", 342 ahc_aic7892_setup 343 }, 344 { 345 ID_AHA_29160_CPQ, 346 ID_ALL_MASK, 347 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 348 ahc_aic7892_setup 349 }, 350 { 351 ID_AHA_29160N, 352 ID_ALL_MASK, 353 "Adaptec 29160N Ultra160 SCSI adapter", 354 ahc_aic7892_setup 355 }, 356 { 357 ID_AHA_29160B, 358 ID_ALL_MASK, 359 "Adaptec 29160B Ultra160 SCSI adapter", 360 ahc_aic7892_setup 361 }, 362 { 363 ID_AHA_19160B, 364 ID_ALL_MASK, 365 "Adaptec 19160B Ultra160 SCSI adapter", 366 ahc_aic7892_setup 367 }, 368 /* aic7895 based controllers */ 369 { 370 ID_AHA_2940U_DUAL, 371 ID_ALL_MASK, 372 "Adaptec 2940/DUAL Ultra SCSI adapter", 373 ahc_aic7895_setup 374 }, 375 { 376 ID_AHA_3940AU, 377 ID_ALL_MASK, 378 "Adaptec 3940A Ultra SCSI adapter", 379 ahc_aic7895_setup 380 }, 381 { 382 ID_AHA_3944AU, 383 ID_ALL_MASK, 384 "Adaptec 3944A Ultra SCSI adapter", 385 ahc_aic7895_setup 386 }, 387 /* aic7896/97 based controllers */ 388 { 389 ID_AHA_3950U2B_0, 390 ID_ALL_MASK, 391 "Adaptec 3950B Ultra2 SCSI adapter", 392 ahc_aic7896_setup 393 }, 394 { 395 ID_AHA_3950U2B_1, 396 ID_ALL_MASK, 397 "Adaptec 3950B Ultra2 SCSI adapter", 398 ahc_aic7896_setup 399 }, 400 { 401 ID_AHA_3950U2D_0, 402 ID_ALL_MASK, 403 "Adaptec 3950D Ultra2 SCSI adapter", 404 ahc_aic7896_setup 405 }, 406 { 407 ID_AHA_3950U2D_1, 408 ID_ALL_MASK, 409 "Adaptec 3950D Ultra2 SCSI adapter", 410 ahc_aic7896_setup 411 }, 412 /* aic7899 based controllers */ 413 { 414 ID_AHA_3960D, 415 ID_ALL_MASK, 416 "Adaptec 3960D Ultra160 SCSI adapter", 417 ahc_aic7899_setup 418 }, 419 { 420 ID_AHA_3960D_CPQ, 421 ID_ALL_MASK, 422 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 423 ahc_aic7899_setup 424 }, 425 /* Generic chip probes for devices we don't know 'exactly' */ 426 { 427 ID_AIC7850 & ID_DEV_VENDOR_MASK, 428 ID_DEV_VENDOR_MASK, 429 "Adaptec aic7850 SCSI adapter", 430 ahc_aic7850_setup 431 }, 432 { 433 ID_AIC7855 & ID_DEV_VENDOR_MASK, 434 ID_DEV_VENDOR_MASK, 435 "Adaptec aic7855 SCSI adapter", 436 ahc_aic7855_setup 437 }, 438 { 439 ID_AIC7859 & ID_DEV_VENDOR_MASK, 440 ID_DEV_VENDOR_MASK, 441 "Adaptec aic7859 SCSI adapter", 442 ahc_aic7859_setup 443 }, 444 { 445 ID_AIC7860 & ID_DEV_VENDOR_MASK, 446 ID_DEV_VENDOR_MASK, 447 "Adaptec aic7860 SCSI adapter", 448 ahc_aic7860_setup 449 }, 450 { 451 ID_AIC7870 & ID_DEV_VENDOR_MASK, 452 ID_DEV_VENDOR_MASK, 453 "Adaptec aic7870 SCSI adapter", 454 ahc_aic7870_setup 455 }, 456 { 457 ID_AIC7880 & ID_DEV_VENDOR_MASK, 458 ID_DEV_VENDOR_MASK, 459 "Adaptec aic7880 Ultra SCSI adapter", 460 ahc_aic7880_setup 461 }, 462 { 463 ID_AIC7890 & ID_DEV_VENDOR_MASK, 464 ID_DEV_VENDOR_MASK, 465 "Adaptec aic7890/91 Ultra2 SCSI adapter", 466 ahc_aic7890_setup 467 }, 468 { 469 ID_AIC7892 & ID_DEV_VENDOR_MASK, 470 ID_DEV_VENDOR_MASK, 471 "Adaptec aic7892 Ultra160 SCSI adapter", 472 ahc_aic7892_setup 473 }, 474 { 475 ID_AIC7895 & ID_DEV_VENDOR_MASK, 476 ID_DEV_VENDOR_MASK, 477 "Adaptec aic7895 Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 482 ID_DEV_VENDOR_MASK, 483 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AIC7896 & ID_DEV_VENDOR_MASK, 488 ID_DEV_VENDOR_MASK, 489 "Adaptec aic7896/97 Ultra2 SCSI adapter", 490 ahc_aic7896_setup 491 }, 492 { 493 ID_AIC7899 & ID_DEV_VENDOR_MASK, 494 ID_DEV_VENDOR_MASK, 495 "Adaptec aic7899 Ultra160 SCSI adapter", 496 ahc_aic7899_setup 497 }, 498 { 499 ID_AIC7810 & ID_DEV_VENDOR_MASK, 500 ID_DEV_VENDOR_MASK, 501 "Adaptec aic7810 RAID memory controller", 502 ahc_raid_setup 503 }, 504 { 505 ID_AIC7815 & ID_DEV_VENDOR_MASK, 506 ID_DEV_VENDOR_MASK, 507 "Adaptec aic7815 RAID memory controller", 508 ahc_raid_setup 509 } 510}; 511 512static const int ahc_num_pci_devs = 513 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 514 515#define AHC_394X_SLOT_CHANNEL_A 4 516#define AHC_394X_SLOT_CHANNEL_B 5 517 518#define AHC_398X_SLOT_CHANNEL_A 4 519#define AHC_398X_SLOT_CHANNEL_B 8 520#define AHC_398X_SLOT_CHANNEL_C 12 521 522#define DEVCONFIG 0x40 523#define SCBSIZE32 0x00010000ul /* aic789X only */ 524#define MPORTMODE 0x00000400ul /* aic7870 only */ 525#define RAMPSM 0x00000200ul /* aic7870 only */ 526#define VOLSENSE 0x00000100ul 527#define SCBRAMSEL 0x00000080ul 528#define MRDCEN 0x00000040ul 529#define EXTSCBTIME 0x00000020ul /* aic7870 only */ 530#define EXTSCBPEN 0x00000010ul /* aic7870 only */ 531#define BERREN 0x00000008ul 532#define DACEN 0x00000004ul 533#define STPWLEVEL 0x00000002ul 534#define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 535 536#define CSIZE_LATTIME 0x0c 537#define CACHESIZE 0x0000003ful /* only 5 bits */ 538#define LATTIME 0x0000ff00ul 539 540static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 541static int ahc_ext_scbram_present(struct ahc_softc *ahc); 542static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 543 int pcheck, int fast); 544static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 545static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 546static void configure_termination(struct ahc_softc *ahc, 547 struct seeprom_descriptor *sd, 548 u_int adapter_control, 549 u_int *sxfrctl1); 550 551static void ahc_new_term_detect(struct ahc_softc *ahc, 552 int *enableSEC_low, 553 int *enableSEC_high, 554 int *enablePRI_low, 555 int *enablePRI_high, 556 int *eeprom_present); 557static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 558 int *internal68_present, 559 int *externalcable_present, 560 int *eeprom_present); 561static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 562 int *externalcable_present, 563 int *eeprom_present); 564static int acquire_seeprom(struct ahc_softc *ahc, 565 struct seeprom_descriptor *sd); 566static void release_seeprom(struct seeprom_descriptor *sd); 567static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 568static u_int8_t read_brdctl(struct ahc_softc *ahc); 569 570static struct ahc_softc *first_398X; 571 572static int ahc_pci_probe(device_t dev); 573static int ahc_pci_attach(device_t dev); 574 575/* Exported for use in the ahc_intr routine */ 576void ahc_pci_intr(struct ahc_softc *ahc); 577 578static device_method_t ahc_pci_methods[] = { 579 /* Device interface */ 580 DEVMETHOD(device_probe, ahc_pci_probe), 581 DEVMETHOD(device_attach, ahc_pci_attach), 582 { 0, 0 } 583}; 584 585static driver_t ahc_pci_driver = { 586 "ahc", 587 ahc_pci_methods, 588 sizeof(struct ahc_softc) 589}; 590 591static devclass_t ahc_devclass; 592 593DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 594 595static struct ahc_pci_identity * 596ahc_find_pci_device(device_t dev) 597{ 598 u_int64_t full_id; 599 struct ahc_pci_identity *entry; 600 u_int i; 601 602 full_id = ahc_compose_id(pci_get_device(dev), 603 pci_get_vendor(dev), 604 pci_get_subdevice(dev), 605 pci_get_subvendor(dev)); 606 607 for (i = 0; i < ahc_num_pci_devs; i++) { 608 entry = &ahc_pci_ident_table[i]; 609 if (entry->full_id == (full_id & entry->id_mask)) 610 return (entry); 611 } 612 return (NULL); 613} 614 615static int 616ahc_pci_probe(device_t dev) 617{ 618 struct ahc_pci_identity *entry; 619 620 entry = ahc_find_pci_device(dev); 621 if (entry != NULL) { 622 device_set_desc(dev, entry->name); 623 return (0); 624 } 625 return (ENXIO); 626} 627 628static int 629ahc_pci_attach(device_t dev) 630{ 631 bus_dma_tag_t parent_dmat; 632 struct ahc_pci_identity *entry; 633 struct resource *regs; 634 struct ahc_softc *ahc; 635 u_int command; 636 struct scb_data *shared_scb_data; 637 ahc_chip ahc_t = AHC_NONE; 638 ahc_feature ahc_fe = AHC_FENONE; 639 ahc_flag ahc_f = AHC_FNONE; 640 int regs_type; 641 int regs_id; 642 u_int our_id = 0; 643 u_int sxfrctl1; 644 u_int scsiseq; 645 int error; 646 int zero; 647 char channel; 648 649 shared_scb_data = NULL; 650 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 651 entry = ahc_find_pci_device(dev); 652 if (entry == NULL) 653 return (ENXIO); 654 error = entry->setup(dev, &channel, &ahc_t, &ahc_fe, &ahc_f); 655 if (error != 0) 656 return (error); 657 658 regs = NULL; 659 regs_type = 0; 660 regs_id = 0; 661#ifdef AHC_ALLOW_MEMIO 662 if ((command & PCIM_CMD_MEMEN) != 0) { 663 regs_type = SYS_RES_MEMORY; 664 regs_id = AHC_PCI_MEMADDR; 665 regs = bus_alloc_resource(dev, regs_type, 666 ®s_id, 0, ~0, 1, RF_ACTIVE); 667 } 668#endif 669 if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) { 670 regs_type = SYS_RES_IOPORT; 671 regs_id = AHC_PCI_IOADDR; 672 regs = bus_alloc_resource(dev, regs_type, 673 ®s_id, 0, ~0, 1, RF_ACTIVE); 674 } 675 676 if (regs == NULL) { 677 device_printf(dev, "can't allocate register resources\n"); 678 return (ENOMEM); 679 } 680 681 /* Ensure busmastering is enabled */ 682 command |= PCIM_CMD_BUSMASTEREN; 683 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 684 685 /* Allocate a dmatag for our SCB DMA maps */ 686 /* XXX Should be a child of the PCI bus dma tag */ 687 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 688 /*boundary*/0, 689 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 690 /*highaddr*/BUS_SPACE_MAXADDR, 691 /*filter*/NULL, /*filterarg*/NULL, 692 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 693 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 694 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 695 696 if (error != 0) { 697 printf("ahc_pci_attach: Could not allocate DMA tag " 698 "- error %d\n", error); 699 return (ENOMEM); 700 } 701 702 /* On all PCI adapters, we allow SCB paging */ 703 ahc_f |= AHC_PAGESCBS; 704 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 705 ahc_t|AHC_PCI, ahc_fe, ahc_f, 706 shared_scb_data)) == NULL) 707 return (ENOMEM); 708 709 ahc->channel = channel; 710 711 /* Store our PCI bus information for use in our PCI error handler */ 712 ahc->device = dev; 713 714 /* Remeber how the card was setup in case there is no SEEPROM */ 715 ahc_outb(ahc, HCNTRL, ahc->pause); 716 if ((ahc->features & AHC_ULTRA2) != 0) 717 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 718 else 719 our_id = ahc_inb(ahc, SCSIID) & OID; 720 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 721 scsiseq = ahc_inb(ahc, SCSISEQ); 722 723 if (ahc_reset(ahc) != 0) { 724 /* Failed */ 725 ahc_free(ahc); 726 return (ENXIO); 727 } 728 729 if ((ahc->features & AHC_DT) != 0) { 730 u_int optionmode; 731 u_int sfunct; 732 733 /* Perform ALT-Mode Setup */ 734 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 735 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 736 optionmode = ahc_inb(ahc, OPTIONMODE); 737 printf("OptionMode = %x\n", optionmode); 738 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 739 /* Send CRC info in target mode every 4K */ 740 ahc_outb(ahc, TARGCRCCNT, 0); 741 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 742 ahc_outb(ahc, SFUNCT, sfunct); 743 744 /* Normal mode setup */ 745 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 746 |TARGCRCENDEN|TARGCRCCNTEN); 747 } 748 zero = 0; 749 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 750 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 751 if (ahc->irq == NULL) { 752 ahc_free(ahc); 753 return (ENOMEM); 754 } 755 756 ahc->irq_res_type = SYS_RES_IRQ; 757 758 /* 759 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 760 */ 761 { 762 u_int8_t sblkctl; 763 u_int dscommand0; 764 765 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 766 dscommand0 |= MPARCKEN; 767 if ((ahc->features & AHC_ULTRA2) != 0) { 768 769 /* 770 * DPARCKEN doesn't work correctly on 771 * some MBs so don't use it. 772 */ 773 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 774 dscommand0 |= CACHETHEN; 775 } 776 777 ahc_outb(ahc, DSCOMMAND0, dscommand0); 778 779 /* See if we have an SEEPROM and perform auto-term */ 780 check_extport(ahc, &sxfrctl1); 781 782 /* 783 * Take the LED out of diagnostic mode 784 */ 785 sblkctl = ahc_inb(ahc, SBLKCTL); 786 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 787 788 /* 789 * I don't know where this is set in the SEEPROM or by the 790 * BIOS, so we default to 100% on Ultra or slower controllers 791 * and 75% on ULTRA2 controllers. 792 */ 793 if ((ahc->features & AHC_ULTRA2) != 0) { 794 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 795 } else { 796 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 797 } 798 799 if (ahc->flags & AHC_USEDEFAULTS) { 800 /* 801 * PCI Adapter default setup 802 * Should only be used if the adapter does not have 803 * an SEEPROM. 804 */ 805 /* See if someone else set us up already */ 806 if (scsiseq != 0) { 807 printf("%s: Using left over BIOS settings\n", 808 ahc_name(ahc)); 809 ahc->flags &= ~AHC_USEDEFAULTS; 810 } else { 811 /* 812 * Assume only one connector and always turn 813 * on termination. 814 */ 815 our_id = 0x07; 816 sxfrctl1 = STPWEN; 817 } 818 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 819 820 ahc->our_id = our_id; 821 } 822 } 823 824 /* 825 * Take a look to see if we have external SRAM. 826 * We currently do not attempt to use SRAM that is 827 * shared among multiple controllers. 828 */ 829 ahc_probe_ext_scbram(ahc); 830 831 832 printf("%s: %s ", ahc_name(ahc), 833 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 834 835 /* 836 * Record our termination setting for the 837 * generic initialization routine. 838 */ 839 if ((sxfrctl1 & STPWEN) != 0) 840 ahc->flags |= AHC_TERM_ENB_A; 841 842 if (ahc_init(ahc)) { 843 ahc_free(ahc); 844 return (ENOMEM); 845 } 846 847 /* XXX Crude hack - fix sometime */ 848 if (ahc->flags & AHC_SHARED_SRAM) { 849 /* Only set this once we've successfully probed */ 850 if (shared_scb_data == NULL) 851 first_398X = ahc; 852 } 853 854 ahc_attach(ahc); 855 return (0); 856} 857 858/* 859 * Test for the presense of external sram in an 860 * "unshared" configuration. 861 */ 862static int 863ahc_ext_scbram_present(struct ahc_softc *ahc) 864{ 865 int ramps; 866 int single_user; 867 u_int32_t devconfig; 868 869 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 870 single_user = (devconfig & MPORTMODE) != 0; 871 872 if ((ahc->features & AHC_ULTRA2) != 0) 873 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 874 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 875 ramps = (devconfig & RAMPSM) != 0; 876 else 877 ramps = 0; 878 879 if (ramps && single_user) 880 return (1); 881 return (0); 882} 883 884/* 885 * Enable external scbram. 886 */ 887static void 888ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 889{ 890 u_int32_t devconfig; 891 892 if (ahc->features & AHC_MULTI_FUNC) { 893 /* 894 * Set the SCB Base addr (highest address bit) 895 * depending on which channel we are. 896 */ 897 ahc_outb(ahc, SCBBADDR, pci_get_function(ahc->device)); 898 } 899 900 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 901 if ((ahc->features & AHC_ULTRA2) != 0) { 902 u_int dscommand0; 903 904 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 905 if (enable) 906 dscommand0 &= ~INTSCBRAMSEL; 907 else 908 dscommand0 |= INTSCBRAMSEL; 909 ahc_outb(ahc, DSCOMMAND0, dscommand0); 910 } else { 911 if (fast) 912 devconfig &= ~EXTSCBTIME; 913 else 914 devconfig |= EXTSCBTIME; 915 if (enable) 916 devconfig &= ~SCBRAMSEL; 917 else 918 devconfig |= SCBRAMSEL; 919 } 920 if (pcheck) 921 devconfig |= EXTSCBPEN; 922 else 923 devconfig &= ~EXTSCBPEN; 924 925 pci_write_config(ahc->device, DEVCONFIG, devconfig, /*bytes*/4); 926} 927 928/* 929 * Take a look to see if we have external SRAM. 930 * We currently do not attempt to use SRAM that is 931 * shared among multiple controllers. 932 */ 933static void 934ahc_probe_ext_scbram(struct ahc_softc *ahc) 935{ 936 int num_scbs; 937 int test_num_scbs; 938 int enable; 939 int pcheck; 940 int fast; 941 942 if (ahc_ext_scbram_present(ahc) == 0) 943 return; 944 945 /* 946 * Probe for the best parameters to use. 947 */ 948 enable = FALSE; 949 pcheck = FALSE; 950 fast = FALSE; 951 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 952 num_scbs = ahc_probe_scbs(ahc); 953 if (num_scbs == 0) { 954 /* The SRAM wasn't really present. */ 955 goto done; 956 } 957 enable = TRUE; 958 959 /* Now see if we can do parity */ 960 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 961 num_scbs = ahc_probe_scbs(ahc); 962 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 963 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 964 pcheck = TRUE; 965 966 /* Clear any resulting parity error */ 967 ahc_outb(ahc, CLRINT, CLRPARERR); 968 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 969 970 /* Now see if we can do fast timing */ 971 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 972 test_num_scbs = ahc_probe_scbs(ahc); 973 if (test_num_scbs == num_scbs 974 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 975 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 976 fast = TRUE; 977 978done: 979 /* Clear any resulting parity error */ 980 ahc_outb(ahc, CLRINT, CLRPARERR); 981 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 982 if (bootverbose && enable) { 983 printf("%s: External SRAM, %dns access%s\n", 984 ahc_name(ahc), fast ? 10 : 20, 985 pcheck ? ", parity checking enabled" : ""); 986 987 } 988 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 989} 990 991/* 992 * Check the external port logic for a serial eeprom 993 * and termination/cable detection contrls. 994 */ 995static void 996check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 997{ 998 struct seeprom_descriptor sd; 999 struct seeprom_config sc; 1000 u_int scsi_conf; 1001 u_int adapter_control; 1002 int have_seeprom; 1003 int have_autoterm; 1004 1005 sd.sd_tag = ahc->tag; 1006 sd.sd_bsh = ahc->bsh; 1007 sd.sd_control_offset = SEECTL; 1008 sd.sd_status_offset = SEECTL; 1009 sd.sd_dataout_offset = SEECTL; 1010 1011 /* 1012 * For some multi-channel devices, the c46 is simply too 1013 * small to work. For the other controller types, we can 1014 * get our information from either SEEPROM type. Set the 1015 * type to start our probe with accordingly. 1016 */ 1017 if (ahc->flags & AHC_LARGE_SEEPROM) 1018 sd.sd_chip = C56_66; 1019 else 1020 sd.sd_chip = C46; 1021 1022 sd.sd_MS = SEEMS; 1023 sd.sd_RDY = SEERDY; 1024 sd.sd_CS = SEECS; 1025 sd.sd_CK = SEECK; 1026 sd.sd_DO = SEEDO; 1027 sd.sd_DI = SEEDI; 1028 1029 have_seeprom = acquire_seeprom(ahc, &sd); 1030 if (have_seeprom) { 1031 1032 if (bootverbose) 1033 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1034 1035 for (;;) { 1036 bus_size_t start_addr; 1037 1038 start_addr = 32 * (ahc->channel - 'A'); 1039 1040 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 1041 start_addr, sizeof(sc)/2); 1042 1043 if (have_seeprom) { 1044 /* Check checksum */ 1045 int i; 1046 int maxaddr; 1047 u_int32_t checksum; 1048 u_int16_t *scarray; 1049 1050 maxaddr = (sizeof(sc)/2) - 1; 1051 checksum = 0; 1052 scarray = (u_int16_t *)≻ 1053 1054 for (i = 0; i < maxaddr; i++) 1055 checksum = checksum + scarray[i]; 1056 if (checksum == 0 1057 || (checksum & 0xFFFF) != sc.checksum) { 1058 if (bootverbose && sd.sd_chip == C56_66) 1059 printf ("checksum error\n"); 1060 have_seeprom = 0; 1061 } else { 1062 if (bootverbose) 1063 printf("done.\n"); 1064 break; 1065 } 1066 } 1067 1068 if (sd.sd_chip == C56_66) 1069 break; 1070 sd.sd_chip = C56_66; 1071 } 1072 } 1073 1074 if (!have_seeprom) { 1075 if (bootverbose) 1076 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1077 ahc->flags |= AHC_USEDEFAULTS; 1078 } else { 1079 /* 1080 * Put the data we've collected down into SRAM 1081 * where ahc_init will find it. 1082 */ 1083 int i; 1084 int max_targ = sc.max_targets & CFMAXTARG; 1085 u_int16_t discenable; 1086 u_int16_t ultraenb; 1087 1088 discenable = 0; 1089 ultraenb = 0; 1090 if ((sc.adapter_control & CFULTRAEN) != 0) { 1091 /* 1092 * Determine if this adapter has a "newstyle" 1093 * SEEPROM format. 1094 */ 1095 for (i = 0; i < max_targ; i++) { 1096 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1097 ahc->flags |= AHC_NEWEEPROM_FMT; 1098 break; 1099 } 1100 } 1101 } 1102 1103 for (i = 0; i < max_targ; i++) { 1104 u_int scsirate; 1105 u_int16_t target_mask; 1106 1107 target_mask = 0x01 << i; 1108 if (sc.device_flags[i] & CFDISC) 1109 discenable |= target_mask; 1110 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1111 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1112 ultraenb |= target_mask; 1113 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1114 ultraenb |= target_mask; 1115 } 1116 if ((sc.device_flags[i] & CFXFER) == 0x04 1117 && (ultraenb & target_mask) != 0) { 1118 /* Treat 10MHz as a non-ultra speed */ 1119 sc.device_flags[i] &= ~CFXFER; 1120 ultraenb &= ~target_mask; 1121 } 1122 if ((ahc->features & AHC_ULTRA2) != 0) { 1123 u_int offset; 1124 1125 if (sc.device_flags[i] & CFSYNCH) 1126 offset = MAX_OFFSET_ULTRA2; 1127 else 1128 offset = 0; 1129 ahc_outb(ahc, TARG_OFFSET + i, offset); 1130 1131 scsirate = (sc.device_flags[i] & CFXFER) 1132 | ((ultraenb & target_mask) 1133 ? 0x8 : 0x0); 1134 if (sc.device_flags[i] & CFWIDEB) 1135 scsirate |= WIDEXFER; 1136 } else { 1137 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1138 if (sc.device_flags[i] & CFSYNCH) 1139 scsirate |= SOFS; 1140 if (sc.device_flags[i] & CFWIDEB) 1141 scsirate |= WIDEXFER; 1142 } 1143 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1144 } 1145 ahc->our_id = sc.brtime_id & CFSCSIID; 1146 1147 scsi_conf = (ahc->our_id & 0x7); 1148 if (sc.adapter_control & CFSPARITY) 1149 scsi_conf |= ENSPCHK; 1150 if (sc.adapter_control & CFRESETB) 1151 scsi_conf |= RESET_SCSI; 1152 1153 if (sc.bios_control & CFEXTEND) 1154 ahc->flags |= AHC_EXTENDED_TRANS_A; 1155 if (ahc->features & AHC_ULTRA 1156 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1157 /* Should we enable Ultra mode? */ 1158 if (!(sc.adapter_control & CFULTRAEN)) 1159 /* Treat us as a non-ultra card */ 1160 ultraenb = 0; 1161 } 1162 /* Set SCSICONF info */ 1163 ahc_outb(ahc, SCSICONF, scsi_conf); 1164 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1165 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1166 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1167 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1168 } 1169 1170 /* 1171 * Cards that have the external logic necessary to talk to 1172 * a SEEPROM, are almost certain to have the remaining logic 1173 * necessary for auto-termination control. This assumption 1174 * hasn't failed yet... 1175 */ 1176 have_autoterm = have_seeprom; 1177 if (have_seeprom) 1178 adapter_control = sc.adapter_control; 1179 else 1180 adapter_control = CFAUTOTERM; 1181 1182 /* 1183 * Some low-cost chips have SEEPROM and auto-term control built 1184 * in, instead of using a GAL. They can tell us directly 1185 * if the termination logic is enabled. 1186 */ 1187 if ((ahc->features & AHC_SPIOCAP) != 0) { 1188 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1189 have_autoterm = TRUE; 1190 else 1191 have_autoterm = FALSE; 1192 } 1193 1194 if (have_autoterm) 1195 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1196 1197 release_seeprom(&sd); 1198} 1199 1200static void 1201configure_termination(struct ahc_softc *ahc, 1202 struct seeprom_descriptor *sd, 1203 u_int adapter_control, 1204 u_int *sxfrctl1) 1205{ 1206 u_int8_t brddat; 1207 1208 brddat = 0; 1209 1210 /* 1211 * Update the settings in sxfrctl1 to match the 1212 * termination settings 1213 */ 1214 *sxfrctl1 = 0; 1215 1216 /* 1217 * SEECS must be on for the GALS to latch 1218 * the data properly. Be sure to leave MS 1219 * on or we will release the seeprom. 1220 */ 1221 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1222 if ((adapter_control & CFAUTOTERM) != 0 1223 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1224 int internal50_present; 1225 int internal68_present; 1226 int externalcable_present; 1227 int eeprom_present; 1228 int enableSEC_low; 1229 int enableSEC_high; 1230 int enablePRI_low; 1231 int enablePRI_high; 1232 1233 enableSEC_low = 0; 1234 enableSEC_high = 0; 1235 enablePRI_low = 0; 1236 enablePRI_high = 0; 1237 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1238 ahc_new_term_detect(ahc, &enableSEC_low, 1239 &enableSEC_high, 1240 &enablePRI_low, 1241 &enablePRI_high, 1242 &eeprom_present); 1243 if ((adapter_control & CFSEAUTOTERM) == 0) { 1244 if (bootverbose) 1245 printf("%s: Manual SE Termination\n", 1246 ahc_name(ahc)); 1247 enableSEC_low = (adapter_control & CFSTERM); 1248 enableSEC_high = (adapter_control & CFWSTERM); 1249 } 1250 if ((adapter_control & CFAUTOTERM) == 0) { 1251 if (bootverbose) 1252 printf("%s: Manual LVD Termination\n", 1253 ahc_name(ahc)); 1254 enablePRI_low = enablePRI_high = 1255 (adapter_control & CFLVDSTERM); 1256 } 1257 /* Make the table calculations below happy */ 1258 internal50_present = 0; 1259 internal68_present = 1; 1260 externalcable_present = 1; 1261 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1262 aic785X_cable_detect(ahc, &internal50_present, 1263 &externalcable_present, 1264 &eeprom_present); 1265 } else { 1266 aic787X_cable_detect(ahc, &internal50_present, 1267 &internal68_present, 1268 &externalcable_present, 1269 &eeprom_present); 1270 } 1271 1272 if ((ahc->features & AHC_WIDE) == 0) 1273 internal68_present = 0; 1274 1275 if (bootverbose) { 1276 if ((ahc->features & AHC_ULTRA2) == 0) { 1277 printf("%s: internal 50 cable %s present, " 1278 "internal 68 cable %s present\n", 1279 ahc_name(ahc), 1280 internal50_present ? "is":"not", 1281 internal68_present ? "is":"not"); 1282 1283 printf("%s: external cable %s present\n", 1284 ahc_name(ahc), 1285 externalcable_present ? "is":"not"); 1286 } 1287 printf("%s: BIOS eeprom %s present\n", 1288 ahc_name(ahc), eeprom_present ? "is" : "not"); 1289 } 1290 1291 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1292 /* 1293 * The 50 pin connector is a separate bus, 1294 * so force it to always be terminated. 1295 * In the future, perform current sensing 1296 * to determine if we are in the middle of 1297 * a properly terminated bus. 1298 */ 1299 internal50_present = 0; 1300 } 1301 1302 /* 1303 * Now set the termination based on what 1304 * we found. 1305 * Flash Enable = BRDDAT7 1306 * Secondary High Term Enable = BRDDAT6 1307 * Secondary Low Term Enable = BRDDAT5 (7890) 1308 * Primary High Term Enable = BRDDAT4 (7890) 1309 */ 1310 if ((ahc->features & AHC_ULTRA2) == 0 1311 && (internal50_present != 0) 1312 && (internal68_present != 0) 1313 && (externalcable_present != 0)) { 1314 printf("%s: Illegal cable configuration!!. " 1315 "Only two connectors on the " 1316 "adapter may be used at a " 1317 "time!\n", ahc_name(ahc)); 1318 } 1319 1320 if ((ahc->features & AHC_WIDE) != 0 1321 && ((externalcable_present == 0) 1322 || (internal68_present == 0) 1323 || (enableSEC_high != 0))) { 1324 brddat |= BRDDAT6; 1325 if (bootverbose) { 1326 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1327 printf("%s: 68 pin termination " 1328 "Enabled\n", ahc_name(ahc)); 1329 else 1330 printf("%s: %sHigh byte termination " 1331 "Enabled\n", ahc_name(ahc), 1332 enableSEC_high ? "Secondary " 1333 : ""); 1334 } 1335 } 1336 1337 if (((internal50_present ? 1 : 0) 1338 + (internal68_present ? 1 : 0) 1339 + (externalcable_present ? 1 : 0)) <= 1 1340 || (enableSEC_low != 0)) { 1341 if ((ahc->features & AHC_ULTRA2) != 0) 1342 brddat |= BRDDAT5; 1343 else 1344 *sxfrctl1 |= STPWEN; 1345 if (bootverbose) { 1346 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1347 printf("%s: 50 pin termination " 1348 "Enabled\n", ahc_name(ahc)); 1349 else 1350 printf("%s: %sLow byte termination " 1351 "Enabled\n", ahc_name(ahc), 1352 enableSEC_low ? "Secondary " 1353 : ""); 1354 } 1355 } 1356 1357 if (enablePRI_low != 0) { 1358 *sxfrctl1 |= STPWEN; 1359 if (bootverbose) 1360 printf("%s: Primary Low Byte termination " 1361 "Enabled\n", ahc_name(ahc)); 1362 } 1363 1364 /* 1365 * Setup STPWEN before setting up the rest of 1366 * the termination per the tech note on the U160 cards. 1367 */ 1368 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1369 1370 if (enablePRI_high != 0) { 1371 brddat |= BRDDAT4; 1372 if (bootverbose) 1373 printf("%s: Primary High Byte " 1374 "termination Enabled\n", 1375 ahc_name(ahc)); 1376 } 1377 1378 write_brdctl(ahc, brddat); 1379 1380 } else { 1381 if ((adapter_control & CFSTERM) != 0) { 1382 *sxfrctl1 |= STPWEN; 1383 1384 if (bootverbose) 1385 printf("%s: %sLow byte termination Enabled\n", 1386 ahc_name(ahc), 1387 (ahc->features & AHC_ULTRA2) ? "Primary " 1388 : ""); 1389 } 1390 1391 if ((adapter_control & CFWSTERM) != 0) { 1392 brddat |= BRDDAT6; 1393 if (bootverbose) 1394 printf("%s: %sHigh byte termination Enabled\n", 1395 ahc_name(ahc), 1396 (ahc->features & AHC_ULTRA2) 1397 ? "Secondary " : ""); 1398 } 1399 1400 /* 1401 * Setup STPWEN before setting up the rest of 1402 * the termination per the tech note on the U160 cards. 1403 */ 1404 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1405 1406 write_brdctl(ahc, brddat); 1407 } 1408 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1409} 1410 1411static void 1412ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1413 int *enableSEC_high, int *enablePRI_low, 1414 int *enablePRI_high, int *eeprom_present) 1415{ 1416 u_int8_t brdctl; 1417 1418 /* 1419 * BRDDAT7 = Eeprom 1420 * BRDDAT6 = Enable Secondary High Byte termination 1421 * BRDDAT5 = Enable Secondary Low Byte termination 1422 * BRDDAT4 = Enable Primary high byte termination 1423 * BRDDAT3 = Enable Primary low byte termination 1424 */ 1425 brdctl = read_brdctl(ahc); 1426 *eeprom_present = brdctl & BRDDAT7; 1427 *enableSEC_high = (brdctl & BRDDAT6); 1428 *enableSEC_low = (brdctl & BRDDAT5); 1429 *enablePRI_high = (brdctl & BRDDAT4); 1430 *enablePRI_low = (brdctl & BRDDAT3); 1431} 1432 1433static void 1434aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1435 int *internal68_present, int *externalcable_present, 1436 int *eeprom_present) 1437{ 1438 u_int8_t brdctl; 1439 1440 /* 1441 * First read the status of our cables. 1442 * Set the rom bank to 0 since the 1443 * bank setting serves as a multiplexor 1444 * for the cable detection logic. 1445 * BRDDAT5 controls the bank switch. 1446 */ 1447 write_brdctl(ahc, 0); 1448 1449 /* 1450 * Now read the state of the internal 1451 * connectors. BRDDAT6 is INT50 and 1452 * BRDDAT7 is INT68. 1453 */ 1454 brdctl = read_brdctl(ahc); 1455 *internal50_present = !(brdctl & BRDDAT6); 1456 *internal68_present = !(brdctl & BRDDAT7); 1457 1458 /* 1459 * Set the rom bank to 1 and determine 1460 * the other signals. 1461 */ 1462 write_brdctl(ahc, BRDDAT5); 1463 1464 /* 1465 * Now read the state of the external 1466 * connectors. BRDDAT6 is EXT68 and 1467 * BRDDAT7 is EPROMPS. 1468 */ 1469 brdctl = read_brdctl(ahc); 1470 *externalcable_present = !(brdctl & BRDDAT6); 1471 *eeprom_present = brdctl & BRDDAT7; 1472} 1473 1474static void 1475aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1476 int *externalcable_present, int *eeprom_present) 1477{ 1478 u_int8_t brdctl; 1479 1480 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1481 ahc_outb(ahc, BRDCTL, 0); 1482 brdctl = ahc_inb(ahc, BRDCTL); 1483 *internal50_present = !(brdctl & BRDDAT5); 1484 *externalcable_present = !(brdctl & BRDDAT6); 1485 1486 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1487} 1488 1489static int 1490acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1491{ 1492 int wait; 1493 1494 if ((ahc->features & AHC_SPIOCAP) != 0 1495 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1496 return (0); 1497 1498 /* 1499 * Request access of the memory port. When access is 1500 * granted, SEERDY will go high. We use a 1 second 1501 * timeout which should be near 1 second more than 1502 * is needed. Reason: after the chip reset, there 1503 * should be no contention. 1504 */ 1505 SEEPROM_OUTB(sd, sd->sd_MS); 1506 wait = 1000; /* 1 second timeout in msec */ 1507 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1508 DELAY(1000); /* delay 1 msec */ 1509 } 1510 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1511 SEEPROM_OUTB(sd, 0); 1512 return (0); 1513 } 1514 return(1); 1515} 1516 1517static void 1518release_seeprom(sd) 1519 struct seeprom_descriptor *sd; 1520{ 1521 /* Release access to the memory port and the serial EEPROM. */ 1522 SEEPROM_OUTB(sd, 0); 1523} 1524 1525static void 1526write_brdctl(ahc, value) 1527 struct ahc_softc *ahc; 1528 u_int8_t value; 1529{ 1530 u_int8_t brdctl; 1531 1532 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1533 brdctl = BRDSTB; 1534 if (ahc->channel == 'B') 1535 brdctl |= BRDCS; 1536 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1537 brdctl = 0; 1538 } else { 1539 brdctl = BRDSTB|BRDCS; 1540 } 1541 ahc_outb(ahc, BRDCTL, brdctl); 1542 DELAY(20); 1543 brdctl |= value; 1544 ahc_outb(ahc, BRDCTL, brdctl); 1545 DELAY(20); 1546 if ((ahc->features & AHC_ULTRA2) != 0) 1547 brdctl |= BRDSTB_ULTRA2; 1548 else 1549 brdctl &= ~BRDSTB; 1550 ahc_outb(ahc, BRDCTL, brdctl); 1551 DELAY(20); 1552 if ((ahc->features & AHC_ULTRA2) != 0) 1553 brdctl = 0; 1554 else 1555 brdctl &= ~BRDCS; 1556 ahc_outb(ahc, BRDCTL, brdctl); 1557} 1558 1559static u_int8_t 1560read_brdctl(ahc) 1561 struct ahc_softc *ahc; 1562{ 1563 u_int8_t brdctl; 1564 u_int8_t value; 1565 1566 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1567 brdctl = BRDRW; 1568 if (ahc->channel == 'B') 1569 brdctl |= BRDCS; 1570 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1571 brdctl = BRDRW_ULTRA2; 1572 } else { 1573 brdctl = BRDRW|BRDCS; 1574 } 1575 ahc_outb(ahc, BRDCTL, brdctl); 1576 DELAY(20); 1577 value = ahc_inb(ahc, BRDCTL); 1578 ahc_outb(ahc, BRDCTL, 0); 1579 return (value); 1580} 1581 1582#define DPE 0x80 1583#define SSE 0x40 1584#define RMA 0x20 1585#define RTA 0x10 1586#define STA 0x08 1587#define DPR 0x01 1588 1589void 1590ahc_pci_intr(struct ahc_softc *ahc) 1591{ 1592 u_int8_t status1; 1593 1594 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1595 1596 if (status1 & DPE) { 1597 printf("%s: Data Parity Error Detected during address " 1598 "or write data phase\n", ahc_name(ahc)); 1599 } 1600 if (status1 & SSE) { 1601 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1602 } 1603 if (status1 & RMA) { 1604 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1605 } 1606 if (status1 & RTA) { 1607 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1608 } 1609 if (status1 & STA) { 1610 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1611 } 1612 if (status1 & DPR) { 1613 printf("%s: Data Parity Error has been reported via PERR#\n", 1614 ahc_name(ahc)); 1615 } 1616 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1617 printf("%s: Latched PCIERR interrupt with " 1618 "no status bits set\n", ahc_name(ahc)); 1619 } 1620 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1621 1622 if (status1 & (DPR|RMA|RTA)) { 1623 ahc_outb(ahc, CLRINT, CLRPARERR); 1624 } 1625} 1626 1627static int 1628ahc_aic7850_setup(device_t dev, char *channel, ahc_chip *chip, 1629 ahc_feature *features, ahc_flag *flags) 1630{ 1631 *channel = 'A'; 1632 *chip = AHC_AIC7850; 1633 *features = AHC_AIC7850_FE; 1634 return (0); 1635} 1636 1637static int 1638ahc_aic7855_setup(device_t dev, char *channel, ahc_chip *chip, 1639 ahc_feature *features, ahc_flag *flags) 1640{ 1641 *channel = 'A'; 1642 *chip = AHC_AIC7855; 1643 *features = AHC_AIC7855_FE; 1644 return (0); 1645} 1646 1647static int 1648ahc_aic7859_setup(device_t dev, char *channel, ahc_chip *chip, 1649 ahc_feature *features, ahc_flag *flags) 1650{ 1651 *channel = 'A'; 1652 *chip = AHC_AIC7859; 1653 *features = AHC_AIC7859_FE; 1654 return (0); 1655} 1656 1657static int 1658ahc_aic7860_setup(device_t dev, char *channel, ahc_chip *chip, 1659 ahc_feature *features, ahc_flag *flags) 1660{ 1661 *channel = 'A'; 1662 *chip = AHC_AIC7860; 1663 *features = AHC_AIC7860_FE; 1664 return (0); 1665} 1666 1667static int 1668ahc_aic7870_setup(device_t dev, char *channel, ahc_chip *chip, 1669 ahc_feature *features, ahc_flag *flags) 1670{ 1671 *channel = 'A'; 1672 *chip = AHC_AIC7870; 1673 *features = AHC_AIC7870_FE; 1674 return (0); 1675} 1676 1677static int 1678ahc_aha394X_setup(device_t dev, char *channel, ahc_chip *chip, 1679 ahc_feature *features, ahc_flag *flags) 1680{ 1681 int error; 1682 1683 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1684 if (error == 0) 1685 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1686 return (error); 1687} 1688 1689static int 1690ahc_aha398X_setup(device_t dev, char *channel, ahc_chip *chip, 1691 ahc_feature *features, ahc_flag *flags) 1692{ 1693 int error; 1694 1695 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1696 if (error == 0) 1697 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1698 return (error); 1699} 1700 1701static int 1702ahc_aic7880_setup(device_t dev, char *channel, ahc_chip *chip, 1703 ahc_feature *features, ahc_flag *flags) 1704{ 1705 *channel = 'A'; 1706 *chip = AHC_AIC7880; 1707 *features = AHC_AIC7880_FE; 1708 return (0); 1709} 1710 1711static int 1712ahc_2940Pro_setup(device_t dev, char *channel, ahc_chip *chip, 1713 ahc_feature *features, ahc_flag *flags) 1714{ 1715 int error; 1716 1717 *flags |= AHC_INT50_SPEEDFLEX; 1718 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1719 return (0); 1720} 1721 1722static int 1723ahc_aha394XU_setup(device_t dev, char *channel, ahc_chip *chip, 1724 ahc_feature *features, ahc_flag *flags) 1725{ 1726 int error; 1727 1728 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1729 if (error == 0) 1730 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1731 return (error); 1732} 1733 1734static int 1735ahc_aha398XU_setup(device_t dev, char *channel, ahc_chip *chip, 1736 ahc_feature *features, ahc_flag *flags) 1737{ 1738 int error; 1739 1740 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1741 if (error == 0) 1742 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1743 return (error); 1744} 1745 1746static int 1747ahc_aic7890_setup(device_t dev, char *channel, ahc_chip *chip, 1748 ahc_feature *features, ahc_flag *flags) 1749{ 1750 *channel = 'A'; 1751 *chip = AHC_AIC7890; 1752 *features = AHC_AIC7890_FE; 1753 *flags |= AHC_NEWEEPROM_FMT; 1754 return (0); 1755} 1756 1757static int 1758ahc_aic7892_setup(device_t dev, char *channel, ahc_chip *chip, 1759 ahc_feature *features, ahc_flag *flags) 1760{ 1761 *channel = 'A'; 1762 *chip = AHC_AIC7892; 1763 *features = AHC_AIC7892_FE; 1764 *flags |= AHC_NEWEEPROM_FMT; 1765 return (0); 1766} 1767 1768static int 1769ahc_aic7895_setup(device_t dev, char *channel, ahc_chip *chip, 1770 ahc_feature *features, ahc_flag *flags) 1771{ 1772 u_int32_t devconfig; 1773 1774 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1775 *chip = AHC_AIC7895; 1776 /* The 'C' revision of the aic7895 has a few additional features */ 1777 if (pci_get_revid(dev) >= 4) 1778 *features = AHC_AIC7895C_FE; 1779 else 1780 *features = AHC_AIC7895_FE; 1781 *flags |= AHC_NEWEEPROM_FMT; 1782 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1783 devconfig &= ~SCBSIZE32; 1784 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1785 return (0); 1786} 1787 1788static int 1789ahc_aic7896_setup(device_t dev, char *channel, ahc_chip *chip, 1790 ahc_feature *features, ahc_flag *flags) 1791{ 1792 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1793 *chip = AHC_AIC7896; 1794 *features = AHC_AIC7896_FE; 1795 *flags |= AHC_NEWEEPROM_FMT; 1796 return (0); 1797} 1798 1799static int 1800ahc_aic7899_setup(device_t dev, char *channel, ahc_chip *chip, 1801 ahc_feature *features, ahc_flag *flags) 1802{ 1803 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1804 *chip = AHC_AIC7899; 1805 *features = AHC_AIC7899_FE; 1806 *flags |= AHC_NEWEEPROM_FMT; 1807 return (0); 1808} 1809 1810static int 1811ahc_raid_setup(device_t dev, char *channel, ahc_chip *chip, 1812 ahc_feature *features, ahc_flag *flags) 1813{ 1814 printf("RAID functionality unsupported\n"); 1815 return (ENXIO); 1816} 1817 1818static int 1819ahc_aha394XX_setup(device_t dev, char *channel, ahc_chip *chip, 1820 ahc_feature *features, ahc_flag *flags) 1821{ 1822 switch (pci_get_slot(dev)) { 1823 case AHC_394X_SLOT_CHANNEL_A: 1824 *channel = 'A'; 1825 break; 1826 case AHC_394X_SLOT_CHANNEL_B: 1827 *channel = 'B'; 1828 break; 1829 default: 1830 printf("adapter at unexpected slot %d\n" 1831 "unable to map to a channel\n", 1832 pci_get_slot(dev)); 1833 *channel = 'A'; 1834 } 1835 return (0); 1836} 1837 1838static int 1839ahc_aha398XX_setup(device_t dev, char *channel, ahc_chip *chip, 1840 ahc_feature *features, ahc_flag *flags) 1841{ 1842 switch (pci_get_slot(dev)) { 1843 case AHC_398X_SLOT_CHANNEL_A: 1844 *channel = 'A'; 1845 break; 1846 case AHC_398X_SLOT_CHANNEL_B: 1847 *channel = 'B'; 1848 break; 1849 case AHC_398X_SLOT_CHANNEL_C: 1850 *channel = 'C'; 1851 break; 1852 default: 1853 printf("adapter at unexpected slot %d\n" 1854 "unable to map to a channel\n", 1855 pci_get_slot(dev)); 1856 *channel = 'A'; 1857 } 1858 *flags |= AHC_LARGE_SEEPROM; 1859 return (0); 1860} 1861