ahci_pci.c revision 244983
1/*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 244983 2013-01-02 22:26:46Z jfv $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "ahci.h" 47 48#include <cam/cam.h> 49#include <cam/cam_ccb.h> 50#include <cam/cam_sim.h> 51#include <cam/cam_xpt_sim.h> 52#include <cam/cam_debug.h> 53 54/* local prototypes */ 55static int ahci_setup_interrupt(device_t dev); 56static void ahci_intr(void *data); 57static void ahci_intr_one(void *data); 58static int ahci_suspend(device_t dev); 59static int ahci_resume(device_t dev); 60static int ahci_ch_init(device_t dev); 61static int ahci_ch_deinit(device_t dev); 62static int ahci_ch_suspend(device_t dev); 63static int ahci_ch_resume(device_t dev); 64static void ahci_ch_pm(void *arg); 65static void ahci_ch_intr_locked(void *data); 66static void ahci_ch_intr(void *data); 67static int ahci_ctlr_reset(device_t dev); 68static int ahci_ctlr_setup(device_t dev); 69static void ahci_begin_transaction(device_t dev, union ccb *ccb); 70static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 71static void ahci_execute_transaction(struct ahci_slot *slot); 72static void ahci_timeout(struct ahci_slot *slot); 73static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 74static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 75static void ahci_dmainit(device_t dev); 76static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 77static void ahci_dmafini(device_t dev); 78static void ahci_slotsalloc(device_t dev); 79static void ahci_slotsfree(device_t dev); 80static void ahci_reset(device_t dev); 81static void ahci_start(device_t dev, int fbs); 82static void ahci_stop(device_t dev); 83static void ahci_clo(device_t dev); 84static void ahci_start_fr(device_t dev); 85static void ahci_stop_fr(device_t dev); 86 87static int ahci_sata_connect(struct ahci_channel *ch); 88static int ahci_sata_phy_reset(device_t dev); 89static int ahci_wait_ready(device_t dev, int t, int t0); 90 91static void ahci_issue_recovery(device_t dev); 92static void ahci_process_read_log(device_t dev, union ccb *ccb); 93static void ahci_process_request_sense(device_t dev, union ccb *ccb); 94 95static void ahciaction(struct cam_sim *sim, union ccb *ccb); 96static void ahcipoll(struct cam_sim *sim); 97 98static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 99 100static struct { 101 uint32_t id; 102 uint8_t rev; 103 const char *name; 104 int quirks; 105#define AHCI_Q_NOFORCE 1 106#define AHCI_Q_NOPMP 2 107#define AHCI_Q_NONCQ 4 108#define AHCI_Q_1CH 8 109#define AHCI_Q_2CH 16 110#define AHCI_Q_4CH 32 111#define AHCI_Q_EDGEIS 64 112#define AHCI_Q_SATA2 128 113#define AHCI_Q_NOBSYRES 256 114#define AHCI_Q_NOAA 512 115#define AHCI_Q_NOCOUNT 1024 116#define AHCI_Q_ALTSIG 2048 117} ahci_ids[] = { 118 {0x43801002, 0x00, "ATI IXP600", 0}, 119 {0x43901002, 0x00, "ATI IXP700", 0}, 120 {0x43911002, 0x00, "ATI IXP700", 0}, 121 {0x43921002, 0x00, "ATI IXP700", 0}, 122 {0x43931002, 0x00, "ATI IXP700", 0}, 123 {0x43941002, 0x00, "ATI IXP800", 0}, 124 {0x43951002, 0x00, "ATI IXP800", 0}, 125 {0x78001022, 0x00, "AMD Hudson-2", 0}, 126 {0x78011022, 0x00, "AMD Hudson-2", 0}, 127 {0x78021022, 0x00, "AMD Hudson-2", 0}, 128 {0x78031022, 0x00, "AMD Hudson-2", 0}, 129 {0x78041022, 0x00, "AMD Hudson-2", 0}, 130 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 131 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 132 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 133 {0x26818086, 0x00, "Intel ESB2", 0}, 134 {0x26828086, 0x00, "Intel ESB2", 0}, 135 {0x26838086, 0x00, "Intel ESB2", 0}, 136 {0x27c18086, 0x00, "Intel ICH7", 0}, 137 {0x27c38086, 0x00, "Intel ICH7", 0}, 138 {0x27c58086, 0x00, "Intel ICH7M", 0}, 139 {0x27c68086, 0x00, "Intel ICH7M", 0}, 140 {0x28218086, 0x00, "Intel ICH8", 0}, 141 {0x28228086, 0x00, "Intel ICH8", 0}, 142 {0x28248086, 0x00, "Intel ICH8", 0}, 143 {0x28298086, 0x00, "Intel ICH8M", 0}, 144 {0x282a8086, 0x00, "Intel ICH8M", 0}, 145 {0x29228086, 0x00, "Intel ICH9", 0}, 146 {0x29238086, 0x00, "Intel ICH9", 0}, 147 {0x29248086, 0x00, "Intel ICH9", 0}, 148 {0x29258086, 0x00, "Intel ICH9", 0}, 149 {0x29278086, 0x00, "Intel ICH9", 0}, 150 {0x29298086, 0x00, "Intel ICH9M", 0}, 151 {0x292a8086, 0x00, "Intel ICH9M", 0}, 152 {0x292b8086, 0x00, "Intel ICH9M", 0}, 153 {0x292c8086, 0x00, "Intel ICH9M", 0}, 154 {0x292f8086, 0x00, "Intel ICH9M", 0}, 155 {0x294d8086, 0x00, "Intel ICH9", 0}, 156 {0x294e8086, 0x00, "Intel ICH9M", 0}, 157 {0x3a058086, 0x00, "Intel ICH10", 0}, 158 {0x3a228086, 0x00, "Intel ICH10", 0}, 159 {0x3a258086, 0x00, "Intel ICH10", 0}, 160 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 161 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 162 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 163 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 164 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 165 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 166 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 167 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 168 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 169 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 170 {0x1d028086, 0x00, "Intel Patsburg", 0}, 171 {0x1d048086, 0x00, "Intel Patsburg", 0}, 172 {0x1d068086, 0x00, "Intel Patsburg", 0}, 173 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 174 {0x1e028086, 0x00, "Intel Panther Point", 0}, 175 {0x1e038086, 0x00, "Intel Panther Point", 0}, 176 {0x1e048086, 0x00, "Intel Panther Point", 0}, 177 {0x1e058086, 0x00, "Intel Panther Point", 0}, 178 {0x1e068086, 0x00, "Intel Panther Point", 0}, 179 {0x1e078086, 0x00, "Intel Panther Point", 0}, 180 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 181 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 182 {0x8c028086, 0x00, "Intel Lynx Point", 0}, 183 {0x8c038086, 0x00, "Intel Lynx Point", 0}, 184 {0x8c048086, 0x00, "Intel Lynx Point", 0}, 185 {0x8c058086, 0x00, "Intel Lynx Point", 0}, 186 {0x8c068086, 0x00, "Intel Lynx Point", 0}, 187 {0x8c078086, 0x00, "Intel Lynx Point", 0}, 188 {0x8c0e8086, 0x00, "Intel Lynx Point", 0}, 189 {0x8c0f8086, 0x00, "Intel Lynx Point", 0}, 190 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 191 {0x2360197b, 0x00, "JMicron JMB360", 0}, 192 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 193 {0x2362197b, 0x00, "JMicron JMB362", 0}, 194 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 195 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 196 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 197 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 198 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 199 AHCI_Q_EDGEIS}, 200 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 201 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 202 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 203 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 204 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 205 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 206 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 207 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 208 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 209 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 210 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 211 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 212 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 213 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 214 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 215 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 216 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 217 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 218 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 219 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 220 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 221 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 222 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 223 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 224 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 225 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 226 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 227 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 228 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 229 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 230 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 231 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 232 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 233 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 234 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 235 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 236 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 237 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 238 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 239 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 240 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 241 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 242 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 243 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 244 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 245 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 246 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 247 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 248 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 249 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 250 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 251 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 252 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 253 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 254 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 255 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 256 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 257 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 258 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 259 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 260 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 261 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 262 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 263 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 264 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 265 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 266 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 267 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 268 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 269 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 270 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 271 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 272 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 273 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 274 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 275 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 276 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 277 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 278 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 279 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 280 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 281 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 282 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 283 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 284 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 285 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 286 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 287 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 288 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 289 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 290 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 291 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 292 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 293 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 294 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 295 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 296 {0x11841039, 0x00, "SiS 966", 0}, 297 {0x11851039, 0x00, "SiS 968", 0}, 298 {0x01861039, 0x00, "SiS 968", 0}, 299 {0x00000000, 0x00, NULL, 0} 300}; 301 302#define recovery_type spriv_field0 303#define RECOVERY_NONE 0 304#define RECOVERY_READ_LOG 1 305#define RECOVERY_REQUEST_SENSE 2 306#define recovery_slot spriv_field1 307 308static int force_ahci = 1; 309TUNABLE_INT("hw.ahci.force", &force_ahci); 310 311static int 312ahci_probe(device_t dev) 313{ 314 char buf[64]; 315 int i, valid = 0; 316 uint32_t devid = pci_get_devid(dev); 317 uint8_t revid = pci_get_revid(dev); 318 319 /* Is this a possible AHCI candidate? */ 320 if (pci_get_class(dev) == PCIC_STORAGE && 321 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 322 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 323 valid = 1; 324 /* Is this a known AHCI chip? */ 325 for (i = 0; ahci_ids[i].id != 0; i++) { 326 if (ahci_ids[i].id == devid && 327 ahci_ids[i].rev <= revid && 328 (valid || (force_ahci == 1 && 329 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 330 /* Do not attach JMicrons with single PCI function. */ 331 if (pci_get_vendor(dev) == 0x197b && 332 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 333 return (ENXIO); 334 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 335 ahci_ids[i].name); 336 device_set_desc_copy(dev, buf); 337 return (BUS_PROBE_VENDOR); 338 } 339 } 340 if (!valid) 341 return (ENXIO); 342 device_set_desc_copy(dev, "AHCI SATA controller"); 343 return (BUS_PROBE_VENDOR); 344} 345 346static int 347ahci_ata_probe(device_t dev) 348{ 349 char buf[64]; 350 int i; 351 uint32_t devid = pci_get_devid(dev); 352 uint8_t revid = pci_get_revid(dev); 353 354 if ((intptr_t)device_get_ivars(dev) >= 0) 355 return (ENXIO); 356 /* Is this a known AHCI chip? */ 357 for (i = 0; ahci_ids[i].id != 0; i++) { 358 if (ahci_ids[i].id == devid && 359 ahci_ids[i].rev <= revid) { 360 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 361 ahci_ids[i].name); 362 device_set_desc_copy(dev, buf); 363 return (BUS_PROBE_VENDOR); 364 } 365 } 366 device_set_desc_copy(dev, "AHCI SATA controller"); 367 return (BUS_PROBE_VENDOR); 368} 369 370static int 371ahci_attach(device_t dev) 372{ 373 struct ahci_controller *ctlr = device_get_softc(dev); 374 device_t child; 375 int error, unit, speed, i; 376 uint32_t devid = pci_get_devid(dev); 377 uint8_t revid = pci_get_revid(dev); 378 u_int32_t version; 379 380 ctlr->dev = dev; 381 i = 0; 382 while (ahci_ids[i].id != 0 && 383 (ahci_ids[i].id != devid || 384 ahci_ids[i].rev > revid)) 385 i++; 386 ctlr->quirks = ahci_ids[i].quirks; 387 resource_int_value(device_get_name(dev), 388 device_get_unit(dev), "ccc", &ctlr->ccc); 389 /* if we have a memory BAR(5) we are likely on an AHCI part */ 390 ctlr->r_rid = PCIR_BAR(5); 391 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 392 &ctlr->r_rid, RF_ACTIVE))) 393 return ENXIO; 394 /* Setup our own memory management for channels. */ 395 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 396 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 397 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 398 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 399 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 400 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 401 return (error); 402 } 403 if ((error = rman_manage_region(&ctlr->sc_iomem, 404 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 405 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 406 rman_fini(&ctlr->sc_iomem); 407 return (error); 408 } 409 pci_enable_busmaster(dev); 410 /* Reset controller */ 411 if ((error = ahci_ctlr_reset(dev)) != 0) { 412 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 413 rman_fini(&ctlr->sc_iomem); 414 return (error); 415 }; 416 /* Get the HW capabilities */ 417 version = ATA_INL(ctlr->r_mem, AHCI_VS); 418 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 419 if (version >= 0x00010200) 420 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 421 if (ctlr->caps & AHCI_CAP_EMS) 422 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 423 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 424 425 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 426 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 427 (ctlr->quirks & AHCI_Q_ALTSIG) && 428 (ctlr->caps & AHCI_CAP_SPM) == 0) 429 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 430 431 if (ctlr->quirks & AHCI_Q_1CH) { 432 ctlr->caps &= ~AHCI_CAP_NPMASK; 433 ctlr->ichannels &= 0x01; 434 } 435 if (ctlr->quirks & AHCI_Q_2CH) { 436 ctlr->caps &= ~AHCI_CAP_NPMASK; 437 ctlr->caps |= 1; 438 ctlr->ichannels &= 0x03; 439 } 440 if (ctlr->quirks & AHCI_Q_4CH) { 441 ctlr->caps &= ~AHCI_CAP_NPMASK; 442 ctlr->caps |= 3; 443 ctlr->ichannels &= 0x0f; 444 } 445 ctlr->channels = MAX(flsl(ctlr->ichannels), 446 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 447 if (ctlr->quirks & AHCI_Q_NOPMP) 448 ctlr->caps &= ~AHCI_CAP_SPM; 449 if (ctlr->quirks & AHCI_Q_NONCQ) 450 ctlr->caps &= ~AHCI_CAP_SNCQ; 451 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 452 ctlr->ccc = 0; 453 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 454 ahci_ctlr_setup(dev); 455 /* Setup interrupts. */ 456 if (ahci_setup_interrupt(dev)) { 457 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 458 rman_fini(&ctlr->sc_iomem); 459 return ENXIO; 460 } 461 /* Announce HW capabilities. */ 462 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 463 device_printf(dev, 464 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 465 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 466 ((version >> 4) & 0xf0) + (version & 0x0f), 467 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 468 ((speed == 1) ? "1.5":((speed == 2) ? "3": 469 ((speed == 3) ? "6":"?"))), 470 (ctlr->caps & AHCI_CAP_SPM) ? 471 "supported" : "not supported", 472 (ctlr->caps & AHCI_CAP_FBSS) ? 473 " with FBS" : ""); 474 if (bootverbose) { 475 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 476 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 477 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 478 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 479 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 480 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 481 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 482 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 483 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 484 ((speed == 1) ? "1.5":((speed == 2) ? "3": 485 ((speed == 3) ? "6":"?")))); 486 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 487 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 488 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 489 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 490 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 491 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 492 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 493 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 494 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 495 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 496 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 497 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 498 } 499 if (bootverbose && version >= 0x00010200) { 500 device_printf(dev, "Caps2:%s%s%s\n", 501 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 502 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 503 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 504 } 505 /* Attach all channels on this controller */ 506 for (unit = 0; unit < ctlr->channels; unit++) { 507 child = device_add_child(dev, "ahcich", -1); 508 if (child == NULL) { 509 device_printf(dev, "failed to add channel device\n"); 510 continue; 511 } 512 device_set_ivars(child, (void *)(intptr_t)unit); 513 if ((ctlr->ichannels & (1 << unit)) == 0) 514 device_disable(child); 515 } 516 if (ctlr->caps & AHCI_CAP_EMS) { 517 child = device_add_child(dev, "ahciem", -1); 518 if (child == NULL) 519 device_printf(dev, "failed to add enclosure device\n"); 520 else 521 device_set_ivars(child, (void *)(intptr_t)-1); 522 } 523 bus_generic_attach(dev); 524 return 0; 525} 526 527static int 528ahci_detach(device_t dev) 529{ 530 struct ahci_controller *ctlr = device_get_softc(dev); 531 int i; 532 533 /* Detach & delete all children */ 534 device_delete_children(dev); 535 536 /* Free interrupts. */ 537 for (i = 0; i < ctlr->numirqs; i++) { 538 if (ctlr->irqs[i].r_irq) { 539 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 540 ctlr->irqs[i].handle); 541 bus_release_resource(dev, SYS_RES_IRQ, 542 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 543 } 544 } 545 pci_release_msi(dev); 546 /* Free memory. */ 547 rman_fini(&ctlr->sc_iomem); 548 if (ctlr->r_mem) 549 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 550 return (0); 551} 552 553static int 554ahci_ctlr_reset(device_t dev) 555{ 556 struct ahci_controller *ctlr = device_get_softc(dev); 557 int timeout; 558 559 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 && 560 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 561 pci_write_config(dev, 0x92, 0x01, 1); 562 /* Enable AHCI mode */ 563 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 564 /* Reset AHCI controller */ 565 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 566 for (timeout = 1000; timeout > 0; timeout--) { 567 DELAY(1000); 568 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 569 break; 570 } 571 if (timeout == 0) { 572 device_printf(dev, "AHCI controller reset failure\n"); 573 return ENXIO; 574 } 575 /* Reenable AHCI mode */ 576 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 577 return (0); 578} 579 580static int 581ahci_ctlr_setup(device_t dev) 582{ 583 struct ahci_controller *ctlr = device_get_softc(dev); 584 /* Clear interrupts */ 585 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 586 /* Configure CCC */ 587 if (ctlr->ccc) { 588 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 589 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 590 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 591 (4 << AHCI_CCCC_CC_SHIFT) | 592 AHCI_CCCC_EN); 593 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 594 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 595 if (bootverbose) { 596 device_printf(dev, 597 "CCC with %dms/4cmd enabled on vector %d\n", 598 ctlr->ccc, ctlr->cccv); 599 } 600 } 601 /* Enable AHCI interrupts */ 602 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 603 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 604 return (0); 605} 606 607static int 608ahci_suspend(device_t dev) 609{ 610 struct ahci_controller *ctlr = device_get_softc(dev); 611 612 bus_generic_suspend(dev); 613 /* Disable interupts, so the state change(s) doesn't trigger */ 614 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 615 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 616 return 0; 617} 618 619static int 620ahci_resume(device_t dev) 621{ 622 int res; 623 624 if ((res = ahci_ctlr_reset(dev)) != 0) 625 return (res); 626 ahci_ctlr_setup(dev); 627 return (bus_generic_resume(dev)); 628} 629 630static int 631ahci_setup_interrupt(device_t dev) 632{ 633 struct ahci_controller *ctlr = device_get_softc(dev); 634 int i, msi = 1; 635 636 /* Process hints. */ 637 resource_int_value(device_get_name(dev), 638 device_get_unit(dev), "msi", &msi); 639 if (msi < 0) 640 msi = 0; 641 else if (msi == 1) 642 msi = min(1, pci_msi_count(dev)); 643 else if (msi > 1) 644 msi = pci_msi_count(dev); 645 /* Allocate MSI if needed/present. */ 646 if (msi && pci_alloc_msi(dev, &msi) == 0) { 647 ctlr->numirqs = msi; 648 } else { 649 msi = 0; 650 ctlr->numirqs = 1; 651 } 652 /* Check for single MSI vector fallback. */ 653 if (ctlr->numirqs > 1 && 654 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 655 device_printf(dev, "Falling back to one MSI\n"); 656 ctlr->numirqs = 1; 657 } 658 /* Allocate all IRQs. */ 659 for (i = 0; i < ctlr->numirqs; i++) { 660 ctlr->irqs[i].ctlr = ctlr; 661 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 662 if (ctlr->numirqs == 1 || i >= ctlr->channels || 663 (ctlr->ccc && i == ctlr->cccv)) 664 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 665 else if (i == ctlr->numirqs - 1) 666 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 667 else 668 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 669 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 670 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 671 device_printf(dev, "unable to map interrupt\n"); 672 return ENXIO; 673 } 674 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 675 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 676 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 677 /* SOS XXX release r_irq */ 678 device_printf(dev, "unable to setup interrupt\n"); 679 return ENXIO; 680 } 681 if (ctlr->numirqs > 1) { 682 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 683 ctlr->irqs[i].handle, 684 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 685 "ch%d" : "%d", i); 686 } 687 } 688 return (0); 689} 690 691/* 692 * Common case interrupt handler. 693 */ 694static void 695ahci_intr(void *data) 696{ 697 struct ahci_controller_irq *irq = data; 698 struct ahci_controller *ctlr = irq->ctlr; 699 u_int32_t is, ise = 0; 700 void *arg; 701 int unit; 702 703 if (irq->mode == AHCI_IRQ_MODE_ALL) { 704 unit = 0; 705 if (ctlr->ccc) 706 is = ctlr->ichannels; 707 else 708 is = ATA_INL(ctlr->r_mem, AHCI_IS); 709 } else { /* AHCI_IRQ_MODE_AFTER */ 710 unit = irq->r_irq_rid - 1; 711 is = ATA_INL(ctlr->r_mem, AHCI_IS); 712 } 713 /* CCC interrupt is edge triggered. */ 714 if (ctlr->ccc) 715 ise = 1 << ctlr->cccv; 716 /* Some controllers have edge triggered IS. */ 717 if (ctlr->quirks & AHCI_Q_EDGEIS) 718 ise |= is; 719 if (ise != 0) 720 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 721 for (; unit < ctlr->channels; unit++) { 722 if ((is & (1 << unit)) != 0 && 723 (arg = ctlr->interrupt[unit].argument)) { 724 ctlr->interrupt[unit].function(arg); 725 } 726 } 727 /* AHCI declares level triggered IS. */ 728 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 729 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 730} 731 732/* 733 * Simplified interrupt handler for multivector MSI mode. 734 */ 735static void 736ahci_intr_one(void *data) 737{ 738 struct ahci_controller_irq *irq = data; 739 struct ahci_controller *ctlr = irq->ctlr; 740 void *arg; 741 int unit; 742 743 unit = irq->r_irq_rid - 1; 744 /* Some controllers have edge triggered IS. */ 745 if (ctlr->quirks & AHCI_Q_EDGEIS) 746 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 747 if ((arg = ctlr->interrupt[unit].argument)) 748 ctlr->interrupt[unit].function(arg); 749 /* AHCI declares level triggered IS. */ 750 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 751 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 752} 753 754static struct resource * 755ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 756 u_long start, u_long end, u_long count, u_int flags) 757{ 758 struct ahci_controller *ctlr = device_get_softc(dev); 759 struct resource *res; 760 long st; 761 int offset, size, unit; 762 763 unit = (intptr_t)device_get_ivars(child); 764 res = NULL; 765 switch (type) { 766 case SYS_RES_MEMORY: 767 if (unit >= 0) { 768 offset = AHCI_OFFSET + (unit << 7); 769 size = 128; 770 } else if (*rid == 0) { 771 offset = AHCI_EM_CTL; 772 size = 4; 773 } else { 774 offset = (ctlr->emloc & 0xffff0000) >> 14; 775 size = (ctlr->emloc & 0x0000ffff) << 2; 776 if (*rid != 1) { 777 if (*rid == 2 && (ctlr->capsem & 778 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 779 offset += size; 780 else 781 break; 782 } 783 } 784 st = rman_get_start(ctlr->r_mem); 785 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 786 st + offset + size - 1, size, RF_ACTIVE, child); 787 if (res) { 788 bus_space_handle_t bsh; 789 bus_space_tag_t bst; 790 bsh = rman_get_bushandle(ctlr->r_mem); 791 bst = rman_get_bustag(ctlr->r_mem); 792 bus_space_subregion(bst, bsh, offset, 128, &bsh); 793 rman_set_bushandle(res, bsh); 794 rman_set_bustag(res, bst); 795 } 796 break; 797 case SYS_RES_IRQ: 798 if (*rid == ATA_IRQ_RID) 799 res = ctlr->irqs[0].r_irq; 800 break; 801 } 802 return (res); 803} 804 805static int 806ahci_release_resource(device_t dev, device_t child, int type, int rid, 807 struct resource *r) 808{ 809 810 switch (type) { 811 case SYS_RES_MEMORY: 812 rman_release_resource(r); 813 return (0); 814 case SYS_RES_IRQ: 815 if (rid != ATA_IRQ_RID) 816 return ENOENT; 817 return (0); 818 } 819 return (EINVAL); 820} 821 822static int 823ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 824 int flags, driver_filter_t *filter, driver_intr_t *function, 825 void *argument, void **cookiep) 826{ 827 struct ahci_controller *ctlr = device_get_softc(dev); 828 int unit = (intptr_t)device_get_ivars(child); 829 830 if (filter != NULL) { 831 printf("ahci.c: we cannot use a filter here\n"); 832 return (EINVAL); 833 } 834 ctlr->interrupt[unit].function = function; 835 ctlr->interrupt[unit].argument = argument; 836 return (0); 837} 838 839static int 840ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 841 void *cookie) 842{ 843 struct ahci_controller *ctlr = device_get_softc(dev); 844 int unit = (intptr_t)device_get_ivars(child); 845 846 ctlr->interrupt[unit].function = NULL; 847 ctlr->interrupt[unit].argument = NULL; 848 return (0); 849} 850 851static int 852ahci_print_child(device_t dev, device_t child) 853{ 854 int retval, channel; 855 856 retval = bus_print_child_header(dev, child); 857 channel = (int)(intptr_t)device_get_ivars(child); 858 if (channel >= 0) 859 retval += printf(" at channel %d", channel); 860 retval += bus_print_child_footer(dev, child); 861 return (retval); 862} 863 864static int 865ahci_child_location_str(device_t dev, device_t child, char *buf, 866 size_t buflen) 867{ 868 int channel; 869 870 channel = (int)(intptr_t)device_get_ivars(child); 871 if (channel >= 0) 872 snprintf(buf, buflen, "channel=%d", channel); 873 return (0); 874} 875 876devclass_t ahci_devclass; 877static device_method_t ahci_methods[] = { 878 DEVMETHOD(device_probe, ahci_probe), 879 DEVMETHOD(device_attach, ahci_attach), 880 DEVMETHOD(device_detach, ahci_detach), 881 DEVMETHOD(device_suspend, ahci_suspend), 882 DEVMETHOD(device_resume, ahci_resume), 883 DEVMETHOD(bus_print_child, ahci_print_child), 884 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 885 DEVMETHOD(bus_release_resource, ahci_release_resource), 886 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 887 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 888 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 889 { 0, 0 } 890}; 891static driver_t ahci_driver = { 892 "ahci", 893 ahci_methods, 894 sizeof(struct ahci_controller) 895}; 896DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 897static device_method_t ahci_ata_methods[] = { 898 DEVMETHOD(device_probe, ahci_ata_probe), 899 DEVMETHOD(device_attach, ahci_attach), 900 DEVMETHOD(device_detach, ahci_detach), 901 DEVMETHOD(device_suspend, ahci_suspend), 902 DEVMETHOD(device_resume, ahci_resume), 903 DEVMETHOD(bus_print_child, ahci_print_child), 904 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 905 DEVMETHOD(bus_release_resource, ahci_release_resource), 906 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 907 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 908 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 909 { 0, 0 } 910}; 911static driver_t ahci_ata_driver = { 912 "ahci", 913 ahci_ata_methods, 914 sizeof(struct ahci_controller) 915}; 916DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 917MODULE_VERSION(ahci, 1); 918MODULE_DEPEND(ahci, cam, 1, 1, 1); 919 920static int 921ahci_ch_probe(device_t dev) 922{ 923 924 device_set_desc_copy(dev, "AHCI channel"); 925 return (0); 926} 927 928static int 929ahci_ch_attach(device_t dev) 930{ 931 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 932 struct ahci_channel *ch = device_get_softc(dev); 933 struct cam_devq *devq; 934 int rid, error, i, sata_rev = 0; 935 u_int32_t version; 936 937 ch->dev = dev; 938 ch->unit = (intptr_t)device_get_ivars(dev); 939 ch->caps = ctlr->caps; 940 ch->caps2 = ctlr->caps2; 941 ch->quirks = ctlr->quirks; 942 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 943 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 944 resource_int_value(device_get_name(dev), 945 device_get_unit(dev), "pm_level", &ch->pm_level); 946 if (ch->pm_level > 3) 947 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 948 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 949 /* Limit speed for my onboard JMicron external port. 950 * It is not eSATA really. */ 951 if (pci_get_devid(ctlr->dev) == 0x2363197b && 952 pci_get_subvendor(ctlr->dev) == 0x1043 && 953 pci_get_subdevice(ctlr->dev) == 0x81e4 && 954 ch->unit == 0) 955 sata_rev = 1; 956 if (ch->quirks & AHCI_Q_SATA2) 957 sata_rev = 2; 958 resource_int_value(device_get_name(dev), 959 device_get_unit(dev), "sata_rev", &sata_rev); 960 for (i = 0; i < 16; i++) { 961 ch->user[i].revision = sata_rev; 962 ch->user[i].mode = 0; 963 ch->user[i].bytecount = 8192; 964 ch->user[i].tags = ch->numslots; 965 ch->user[i].caps = 0; 966 ch->curr[i] = ch->user[i]; 967 if (ch->pm_level) { 968 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 969 CTS_SATA_CAPS_H_APST | 970 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 971 } 972 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 973 CTS_SATA_CAPS_H_AN; 974 } 975 rid = 0; 976 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 977 &rid, RF_ACTIVE))) 978 return (ENXIO); 979 ahci_dmainit(dev); 980 ahci_slotsalloc(dev); 981 ahci_ch_init(dev); 982 mtx_lock(&ch->mtx); 983 rid = ATA_IRQ_RID; 984 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 985 &rid, RF_SHAREABLE | RF_ACTIVE))) { 986 device_printf(dev, "Unable to map interrupt\n"); 987 error = ENXIO; 988 goto err0; 989 } 990 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 991 ahci_ch_intr_locked, dev, &ch->ih))) { 992 device_printf(dev, "Unable to setup interrupt\n"); 993 error = ENXIO; 994 goto err1; 995 } 996 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 997 version = ATA_INL(ctlr->r_mem, AHCI_VS); 998 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 999 ch->chcaps |= AHCI_P_CMD_FBSCP; 1000 if (bootverbose) { 1001 device_printf(dev, "Caps:%s%s%s%s%s\n", 1002 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1003 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1004 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1005 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1006 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1007 } 1008 /* Create the device queue for our SIM. */ 1009 devq = cam_simq_alloc(ch->numslots); 1010 if (devq == NULL) { 1011 device_printf(dev, "Unable to allocate simq\n"); 1012 error = ENOMEM; 1013 goto err1; 1014 } 1015 /* Construct SIM entry */ 1016 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1017 device_get_unit(dev), &ch->mtx, 1018 min(2, ch->numslots), 1019 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1020 devq); 1021 if (ch->sim == NULL) { 1022 cam_simq_free(devq); 1023 device_printf(dev, "unable to allocate sim\n"); 1024 error = ENOMEM; 1025 goto err1; 1026 } 1027 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1028 device_printf(dev, "unable to register xpt bus\n"); 1029 error = ENXIO; 1030 goto err2; 1031 } 1032 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1033 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1034 device_printf(dev, "unable to create path\n"); 1035 error = ENXIO; 1036 goto err3; 1037 } 1038 if (ch->pm_level > 3) { 1039 callout_reset(&ch->pm_timer, 1040 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1041 ahci_ch_pm, dev); 1042 } 1043 mtx_unlock(&ch->mtx); 1044 return (0); 1045 1046err3: 1047 xpt_bus_deregister(cam_sim_path(ch->sim)); 1048err2: 1049 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1050err1: 1051 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1052err0: 1053 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1054 mtx_unlock(&ch->mtx); 1055 mtx_destroy(&ch->mtx); 1056 return (error); 1057} 1058 1059static int 1060ahci_ch_detach(device_t dev) 1061{ 1062 struct ahci_channel *ch = device_get_softc(dev); 1063 1064 mtx_lock(&ch->mtx); 1065 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1066 /* Forget about reset. */ 1067 if (ch->resetting) { 1068 ch->resetting = 0; 1069 xpt_release_simq(ch->sim, TRUE); 1070 } 1071 xpt_free_path(ch->path); 1072 xpt_bus_deregister(cam_sim_path(ch->sim)); 1073 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1074 mtx_unlock(&ch->mtx); 1075 1076 if (ch->pm_level > 3) 1077 callout_drain(&ch->pm_timer); 1078 callout_drain(&ch->reset_timer); 1079 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1080 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1081 1082 ahci_ch_deinit(dev); 1083 ahci_slotsfree(dev); 1084 ahci_dmafini(dev); 1085 1086 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1087 mtx_destroy(&ch->mtx); 1088 return (0); 1089} 1090 1091static int 1092ahci_ch_init(device_t dev) 1093{ 1094 struct ahci_channel *ch = device_get_softc(dev); 1095 uint64_t work; 1096 1097 /* Disable port interrupts */ 1098 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1099 /* Setup work areas */ 1100 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1101 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1102 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1103 work = ch->dma.rfis_bus; 1104 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1105 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1106 /* Activate the channel and power/spin up device */ 1107 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1108 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1109 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1110 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1111 ahci_start_fr(dev); 1112 ahci_start(dev, 1); 1113 return (0); 1114} 1115 1116static int 1117ahci_ch_deinit(device_t dev) 1118{ 1119 struct ahci_channel *ch = device_get_softc(dev); 1120 1121 /* Disable port interrupts. */ 1122 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1123 /* Reset command register. */ 1124 ahci_stop(dev); 1125 ahci_stop_fr(dev); 1126 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1127 /* Allow everything, including partial and slumber modes. */ 1128 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1129 /* Request slumber mode transition and give some time to get there. */ 1130 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1131 DELAY(100); 1132 /* Disable PHY. */ 1133 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1134 return (0); 1135} 1136 1137static int 1138ahci_ch_suspend(device_t dev) 1139{ 1140 struct ahci_channel *ch = device_get_softc(dev); 1141 1142 mtx_lock(&ch->mtx); 1143 xpt_freeze_simq(ch->sim, 1); 1144 /* Forget about reset. */ 1145 if (ch->resetting) { 1146 ch->resetting = 0; 1147 callout_stop(&ch->reset_timer); 1148 xpt_release_simq(ch->sim, TRUE); 1149 } 1150 while (ch->oslots) 1151 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1152 ahci_ch_deinit(dev); 1153 mtx_unlock(&ch->mtx); 1154 return (0); 1155} 1156 1157static int 1158ahci_ch_resume(device_t dev) 1159{ 1160 struct ahci_channel *ch = device_get_softc(dev); 1161 1162 mtx_lock(&ch->mtx); 1163 ahci_ch_init(dev); 1164 ahci_reset(dev); 1165 xpt_release_simq(ch->sim, TRUE); 1166 mtx_unlock(&ch->mtx); 1167 return (0); 1168} 1169 1170devclass_t ahcich_devclass; 1171static device_method_t ahcich_methods[] = { 1172 DEVMETHOD(device_probe, ahci_ch_probe), 1173 DEVMETHOD(device_attach, ahci_ch_attach), 1174 DEVMETHOD(device_detach, ahci_ch_detach), 1175 DEVMETHOD(device_suspend, ahci_ch_suspend), 1176 DEVMETHOD(device_resume, ahci_ch_resume), 1177 { 0, 0 } 1178}; 1179static driver_t ahcich_driver = { 1180 "ahcich", 1181 ahcich_methods, 1182 sizeof(struct ahci_channel) 1183}; 1184DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1185 1186struct ahci_dc_cb_args { 1187 bus_addr_t maddr; 1188 int error; 1189}; 1190 1191static void 1192ahci_dmainit(device_t dev) 1193{ 1194 struct ahci_channel *ch = device_get_softc(dev); 1195 struct ahci_dc_cb_args dcba; 1196 size_t rfsize; 1197 1198 if (ch->caps & AHCI_CAP_64BIT) 1199 ch->dma.max_address = BUS_SPACE_MAXADDR; 1200 else 1201 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1202 /* Command area. */ 1203 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1204 ch->dma.max_address, BUS_SPACE_MAXADDR, 1205 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1206 0, NULL, NULL, &ch->dma.work_tag)) 1207 goto error; 1208 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1209 &ch->dma.work_map)) 1210 goto error; 1211 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1212 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1213 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1214 goto error; 1215 } 1216 ch->dma.work_bus = dcba.maddr; 1217 /* FIS receive area. */ 1218 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1219 rfsize = 4096; 1220 else 1221 rfsize = 256; 1222 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1223 ch->dma.max_address, BUS_SPACE_MAXADDR, 1224 NULL, NULL, rfsize, 1, rfsize, 1225 0, NULL, NULL, &ch->dma.rfis_tag)) 1226 goto error; 1227 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1228 &ch->dma.rfis_map)) 1229 goto error; 1230 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1231 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1232 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1233 goto error; 1234 } 1235 ch->dma.rfis_bus = dcba.maddr; 1236 /* Data area. */ 1237 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1238 ch->dma.max_address, BUS_SPACE_MAXADDR, 1239 NULL, NULL, 1240 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1241 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1242 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1243 goto error; 1244 } 1245 return; 1246 1247error: 1248 device_printf(dev, "WARNING - DMA initialization failed\n"); 1249 ahci_dmafini(dev); 1250} 1251 1252static void 1253ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1254{ 1255 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1256 1257 if (!(dcba->error = error)) 1258 dcba->maddr = segs[0].ds_addr; 1259} 1260 1261static void 1262ahci_dmafini(device_t dev) 1263{ 1264 struct ahci_channel *ch = device_get_softc(dev); 1265 1266 if (ch->dma.data_tag) { 1267 bus_dma_tag_destroy(ch->dma.data_tag); 1268 ch->dma.data_tag = NULL; 1269 } 1270 if (ch->dma.rfis_bus) { 1271 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1272 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1273 ch->dma.rfis_bus = 0; 1274 ch->dma.rfis_map = NULL; 1275 ch->dma.rfis = NULL; 1276 } 1277 if (ch->dma.work_bus) { 1278 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1279 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1280 ch->dma.work_bus = 0; 1281 ch->dma.work_map = NULL; 1282 ch->dma.work = NULL; 1283 } 1284 if (ch->dma.work_tag) { 1285 bus_dma_tag_destroy(ch->dma.work_tag); 1286 ch->dma.work_tag = NULL; 1287 } 1288} 1289 1290static void 1291ahci_slotsalloc(device_t dev) 1292{ 1293 struct ahci_channel *ch = device_get_softc(dev); 1294 int i; 1295 1296 /* Alloc and setup command/dma slots */ 1297 bzero(ch->slot, sizeof(ch->slot)); 1298 for (i = 0; i < ch->numslots; i++) { 1299 struct ahci_slot *slot = &ch->slot[i]; 1300 1301 slot->dev = dev; 1302 slot->slot = i; 1303 slot->state = AHCI_SLOT_EMPTY; 1304 slot->ccb = NULL; 1305 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1306 1307 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1308 device_printf(ch->dev, "FAILURE - create data_map\n"); 1309 } 1310} 1311 1312static void 1313ahci_slotsfree(device_t dev) 1314{ 1315 struct ahci_channel *ch = device_get_softc(dev); 1316 int i; 1317 1318 /* Free all dma slots */ 1319 for (i = 0; i < ch->numslots; i++) { 1320 struct ahci_slot *slot = &ch->slot[i]; 1321 1322 callout_drain(&slot->timeout); 1323 if (slot->dma.data_map) { 1324 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1325 slot->dma.data_map = NULL; 1326 } 1327 } 1328} 1329 1330static int 1331ahci_phy_check_events(device_t dev, u_int32_t serr) 1332{ 1333 struct ahci_channel *ch = device_get_softc(dev); 1334 1335 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1336 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1337 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1338 union ccb *ccb; 1339 1340 if (bootverbose) { 1341 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1342 device_printf(dev, "CONNECT requested\n"); 1343 else 1344 device_printf(dev, "DISCONNECT requested\n"); 1345 } 1346 ahci_reset(dev); 1347 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1348 return (0); 1349 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1350 cam_sim_path(ch->sim), 1351 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1352 xpt_free_ccb(ccb); 1353 return (0); 1354 } 1355 xpt_rescan(ccb); 1356 return (1); 1357 } 1358 return (0); 1359} 1360 1361static void 1362ahci_cpd_check_events(device_t dev) 1363{ 1364 struct ahci_channel *ch = device_get_softc(dev); 1365 u_int32_t status; 1366 union ccb *ccb; 1367 1368 if (ch->pm_level == 0) 1369 return; 1370 1371 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1372 if ((status & AHCI_P_CMD_CPD) == 0) 1373 return; 1374 1375 if (bootverbose) { 1376 if (status & AHCI_P_CMD_CPS) { 1377 device_printf(dev, "COLD CONNECT requested\n"); 1378 } else 1379 device_printf(dev, "COLD DISCONNECT requested\n"); 1380 } 1381 ahci_reset(dev); 1382 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1383 return; 1384 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1385 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1386 xpt_free_ccb(ccb); 1387 return; 1388 } 1389 xpt_rescan(ccb); 1390} 1391 1392static void 1393ahci_notify_events(device_t dev, u_int32_t status) 1394{ 1395 struct ahci_channel *ch = device_get_softc(dev); 1396 struct cam_path *dpath; 1397 int i; 1398 1399 if (ch->caps & AHCI_CAP_SSNTF) 1400 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1401 if (bootverbose) 1402 device_printf(dev, "SNTF 0x%04x\n", status); 1403 for (i = 0; i < 16; i++) { 1404 if ((status & (1 << i)) == 0) 1405 continue; 1406 if (xpt_create_path(&dpath, NULL, 1407 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1408 xpt_async(AC_SCSI_AEN, dpath, NULL); 1409 xpt_free_path(dpath); 1410 } 1411 } 1412} 1413 1414static void 1415ahci_ch_intr_locked(void *data) 1416{ 1417 device_t dev = (device_t)data; 1418 struct ahci_channel *ch = device_get_softc(dev); 1419 1420 mtx_lock(&ch->mtx); 1421 xpt_batch_start(ch->sim); 1422 ahci_ch_intr(data); 1423 xpt_batch_done(ch->sim); 1424 mtx_unlock(&ch->mtx); 1425} 1426 1427static void 1428ahci_ch_pm(void *arg) 1429{ 1430 device_t dev = (device_t)arg; 1431 struct ahci_channel *ch = device_get_softc(dev); 1432 uint32_t work; 1433 1434 if (ch->numrslots != 0) 1435 return; 1436 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1437 if (ch->pm_level == 4) 1438 work |= AHCI_P_CMD_PARTIAL; 1439 else 1440 work |= AHCI_P_CMD_SLUMBER; 1441 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1442} 1443 1444static void 1445ahci_ch_intr(void *data) 1446{ 1447 device_t dev = (device_t)data; 1448 struct ahci_channel *ch = device_get_softc(dev); 1449 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1450 enum ahci_err_type et; 1451 int i, ccs, port, reset = 0; 1452 1453 /* Read and clear interrupt statuses. */ 1454 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1455 if (istatus == 0) 1456 return; 1457 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1458 /* Read command statuses. */ 1459 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1460 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1461 if (istatus & AHCI_P_IX_SDB) { 1462 if (ch->caps & AHCI_CAP_SSNTF) 1463 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1464 else if (ch->fbs_enabled) { 1465 u_int8_t *fis = ch->dma.rfis + 0x58; 1466 1467 for (i = 0; i < 16; i++) { 1468 if (fis[1] & 0x80) { 1469 fis[1] &= 0x7f; 1470 sntf |= 1 << i; 1471 } 1472 fis += 256; 1473 } 1474 } else { 1475 u_int8_t *fis = ch->dma.rfis + 0x58; 1476 1477 if (fis[1] & 0x80) 1478 sntf = (1 << (fis[1] & 0x0f)); 1479 } 1480 } 1481 /* Process PHY events */ 1482 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1483 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1484 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1485 if (serr) { 1486 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1487 reset = ahci_phy_check_events(dev, serr); 1488 } 1489 } 1490 /* Process cold presence detection events */ 1491 if ((istatus & AHCI_P_IX_CPD) && !reset) 1492 ahci_cpd_check_events(dev); 1493 /* Process command errors */ 1494 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1495 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1496 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1497 >> AHCI_P_CMD_CCS_SHIFT; 1498//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1499// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1500// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1501 port = -1; 1502 if (ch->fbs_enabled) { 1503 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1504 if (fbs & AHCI_P_FBS_SDE) { 1505 port = (fbs & AHCI_P_FBS_DWE) 1506 >> AHCI_P_FBS_DWE_SHIFT; 1507 } else { 1508 for (i = 0; i < 16; i++) { 1509 if (ch->numrslotspd[i] == 0) 1510 continue; 1511 if (port == -1) 1512 port = i; 1513 else if (port != i) { 1514 port = -2; 1515 break; 1516 } 1517 } 1518 } 1519 } 1520 err = ch->rslots & (cstatus | sstatus); 1521 } else { 1522 ccs = 0; 1523 err = 0; 1524 port = -1; 1525 } 1526 /* Complete all successfull commands. */ 1527 ok = ch->rslots & ~(cstatus | sstatus); 1528 for (i = 0; i < ch->numslots; i++) { 1529 if ((ok >> i) & 1) 1530 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1531 } 1532 /* On error, complete the rest of commands with error statuses. */ 1533 if (err) { 1534 if (ch->frozen) { 1535 union ccb *fccb = ch->frozen; 1536 ch->frozen = NULL; 1537 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1538 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1539 xpt_freeze_devq(fccb->ccb_h.path, 1); 1540 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1541 } 1542 xpt_done(fccb); 1543 } 1544 for (i = 0; i < ch->numslots; i++) { 1545 /* XXX: reqests in loading state. */ 1546 if (((err >> i) & 1) == 0) 1547 continue; 1548 if (port >= 0 && 1549 ch->slot[i].ccb->ccb_h.target_id != port) 1550 continue; 1551 if (istatus & AHCI_P_IX_TFE) { 1552 if (port != -2) { 1553 /* Task File Error */ 1554 if (ch->numtslotspd[ 1555 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1556 /* Untagged operation. */ 1557 if (i == ccs) 1558 et = AHCI_ERR_TFE; 1559 else 1560 et = AHCI_ERR_INNOCENT; 1561 } else { 1562 /* Tagged operation. */ 1563 et = AHCI_ERR_NCQ; 1564 } 1565 } else { 1566 et = AHCI_ERR_TFE; 1567 ch->fatalerr = 1; 1568 } 1569 } else if (istatus & AHCI_P_IX_IF) { 1570 if (ch->numtslots == 0 && i != ccs && port != -2) 1571 et = AHCI_ERR_INNOCENT; 1572 else 1573 et = AHCI_ERR_SATA; 1574 } else 1575 et = AHCI_ERR_INVALID; 1576 ahci_end_transaction(&ch->slot[i], et); 1577 } 1578 /* 1579 * We can't reinit port if there are some other 1580 * commands active, use resume to complete them. 1581 */ 1582 if (ch->rslots != 0 && !ch->recoverycmd) 1583 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1584 } 1585 /* Process NOTIFY events */ 1586 if (sntf) 1587 ahci_notify_events(dev, sntf); 1588} 1589 1590/* Must be called with channel locked. */ 1591static int 1592ahci_check_collision(device_t dev, union ccb *ccb) 1593{ 1594 struct ahci_channel *ch = device_get_softc(dev); 1595 int t = ccb->ccb_h.target_id; 1596 1597 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1598 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1599 /* Tagged command while we have no supported tag free. */ 1600 if (((~ch->oslots) & (0xffffffff >> (32 - 1601 ch->curr[t].tags))) == 0) 1602 return (1); 1603 /* If we have FBS */ 1604 if (ch->fbs_enabled) { 1605 /* Tagged command while untagged are active. */ 1606 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1607 return (1); 1608 } else { 1609 /* Tagged command while untagged are active. */ 1610 if (ch->numrslots != 0 && ch->numtslots == 0) 1611 return (1); 1612 /* Tagged command while tagged to other target is active. */ 1613 if (ch->numtslots != 0 && 1614 ch->taggedtarget != ccb->ccb_h.target_id) 1615 return (1); 1616 } 1617 } else { 1618 /* If we have FBS */ 1619 if (ch->fbs_enabled) { 1620 /* Untagged command while tagged are active. */ 1621 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1622 return (1); 1623 } else { 1624 /* Untagged command while tagged are active. */ 1625 if (ch->numrslots != 0 && ch->numtslots != 0) 1626 return (1); 1627 } 1628 } 1629 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1630 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1631 /* Atomic command while anything active. */ 1632 if (ch->numrslots != 0) 1633 return (1); 1634 } 1635 /* We have some atomic command running. */ 1636 if (ch->aslots != 0) 1637 return (1); 1638 return (0); 1639} 1640 1641/* Must be called with channel locked. */ 1642static void 1643ahci_begin_transaction(device_t dev, union ccb *ccb) 1644{ 1645 struct ahci_channel *ch = device_get_softc(dev); 1646 struct ahci_slot *slot; 1647 int tag, tags; 1648 1649 /* Choose empty slot. */ 1650 tags = ch->numslots; 1651 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1652 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1653 tags = ch->curr[ccb->ccb_h.target_id].tags; 1654 tag = ch->lastslot; 1655 while (1) { 1656 if (tag >= tags) 1657 tag = 0; 1658 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1659 break; 1660 tag++; 1661 }; 1662 ch->lastslot = tag; 1663 /* Occupy chosen slot. */ 1664 slot = &ch->slot[tag]; 1665 slot->ccb = ccb; 1666 /* Stop PM timer. */ 1667 if (ch->numrslots == 0 && ch->pm_level > 3) 1668 callout_stop(&ch->pm_timer); 1669 /* Update channel stats. */ 1670 ch->oslots |= (1 << slot->slot); 1671 ch->numrslots++; 1672 ch->numrslotspd[ccb->ccb_h.target_id]++; 1673 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1674 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1675 ch->numtslots++; 1676 ch->numtslotspd[ccb->ccb_h.target_id]++; 1677 ch->taggedtarget = ccb->ccb_h.target_id; 1678 } 1679 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1680 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1681 ch->aslots |= (1 << slot->slot); 1682 slot->dma.nsegs = 0; 1683 /* If request moves data, setup and load SG list */ 1684 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1685 void *buf; 1686 bus_size_t size; 1687 1688 slot->state = AHCI_SLOT_LOADING; 1689 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1690 buf = ccb->ataio.data_ptr; 1691 size = ccb->ataio.dxfer_len; 1692 } else { 1693 buf = ccb->csio.data_ptr; 1694 size = ccb->csio.dxfer_len; 1695 } 1696 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1697 buf, size, ahci_dmasetprd, slot, 0); 1698 } else 1699 ahci_execute_transaction(slot); 1700} 1701 1702/* Locked by busdma engine. */ 1703static void 1704ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1705{ 1706 struct ahci_slot *slot = arg; 1707 struct ahci_channel *ch = device_get_softc(slot->dev); 1708 struct ahci_cmd_tab *ctp; 1709 struct ahci_dma_prd *prd; 1710 int i; 1711 1712 if (error) { 1713 device_printf(slot->dev, "DMA load error\n"); 1714 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1715 return; 1716 } 1717 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1718 /* Get a piece of the workspace for this request */ 1719 ctp = (struct ahci_cmd_tab *) 1720 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1721 /* Fill S/G table */ 1722 prd = &ctp->prd_tab[0]; 1723 for (i = 0; i < nsegs; i++) { 1724 prd[i].dba = htole64(segs[i].ds_addr); 1725 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1726 } 1727 slot->dma.nsegs = nsegs; 1728 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1729 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1730 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1731 ahci_execute_transaction(slot); 1732} 1733 1734/* Must be called with channel locked. */ 1735static void 1736ahci_execute_transaction(struct ahci_slot *slot) 1737{ 1738 device_t dev = slot->dev; 1739 struct ahci_channel *ch = device_get_softc(dev); 1740 struct ahci_cmd_tab *ctp; 1741 struct ahci_cmd_list *clp; 1742 union ccb *ccb = slot->ccb; 1743 int port = ccb->ccb_h.target_id & 0x0f; 1744 int fis_size, i, softreset; 1745 uint8_t *fis = ch->dma.rfis + 0x40; 1746 uint8_t val; 1747 1748 /* Get a piece of the workspace for this request */ 1749 ctp = (struct ahci_cmd_tab *) 1750 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1751 /* Setup the FIS for this request */ 1752 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1753 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1754 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1755 return; 1756 } 1757 /* Setup the command list entry */ 1758 clp = (struct ahci_cmd_list *) 1759 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1760 clp->cmd_flags = htole16( 1761 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1762 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1763 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1764 (fis_size / sizeof(u_int32_t)) | 1765 (port << 12)); 1766 clp->prd_length = htole16(slot->dma.nsegs); 1767 /* Special handling for Soft Reset command. */ 1768 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1769 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1770 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1771 softreset = 1; 1772 /* Kick controller into sane state */ 1773 ahci_stop(dev); 1774 ahci_clo(dev); 1775 ahci_start(dev, 0); 1776 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1777 } else { 1778 softreset = 2; 1779 /* Prepare FIS receive area for check. */ 1780 for (i = 0; i < 20; i++) 1781 fis[i] = 0xff; 1782 } 1783 } else 1784 softreset = 0; 1785 clp->bytecount = 0; 1786 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1787 (AHCI_CT_SIZE * slot->slot)); 1788 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1789 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1790 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1791 BUS_DMASYNC_PREREAD); 1792 /* Set ACTIVE bit for NCQ commands. */ 1793 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1794 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1795 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1796 } 1797 /* If FBS is enabled, set PMP port. */ 1798 if (ch->fbs_enabled) { 1799 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1800 (port << AHCI_P_FBS_DEV_SHIFT)); 1801 } 1802 /* Issue command to the controller. */ 1803 slot->state = AHCI_SLOT_RUNNING; 1804 ch->rslots |= (1 << slot->slot); 1805 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1806 /* Device reset commands doesn't interrupt. Poll them. */ 1807 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1808 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1809 int count, timeout = ccb->ccb_h.timeout * 100; 1810 enum ahci_err_type et = AHCI_ERR_NONE; 1811 1812 for (count = 0; count < timeout; count++) { 1813 DELAY(10); 1814 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1815 break; 1816 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1817 softreset != 1) { 1818#if 0 1819 device_printf(ch->dev, 1820 "Poll error on slot %d, TFD: %04x\n", 1821 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1822#endif 1823 et = AHCI_ERR_TFE; 1824 break; 1825 } 1826 /* Workaround for ATI SB600/SB700 chipsets. */ 1827 if (ccb->ccb_h.target_id == 15 && 1828 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1829 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1830 et = AHCI_ERR_TIMEOUT; 1831 break; 1832 } 1833 } 1834 1835 /* Marvell controllers do not wait for readyness. */ 1836 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1837 et == AHCI_ERR_NONE) { 1838 while ((val = fis[2]) & ATA_S_BUSY) { 1839 DELAY(10); 1840 if (count++ >= timeout) 1841 break; 1842 } 1843 } 1844 1845 if (timeout && (count >= timeout)) { 1846 device_printf(dev, "Poll timeout on slot %d port %d\n", 1847 slot->slot, port); 1848 device_printf(dev, "is %08x cs %08x ss %08x " 1849 "rs %08x tfd %02x serr %08x cmd %08x\n", 1850 ATA_INL(ch->r_mem, AHCI_P_IS), 1851 ATA_INL(ch->r_mem, AHCI_P_CI), 1852 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1853 ATA_INL(ch->r_mem, AHCI_P_TFD), 1854 ATA_INL(ch->r_mem, AHCI_P_SERR), 1855 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1856 et = AHCI_ERR_TIMEOUT; 1857 } 1858 1859 /* Kick controller into sane state and enable FBS. */ 1860 if (softreset == 2) 1861 ch->eslots |= (1 << slot->slot); 1862 ahci_end_transaction(slot, et); 1863 return; 1864 } 1865 /* Start command execution timeout */ 1866 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1867 (timeout_t*)ahci_timeout, slot); 1868 return; 1869} 1870 1871/* Must be called with channel locked. */ 1872static void 1873ahci_process_timeout(device_t dev) 1874{ 1875 struct ahci_channel *ch = device_get_softc(dev); 1876 int i; 1877 1878 mtx_assert(&ch->mtx, MA_OWNED); 1879 /* Handle the rest of commands. */ 1880 for (i = 0; i < ch->numslots; i++) { 1881 /* Do we have a running request on slot? */ 1882 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1883 continue; 1884 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1885 } 1886} 1887 1888/* Must be called with channel locked. */ 1889static void 1890ahci_rearm_timeout(device_t dev) 1891{ 1892 struct ahci_channel *ch = device_get_softc(dev); 1893 int i; 1894 1895 mtx_assert(&ch->mtx, MA_OWNED); 1896 for (i = 0; i < ch->numslots; i++) { 1897 struct ahci_slot *slot = &ch->slot[i]; 1898 1899 /* Do we have a running request on slot? */ 1900 if (slot->state < AHCI_SLOT_RUNNING) 1901 continue; 1902 if ((ch->toslots & (1 << i)) == 0) 1903 continue; 1904 callout_reset(&slot->timeout, 1905 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1906 (timeout_t*)ahci_timeout, slot); 1907 } 1908} 1909 1910/* Locked by callout mechanism. */ 1911static void 1912ahci_timeout(struct ahci_slot *slot) 1913{ 1914 device_t dev = slot->dev; 1915 struct ahci_channel *ch = device_get_softc(dev); 1916 uint32_t sstatus; 1917 int ccs; 1918 int i; 1919 1920 /* Check for stale timeout. */ 1921 if (slot->state < AHCI_SLOT_RUNNING) 1922 return; 1923 1924 /* Check if slot was not being executed last time we checked. */ 1925 if (slot->state < AHCI_SLOT_EXECUTING) { 1926 /* Check if slot started executing. */ 1927 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1928 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1929 >> AHCI_P_CMD_CCS_SHIFT; 1930 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1931 ch->fbs_enabled || ch->wrongccs) 1932 slot->state = AHCI_SLOT_EXECUTING; 1933 else if ((ch->rslots & (1 << ccs)) == 0) { 1934 ch->wrongccs = 1; 1935 slot->state = AHCI_SLOT_EXECUTING; 1936 } 1937 1938 callout_reset(&slot->timeout, 1939 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1940 (timeout_t*)ahci_timeout, slot); 1941 return; 1942 } 1943 1944 device_printf(dev, "Timeout on slot %d port %d\n", 1945 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1946 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1947 "serr %08x cmd %08x\n", 1948 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1949 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1950 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1951 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1952 1953 /* Handle frozen command. */ 1954 if (ch->frozen) { 1955 union ccb *fccb = ch->frozen; 1956 ch->frozen = NULL; 1957 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1958 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1959 xpt_freeze_devq(fccb->ccb_h.path, 1); 1960 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1961 } 1962 xpt_done(fccb); 1963 } 1964 if (!ch->fbs_enabled && !ch->wrongccs) { 1965 /* Without FBS we know real timeout source. */ 1966 ch->fatalerr = 1; 1967 /* Handle command with timeout. */ 1968 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1969 /* Handle the rest of commands. */ 1970 for (i = 0; i < ch->numslots; i++) { 1971 /* Do we have a running request on slot? */ 1972 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1973 continue; 1974 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1975 } 1976 } else { 1977 /* With FBS we wait for other commands timeout and pray. */ 1978 if (ch->toslots == 0) 1979 xpt_freeze_simq(ch->sim, 1); 1980 ch->toslots |= (1 << slot->slot); 1981 if ((ch->rslots & ~ch->toslots) == 0) 1982 ahci_process_timeout(dev); 1983 else 1984 device_printf(dev, " ... waiting for slots %08x\n", 1985 ch->rslots & ~ch->toslots); 1986 } 1987} 1988 1989/* Must be called with channel locked. */ 1990static void 1991ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1992{ 1993 device_t dev = slot->dev; 1994 struct ahci_channel *ch = device_get_softc(dev); 1995 union ccb *ccb = slot->ccb; 1996 struct ahci_cmd_list *clp; 1997 int lastto; 1998 uint32_t sig; 1999 2000 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2001 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2002 clp = (struct ahci_cmd_list *) 2003 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2004 /* Read result registers to the result struct 2005 * May be incorrect if several commands finished same time, 2006 * so read only when sure or have to. 2007 */ 2008 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2009 struct ata_res *res = &ccb->ataio.res; 2010 2011 if ((et == AHCI_ERR_TFE) || 2012 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2013 u_int8_t *fis = ch->dma.rfis + 0x40; 2014 2015 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2016 BUS_DMASYNC_POSTREAD); 2017 if (ch->fbs_enabled) { 2018 fis += ccb->ccb_h.target_id * 256; 2019 res->status = fis[2]; 2020 res->error = fis[3]; 2021 } else { 2022 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2023 2024 res->status = tfd; 2025 res->error = tfd >> 8; 2026 } 2027 res->lba_low = fis[4]; 2028 res->lba_mid = fis[5]; 2029 res->lba_high = fis[6]; 2030 res->device = fis[7]; 2031 res->lba_low_exp = fis[8]; 2032 res->lba_mid_exp = fis[9]; 2033 res->lba_high_exp = fis[10]; 2034 res->sector_count = fis[12]; 2035 res->sector_count_exp = fis[13]; 2036 2037 /* 2038 * Some weird controllers do not return signature in 2039 * FIS receive area. Read it from PxSIG register. 2040 */ 2041 if ((ch->quirks & AHCI_Q_ALTSIG) && 2042 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2043 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2044 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2045 res->lba_high = sig >> 24; 2046 res->lba_mid = sig >> 16; 2047 res->lba_low = sig >> 8; 2048 res->sector_count = sig; 2049 } 2050 } else 2051 bzero(res, sizeof(*res)); 2052 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2053 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2054 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2055 ccb->ataio.resid = 2056 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2057 } 2058 } else { 2059 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2060 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2061 ccb->csio.resid = 2062 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2063 } 2064 } 2065 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2066 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2067 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2068 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2069 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2070 } 2071 if (et != AHCI_ERR_NONE) 2072 ch->eslots |= (1 << slot->slot); 2073 /* In case of error, freeze device for proper recovery. */ 2074 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2075 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2076 xpt_freeze_devq(ccb->ccb_h.path, 1); 2077 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2078 } 2079 /* Set proper result status. */ 2080 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2081 switch (et) { 2082 case AHCI_ERR_NONE: 2083 ccb->ccb_h.status |= CAM_REQ_CMP; 2084 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2085 ccb->csio.scsi_status = SCSI_STATUS_OK; 2086 break; 2087 case AHCI_ERR_INVALID: 2088 ch->fatalerr = 1; 2089 ccb->ccb_h.status |= CAM_REQ_INVALID; 2090 break; 2091 case AHCI_ERR_INNOCENT: 2092 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2093 break; 2094 case AHCI_ERR_TFE: 2095 case AHCI_ERR_NCQ: 2096 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2097 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2098 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2099 } else { 2100 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2101 } 2102 break; 2103 case AHCI_ERR_SATA: 2104 ch->fatalerr = 1; 2105 if (!ch->recoverycmd) { 2106 xpt_freeze_simq(ch->sim, 1); 2107 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2108 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2109 } 2110 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2111 break; 2112 case AHCI_ERR_TIMEOUT: 2113 if (!ch->recoverycmd) { 2114 xpt_freeze_simq(ch->sim, 1); 2115 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2116 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2117 } 2118 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2119 break; 2120 default: 2121 ch->fatalerr = 1; 2122 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2123 } 2124 /* Free slot. */ 2125 ch->oslots &= ~(1 << slot->slot); 2126 ch->rslots &= ~(1 << slot->slot); 2127 ch->aslots &= ~(1 << slot->slot); 2128 slot->state = AHCI_SLOT_EMPTY; 2129 slot->ccb = NULL; 2130 /* Update channel stats. */ 2131 ch->numrslots--; 2132 ch->numrslotspd[ccb->ccb_h.target_id]--; 2133 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2134 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2135 ch->numtslots--; 2136 ch->numtslotspd[ccb->ccb_h.target_id]--; 2137 } 2138 /* Cancel timeout state if request completed normally. */ 2139 if (et != AHCI_ERR_TIMEOUT) { 2140 lastto = (ch->toslots == (1 << slot->slot)); 2141 ch->toslots &= ~(1 << slot->slot); 2142 if (lastto) 2143 xpt_release_simq(ch->sim, TRUE); 2144 } 2145 /* If it was first request of reset sequence and there is no error, 2146 * proceed to second request. */ 2147 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2148 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2149 (ccb->ataio.cmd.control & ATA_A_RESET) && 2150 et == AHCI_ERR_NONE) { 2151 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2152 ahci_begin_transaction(dev, ccb); 2153 return; 2154 } 2155 /* If it was our READ LOG command - process it. */ 2156 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2157 ahci_process_read_log(dev, ccb); 2158 /* If it was our REQUEST SENSE command - process it. */ 2159 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2160 ahci_process_request_sense(dev, ccb); 2161 /* If it was NCQ or ATAPI command error, put result on hold. */ 2162 } else if (et == AHCI_ERR_NCQ || 2163 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2164 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2165 ch->hold[slot->slot] = ccb; 2166 ch->numhslots++; 2167 } else 2168 xpt_done(ccb); 2169 /* If we have no other active commands, ... */ 2170 if (ch->rslots == 0) { 2171 /* if there was fatal error - reset port. */ 2172 if (ch->toslots != 0 || ch->fatalerr) { 2173 ahci_reset(dev); 2174 } else { 2175 /* if we have slots in error, we can reinit port. */ 2176 if (ch->eslots != 0) { 2177 ahci_stop(dev); 2178 ahci_clo(dev); 2179 ahci_start(dev, 1); 2180 } 2181 /* if there commands on hold, we can do READ LOG. */ 2182 if (!ch->recoverycmd && ch->numhslots) 2183 ahci_issue_recovery(dev); 2184 } 2185 /* If all the rest of commands are in timeout - give them chance. */ 2186 } else if ((ch->rslots & ~ch->toslots) == 0 && 2187 et != AHCI_ERR_TIMEOUT) 2188 ahci_rearm_timeout(dev); 2189 /* Unfreeze frozen command. */ 2190 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2191 union ccb *fccb = ch->frozen; 2192 ch->frozen = NULL; 2193 ahci_begin_transaction(dev, fccb); 2194 xpt_release_simq(ch->sim, TRUE); 2195 } 2196 /* Start PM timer. */ 2197 if (ch->numrslots == 0 && ch->pm_level > 3 && 2198 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2199 callout_schedule(&ch->pm_timer, 2200 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2201 } 2202} 2203 2204static void 2205ahci_issue_recovery(device_t dev) 2206{ 2207 struct ahci_channel *ch = device_get_softc(dev); 2208 union ccb *ccb; 2209 struct ccb_ataio *ataio; 2210 struct ccb_scsiio *csio; 2211 int i; 2212 2213 /* Find some held command. */ 2214 for (i = 0; i < ch->numslots; i++) { 2215 if (ch->hold[i]) 2216 break; 2217 } 2218 ccb = xpt_alloc_ccb_nowait(); 2219 if (ccb == NULL) { 2220 device_printf(dev, "Unable to allocate recovery command\n"); 2221completeall: 2222 /* We can't do anything -- complete held commands. */ 2223 for (i = 0; i < ch->numslots; i++) { 2224 if (ch->hold[i] == NULL) 2225 continue; 2226 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2227 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2228 xpt_done(ch->hold[i]); 2229 ch->hold[i] = NULL; 2230 ch->numhslots--; 2231 } 2232 ahci_reset(dev); 2233 return; 2234 } 2235 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2236 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2237 /* READ LOG */ 2238 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2239 ccb->ccb_h.func_code = XPT_ATA_IO; 2240 ccb->ccb_h.flags = CAM_DIR_IN; 2241 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2242 ataio = &ccb->ataio; 2243 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2244 if (ataio->data_ptr == NULL) { 2245 xpt_free_ccb(ccb); 2246 device_printf(dev, 2247 "Unable to allocate memory for READ LOG command\n"); 2248 goto completeall; 2249 } 2250 ataio->dxfer_len = 512; 2251 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2252 ataio->cmd.flags = CAM_ATAIO_48BIT; 2253 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2254 ataio->cmd.sector_count = 1; 2255 ataio->cmd.sector_count_exp = 0; 2256 ataio->cmd.lba_low = 0x10; 2257 ataio->cmd.lba_mid = 0; 2258 ataio->cmd.lba_mid_exp = 0; 2259 } else { 2260 /* REQUEST SENSE */ 2261 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2262 ccb->ccb_h.recovery_slot = i; 2263 ccb->ccb_h.func_code = XPT_SCSI_IO; 2264 ccb->ccb_h.flags = CAM_DIR_IN; 2265 ccb->ccb_h.status = 0; 2266 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2267 csio = &ccb->csio; 2268 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2269 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2270 csio->cdb_len = 6; 2271 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2272 csio->cdb_io.cdb_bytes[0] = 0x03; 2273 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2274 } 2275 /* Freeze SIM while doing recovery. */ 2276 ch->recoverycmd = 1; 2277 xpt_freeze_simq(ch->sim, 1); 2278 ahci_begin_transaction(dev, ccb); 2279} 2280 2281static void 2282ahci_process_read_log(device_t dev, union ccb *ccb) 2283{ 2284 struct ahci_channel *ch = device_get_softc(dev); 2285 uint8_t *data; 2286 struct ata_res *res; 2287 int i; 2288 2289 ch->recoverycmd = 0; 2290 2291 data = ccb->ataio.data_ptr; 2292 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2293 (data[0] & 0x80) == 0) { 2294 for (i = 0; i < ch->numslots; i++) { 2295 if (!ch->hold[i]) 2296 continue; 2297 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2298 continue; 2299 if ((data[0] & 0x1F) == i) { 2300 res = &ch->hold[i]->ataio.res; 2301 res->status = data[2]; 2302 res->error = data[3]; 2303 res->lba_low = data[4]; 2304 res->lba_mid = data[5]; 2305 res->lba_high = data[6]; 2306 res->device = data[7]; 2307 res->lba_low_exp = data[8]; 2308 res->lba_mid_exp = data[9]; 2309 res->lba_high_exp = data[10]; 2310 res->sector_count = data[12]; 2311 res->sector_count_exp = data[13]; 2312 } else { 2313 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2314 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2315 } 2316 xpt_done(ch->hold[i]); 2317 ch->hold[i] = NULL; 2318 ch->numhslots--; 2319 } 2320 } else { 2321 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2322 device_printf(dev, "Error while READ LOG EXT\n"); 2323 else if ((data[0] & 0x80) == 0) { 2324 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2325 } 2326 for (i = 0; i < ch->numslots; i++) { 2327 if (!ch->hold[i]) 2328 continue; 2329 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2330 continue; 2331 xpt_done(ch->hold[i]); 2332 ch->hold[i] = NULL; 2333 ch->numhslots--; 2334 } 2335 } 2336 free(ccb->ataio.data_ptr, M_AHCI); 2337 xpt_free_ccb(ccb); 2338 xpt_release_simq(ch->sim, TRUE); 2339} 2340 2341static void 2342ahci_process_request_sense(device_t dev, union ccb *ccb) 2343{ 2344 struct ahci_channel *ch = device_get_softc(dev); 2345 int i; 2346 2347 ch->recoverycmd = 0; 2348 2349 i = ccb->ccb_h.recovery_slot; 2350 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2351 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2352 } else { 2353 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2354 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2355 } 2356 xpt_done(ch->hold[i]); 2357 ch->hold[i] = NULL; 2358 ch->numhslots--; 2359 xpt_free_ccb(ccb); 2360 xpt_release_simq(ch->sim, TRUE); 2361} 2362 2363static void 2364ahci_start(device_t dev, int fbs) 2365{ 2366 struct ahci_channel *ch = device_get_softc(dev); 2367 u_int32_t cmd; 2368 2369 /* Clear SATA error register */ 2370 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2371 /* Clear any interrupts pending on this channel */ 2372 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2373 /* Configure FIS-based switching if supported. */ 2374 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2375 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2376 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2377 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2378 } 2379 /* Start operations on this channel */ 2380 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2381 cmd &= ~AHCI_P_CMD_PMA; 2382 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2383 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2384} 2385 2386static void 2387ahci_stop(device_t dev) 2388{ 2389 struct ahci_channel *ch = device_get_softc(dev); 2390 u_int32_t cmd; 2391 int timeout; 2392 2393 /* Kill all activity on this channel */ 2394 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2395 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2396 /* Wait for activity stop. */ 2397 timeout = 0; 2398 do { 2399 DELAY(10); 2400 if (timeout++ > 50000) { 2401 device_printf(dev, "stopping AHCI engine failed\n"); 2402 break; 2403 } 2404 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2405 ch->eslots = 0; 2406} 2407 2408static void 2409ahci_clo(device_t dev) 2410{ 2411 struct ahci_channel *ch = device_get_softc(dev); 2412 u_int32_t cmd; 2413 int timeout; 2414 2415 /* Issue Command List Override if supported */ 2416 if (ch->caps & AHCI_CAP_SCLO) { 2417 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2418 cmd |= AHCI_P_CMD_CLO; 2419 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2420 timeout = 0; 2421 do { 2422 DELAY(10); 2423 if (timeout++ > 50000) { 2424 device_printf(dev, "executing CLO failed\n"); 2425 break; 2426 } 2427 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2428 } 2429} 2430 2431static void 2432ahci_stop_fr(device_t dev) 2433{ 2434 struct ahci_channel *ch = device_get_softc(dev); 2435 u_int32_t cmd; 2436 int timeout; 2437 2438 /* Kill all FIS reception on this channel */ 2439 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2440 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2441 /* Wait for FIS reception stop. */ 2442 timeout = 0; 2443 do { 2444 DELAY(10); 2445 if (timeout++ > 50000) { 2446 device_printf(dev, "stopping AHCI FR engine failed\n"); 2447 break; 2448 } 2449 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2450} 2451 2452static void 2453ahci_start_fr(device_t dev) 2454{ 2455 struct ahci_channel *ch = device_get_softc(dev); 2456 u_int32_t cmd; 2457 2458 /* Start FIS reception on this channel */ 2459 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2460 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2461} 2462 2463static int 2464ahci_wait_ready(device_t dev, int t, int t0) 2465{ 2466 struct ahci_channel *ch = device_get_softc(dev); 2467 int timeout = 0; 2468 uint32_t val; 2469 2470 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2471 (ATA_S_BUSY | ATA_S_DRQ)) { 2472 if (timeout > t) { 2473 if (t != 0) { 2474 device_printf(dev, 2475 "AHCI reset: device not ready after %dms " 2476 "(tfd = %08x)\n", 2477 MAX(t, 0) + t0, val); 2478 } 2479 return (EBUSY); 2480 } 2481 DELAY(1000); 2482 timeout++; 2483 } 2484 if (bootverbose) 2485 device_printf(dev, "AHCI reset: device ready after %dms\n", 2486 timeout + t0); 2487 return (0); 2488} 2489 2490static void 2491ahci_reset_to(void *arg) 2492{ 2493 device_t dev = arg; 2494 struct ahci_channel *ch = device_get_softc(dev); 2495 2496 if (ch->resetting == 0) 2497 return; 2498 ch->resetting--; 2499 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2500 (310 - ch->resetting) * 100) == 0) { 2501 ch->resetting = 0; 2502 ahci_start(dev, 1); 2503 xpt_release_simq(ch->sim, TRUE); 2504 return; 2505 } 2506 if (ch->resetting == 0) { 2507 ahci_clo(dev); 2508 ahci_start(dev, 1); 2509 xpt_release_simq(ch->sim, TRUE); 2510 return; 2511 } 2512 callout_schedule(&ch->reset_timer, hz / 10); 2513} 2514 2515static void 2516ahci_reset(device_t dev) 2517{ 2518 struct ahci_channel *ch = device_get_softc(dev); 2519 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2520 int i; 2521 2522 xpt_freeze_simq(ch->sim, 1); 2523 if (bootverbose) 2524 device_printf(dev, "AHCI reset...\n"); 2525 /* Forget about previous reset. */ 2526 if (ch->resetting) { 2527 ch->resetting = 0; 2528 callout_stop(&ch->reset_timer); 2529 xpt_release_simq(ch->sim, TRUE); 2530 } 2531 /* Requeue freezed command. */ 2532 if (ch->frozen) { 2533 union ccb *fccb = ch->frozen; 2534 ch->frozen = NULL; 2535 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2536 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2537 xpt_freeze_devq(fccb->ccb_h.path, 1); 2538 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2539 } 2540 xpt_done(fccb); 2541 } 2542 /* Kill the engine and requeue all running commands. */ 2543 ahci_stop(dev); 2544 for (i = 0; i < ch->numslots; i++) { 2545 /* Do we have a running request on slot? */ 2546 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2547 continue; 2548 /* XXX; Commands in loading state. */ 2549 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2550 } 2551 for (i = 0; i < ch->numslots; i++) { 2552 if (!ch->hold[i]) 2553 continue; 2554 xpt_done(ch->hold[i]); 2555 ch->hold[i] = NULL; 2556 ch->numhslots--; 2557 } 2558 if (ch->toslots != 0) 2559 xpt_release_simq(ch->sim, TRUE); 2560 ch->eslots = 0; 2561 ch->toslots = 0; 2562 ch->wrongccs = 0; 2563 ch->fatalerr = 0; 2564 /* Tell the XPT about the event */ 2565 xpt_async(AC_BUS_RESET, ch->path, NULL); 2566 /* Disable port interrupts */ 2567 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2568 /* Reset and reconnect PHY, */ 2569 if (!ahci_sata_phy_reset(dev)) { 2570 if (bootverbose) 2571 device_printf(dev, 2572 "AHCI reset: device not found\n"); 2573 ch->devices = 0; 2574 /* Enable wanted port interrupts */ 2575 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2576 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2577 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2578 xpt_release_simq(ch->sim, TRUE); 2579 return; 2580 } 2581 if (bootverbose) 2582 device_printf(dev, "AHCI reset: device found\n"); 2583 /* Wait for clearing busy status. */ 2584 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2585 if (dumping) 2586 ahci_clo(dev); 2587 else 2588 ch->resetting = 310; 2589 } 2590 ch->devices = 1; 2591 /* Enable wanted port interrupts */ 2592 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2593 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2594 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2595 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2596 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2597 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2598 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2599 if (ch->resetting) 2600 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2601 else { 2602 ahci_start(dev, 1); 2603 xpt_release_simq(ch->sim, TRUE); 2604 } 2605} 2606 2607static int 2608ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2609{ 2610 struct ahci_channel *ch = device_get_softc(dev); 2611 u_int8_t *fis = &ctp->cfis[0]; 2612 2613 bzero(ctp->cfis, 64); 2614 fis[0] = 0x27; /* host to device */ 2615 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2616 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2617 fis[1] |= 0x80; 2618 fis[2] = ATA_PACKET_CMD; 2619 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2620 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2621 fis[3] = ATA_F_DMA; 2622 else { 2623 fis[5] = ccb->csio.dxfer_len; 2624 fis[6] = ccb->csio.dxfer_len >> 8; 2625 } 2626 fis[7] = ATA_D_LBA; 2627 fis[15] = ATA_A_4BIT; 2628 bzero(ctp->acmd, 32); 2629 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2630 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2631 ctp->acmd, ccb->csio.cdb_len); 2632 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2633 fis[1] |= 0x80; 2634 fis[2] = ccb->ataio.cmd.command; 2635 fis[3] = ccb->ataio.cmd.features; 2636 fis[4] = ccb->ataio.cmd.lba_low; 2637 fis[5] = ccb->ataio.cmd.lba_mid; 2638 fis[6] = ccb->ataio.cmd.lba_high; 2639 fis[7] = ccb->ataio.cmd.device; 2640 fis[8] = ccb->ataio.cmd.lba_low_exp; 2641 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2642 fis[10] = ccb->ataio.cmd.lba_high_exp; 2643 fis[11] = ccb->ataio.cmd.features_exp; 2644 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2645 fis[12] = tag << 3; 2646 fis[13] = 0; 2647 } else { 2648 fis[12] = ccb->ataio.cmd.sector_count; 2649 fis[13] = ccb->ataio.cmd.sector_count_exp; 2650 } 2651 fis[15] = ATA_A_4BIT; 2652 } else { 2653 fis[15] = ccb->ataio.cmd.control; 2654 } 2655 return (20); 2656} 2657 2658static int 2659ahci_sata_connect(struct ahci_channel *ch) 2660{ 2661 u_int32_t status; 2662 int timeout, found = 0; 2663 2664 /* Wait up to 100ms for "connect well" */ 2665 for (timeout = 0; timeout < 1000 ; timeout++) { 2666 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2667 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2668 found = 1; 2669 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2670 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2671 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2672 break; 2673 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2674 if (bootverbose) { 2675 device_printf(ch->dev, "SATA offline status=%08x\n", 2676 status); 2677 } 2678 return (0); 2679 } 2680 if (found == 0 && timeout >= 100) 2681 break; 2682 DELAY(100); 2683 } 2684 if (timeout >= 1000 || !found) { 2685 if (bootverbose) { 2686 device_printf(ch->dev, 2687 "SATA connect timeout time=%dus status=%08x\n", 2688 timeout * 100, status); 2689 } 2690 return (0); 2691 } 2692 if (bootverbose) { 2693 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2694 timeout * 100, status); 2695 } 2696 /* Clear SATA error register */ 2697 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2698 return (1); 2699} 2700 2701static int 2702ahci_sata_phy_reset(device_t dev) 2703{ 2704 struct ahci_channel *ch = device_get_softc(dev); 2705 int sata_rev; 2706 uint32_t val; 2707 2708 if (ch->listening) { 2709 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2710 val |= AHCI_P_CMD_SUD; 2711 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2712 ch->listening = 0; 2713 } 2714 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2715 if (sata_rev == 1) 2716 val = ATA_SC_SPD_SPEED_GEN1; 2717 else if (sata_rev == 2) 2718 val = ATA_SC_SPD_SPEED_GEN2; 2719 else if (sata_rev == 3) 2720 val = ATA_SC_SPD_SPEED_GEN3; 2721 else 2722 val = 0; 2723 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2724 ATA_SC_DET_RESET | val | 2725 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2726 DELAY(1000); 2727 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2728 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2729 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2730 if (!ahci_sata_connect(ch)) { 2731 if (ch->caps & AHCI_CAP_SSS) { 2732 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2733 val &= ~AHCI_P_CMD_SUD; 2734 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2735 ch->listening = 1; 2736 } else if (ch->pm_level > 0) 2737 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2738 return (0); 2739 } 2740 return (1); 2741} 2742 2743static int 2744ahci_check_ids(device_t dev, union ccb *ccb) 2745{ 2746 struct ahci_channel *ch = device_get_softc(dev); 2747 2748 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2749 ccb->ccb_h.status = CAM_TID_INVALID; 2750 xpt_done(ccb); 2751 return (-1); 2752 } 2753 if (ccb->ccb_h.target_lun != 0) { 2754 ccb->ccb_h.status = CAM_LUN_INVALID; 2755 xpt_done(ccb); 2756 return (-1); 2757 } 2758 return (0); 2759} 2760 2761static void 2762ahciaction(struct cam_sim *sim, union ccb *ccb) 2763{ 2764 device_t dev, parent; 2765 struct ahci_channel *ch; 2766 2767 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2768 ccb->ccb_h.func_code)); 2769 2770 ch = (struct ahci_channel *)cam_sim_softc(sim); 2771 dev = ch->dev; 2772 switch (ccb->ccb_h.func_code) { 2773 /* Common cases first */ 2774 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2775 case XPT_SCSI_IO: 2776 if (ahci_check_ids(dev, ccb)) 2777 return; 2778 if (ch->devices == 0 || 2779 (ch->pm_present == 0 && 2780 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2781 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2782 break; 2783 } 2784 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2785 /* Check for command collision. */ 2786 if (ahci_check_collision(dev, ccb)) { 2787 /* Freeze command. */ 2788 ch->frozen = ccb; 2789 /* We have only one frozen slot, so freeze simq also. */ 2790 xpt_freeze_simq(ch->sim, 1); 2791 return; 2792 } 2793 ahci_begin_transaction(dev, ccb); 2794 return; 2795 case XPT_EN_LUN: /* Enable LUN as a target */ 2796 case XPT_TARGET_IO: /* Execute target I/O request */ 2797 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2798 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2799 case XPT_ABORT: /* Abort the specified CCB */ 2800 /* XXX Implement */ 2801 ccb->ccb_h.status = CAM_REQ_INVALID; 2802 break; 2803 case XPT_SET_TRAN_SETTINGS: 2804 { 2805 struct ccb_trans_settings *cts = &ccb->cts; 2806 struct ahci_device *d; 2807 2808 if (ahci_check_ids(dev, ccb)) 2809 return; 2810 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2811 d = &ch->curr[ccb->ccb_h.target_id]; 2812 else 2813 d = &ch->user[ccb->ccb_h.target_id]; 2814 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2815 d->revision = cts->xport_specific.sata.revision; 2816 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2817 d->mode = cts->xport_specific.sata.mode; 2818 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2819 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2820 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2821 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2822 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2823 ch->pm_present = cts->xport_specific.sata.pm_present; 2824 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2825 d->atapi = cts->xport_specific.sata.atapi; 2826 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2827 d->caps = cts->xport_specific.sata.caps; 2828 ccb->ccb_h.status = CAM_REQ_CMP; 2829 break; 2830 } 2831 case XPT_GET_TRAN_SETTINGS: 2832 /* Get default/user set transfer settings for the target */ 2833 { 2834 struct ccb_trans_settings *cts = &ccb->cts; 2835 struct ahci_device *d; 2836 uint32_t status; 2837 2838 if (ahci_check_ids(dev, ccb)) 2839 return; 2840 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2841 d = &ch->curr[ccb->ccb_h.target_id]; 2842 else 2843 d = &ch->user[ccb->ccb_h.target_id]; 2844 cts->protocol = PROTO_UNSPECIFIED; 2845 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2846 cts->transport = XPORT_SATA; 2847 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2848 cts->proto_specific.valid = 0; 2849 cts->xport_specific.sata.valid = 0; 2850 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2851 (ccb->ccb_h.target_id == 15 || 2852 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2853 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2854 if (status & 0x0f0) { 2855 cts->xport_specific.sata.revision = 2856 (status & 0x0f0) >> 4; 2857 cts->xport_specific.sata.valid |= 2858 CTS_SATA_VALID_REVISION; 2859 } 2860 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2861 if (ch->pm_level) { 2862 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2863 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2864 if (ch->caps2 & AHCI_CAP2_APST) 2865 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2866 } 2867 if ((ch->caps & AHCI_CAP_SNCQ) && 2868 (ch->quirks & AHCI_Q_NOAA) == 0) 2869 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2870 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2871 cts->xport_specific.sata.caps &= 2872 ch->user[ccb->ccb_h.target_id].caps; 2873 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2874 } else { 2875 cts->xport_specific.sata.revision = d->revision; 2876 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2877 cts->xport_specific.sata.caps = d->caps; 2878 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2879 } 2880 cts->xport_specific.sata.mode = d->mode; 2881 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2882 cts->xport_specific.sata.bytecount = d->bytecount; 2883 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2884 cts->xport_specific.sata.pm_present = ch->pm_present; 2885 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2886 cts->xport_specific.sata.tags = d->tags; 2887 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2888 cts->xport_specific.sata.atapi = d->atapi; 2889 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2890 ccb->ccb_h.status = CAM_REQ_CMP; 2891 break; 2892 } 2893 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2894 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2895 ahci_reset(dev); 2896 ccb->ccb_h.status = CAM_REQ_CMP; 2897 break; 2898 case XPT_TERM_IO: /* Terminate the I/O process */ 2899 /* XXX Implement */ 2900 ccb->ccb_h.status = CAM_REQ_INVALID; 2901 break; 2902 case XPT_PATH_INQ: /* Path routing inquiry */ 2903 { 2904 struct ccb_pathinq *cpi = &ccb->cpi; 2905 2906 parent = device_get_parent(dev); 2907 cpi->version_num = 1; /* XXX??? */ 2908 cpi->hba_inquiry = PI_SDTR_ABLE; 2909 if (ch->caps & AHCI_CAP_SNCQ) 2910 cpi->hba_inquiry |= PI_TAG_ABLE; 2911 if (ch->caps & AHCI_CAP_SPM) 2912 cpi->hba_inquiry |= PI_SATAPM; 2913 cpi->target_sprt = 0; 2914 cpi->hba_misc = PIM_SEQSCAN; 2915 cpi->hba_eng_cnt = 0; 2916 if (ch->caps & AHCI_CAP_SPM) 2917 cpi->max_target = 15; 2918 else 2919 cpi->max_target = 0; 2920 cpi->max_lun = 0; 2921 cpi->initiator_id = 0; 2922 cpi->bus_id = cam_sim_bus(sim); 2923 cpi->base_transfer_speed = 150000; 2924 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2925 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2926 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2927 cpi->unit_number = cam_sim_unit(sim); 2928 cpi->transport = XPORT_SATA; 2929 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2930 cpi->protocol = PROTO_ATA; 2931 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2932 cpi->maxio = MAXPHYS; 2933 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2934 if (pci_get_devid(parent) == 0x43801002) 2935 cpi->maxio = min(cpi->maxio, 128 * 512); 2936 cpi->hba_vendor = pci_get_vendor(parent); 2937 cpi->hba_device = pci_get_device(parent); 2938 cpi->hba_subvendor = pci_get_subvendor(parent); 2939 cpi->hba_subdevice = pci_get_subdevice(parent); 2940 cpi->ccb_h.status = CAM_REQ_CMP; 2941 break; 2942 } 2943 default: 2944 ccb->ccb_h.status = CAM_REQ_INVALID; 2945 break; 2946 } 2947 xpt_done(ccb); 2948} 2949 2950static void 2951ahcipoll(struct cam_sim *sim) 2952{ 2953 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2954 2955 ahci_ch_intr(ch->dev); 2956 if (ch->resetting != 0 && 2957 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2958 ch->resetpolldiv = 1000; 2959 ahci_reset_to(ch->dev); 2960 } 2961} 2962