ahci_pci.c revision 203108
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 203108 2010-01-28 08:41:30Z mav $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_debug.h> 56 57/* local prototypes */ 58static int ahci_setup_interrupt(device_t dev); 59static void ahci_intr(void *data); 60static void ahci_intr_one(void *data); 61static int ahci_suspend(device_t dev); 62static int ahci_resume(device_t dev); 63static int ahci_ch_suspend(device_t dev); 64static int ahci_ch_resume(device_t dev); 65static void ahci_ch_pm(void *arg); 66static void ahci_ch_intr_locked(void *data); 67static void ahci_ch_intr(void *data); 68static int ahci_ctlr_reset(device_t dev); 69static void ahci_begin_transaction(device_t dev, union ccb *ccb); 70static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 71static void ahci_execute_transaction(struct ahci_slot *slot); 72static void ahci_timeout(struct ahci_slot *slot); 73static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 74static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 75static void ahci_dmainit(device_t dev); 76static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 77static void ahci_dmafini(device_t dev); 78static void ahci_slotsalloc(device_t dev); 79static void ahci_slotsfree(device_t dev); 80static void ahci_reset(device_t dev); 81static void ahci_start(device_t dev); 82static void ahci_stop(device_t dev); 83static void ahci_clo(device_t dev); 84static void ahci_start_fr(device_t dev); 85static void ahci_stop_fr(device_t dev); 86 87static int ahci_sata_connect(struct ahci_channel *ch); 88static int ahci_sata_phy_reset(device_t dev); 89 90static void ahci_issue_read_log(device_t dev); 91static void ahci_process_read_log(device_t dev, union ccb *ccb); 92 93static void ahciaction(struct cam_sim *sim, union ccb *ccb); 94static void ahcipoll(struct cam_sim *sim); 95 96MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 97 98static struct { 99 uint32_t id; 100 uint8_t rev; 101 const char *name; 102 int quirks; 103#define AHCI_Q_NOFORCE 1 104#define AHCI_Q_NOPMP 2 105#define AHCI_Q_NONCQ 4 106#define AHCI_Q_1CH 8 107#define AHCI_Q_2CH 16 108#define AHCI_Q_4CH 32 109#define AHCI_Q_EDGEIS 64 110#define AHCI_Q_SATA2 128 111} ahci_ids[] = { 112 {0x43801002, 0x00, "ATI IXP600", 0}, 113 {0x43901002, 0x00, "ATI IXP700", 0}, 114 {0x43911002, 0x00, "ATI IXP700", 0}, 115 {0x43921002, 0x00, "ATI IXP700", 0}, 116 {0x43931002, 0x00, "ATI IXP700", 0}, 117 {0x43941002, 0x00, "ATI IXP800", 0}, 118 {0x43951002, 0x00, "ATI IXP800", 0}, 119 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 120 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 121 {0x26818086, 0x00, "Intel ESB2", 0}, 122 {0x26828086, 0x00, "Intel ESB2", 0}, 123 {0x26838086, 0x00, "Intel ESB2", 0}, 124 {0x27c18086, 0x00, "Intel ICH7", 0}, 125 {0x27c38086, 0x00, "Intel ICH7", 0}, 126 {0x27c58086, 0x00, "Intel ICH7M", 0}, 127 {0x27c68086, 0x00, "Intel ICH7M", 0}, 128 {0x28218086, 0x00, "Intel ICH8", 0}, 129 {0x28228086, 0x00, "Intel ICH8", 0}, 130 {0x28248086, 0x00, "Intel ICH8", 0}, 131 {0x28298086, 0x00, "Intel ICH8M", 0}, 132 {0x282a8086, 0x00, "Intel ICH8M", 0}, 133 {0x29228086, 0x00, "Intel ICH9", 0}, 134 {0x29238086, 0x00, "Intel ICH9", 0}, 135 {0x29248086, 0x00, "Intel ICH9", 0}, 136 {0x29258086, 0x00, "Intel ICH9", 0}, 137 {0x29278086, 0x00, "Intel ICH9", 0}, 138 {0x29298086, 0x00, "Intel ICH9M", 0}, 139 {0x292a8086, 0x00, "Intel ICH9M", 0}, 140 {0x292b8086, 0x00, "Intel ICH9M", 0}, 141 {0x292c8086, 0x00, "Intel ICH9M", 0}, 142 {0x292f8086, 0x00, "Intel ICH9M", 0}, 143 {0x294d8086, 0x00, "Intel ICH9", 0}, 144 {0x294e8086, 0x00, "Intel ICH9M", 0}, 145 {0x3a058086, 0x00, "Intel ICH10", 0}, 146 {0x3a228086, 0x00, "Intel ICH10", 0}, 147 {0x3a258086, 0x00, "Intel ICH10", 0}, 148 {0x3b228086, 0x00, "Intel PCH", 0}, 149 {0x3b238086, 0x00, "Intel PCH", 0}, 150 {0x3b248086, 0x00, "Intel PCH", 0}, 151 {0x3b258086, 0x00, "Intel PCH", 0}, 152 {0x3b298086, 0x00, "Intel PCH", 0}, 153 {0x3b2b8086, 0x00, "Intel PCH", 0}, 154 {0x3b2c8086, 0x00, "Intel PCH", 0}, 155 {0x3b2f8086, 0x00, "Intel PCH", 0}, 156 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 157 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 158 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 159 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 160 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 161 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS}, 162 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS}, 163 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 164 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 165 {0x91231b4b, 0x11, "Marvell 88SE912x", 0}, 166 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2}, 167 {0x044c10de, 0x00, "NVIDIA MCP65", 0}, 168 {0x044d10de, 0x00, "NVIDIA MCP65", 0}, 169 {0x044e10de, 0x00, "NVIDIA MCP65", 0}, 170 {0x044f10de, 0x00, "NVIDIA MCP65", 0}, 171 {0x045c10de, 0x00, "NVIDIA MCP65", 0}, 172 {0x045d10de, 0x00, "NVIDIA MCP65", 0}, 173 {0x045e10de, 0x00, "NVIDIA MCP65", 0}, 174 {0x045f10de, 0x00, "NVIDIA MCP65", 0}, 175 {0x055010de, 0x00, "NVIDIA MCP67", 0}, 176 {0x055110de, 0x00, "NVIDIA MCP67", 0}, 177 {0x055210de, 0x00, "NVIDIA MCP67", 0}, 178 {0x055310de, 0x00, "NVIDIA MCP67", 0}, 179 {0x055410de, 0x00, "NVIDIA MCP67", 0}, 180 {0x055510de, 0x00, "NVIDIA MCP67", 0}, 181 {0x055610de, 0x00, "NVIDIA MCP67", 0}, 182 {0x055710de, 0x00, "NVIDIA MCP67", 0}, 183 {0x055810de, 0x00, "NVIDIA MCP67", 0}, 184 {0x055910de, 0x00, "NVIDIA MCP67", 0}, 185 {0x055A10de, 0x00, "NVIDIA MCP67", 0}, 186 {0x055B10de, 0x00, "NVIDIA MCP67", 0}, 187 {0x058410de, 0x00, "NVIDIA MCP67", 0}, 188 {0x07f010de, 0x00, "NVIDIA MCP73", 0}, 189 {0x07f110de, 0x00, "NVIDIA MCP73", 0}, 190 {0x07f210de, 0x00, "NVIDIA MCP73", 0}, 191 {0x07f310de, 0x00, "NVIDIA MCP73", 0}, 192 {0x07f410de, 0x00, "NVIDIA MCP73", 0}, 193 {0x07f510de, 0x00, "NVIDIA MCP73", 0}, 194 {0x07f610de, 0x00, "NVIDIA MCP73", 0}, 195 {0x07f710de, 0x00, "NVIDIA MCP73", 0}, 196 {0x07f810de, 0x00, "NVIDIA MCP73", 0}, 197 {0x07f910de, 0x00, "NVIDIA MCP73", 0}, 198 {0x07fa10de, 0x00, "NVIDIA MCP73", 0}, 199 {0x07fb10de, 0x00, "NVIDIA MCP73", 0}, 200 {0x0ad010de, 0x00, "NVIDIA MCP77", 0}, 201 {0x0ad110de, 0x00, "NVIDIA MCP77", 0}, 202 {0x0ad210de, 0x00, "NVIDIA MCP77", 0}, 203 {0x0ad310de, 0x00, "NVIDIA MCP77", 0}, 204 {0x0ad410de, 0x00, "NVIDIA MCP77", 0}, 205 {0x0ad510de, 0x00, "NVIDIA MCP77", 0}, 206 {0x0ad610de, 0x00, "NVIDIA MCP77", 0}, 207 {0x0ad710de, 0x00, "NVIDIA MCP77", 0}, 208 {0x0ad810de, 0x00, "NVIDIA MCP77", 0}, 209 {0x0ad910de, 0x00, "NVIDIA MCP77", 0}, 210 {0x0ada10de, 0x00, "NVIDIA MCP77", 0}, 211 {0x0adb10de, 0x00, "NVIDIA MCP77", 0}, 212 {0x0ab410de, 0x00, "NVIDIA MCP79", 0}, 213 {0x0ab510de, 0x00, "NVIDIA MCP79", 0}, 214 {0x0ab610de, 0x00, "NVIDIA MCP79", 0}, 215 {0x0ab710de, 0x00, "NVIDIA MCP79", 0}, 216 {0x0ab810de, 0x00, "NVIDIA MCP79", 0}, 217 {0x0ab910de, 0x00, "NVIDIA MCP79", 0}, 218 {0x0aba10de, 0x00, "NVIDIA MCP79", 0}, 219 {0x0abb10de, 0x00, "NVIDIA MCP79", 0}, 220 {0x0abc10de, 0x00, "NVIDIA MCP79", 0}, 221 {0x0abd10de, 0x00, "NVIDIA MCP79", 0}, 222 {0x0abe10de, 0x00, "NVIDIA MCP79", 0}, 223 {0x0abf10de, 0x00, "NVIDIA MCP79", 0}, 224 {0x0d8410de, 0x00, "NVIDIA MCP89", 0}, 225 {0x0d8510de, 0x00, "NVIDIA MCP89", 0}, 226 {0x0d8610de, 0x00, "NVIDIA MCP89", 0}, 227 {0x0d8710de, 0x00, "NVIDIA MCP89", 0}, 228 {0x0d8810de, 0x00, "NVIDIA MCP89", 0}, 229 {0x0d8910de, 0x00, "NVIDIA MCP89", 0}, 230 {0x0d8a10de, 0x00, "NVIDIA MCP89", 0}, 231 {0x0d8b10de, 0x00, "NVIDIA MCP89", 0}, 232 {0x0d8c10de, 0x00, "NVIDIA MCP89", 0}, 233 {0x0d8d10de, 0x00, "NVIDIA MCP89", 0}, 234 {0x0d8e10de, 0x00, "NVIDIA MCP89", 0}, 235 {0x0d8f10de, 0x00, "NVIDIA MCP89", 0}, 236 {0x33491106, 0x00, "VIA VT8251", 0}, 237 {0x62871106, 0x00, "VIA VT8251", 0}, 238 {0x11841039, 0x00, "SiS 966", 0}, 239 {0x11851039, 0x00, "SiS 968", 0}, 240 {0x01861039, 0x00, "SiS 968", 0}, 241 {0x00000000, 0x00, NULL, 0} 242}; 243 244static int 245ahci_probe(device_t dev) 246{ 247 char buf[64]; 248 int i, valid = 0; 249 uint32_t devid = pci_get_devid(dev); 250 uint8_t revid = pci_get_revid(dev); 251 252 /* Is this a possible AHCI candidate? */ 253 if (pci_get_class(dev) == PCIC_STORAGE && 254 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 255 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 256 valid = 1; 257 /* Is this a known AHCI chip? */ 258 for (i = 0; ahci_ids[i].id != 0; i++) { 259 if (ahci_ids[i].id == devid && 260 ahci_ids[i].rev <= revid && 261 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 262 /* Do not attach JMicrons with single PCI function. */ 263 if (pci_get_vendor(dev) == 0x197b && 264 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 265 return (ENXIO); 266 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 267 ahci_ids[i].name); 268 device_set_desc_copy(dev, buf); 269 return (BUS_PROBE_VENDOR); 270 } 271 } 272 if (!valid) 273 return (ENXIO); 274 device_set_desc_copy(dev, "AHCI SATA controller"); 275 return (BUS_PROBE_VENDOR); 276} 277 278static int 279ahci_ata_probe(device_t dev) 280{ 281 char buf[64]; 282 int i; 283 uint32_t devid = pci_get_devid(dev); 284 uint8_t revid = pci_get_revid(dev); 285 286 if ((intptr_t)device_get_ivars(dev) >= 0) 287 return (ENXIO); 288 /* Is this a known AHCI chip? */ 289 for (i = 0; ahci_ids[i].id != 0; i++) { 290 if (ahci_ids[i].id == devid && 291 ahci_ids[i].rev <= revid) { 292 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 293 ahci_ids[i].name); 294 device_set_desc_copy(dev, buf); 295 return (BUS_PROBE_VENDOR); 296 } 297 } 298 device_set_desc_copy(dev, "AHCI SATA controller"); 299 return (BUS_PROBE_VENDOR); 300} 301 302static int 303ahci_attach(device_t dev) 304{ 305 struct ahci_controller *ctlr = device_get_softc(dev); 306 device_t child; 307 int error, unit, speed, i; 308 uint32_t devid = pci_get_devid(dev); 309 uint8_t revid = pci_get_revid(dev); 310 u_int32_t version; 311 312 ctlr->dev = dev; 313 i = 0; 314 while (ahci_ids[i].id != 0 && 315 (ahci_ids[i].id != devid || 316 ahci_ids[i].rev > revid)) 317 i++; 318 ctlr->quirks = ahci_ids[i].quirks; 319 resource_int_value(device_get_name(dev), 320 device_get_unit(dev), "ccc", &ctlr->ccc); 321 /* if we have a memory BAR(5) we are likely on an AHCI part */ 322 ctlr->r_rid = PCIR_BAR(5); 323 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 324 &ctlr->r_rid, RF_ACTIVE))) 325 return ENXIO; 326 /* Setup our own memory management for channels. */ 327 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 328 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 329 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 330 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 331 return (error); 332 } 333 if ((error = rman_manage_region(&ctlr->sc_iomem, 334 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 335 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 336 rman_fini(&ctlr->sc_iomem); 337 return (error); 338 } 339 /* Reset controller */ 340 if ((error = ahci_ctlr_reset(dev)) != 0) { 341 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 342 rman_fini(&ctlr->sc_iomem); 343 return (error); 344 }; 345 /* Get the HW capabilities */ 346 version = ATA_INL(ctlr->r_mem, AHCI_VS); 347 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 348 if (version >= 0x00010020) 349 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 350 if (ctlr->caps & AHCI_CAP_EMS) 351 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 352 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 353 if (ctlr->quirks & AHCI_Q_1CH) { 354 ctlr->caps &= ~AHCI_CAP_NPMASK; 355 ctlr->ichannels &= 0x01; 356 } 357 if (ctlr->quirks & AHCI_Q_2CH) { 358 ctlr->caps &= ~AHCI_CAP_NPMASK; 359 ctlr->caps |= 1; 360 ctlr->ichannels &= 0x03; 361 } 362 if (ctlr->quirks & AHCI_Q_4CH) { 363 ctlr->caps &= ~AHCI_CAP_NPMASK; 364 ctlr->caps |= 3; 365 ctlr->ichannels &= 0x0f; 366 } 367 ctlr->channels = MAX(flsl(ctlr->ichannels), 368 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 369 if (ctlr->quirks & AHCI_Q_NOPMP) 370 ctlr->caps &= ~AHCI_CAP_SPM; 371 if (ctlr->quirks & AHCI_Q_NONCQ) 372 ctlr->caps &= ~AHCI_CAP_SNCQ; 373 /* Setup interrupts. */ 374 if (ahci_setup_interrupt(dev)) { 375 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 376 rman_fini(&ctlr->sc_iomem); 377 return ENXIO; 378 } 379 /* Announce HW capabilities. */ 380 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 381 device_printf(dev, 382 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n", 383 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 384 ((version >> 4) & 0xf0) + (version & 0x0f), 385 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 386 ((speed == 1) ? "1.5":((speed == 2) ? "3": 387 ((speed == 3) ? "6":"?"))), 388 (ctlr->caps & AHCI_CAP_SPM) ? 389 "supported" : "not supported"); 390 if (bootverbose) { 391 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 392 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 393 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 394 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 395 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 396 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 397 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 398 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 399 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 400 ((speed == 1) ? "1.5":((speed == 2) ? "3": 401 ((speed == 3) ? "6":"?")))); 402 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 403 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 404 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 405 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 406 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 407 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 408 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 409 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 410 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 411 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 412 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 413 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 414 } 415 if (bootverbose && version >= 0x00010020) { 416 device_printf(dev, "Caps2:%s%s%s\n", 417 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 418 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 419 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 420 } 421 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 422 device_printf(dev, "EM Caps: %s%s%s%s%s%s%s%s\n", 423 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 424 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 425 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 426 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 427 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 428 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 429 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 430 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 431 } 432 /* Attach all channels on this controller */ 433 for (unit = 0; unit < ctlr->channels; unit++) { 434 if ((ctlr->ichannels & (1 << unit)) == 0) 435 continue; 436 child = device_add_child(dev, "ahcich", -1); 437 if (child == NULL) 438 device_printf(dev, "failed to add channel device\n"); 439 else 440 device_set_ivars(child, (void *)(intptr_t)unit); 441 } 442 bus_generic_attach(dev); 443 return 0; 444} 445 446static int 447ahci_detach(device_t dev) 448{ 449 struct ahci_controller *ctlr = device_get_softc(dev); 450 device_t *children; 451 int nchildren, i; 452 453 /* Detach & delete all children */ 454 if (!device_get_children(dev, &children, &nchildren)) { 455 for (i = 0; i < nchildren; i++) 456 device_delete_child(dev, children[i]); 457 free(children, M_TEMP); 458 } 459 /* Free interrupts. */ 460 for (i = 0; i < ctlr->numirqs; i++) { 461 if (ctlr->irqs[i].r_irq) { 462 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 463 ctlr->irqs[i].handle); 464 bus_release_resource(dev, SYS_RES_IRQ, 465 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 466 } 467 } 468 pci_release_msi(dev); 469 /* Free memory. */ 470 rman_fini(&ctlr->sc_iomem); 471 if (ctlr->r_mem) 472 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 473 return (0); 474} 475 476static int 477ahci_ctlr_reset(device_t dev) 478{ 479 struct ahci_controller *ctlr = device_get_softc(dev); 480 int timeout; 481 482 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 483 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 484 pci_write_config(dev, 0x92, 0x01, 1); 485 /* Enable AHCI mode */ 486 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 487 /* Reset AHCI controller */ 488 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 489 for (timeout = 1000; timeout > 0; timeout--) { 490 DELAY(1000); 491 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 492 break; 493 } 494 if (timeout == 0) { 495 device_printf(dev, "AHCI controller reset failure\n"); 496 return ENXIO; 497 } 498 /* Reenable AHCI mode */ 499 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 500 /* Clear interrupts */ 501 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 502 /* Configure CCC */ 503 if (ctlr->ccc) { 504 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 505 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 506 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 507 (4 << AHCI_CCCC_CC_SHIFT) | 508 AHCI_CCCC_EN); 509 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 510 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 511 if (bootverbose) { 512 device_printf(dev, 513 "CCC with %dms/4cmd enabled on vector %d\n", 514 ctlr->ccc, ctlr->cccv); 515 } 516 } 517 /* Enable AHCI interrupts */ 518 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 519 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 520 return (0); 521} 522 523static int 524ahci_suspend(device_t dev) 525{ 526 struct ahci_controller *ctlr = device_get_softc(dev); 527 528 bus_generic_suspend(dev); 529 /* Disable interupts, so the state change(s) doesn't trigger */ 530 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 531 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 532 return 0; 533} 534 535static int 536ahci_resume(device_t dev) 537{ 538 int res; 539 540 if ((res = ahci_ctlr_reset(dev)) != 0) 541 return (res); 542 return (bus_generic_resume(dev)); 543} 544 545static int 546ahci_setup_interrupt(device_t dev) 547{ 548 struct ahci_controller *ctlr = device_get_softc(dev); 549 int i, msi = 1; 550 551 /* Process hints. */ 552 resource_int_value(device_get_name(dev), 553 device_get_unit(dev), "msi", &msi); 554 if (msi < 0) 555 msi = 0; 556 else if (msi == 1) 557 msi = min(1, pci_msi_count(dev)); 558 else if (msi > 1) 559 msi = pci_msi_count(dev); 560 /* Allocate MSI if needed/present. */ 561 if (msi && pci_alloc_msi(dev, &msi) == 0) { 562 ctlr->numirqs = msi; 563 } else { 564 msi = 0; 565 ctlr->numirqs = 1; 566 } 567 /* Check for single MSI vector fallback. */ 568 if (ctlr->numirqs > 1 && 569 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 570 device_printf(dev, "Falling back to one MSI\n"); 571 ctlr->numirqs = 1; 572 } 573 /* Allocate all IRQs. */ 574 for (i = 0; i < ctlr->numirqs; i++) { 575 ctlr->irqs[i].ctlr = ctlr; 576 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 577 if (ctlr->numirqs == 1 || i >= ctlr->channels || 578 (ctlr->ccc && i == ctlr->cccv)) 579 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 580 else if (i == ctlr->numirqs - 1) 581 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 582 else 583 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 584 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 585 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 586 device_printf(dev, "unable to map interrupt\n"); 587 return ENXIO; 588 } 589 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 590 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 591 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 592 /* SOS XXX release r_irq */ 593 device_printf(dev, "unable to setup interrupt\n"); 594 return ENXIO; 595 } 596 if (ctlr->numirqs > 1) { 597 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 598 ctlr->irqs[i].handle, 599 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 600 "ch%d" : "%d", i); 601 } 602 } 603 return (0); 604} 605 606/* 607 * Common case interrupt handler. 608 */ 609static void 610ahci_intr(void *data) 611{ 612 struct ahci_controller_irq *irq = data; 613 struct ahci_controller *ctlr = irq->ctlr; 614 u_int32_t is; 615 void *arg; 616 int unit; 617 618 if (irq->mode == AHCI_IRQ_MODE_ALL) { 619 unit = 0; 620 if (ctlr->ccc) 621 is = ctlr->ichannels; 622 else 623 is = ATA_INL(ctlr->r_mem, AHCI_IS); 624 } else { /* AHCI_IRQ_MODE_AFTER */ 625 unit = irq->r_irq_rid - 1; 626 is = ATA_INL(ctlr->r_mem, AHCI_IS); 627 } 628 /* Some controllers have edge triggered IS. */ 629 if (ctlr->quirks & AHCI_Q_EDGEIS) 630 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 631 for (; unit < ctlr->channels; unit++) { 632 if ((is & (1 << unit)) != 0 && 633 (arg = ctlr->interrupt[unit].argument)) { 634 ctlr->interrupt[unit].function(arg); 635 } 636 } 637 /* AHCI declares level triggered IS. */ 638 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 639 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 640} 641 642/* 643 * Simplified interrupt handler for multivector MSI mode. 644 */ 645static void 646ahci_intr_one(void *data) 647{ 648 struct ahci_controller_irq *irq = data; 649 struct ahci_controller *ctlr = irq->ctlr; 650 void *arg; 651 int unit; 652 653 unit = irq->r_irq_rid - 1; 654 /* Some controllers have edge triggered IS. */ 655 if (ctlr->quirks & AHCI_Q_EDGEIS) 656 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 657 if ((arg = ctlr->interrupt[unit].argument)) 658 ctlr->interrupt[unit].function(arg); 659 /* AHCI declares level triggered IS. */ 660 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 661 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 662} 663 664static struct resource * 665ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 666 u_long start, u_long end, u_long count, u_int flags) 667{ 668 struct ahci_controller *ctlr = device_get_softc(dev); 669 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 670 struct resource *res = NULL; 671 int offset = AHCI_OFFSET + (unit << 7); 672 long st; 673 674 switch (type) { 675 case SYS_RES_MEMORY: 676 st = rman_get_start(ctlr->r_mem); 677 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 678 st + offset + 127, 128, RF_ACTIVE, child); 679 if (res) { 680 bus_space_handle_t bsh; 681 bus_space_tag_t bst; 682 bsh = rman_get_bushandle(ctlr->r_mem); 683 bst = rman_get_bustag(ctlr->r_mem); 684 bus_space_subregion(bst, bsh, offset, 128, &bsh); 685 rman_set_bushandle(res, bsh); 686 rman_set_bustag(res, bst); 687 } 688 break; 689 case SYS_RES_IRQ: 690 if (*rid == ATA_IRQ_RID) 691 res = ctlr->irqs[0].r_irq; 692 break; 693 } 694 return (res); 695} 696 697static int 698ahci_release_resource(device_t dev, device_t child, int type, int rid, 699 struct resource *r) 700{ 701 702 switch (type) { 703 case SYS_RES_MEMORY: 704 rman_release_resource(r); 705 return (0); 706 case SYS_RES_IRQ: 707 if (rid != ATA_IRQ_RID) 708 return ENOENT; 709 return (0); 710 } 711 return (EINVAL); 712} 713 714static int 715ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 716 int flags, driver_filter_t *filter, driver_intr_t *function, 717 void *argument, void **cookiep) 718{ 719 struct ahci_controller *ctlr = device_get_softc(dev); 720 int unit = (intptr_t)device_get_ivars(child); 721 722 if (filter != NULL) { 723 printf("ahci.c: we cannot use a filter here\n"); 724 return (EINVAL); 725 } 726 ctlr->interrupt[unit].function = function; 727 ctlr->interrupt[unit].argument = argument; 728 return (0); 729} 730 731static int 732ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 733 void *cookie) 734{ 735 struct ahci_controller *ctlr = device_get_softc(dev); 736 int unit = (intptr_t)device_get_ivars(child); 737 738 ctlr->interrupt[unit].function = NULL; 739 ctlr->interrupt[unit].argument = NULL; 740 return (0); 741} 742 743static int 744ahci_print_child(device_t dev, device_t child) 745{ 746 int retval; 747 748 retval = bus_print_child_header(dev, child); 749 retval += printf(" at channel %d", 750 (int)(intptr_t)device_get_ivars(child)); 751 retval += bus_print_child_footer(dev, child); 752 753 return (retval); 754} 755 756devclass_t ahci_devclass; 757static device_method_t ahci_methods[] = { 758 DEVMETHOD(device_probe, ahci_probe), 759 DEVMETHOD(device_attach, ahci_attach), 760 DEVMETHOD(device_detach, ahci_detach), 761 DEVMETHOD(device_suspend, ahci_suspend), 762 DEVMETHOD(device_resume, ahci_resume), 763 DEVMETHOD(bus_print_child, ahci_print_child), 764 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 765 DEVMETHOD(bus_release_resource, ahci_release_resource), 766 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 767 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 768 { 0, 0 } 769}; 770static driver_t ahci_driver = { 771 "ahci", 772 ahci_methods, 773 sizeof(struct ahci_controller) 774}; 775DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 776static device_method_t ahci_ata_methods[] = { 777 DEVMETHOD(device_probe, ahci_ata_probe), 778 DEVMETHOD(device_attach, ahci_attach), 779 DEVMETHOD(device_detach, ahci_detach), 780 DEVMETHOD(device_suspend, ahci_suspend), 781 DEVMETHOD(device_resume, ahci_resume), 782 DEVMETHOD(bus_print_child, ahci_print_child), 783 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 784 DEVMETHOD(bus_release_resource, ahci_release_resource), 785 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 786 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 787 { 0, 0 } 788}; 789static driver_t ahci_ata_driver = { 790 "ahci", 791 ahci_ata_methods, 792 sizeof(struct ahci_controller) 793}; 794DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 795MODULE_VERSION(ahci, 1); 796MODULE_DEPEND(ahci, cam, 1, 1, 1); 797 798static int 799ahci_ch_probe(device_t dev) 800{ 801 802 device_set_desc_copy(dev, "AHCI channel"); 803 return (0); 804} 805 806static int 807ahci_ch_attach(device_t dev) 808{ 809 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 810 struct ahci_channel *ch = device_get_softc(dev); 811 struct cam_devq *devq; 812 int rid, error, i, sata_rev = 0; 813 814 ch->dev = dev; 815 ch->unit = (intptr_t)device_get_ivars(dev); 816 ch->caps = ctlr->caps; 817 ch->caps2 = ctlr->caps2; 818 ch->quirks = ctlr->quirks; 819 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 820 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 821 resource_int_value(device_get_name(dev), 822 device_get_unit(dev), "pm_level", &ch->pm_level); 823 if (ch->pm_level > 3) 824 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 825 /* Limit speed for my onboard JMicron external port. 826 * It is not eSATA really. */ 827 if (pci_get_devid(ctlr->dev) == 0x2363197b && 828 pci_get_subvendor(ctlr->dev) == 0x1043 && 829 pci_get_subdevice(ctlr->dev) == 0x81e4 && 830 ch->unit == 0) 831 sata_rev = 1; 832 if (ch->quirks & AHCI_Q_SATA2) 833 sata_rev = 2; 834 resource_int_value(device_get_name(dev), 835 device_get_unit(dev), "sata_rev", &sata_rev); 836 for (i = 0; i < 16; i++) { 837 ch->user[i].revision = sata_rev; 838 ch->user[i].mode = 0; 839 ch->user[i].bytecount = 8192; 840 ch->user[i].tags = ch->numslots; 841 ch->curr[i] = ch->user[i]; 842 } 843 rid = ch->unit; 844 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 845 &rid, RF_ACTIVE))) 846 return (ENXIO); 847 ahci_dmainit(dev); 848 ahci_slotsalloc(dev); 849 ahci_ch_resume(dev); 850 mtx_lock(&ch->mtx); 851 rid = ATA_IRQ_RID; 852 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 853 &rid, RF_SHAREABLE | RF_ACTIVE))) { 854 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 855 device_printf(dev, "Unable to map interrupt\n"); 856 return (ENXIO); 857 } 858 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 859 ahci_ch_intr_locked, dev, &ch->ih))) { 860 device_printf(dev, "Unable to setup interrupt\n"); 861 error = ENXIO; 862 goto err1; 863 } 864 /* Create the device queue for our SIM. */ 865 devq = cam_simq_alloc(ch->numslots); 866 if (devq == NULL) { 867 device_printf(dev, "Unable to allocate simq\n"); 868 error = ENOMEM; 869 goto err1; 870 } 871 /* Construct SIM entry */ 872 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 873 device_get_unit(dev), &ch->mtx, 874 min(2, ch->numslots), 875 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 876 devq); 877 if (ch->sim == NULL) { 878 device_printf(dev, "unable to allocate sim\n"); 879 error = ENOMEM; 880 goto err2; 881 } 882 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 883 device_printf(dev, "unable to register xpt bus\n"); 884 error = ENXIO; 885 goto err2; 886 } 887 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 888 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 889 device_printf(dev, "unable to create path\n"); 890 error = ENXIO; 891 goto err3; 892 } 893 if (ch->pm_level > 3) { 894 callout_reset(&ch->pm_timer, 895 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 896 ahci_ch_pm, dev); 897 } 898 mtx_unlock(&ch->mtx); 899 return (0); 900 901err3: 902 xpt_bus_deregister(cam_sim_path(ch->sim)); 903err2: 904 cam_sim_free(ch->sim, /*free_devq*/TRUE); 905err1: 906 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 907 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 908 mtx_unlock(&ch->mtx); 909 return (error); 910} 911 912static int 913ahci_ch_detach(device_t dev) 914{ 915 struct ahci_channel *ch = device_get_softc(dev); 916 917 mtx_lock(&ch->mtx); 918 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 919 xpt_free_path(ch->path); 920 xpt_bus_deregister(cam_sim_path(ch->sim)); 921 cam_sim_free(ch->sim, /*free_devq*/TRUE); 922 mtx_unlock(&ch->mtx); 923 924 if (ch->pm_level > 3) 925 callout_drain(&ch->pm_timer); 926 bus_teardown_intr(dev, ch->r_irq, ch->ih); 927 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 928 929 ahci_ch_suspend(dev); 930 ahci_slotsfree(dev); 931 ahci_dmafini(dev); 932 933 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 934 mtx_destroy(&ch->mtx); 935 return (0); 936} 937 938static int 939ahci_ch_suspend(device_t dev) 940{ 941 struct ahci_channel *ch = device_get_softc(dev); 942 943 /* Disable port interrupts. */ 944 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 945 /* Reset command register. */ 946 ahci_stop(dev); 947 ahci_stop_fr(dev); 948 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 949 /* Allow everything, including partial and slumber modes. */ 950 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 951 /* Request slumber mode transition and give some time to get there. */ 952 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 953 DELAY(100); 954 /* Disable PHY. */ 955 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 956 return (0); 957} 958 959static int 960ahci_ch_resume(device_t dev) 961{ 962 struct ahci_channel *ch = device_get_softc(dev); 963 uint64_t work; 964 965 /* Disable port interrupts */ 966 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 967 /* Setup work areas */ 968 work = ch->dma.work_bus + AHCI_CL_OFFSET; 969 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 970 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 971 work = ch->dma.rfis_bus; 972 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 973 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 974 /* Activate the channel and power/spin up device */ 975 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 976 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 977 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 978 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 979 ahci_start_fr(dev); 980 ahci_start(dev); 981 return (0); 982} 983 984devclass_t ahcich_devclass; 985static device_method_t ahcich_methods[] = { 986 DEVMETHOD(device_probe, ahci_ch_probe), 987 DEVMETHOD(device_attach, ahci_ch_attach), 988 DEVMETHOD(device_detach, ahci_ch_detach), 989 DEVMETHOD(device_suspend, ahci_ch_suspend), 990 DEVMETHOD(device_resume, ahci_ch_resume), 991 { 0, 0 } 992}; 993static driver_t ahcich_driver = { 994 "ahcich", 995 ahcich_methods, 996 sizeof(struct ahci_channel) 997}; 998DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 999 1000struct ahci_dc_cb_args { 1001 bus_addr_t maddr; 1002 int error; 1003}; 1004 1005static void 1006ahci_dmainit(device_t dev) 1007{ 1008 struct ahci_channel *ch = device_get_softc(dev); 1009 struct ahci_dc_cb_args dcba; 1010 1011 if (ch->caps & AHCI_CAP_64BIT) 1012 ch->dma.max_address = BUS_SPACE_MAXADDR; 1013 else 1014 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1015 /* Command area. */ 1016 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1017 ch->dma.max_address, BUS_SPACE_MAXADDR, 1018 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1019 0, NULL, NULL, &ch->dma.work_tag)) 1020 goto error; 1021 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1022 &ch->dma.work_map)) 1023 goto error; 1024 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1025 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1026 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1027 goto error; 1028 } 1029 ch->dma.work_bus = dcba.maddr; 1030 /* FIS receive area. */ 1031 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, 1032 ch->dma.max_address, BUS_SPACE_MAXADDR, 1033 NULL, NULL, 4096, 1, 4096, 1034 0, NULL, NULL, &ch->dma.rfis_tag)) 1035 goto error; 1036 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1037 &ch->dma.rfis_map)) 1038 goto error; 1039 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1040 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1041 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1042 goto error; 1043 } 1044 ch->dma.rfis_bus = dcba.maddr; 1045 /* Data area. */ 1046 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1047 ch->dma.max_address, BUS_SPACE_MAXADDR, 1048 NULL, NULL, 1049 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1050 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1051 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1052 goto error; 1053 } 1054 return; 1055 1056error: 1057 device_printf(dev, "WARNING - DMA initialization failed\n"); 1058 ahci_dmafini(dev); 1059} 1060 1061static void 1062ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1063{ 1064 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1065 1066 if (!(dcba->error = error)) 1067 dcba->maddr = segs[0].ds_addr; 1068} 1069 1070static void 1071ahci_dmafini(device_t dev) 1072{ 1073 struct ahci_channel *ch = device_get_softc(dev); 1074 1075 if (ch->dma.data_tag) { 1076 bus_dma_tag_destroy(ch->dma.data_tag); 1077 ch->dma.data_tag = NULL; 1078 } 1079 if (ch->dma.rfis_bus) { 1080 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1081 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1082 ch->dma.rfis_bus = 0; 1083 ch->dma.rfis_map = NULL; 1084 ch->dma.rfis = NULL; 1085 } 1086 if (ch->dma.work_bus) { 1087 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1088 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1089 ch->dma.work_bus = 0; 1090 ch->dma.work_map = NULL; 1091 ch->dma.work = NULL; 1092 } 1093 if (ch->dma.work_tag) { 1094 bus_dma_tag_destroy(ch->dma.work_tag); 1095 ch->dma.work_tag = NULL; 1096 } 1097} 1098 1099static void 1100ahci_slotsalloc(device_t dev) 1101{ 1102 struct ahci_channel *ch = device_get_softc(dev); 1103 int i; 1104 1105 /* Alloc and setup command/dma slots */ 1106 bzero(ch->slot, sizeof(ch->slot)); 1107 for (i = 0; i < ch->numslots; i++) { 1108 struct ahci_slot *slot = &ch->slot[i]; 1109 1110 slot->dev = dev; 1111 slot->slot = i; 1112 slot->state = AHCI_SLOT_EMPTY; 1113 slot->ccb = NULL; 1114 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1115 1116 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1117 device_printf(ch->dev, "FAILURE - create data_map\n"); 1118 } 1119} 1120 1121static void 1122ahci_slotsfree(device_t dev) 1123{ 1124 struct ahci_channel *ch = device_get_softc(dev); 1125 int i; 1126 1127 /* Free all dma slots */ 1128 for (i = 0; i < ch->numslots; i++) { 1129 struct ahci_slot *slot = &ch->slot[i]; 1130 1131 callout_drain(&slot->timeout); 1132 if (slot->dma.data_map) { 1133 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1134 slot->dma.data_map = NULL; 1135 } 1136 } 1137} 1138 1139static void 1140ahci_phy_check_events(device_t dev, u_int32_t serr) 1141{ 1142 struct ahci_channel *ch = device_get_softc(dev); 1143 1144 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1145 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1146 union ccb *ccb; 1147 1148 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1149 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1150 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1151 if (bootverbose) 1152 device_printf(dev, "CONNECT requested\n"); 1153 ahci_reset(dev); 1154 } else { 1155 if (bootverbose) 1156 device_printf(dev, "DISCONNECT requested\n"); 1157 ch->devices = 0; 1158 } 1159 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1160 return; 1161 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1162 cam_sim_path(ch->sim), 1163 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1164 xpt_free_ccb(ccb); 1165 return; 1166 } 1167 xpt_rescan(ccb); 1168 } 1169} 1170 1171static void 1172ahci_notify_events(device_t dev, u_int32_t status) 1173{ 1174 struct ahci_channel *ch = device_get_softc(dev); 1175 struct cam_path *dpath; 1176 int i; 1177 1178 if (ch->caps & AHCI_CAP_SSNTF) 1179 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1180 if (bootverbose) 1181 device_printf(dev, "SNTF 0x%04x\n", status); 1182 for (i = 0; i < 16; i++) { 1183 if ((status & (1 << i)) == 0) 1184 continue; 1185 if (xpt_create_path(&dpath, NULL, 1186 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1187 xpt_async(AC_SCSI_AEN, dpath, NULL); 1188 xpt_free_path(dpath); 1189 } 1190 } 1191} 1192 1193static void 1194ahci_ch_intr_locked(void *data) 1195{ 1196 device_t dev = (device_t)data; 1197 struct ahci_channel *ch = device_get_softc(dev); 1198 1199 mtx_lock(&ch->mtx); 1200 ahci_ch_intr(data); 1201 mtx_unlock(&ch->mtx); 1202} 1203 1204static void 1205ahci_ch_pm(void *arg) 1206{ 1207 device_t dev = (device_t)arg; 1208 struct ahci_channel *ch = device_get_softc(dev); 1209 uint32_t work; 1210 1211 if (ch->numrslots != 0) 1212 return; 1213 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1214 if (ch->pm_level == 4) 1215 work |= AHCI_P_CMD_PARTIAL; 1216 else 1217 work |= AHCI_P_CMD_SLUMBER; 1218 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1219} 1220 1221static void 1222ahci_ch_intr(void *data) 1223{ 1224 device_t dev = (device_t)data; 1225 struct ahci_channel *ch = device_get_softc(dev); 1226 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1227 enum ahci_err_type et; 1228 int i, ccs, ncq_err = 0; 1229 1230 /* Read and clear interrupt statuses. */ 1231 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1232 if (istatus == 0) 1233 return; 1234 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1235 /* Read command statuses. */ 1236 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1237 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1238 if (istatus & AHCI_P_IX_SDB) { 1239 if (ch->caps & AHCI_CAP_SSNTF) 1240 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1241 else { 1242 u_int8_t *fis = ch->dma.rfis + 0x58; 1243 1244 if (fis[1] & 0x80) 1245 sntf = (1 << (fis[1] & 0x0f)); 1246 } 1247 } 1248 /* Process PHY events */ 1249 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1250 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1251 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1252 if (serr) { 1253 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1254 ahci_phy_check_events(dev, serr); 1255 } 1256 } 1257 /* Process command errors */ 1258 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1259 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1260//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1261// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1262// serr); 1263 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1264 >> AHCI_P_CMD_CCS_SHIFT; 1265 err = ch->rslots & (cstatus | sstatus); 1266 /* Kick controller into sane state */ 1267 ahci_stop(dev); 1268 ahci_start(dev); 1269 } else { 1270 ccs = 0; 1271 err = 0; 1272 } 1273 /* Complete all successfull commands. */ 1274 ok = ch->rslots & ~(cstatus | sstatus); 1275 for (i = 0; i < ch->numslots; i++) { 1276 if ((ok >> i) & 1) 1277 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1278 } 1279 /* On error, complete the rest of commands with error statuses. */ 1280 if (err) { 1281 if (ch->frozen) { 1282 union ccb *fccb = ch->frozen; 1283 ch->frozen = NULL; 1284 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1285 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1286 xpt_freeze_devq(fccb->ccb_h.path, 1); 1287 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1288 } 1289 xpt_done(fccb); 1290 } 1291 for (i = 0; i < ch->numslots; i++) { 1292 /* XXX: reqests in loading state. */ 1293 if (((err >> i) & 1) == 0) 1294 continue; 1295 if (istatus & AHCI_P_IX_TFE) { 1296 /* Task File Error */ 1297 if (ch->numtslots == 0) { 1298 /* Untagged operation. */ 1299 if (i == ccs) 1300 et = AHCI_ERR_TFE; 1301 else 1302 et = AHCI_ERR_INNOCENT; 1303 } else { 1304 /* Tagged operation. */ 1305 et = AHCI_ERR_NCQ; 1306 ncq_err = 1; 1307 } 1308 } else if (istatus & AHCI_P_IX_IF) { 1309 if (ch->numtslots == 0 && i != ccs) 1310 et = AHCI_ERR_INNOCENT; 1311 else 1312 et = AHCI_ERR_SATA; 1313 } else 1314 et = AHCI_ERR_INVALID; 1315 ahci_end_transaction(&ch->slot[i], et); 1316 } 1317 if (ncq_err) 1318 ahci_issue_read_log(dev); 1319 } 1320 /* Process NOTIFY events */ 1321 if (sntf) 1322 ahci_notify_events(dev, sntf); 1323} 1324 1325/* Must be called with channel locked. */ 1326static int 1327ahci_check_collision(device_t dev, union ccb *ccb) 1328{ 1329 struct ahci_channel *ch = device_get_softc(dev); 1330 1331 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1332 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1333 /* Tagged command while untagged are active. */ 1334 if (ch->numrslots != 0 && ch->numtslots == 0) 1335 return (1); 1336 /* Tagged command while tagged to other target is active. */ 1337 if (ch->numtslots != 0 && 1338 ch->taggedtarget != ccb->ccb_h.target_id) 1339 return (1); 1340 /* Tagged command while we have no supported tag free. */ 1341 if (((~ch->oslots) & (0xffffffff >> (32 - 1342 ch->curr[ccb->ccb_h.target_id].tags))) == 0) 1343 return (1); 1344 } else { 1345 /* Untagged command while tagged are active. */ 1346 if (ch->numrslots != 0 && ch->numtslots != 0) 1347 return (1); 1348 } 1349 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1350 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1351 /* Atomic command while anything active. */ 1352 if (ch->numrslots != 0) 1353 return (1); 1354 } 1355 /* We have some atomic command running. */ 1356 if (ch->aslots != 0) 1357 return (1); 1358 return (0); 1359} 1360 1361/* Must be called with channel locked. */ 1362static void 1363ahci_begin_transaction(device_t dev, union ccb *ccb) 1364{ 1365 struct ahci_channel *ch = device_get_softc(dev); 1366 struct ahci_slot *slot; 1367 int tag, tags; 1368 1369 /* Choose empty slot. */ 1370 tags = ch->numslots; 1371 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1372 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1373 tags = ch->curr[ccb->ccb_h.target_id].tags; 1374 tag = ch->lastslot; 1375 while (1) { 1376 if (tag >= tags) 1377 tag = 0; 1378 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1379 break; 1380 tag++; 1381 }; 1382 ch->lastslot = tag; 1383 /* Occupy chosen slot. */ 1384 slot = &ch->slot[tag]; 1385 slot->ccb = ccb; 1386 /* Stop PM timer. */ 1387 if (ch->numrslots == 0 && ch->pm_level > 3) 1388 callout_stop(&ch->pm_timer); 1389 /* Update channel stats. */ 1390 ch->oslots |= (1 << slot->slot); 1391 ch->numrslots++; 1392 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1393 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1394 ch->numtslots++; 1395 ch->taggedtarget = ccb->ccb_h.target_id; 1396 } 1397 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1398 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1399 ch->aslots |= (1 << slot->slot); 1400 slot->dma.nsegs = 0; 1401 /* If request moves data, setup and load SG list */ 1402 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1403 void *buf; 1404 bus_size_t size; 1405 1406 slot->state = AHCI_SLOT_LOADING; 1407 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1408 buf = ccb->ataio.data_ptr; 1409 size = ccb->ataio.dxfer_len; 1410 } else { 1411 buf = ccb->csio.data_ptr; 1412 size = ccb->csio.dxfer_len; 1413 } 1414 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1415 buf, size, ahci_dmasetprd, slot, 0); 1416 } else 1417 ahci_execute_transaction(slot); 1418} 1419 1420/* Locked by busdma engine. */ 1421static void 1422ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1423{ 1424 struct ahci_slot *slot = arg; 1425 struct ahci_channel *ch = device_get_softc(slot->dev); 1426 struct ahci_cmd_tab *ctp; 1427 struct ahci_dma_prd *prd; 1428 int i; 1429 1430 if (error) { 1431 device_printf(slot->dev, "DMA load error\n"); 1432 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1433 return; 1434 } 1435 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1436 /* Get a piece of the workspace for this request */ 1437 ctp = (struct ahci_cmd_tab *) 1438 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1439 /* Fill S/G table */ 1440 prd = &ctp->prd_tab[0]; 1441 for (i = 0; i < nsegs; i++) { 1442 prd[i].dba = htole64(segs[i].ds_addr); 1443 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1444 } 1445 slot->dma.nsegs = nsegs; 1446 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1447 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1448 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1449 ahci_execute_transaction(slot); 1450} 1451 1452/* Must be called with channel locked. */ 1453static void 1454ahci_execute_transaction(struct ahci_slot *slot) 1455{ 1456 device_t dev = slot->dev; 1457 struct ahci_channel *ch = device_get_softc(dev); 1458 struct ahci_cmd_tab *ctp; 1459 struct ahci_cmd_list *clp; 1460 union ccb *ccb = slot->ccb; 1461 int port = ccb->ccb_h.target_id & 0x0f; 1462 int fis_size; 1463 1464 /* Get a piece of the workspace for this request */ 1465 ctp = (struct ahci_cmd_tab *) 1466 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1467 /* Setup the FIS for this request */ 1468 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1469 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1470 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1471 return; 1472 } 1473 /* Setup the command list entry */ 1474 clp = (struct ahci_cmd_list *) 1475 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1476 clp->prd_length = slot->dma.nsegs; 1477 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1478 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1479 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1480 (fis_size / sizeof(u_int32_t)) | 1481 (port << 12); 1482 /* Special handling for Soft Reset command. */ 1483 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1484 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1485 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1486 /* Kick controller into sane state */ 1487 ahci_stop(dev); 1488 ahci_clo(dev); 1489 ahci_start(dev); 1490 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1491 } 1492 clp->bytecount = 0; 1493 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1494 (AHCI_CT_SIZE * slot->slot)); 1495 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1496 BUS_DMASYNC_PREWRITE); 1497 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1498 BUS_DMASYNC_PREREAD); 1499 /* Set ACTIVE bit for NCQ commands. */ 1500 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1501 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1502 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1503 } 1504 /* Issue command to the controller. */ 1505 slot->state = AHCI_SLOT_RUNNING; 1506 ch->rslots |= (1 << slot->slot); 1507 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1508 /* Device reset commands doesn't interrupt. Poll them. */ 1509 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1510 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1511 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1512 int count, timeout = ccb->ccb_h.timeout; 1513 enum ahci_err_type et = AHCI_ERR_NONE; 1514 1515 for (count = 0; count < timeout; count++) { 1516 DELAY(1000); 1517 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1518 break; 1519 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1520 device_printf(ch->dev, 1521 "Poll error on slot %d, TFD: %04x\n", 1522 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1523 et = AHCI_ERR_TFE; 1524 break; 1525 } 1526 /* Workaround for ATI SB600/SB700 chipsets. */ 1527 if (ccb->ccb_h.target_id == 15 && 1528 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1529 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1530 et = AHCI_ERR_TIMEOUT; 1531 break; 1532 } 1533 } 1534 if (timeout && (count >= timeout)) { 1535 device_printf(ch->dev, 1536 "Poll timeout on slot %d\n", slot->slot); 1537 device_printf(dev, "is %08x cs %08x ss %08x " 1538 "rs %08x tfd %02x serr %08x\n", 1539 ATA_INL(ch->r_mem, AHCI_P_IS), 1540 ATA_INL(ch->r_mem, AHCI_P_CI), 1541 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1542 ATA_INL(ch->r_mem, AHCI_P_TFD), 1543 ATA_INL(ch->r_mem, AHCI_P_SERR)); 1544 et = AHCI_ERR_TIMEOUT; 1545 } 1546 if (et != AHCI_ERR_NONE) { 1547 /* Kick controller into sane state */ 1548 ahci_stop(ch->dev); 1549 ahci_start(ch->dev); 1550 } 1551 ahci_end_transaction(slot, et); 1552 return; 1553 } 1554 /* Start command execution timeout */ 1555 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1556 (timeout_t*)ahci_timeout, slot); 1557 return; 1558} 1559 1560/* Locked by callout mechanism. */ 1561static void 1562ahci_timeout(struct ahci_slot *slot) 1563{ 1564 device_t dev = slot->dev; 1565 struct ahci_channel *ch = device_get_softc(dev); 1566 uint32_t sstatus; 1567 int ccs; 1568 int i; 1569 1570 /* Check for stale timeout. */ 1571 if (slot->state < AHCI_SLOT_RUNNING) 1572 return; 1573 1574 /* Check if slot was not being executed last time we checked. */ 1575 if (slot->state < AHCI_SLOT_EXECUTING) { 1576 /* Check if slot started executing. */ 1577 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1578 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1579 >> AHCI_P_CMD_CCS_SHIFT; 1580 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot) 1581 slot->state = AHCI_SLOT_EXECUTING; 1582 1583 callout_reset(&slot->timeout, 1584 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1585 (timeout_t*)ahci_timeout, slot); 1586 return; 1587 } 1588 1589 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1590 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1591 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1592 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1593 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1594 1595 ch->fatalerr = 1; 1596 /* Handle frozen command. */ 1597 if (ch->frozen) { 1598 union ccb *fccb = ch->frozen; 1599 ch->frozen = NULL; 1600 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1601 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1602 xpt_freeze_devq(fccb->ccb_h.path, 1); 1603 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1604 } 1605 xpt_done(fccb); 1606 } 1607 /* Handle command with timeout. */ 1608 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1609 /* Handle the rest of commands. */ 1610 for (i = 0; i < ch->numslots; i++) { 1611 /* Do we have a running request on slot? */ 1612 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1613 continue; 1614 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1615 } 1616} 1617 1618/* Must be called with channel locked. */ 1619static void 1620ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1621{ 1622 device_t dev = slot->dev; 1623 struct ahci_channel *ch = device_get_softc(dev); 1624 union ccb *ccb = slot->ccb; 1625 1626 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1627 BUS_DMASYNC_POSTWRITE); 1628 /* Read result registers to the result struct 1629 * May be incorrect if several commands finished same time, 1630 * so read only when sure or have to. 1631 */ 1632 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1633 struct ata_res *res = &ccb->ataio.res; 1634 1635 if ((et == AHCI_ERR_TFE) || 1636 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1637 u_int8_t *fis = ch->dma.rfis + 0x40; 1638 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1639 1640 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1641 BUS_DMASYNC_POSTREAD); 1642 res->status = tfd; 1643 res->error = tfd >> 8; 1644 res->lba_low = fis[4]; 1645 res->lba_mid = fis[5]; 1646 res->lba_high = fis[6]; 1647 res->device = fis[7]; 1648 res->lba_low_exp = fis[8]; 1649 res->lba_mid_exp = fis[9]; 1650 res->lba_high_exp = fis[10]; 1651 res->sector_count = fis[12]; 1652 res->sector_count_exp = fis[13]; 1653 } else 1654 bzero(res, sizeof(*res)); 1655 } 1656 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1657 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1658 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1659 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1660 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1661 } 1662 /* In case of error, freeze device for proper recovery. */ 1663 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1664 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1665 xpt_freeze_devq(ccb->ccb_h.path, 1); 1666 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1667 } 1668 /* Set proper result status. */ 1669 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1670 switch (et) { 1671 case AHCI_ERR_NONE: 1672 ccb->ccb_h.status |= CAM_REQ_CMP; 1673 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1674 ccb->csio.scsi_status = SCSI_STATUS_OK; 1675 break; 1676 case AHCI_ERR_INVALID: 1677 ch->fatalerr = 1; 1678 ccb->ccb_h.status |= CAM_REQ_INVALID; 1679 break; 1680 case AHCI_ERR_INNOCENT: 1681 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1682 break; 1683 case AHCI_ERR_TFE: 1684 case AHCI_ERR_NCQ: 1685 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1686 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1687 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1688 } else { 1689 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1690 } 1691 break; 1692 case AHCI_ERR_SATA: 1693 ch->fatalerr = 1; 1694 if (!ch->readlog) { 1695 xpt_freeze_simq(ch->sim, 1); 1696 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1697 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1698 } 1699 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1700 break; 1701 case AHCI_ERR_TIMEOUT: 1702 /* Do no treat soft-reset timeout as fatal here. */ 1703 if (ccb->ccb_h.func_code != XPT_ATA_IO || 1704 !(ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) 1705 ch->fatalerr = 1; 1706 if (!ch->readlog) { 1707 xpt_freeze_simq(ch->sim, 1); 1708 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1709 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1710 } 1711 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1712 break; 1713 default: 1714 ch->fatalerr = 1; 1715 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1716 } 1717 /* Free slot. */ 1718 ch->oslots &= ~(1 << slot->slot); 1719 ch->rslots &= ~(1 << slot->slot); 1720 ch->aslots &= ~(1 << slot->slot); 1721 slot->state = AHCI_SLOT_EMPTY; 1722 slot->ccb = NULL; 1723 /* Update channel stats. */ 1724 ch->numrslots--; 1725 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1726 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1727 ch->numtslots--; 1728 } 1729 /* If it was first request of reset sequence and there is no error, 1730 * proceed to second request. */ 1731 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1732 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1733 (ccb->ataio.cmd.control & ATA_A_RESET) && 1734 et == AHCI_ERR_NONE) { 1735 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1736 ahci_begin_transaction(dev, ccb); 1737 return; 1738 } 1739 /* If it was our READ LOG command - process it. */ 1740 if (ch->readlog) { 1741 ahci_process_read_log(dev, ccb); 1742 /* If it was NCQ command error, put result on hold. */ 1743 } else if (et == AHCI_ERR_NCQ) { 1744 ch->hold[slot->slot] = ccb; 1745 } else 1746 xpt_done(ccb); 1747 /* Unfreeze frozen command. */ 1748 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 1749 union ccb *fccb = ch->frozen; 1750 ch->frozen = NULL; 1751 ahci_begin_transaction(dev, fccb); 1752 xpt_release_simq(ch->sim, TRUE); 1753 } 1754 /* If we have no other active commands, ... */ 1755 if (ch->rslots == 0) { 1756 /* if there was fatal error - reset port. */ 1757 if (ch->fatalerr) { 1758 ahci_reset(dev); 1759 } 1760 } 1761 /* Start PM timer. */ 1762 if (ch->numrslots == 0 && ch->pm_level > 3) { 1763 callout_schedule(&ch->pm_timer, 1764 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1765 } 1766} 1767 1768static void 1769ahci_issue_read_log(device_t dev) 1770{ 1771 struct ahci_channel *ch = device_get_softc(dev); 1772 union ccb *ccb; 1773 struct ccb_ataio *ataio; 1774 int i; 1775 1776 ch->readlog = 1; 1777 /* Find some holden command. */ 1778 for (i = 0; i < ch->numslots; i++) { 1779 if (ch->hold[i]) 1780 break; 1781 } 1782 ccb = xpt_alloc_ccb_nowait(); 1783 if (ccb == NULL) { 1784 device_printf(dev, "Unable allocate READ LOG command"); 1785 return; /* XXX */ 1786 } 1787 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1788 ccb->ccb_h.func_code = XPT_ATA_IO; 1789 ccb->ccb_h.flags = CAM_DIR_IN; 1790 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1791 ataio = &ccb->ataio; 1792 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1793 if (ataio->data_ptr == NULL) { 1794 device_printf(dev, "Unable allocate memory for READ LOG command"); 1795 return; /* XXX */ 1796 } 1797 ataio->dxfer_len = 512; 1798 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1799 ataio->cmd.flags = CAM_ATAIO_48BIT; 1800 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1801 ataio->cmd.sector_count = 1; 1802 ataio->cmd.sector_count_exp = 0; 1803 ataio->cmd.lba_low = 0x10; 1804 ataio->cmd.lba_mid = 0; 1805 ataio->cmd.lba_mid_exp = 0; 1806 /* Freeze SIM while doing READ LOG EXT. */ 1807 xpt_freeze_simq(ch->sim, 1); 1808 ahci_begin_transaction(dev, ccb); 1809} 1810 1811static void 1812ahci_process_read_log(device_t dev, union ccb *ccb) 1813{ 1814 struct ahci_channel *ch = device_get_softc(dev); 1815 uint8_t *data; 1816 struct ata_res *res; 1817 int i; 1818 1819 ch->readlog = 0; 1820 1821 data = ccb->ataio.data_ptr; 1822 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1823 (data[0] & 0x80) == 0) { 1824 for (i = 0; i < ch->numslots; i++) { 1825 if (!ch->hold[i]) 1826 continue; 1827 if ((data[0] & 0x1F) == i) { 1828 res = &ch->hold[i]->ataio.res; 1829 res->status = data[2]; 1830 res->error = data[3]; 1831 res->lba_low = data[4]; 1832 res->lba_mid = data[5]; 1833 res->lba_high = data[6]; 1834 res->device = data[7]; 1835 res->lba_low_exp = data[8]; 1836 res->lba_mid_exp = data[9]; 1837 res->lba_high_exp = data[10]; 1838 res->sector_count = data[12]; 1839 res->sector_count_exp = data[13]; 1840 } else { 1841 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1842 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1843 } 1844 xpt_done(ch->hold[i]); 1845 ch->hold[i] = NULL; 1846 } 1847 } else { 1848 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1849 device_printf(dev, "Error while READ LOG EXT\n"); 1850 else if ((data[0] & 0x80) == 0) { 1851 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1852 } 1853 for (i = 0; i < ch->numslots; i++) { 1854 if (!ch->hold[i]) 1855 continue; 1856 xpt_done(ch->hold[i]); 1857 ch->hold[i] = NULL; 1858 } 1859 } 1860 free(ccb->ataio.data_ptr, M_AHCI); 1861 xpt_free_ccb(ccb); 1862 xpt_release_simq(ch->sim, TRUE); 1863} 1864 1865static void 1866ahci_start(device_t dev) 1867{ 1868 struct ahci_channel *ch = device_get_softc(dev); 1869 u_int32_t cmd; 1870 1871 /* Clear SATA error register */ 1872 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 1873 /* Clear any interrupts pending on this channel */ 1874 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 1875 /* Start operations on this channel */ 1876 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1877 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 1878 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 1879} 1880 1881static void 1882ahci_stop(device_t dev) 1883{ 1884 struct ahci_channel *ch = device_get_softc(dev); 1885 u_int32_t cmd; 1886 int timeout; 1887 1888 /* Kill all activity on this channel */ 1889 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1890 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 1891 /* Wait for activity stop. */ 1892 timeout = 0; 1893 do { 1894 DELAY(1000); 1895 if (timeout++ > 1000) { 1896 device_printf(dev, "stopping AHCI engine failed\n"); 1897 break; 1898 } 1899 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 1900} 1901 1902static void 1903ahci_clo(device_t dev) 1904{ 1905 struct ahci_channel *ch = device_get_softc(dev); 1906 u_int32_t cmd; 1907 int timeout; 1908 1909 /* Issue Command List Override if supported */ 1910 if (ch->caps & AHCI_CAP_SCLO) { 1911 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1912 cmd |= AHCI_P_CMD_CLO; 1913 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 1914 timeout = 0; 1915 do { 1916 DELAY(1000); 1917 if (timeout++ > 1000) { 1918 device_printf(dev, "executing CLO failed\n"); 1919 break; 1920 } 1921 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 1922 } 1923} 1924 1925static void 1926ahci_stop_fr(device_t dev) 1927{ 1928 struct ahci_channel *ch = device_get_softc(dev); 1929 u_int32_t cmd; 1930 int timeout; 1931 1932 /* Kill all FIS reception on this channel */ 1933 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1934 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 1935 /* Wait for FIS reception stop. */ 1936 timeout = 0; 1937 do { 1938 DELAY(1000); 1939 if (timeout++ > 1000) { 1940 device_printf(dev, "stopping AHCI FR engine failed\n"); 1941 break; 1942 } 1943 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 1944} 1945 1946static void 1947ahci_start_fr(device_t dev) 1948{ 1949 struct ahci_channel *ch = device_get_softc(dev); 1950 u_int32_t cmd; 1951 1952 /* Start FIS reception on this channel */ 1953 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1954 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 1955} 1956 1957static int 1958ahci_wait_ready(device_t dev, int t) 1959{ 1960 struct ahci_channel *ch = device_get_softc(dev); 1961 int timeout = 0; 1962 uint32_t val; 1963 1964 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 1965 (ATA_S_BUSY | ATA_S_DRQ)) { 1966 DELAY(1000); 1967 if (timeout++ > t) { 1968 device_printf(dev, "device is not ready (timeout %dms) " 1969 "tfd = %08x\n", t, val); 1970 return (EBUSY); 1971 } 1972 } 1973 if (bootverbose) 1974 device_printf(dev, "ready wait time=%dms\n", timeout); 1975 return (0); 1976} 1977 1978static void 1979ahci_reset(device_t dev) 1980{ 1981 struct ahci_channel *ch = device_get_softc(dev); 1982 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1983 int i; 1984 1985 xpt_freeze_simq(ch->sim, 1); 1986 if (bootverbose) 1987 device_printf(dev, "AHCI reset...\n"); 1988 /* Requeue freezed command. */ 1989 if (ch->frozen) { 1990 union ccb *fccb = ch->frozen; 1991 ch->frozen = NULL; 1992 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1993 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1994 xpt_freeze_devq(fccb->ccb_h.path, 1); 1995 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1996 } 1997 xpt_done(fccb); 1998 } 1999 /* Kill the engine and requeue all running commands. */ 2000 ahci_stop(dev); 2001 for (i = 0; i < ch->numslots; i++) { 2002 /* Do we have a running request on slot? */ 2003 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2004 continue; 2005 /* XXX; Commands in loading state. */ 2006 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2007 } 2008 for (i = 0; i < ch->numslots; i++) { 2009 if (!ch->hold[i]) 2010 continue; 2011 xpt_done(ch->hold[i]); 2012 ch->hold[i] = NULL; 2013 } 2014 ch->fatalerr = 0; 2015 /* Tell the XPT about the event */ 2016 xpt_async(AC_BUS_RESET, ch->path, NULL); 2017 /* Disable port interrupts */ 2018 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2019 /* Reset and reconnect PHY, */ 2020 if (!ahci_sata_phy_reset(dev)) { 2021 if (bootverbose) 2022 device_printf(dev, 2023 "AHCI reset done: phy reset found no device\n"); 2024 ch->devices = 0; 2025 /* Enable wanted port interrupts */ 2026 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2027 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2028 xpt_release_simq(ch->sim, TRUE); 2029 return; 2030 } 2031 /* Wait for clearing busy status. */ 2032 if (ahci_wait_ready(dev, 15000)) 2033 ahci_clo(dev); 2034 ahci_start(dev); 2035 ch->devices = 1; 2036 /* Enable wanted port interrupts */ 2037 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2038 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2039 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2040 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 2041 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2042 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2043 if (bootverbose) 2044 device_printf(dev, "AHCI reset done: device found\n"); 2045 xpt_release_simq(ch->sim, TRUE); 2046} 2047 2048static int 2049ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2050{ 2051 struct ahci_channel *ch = device_get_softc(dev); 2052 u_int8_t *fis = &ctp->cfis[0]; 2053 2054 bzero(ctp->cfis, 64); 2055 fis[0] = 0x27; /* host to device */ 2056 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2057 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2058 fis[1] |= 0x80; 2059 fis[2] = ATA_PACKET_CMD; 2060 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2061 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2062 fis[3] = ATA_F_DMA; 2063 else { 2064 fis[5] = ccb->csio.dxfer_len; 2065 fis[6] = ccb->csio.dxfer_len >> 8; 2066 } 2067 fis[7] = ATA_D_LBA; 2068 fis[15] = ATA_A_4BIT; 2069 bzero(ctp->acmd, 32); 2070 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2071 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2072 ctp->acmd, ccb->csio.cdb_len); 2073 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2074 fis[1] |= 0x80; 2075 fis[2] = ccb->ataio.cmd.command; 2076 fis[3] = ccb->ataio.cmd.features; 2077 fis[4] = ccb->ataio.cmd.lba_low; 2078 fis[5] = ccb->ataio.cmd.lba_mid; 2079 fis[6] = ccb->ataio.cmd.lba_high; 2080 fis[7] = ccb->ataio.cmd.device; 2081 fis[8] = ccb->ataio.cmd.lba_low_exp; 2082 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2083 fis[10] = ccb->ataio.cmd.lba_high_exp; 2084 fis[11] = ccb->ataio.cmd.features_exp; 2085 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2086 fis[12] = tag << 3; 2087 fis[13] = 0; 2088 } else { 2089 fis[12] = ccb->ataio.cmd.sector_count; 2090 fis[13] = ccb->ataio.cmd.sector_count_exp; 2091 } 2092 fis[15] = ATA_A_4BIT; 2093 } else { 2094 fis[15] = ccb->ataio.cmd.control; 2095 } 2096 return (20); 2097} 2098 2099static int 2100ahci_sata_connect(struct ahci_channel *ch) 2101{ 2102 u_int32_t status; 2103 int timeout; 2104 2105 /* Wait up to 100ms for "connect well" */ 2106 for (timeout = 0; timeout < 100 ; timeout++) { 2107 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2108 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2109 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2110 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2111 break; 2112 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2113 if (bootverbose) { 2114 device_printf(ch->dev, "SATA offline status=%08x\n", 2115 status); 2116 } 2117 return (0); 2118 } 2119 DELAY(1000); 2120 } 2121 if (timeout >= 100) { 2122 if (bootverbose) { 2123 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 2124 status); 2125 } 2126 return (0); 2127 } 2128 if (bootverbose) { 2129 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 2130 timeout, status); 2131 } 2132 /* Clear SATA error register */ 2133 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2134 return (1); 2135} 2136 2137static int 2138ahci_sata_phy_reset(device_t dev) 2139{ 2140 struct ahci_channel *ch = device_get_softc(dev); 2141 int sata_rev; 2142 uint32_t val; 2143 2144 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2145 if (sata_rev == 1) 2146 val = ATA_SC_SPD_SPEED_GEN1; 2147 else if (sata_rev == 2) 2148 val = ATA_SC_SPD_SPEED_GEN2; 2149 else if (sata_rev == 3) 2150 val = ATA_SC_SPD_SPEED_GEN3; 2151 else 2152 val = 0; 2153 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2154 ATA_SC_DET_RESET | val | 2155 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2156 DELAY(5000); 2157 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2158 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2159 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2160 DELAY(5000); 2161 return (ahci_sata_connect(ch)); 2162} 2163 2164static void 2165ahciaction(struct cam_sim *sim, union ccb *ccb) 2166{ 2167 device_t dev; 2168 struct ahci_channel *ch; 2169 2170 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2171 ccb->ccb_h.func_code)); 2172 2173 ch = (struct ahci_channel *)cam_sim_softc(sim); 2174 dev = ch->dev; 2175 switch (ccb->ccb_h.func_code) { 2176 /* Common cases first */ 2177 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2178 case XPT_SCSI_IO: 2179 if (ch->devices == 0) { 2180 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2181 xpt_done(ccb); 2182 break; 2183 } 2184 /* Check for command collision. */ 2185 if (ahci_check_collision(dev, ccb)) { 2186 /* Freeze command. */ 2187 ch->frozen = ccb; 2188 /* We have only one frozen slot, so freeze simq also. */ 2189 xpt_freeze_simq(ch->sim, 1); 2190 return; 2191 } 2192 ahci_begin_transaction(dev, ccb); 2193 break; 2194 case XPT_EN_LUN: /* Enable LUN as a target */ 2195 case XPT_TARGET_IO: /* Execute target I/O request */ 2196 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2197 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2198 case XPT_ABORT: /* Abort the specified CCB */ 2199 /* XXX Implement */ 2200 ccb->ccb_h.status = CAM_REQ_INVALID; 2201 xpt_done(ccb); 2202 break; 2203 case XPT_SET_TRAN_SETTINGS: 2204 { 2205 struct ccb_trans_settings *cts = &ccb->cts; 2206 struct ahci_device *d; 2207 2208 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2209 d = &ch->curr[ccb->ccb_h.target_id]; 2210 else 2211 d = &ch->user[ccb->ccb_h.target_id]; 2212 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2213 d->revision = cts->xport_specific.sata.revision; 2214 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2215 d->mode = cts->xport_specific.sata.mode; 2216 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2217 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2218 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2219 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2220 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2221 ch->pm_present = cts->xport_specific.sata.pm_present; 2222 ccb->ccb_h.status = CAM_REQ_CMP; 2223 xpt_done(ccb); 2224 break; 2225 } 2226 case XPT_GET_TRAN_SETTINGS: 2227 /* Get default/user set transfer settings for the target */ 2228 { 2229 struct ccb_trans_settings *cts = &ccb->cts; 2230 struct ahci_device *d; 2231 uint32_t status; 2232 2233 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2234 d = &ch->curr[ccb->ccb_h.target_id]; 2235 else 2236 d = &ch->user[ccb->ccb_h.target_id]; 2237 cts->protocol = PROTO_ATA; 2238 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2239 cts->transport = XPORT_SATA; 2240 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2241 cts->proto_specific.valid = 0; 2242 cts->xport_specific.sata.valid = 0; 2243 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2244 (ccb->ccb_h.target_id == 15 || 2245 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2246 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2247 if (status & 0x0f0) { 2248 cts->xport_specific.sata.revision = 2249 (status & 0x0f0) >> 4; 2250 cts->xport_specific.sata.valid |= 2251 CTS_SATA_VALID_REVISION; 2252 } 2253 } else { 2254 cts->xport_specific.sata.revision = d->revision; 2255 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2256 } 2257 cts->xport_specific.sata.mode = d->mode; 2258 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2259 cts->xport_specific.sata.bytecount = d->bytecount; 2260 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2261 cts->xport_specific.sata.pm_present = ch->pm_present; 2262 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2263 cts->xport_specific.sata.tags = d->tags; 2264 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2265 ccb->ccb_h.status = CAM_REQ_CMP; 2266 xpt_done(ccb); 2267 break; 2268 } 2269#if 0 2270 case XPT_CALC_GEOMETRY: 2271 { 2272 struct ccb_calc_geometry *ccg; 2273 uint32_t size_mb; 2274 uint32_t secs_per_cylinder; 2275 2276 ccg = &ccb->ccg; 2277 size_mb = ccg->volume_size 2278 / ((1024L * 1024L) / ccg->block_size); 2279 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 2280 if (size_mb >= 2048) { 2281 ccg->heads = 255; 2282 ccg->secs_per_track = 63; 2283 } else { 2284 ccg->heads = 128; 2285 ccg->secs_per_track = 32; 2286 } 2287 } else { 2288 ccg->heads = 64; 2289 ccg->secs_per_track = 32; 2290 } 2291 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2292 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2293 ccb->ccb_h.status = CAM_REQ_CMP; 2294 xpt_done(ccb); 2295 break; 2296 } 2297#endif 2298 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2299 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2300 ahci_reset(dev); 2301 ccb->ccb_h.status = CAM_REQ_CMP; 2302 xpt_done(ccb); 2303 break; 2304 case XPT_TERM_IO: /* Terminate the I/O process */ 2305 /* XXX Implement */ 2306 ccb->ccb_h.status = CAM_REQ_INVALID; 2307 xpt_done(ccb); 2308 break; 2309 case XPT_PATH_INQ: /* Path routing inquiry */ 2310 { 2311 struct ccb_pathinq *cpi = &ccb->cpi; 2312 2313 cpi->version_num = 1; /* XXX??? */ 2314 cpi->hba_inquiry = PI_SDTR_ABLE; 2315 if (ch->caps & AHCI_CAP_SNCQ) 2316 cpi->hba_inquiry |= PI_TAG_ABLE; 2317 if (ch->caps & AHCI_CAP_SPM) 2318 cpi->hba_inquiry |= PI_SATAPM; 2319 cpi->target_sprt = 0; 2320 cpi->hba_misc = PIM_SEQSCAN; 2321 cpi->hba_eng_cnt = 0; 2322 if (ch->caps & AHCI_CAP_SPM) 2323 cpi->max_target = 15; 2324 else 2325 cpi->max_target = 0; 2326 cpi->max_lun = 0; 2327 cpi->initiator_id = 0; 2328 cpi->bus_id = cam_sim_bus(sim); 2329 cpi->base_transfer_speed = 150000; 2330 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2331 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2332 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2333 cpi->unit_number = cam_sim_unit(sim); 2334 cpi->transport = XPORT_SATA; 2335 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2336 cpi->protocol = PROTO_ATA; 2337 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2338 cpi->maxio = MAXPHYS; 2339 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2340 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 2341 cpi->maxio = min(cpi->maxio, 128 * 512); 2342 cpi->ccb_h.status = CAM_REQ_CMP; 2343 xpt_done(ccb); 2344 break; 2345 } 2346 default: 2347 ccb->ccb_h.status = CAM_REQ_INVALID; 2348 xpt_done(ccb); 2349 break; 2350 } 2351} 2352 2353static void 2354ahcipoll(struct cam_sim *sim) 2355{ 2356 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2357 2358 ahci_ch_intr(ch->dev); 2359} 2360