ahci_pci.c revision 258162
1195534Sscottl/*- 2238805Smav * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3195534Sscottl * All rights reserved. 4195534Sscottl * 5195534Sscottl * Redistribution and use in source and binary forms, with or without 6195534Sscottl * modification, are permitted provided that the following conditions 7195534Sscottl * are met: 8195534Sscottl * 1. Redistributions of source code must retain the above copyright 9195534Sscottl * notice, this list of conditions and the following disclaimer, 10195534Sscottl * without modification, immediately at the beginning of the file. 11195534Sscottl * 2. Redistributions in binary form must reproduce the above copyright 12195534Sscottl * notice, this list of conditions and the following disclaimer in the 13195534Sscottl * documentation and/or other materials provided with the distribution. 14195534Sscottl * 15195534Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16195534Sscottl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17195534Sscottl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18195534Sscottl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19195534Sscottl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20195534Sscottl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21195534Sscottl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22195534Sscottl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23195534Sscottl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24195534Sscottl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25195534Sscottl */ 26195534Sscottl 27195534Sscottl#include <sys/cdefs.h> 28195534Sscottl__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 258162 2013-11-15 10:28:59Z mav $"); 29195534Sscottl 30195534Sscottl#include <sys/param.h> 31195534Sscottl#include <sys/module.h> 32195534Sscottl#include <sys/systm.h> 33195534Sscottl#include <sys/kernel.h> 34195534Sscottl#include <sys/bus.h> 35220576Smav#include <sys/conf.h> 36195534Sscottl#include <sys/endian.h> 37195534Sscottl#include <sys/malloc.h> 38195534Sscottl#include <sys/lock.h> 39195534Sscottl#include <sys/mutex.h> 40195534Sscottl#include <machine/stdarg.h> 41195534Sscottl#include <machine/resource.h> 42195534Sscottl#include <machine/bus.h> 43195534Sscottl#include <sys/rman.h> 44195534Sscottl#include <dev/pci/pcivar.h> 45195534Sscottl#include <dev/pci/pcireg.h> 46195534Sscottl#include "ahci.h" 47195534Sscottl 48195534Sscottl#include <cam/cam.h> 49195534Sscottl#include <cam/cam_ccb.h> 50195534Sscottl#include <cam/cam_sim.h> 51195534Sscottl#include <cam/cam_xpt_sim.h> 52195534Sscottl#include <cam/cam_debug.h> 53195534Sscottl 54195534Sscottl/* local prototypes */ 55195534Sscottlstatic int ahci_setup_interrupt(device_t dev); 56195534Sscottlstatic void ahci_intr(void *data); 57195534Sscottlstatic void ahci_intr_one(void *data); 58256843Smavstatic void ahci_intr_one_edge(void *data); 59195534Sscottlstatic int ahci_suspend(device_t dev); 60195534Sscottlstatic int ahci_resume(device_t dev); 61208375Smavstatic int ahci_ch_init(device_t dev); 62208375Smavstatic int ahci_ch_deinit(device_t dev); 63195534Sscottlstatic int ahci_ch_suspend(device_t dev); 64195534Sscottlstatic int ahci_ch_resume(device_t dev); 65196656Smavstatic void ahci_ch_pm(void *arg); 66256843Smavstatic void ahci_ch_intr(void *arg); 67256843Smavstatic void ahci_ch_intr_direct(void *arg); 68256843Smavstatic void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 69195534Sscottlstatic int ahci_ctlr_reset(device_t dev); 70205422Smavstatic int ahci_ctlr_setup(device_t dev); 71195534Sscottlstatic void ahci_begin_transaction(device_t dev, union ccb *ccb); 72195534Sscottlstatic void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 73195534Sscottlstatic void ahci_execute_transaction(struct ahci_slot *slot); 74195534Sscottlstatic void ahci_timeout(struct ahci_slot *slot); 75195534Sscottlstatic void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 76199821Smavstatic int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 77195534Sscottlstatic void ahci_dmainit(device_t dev); 78195534Sscottlstatic void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 79195534Sscottlstatic void ahci_dmafini(device_t dev); 80195534Sscottlstatic void ahci_slotsalloc(device_t dev); 81195534Sscottlstatic void ahci_slotsfree(device_t dev); 82195534Sscottlstatic void ahci_reset(device_t dev); 83203123Smavstatic void ahci_start(device_t dev, int fbs); 84195534Sscottlstatic void ahci_stop(device_t dev); 85195534Sscottlstatic void ahci_clo(device_t dev); 86195534Sscottlstatic void ahci_start_fr(device_t dev); 87195534Sscottlstatic void ahci_stop_fr(device_t dev); 88195534Sscottl 89195534Sscottlstatic int ahci_sata_connect(struct ahci_channel *ch); 90203108Smavstatic int ahci_sata_phy_reset(device_t dev); 91220576Smavstatic int ahci_wait_ready(device_t dev, int t, int t0); 92195534Sscottl 93220565Smavstatic void ahci_issue_recovery(device_t dev); 94195534Sscottlstatic void ahci_process_read_log(device_t dev, union ccb *ccb); 95220565Smavstatic void ahci_process_request_sense(device_t dev, union ccb *ccb); 96195534Sscottl 97195534Sscottlstatic void ahciaction(struct cam_sim *sim, union ccb *ccb); 98195534Sscottlstatic void ahcipoll(struct cam_sim *sim); 99195534Sscottl 100227293Sedstatic MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 101195534Sscottl 102199176Smavstatic struct { 103199176Smav uint32_t id; 104203030Smav uint8_t rev; 105199176Smav const char *name; 106199322Smav int quirks; 107199322Smav#define AHCI_Q_NOFORCE 1 108199322Smav#define AHCI_Q_NOPMP 2 109199322Smav#define AHCI_Q_NONCQ 4 110199322Smav#define AHCI_Q_1CH 8 111199322Smav#define AHCI_Q_2CH 16 112199322Smav#define AHCI_Q_4CH 32 113199322Smav#define AHCI_Q_EDGEIS 64 114203030Smav#define AHCI_Q_SATA2 128 115203123Smav#define AHCI_Q_NOBSYRES 256 116207499Smav#define AHCI_Q_NOAA 512 117218596Smav#define AHCI_Q_NOCOUNT 1024 118222304Smav#define AHCI_Q_ALTSIG 2048 119245875Smav#define AHCI_Q_NOMSI 4096 120250792Ssmh 121250792Ssmh#define AHCI_Q_BIT_STRING \ 122250792Ssmh "\020" \ 123250792Ssmh "\001NOFORCE" \ 124250792Ssmh "\002NOPMP" \ 125250792Ssmh "\003NONCQ" \ 126250792Ssmh "\0041CH" \ 127250792Ssmh "\0052CH" \ 128250792Ssmh "\0064CH" \ 129250792Ssmh "\007EDGEIS" \ 130250792Ssmh "\010SATA2" \ 131250792Ssmh "\011NOBSYRES" \ 132250792Ssmh "\012NOAA" \ 133250792Ssmh "\013NOCOUNT" \ 134250792Ssmh "\014ALTSIG" \ 135250792Ssmh "\015NOMSI" 136199176Smav} ahci_ids[] = { 137245875Smav {0x43801002, 0x00, "ATI IXP600", AHCI_Q_NOMSI}, 138203030Smav {0x43901002, 0x00, "ATI IXP700", 0}, 139203030Smav {0x43911002, 0x00, "ATI IXP700", 0}, 140203030Smav {0x43921002, 0x00, "ATI IXP700", 0}, 141203030Smav {0x43931002, 0x00, "ATI IXP700", 0}, 142203030Smav {0x43941002, 0x00, "ATI IXP800", 0}, 143203030Smav {0x43951002, 0x00, "ATI IXP800", 0}, 144244146Smav {0x78001022, 0x00, "AMD Hudson-2", 0}, 145244146Smav {0x78011022, 0x00, "AMD Hudson-2", 0}, 146244146Smav {0x78021022, 0x00, "AMD Hudson-2", 0}, 147244146Smav {0x78031022, 0x00, "AMD Hudson-2", 0}, 148244146Smav {0x78041022, 0x00, "AMD Hudson-2", 0}, 149225140Smav {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 150203030Smav {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 151203030Smav {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 152203030Smav {0x26818086, 0x00, "Intel ESB2", 0}, 153203030Smav {0x26828086, 0x00, "Intel ESB2", 0}, 154203030Smav {0x26838086, 0x00, "Intel ESB2", 0}, 155203030Smav {0x27c18086, 0x00, "Intel ICH7", 0}, 156203030Smav {0x27c38086, 0x00, "Intel ICH7", 0}, 157203030Smav {0x27c58086, 0x00, "Intel ICH7M", 0}, 158203030Smav {0x27c68086, 0x00, "Intel ICH7M", 0}, 159203030Smav {0x28218086, 0x00, "Intel ICH8", 0}, 160203030Smav {0x28228086, 0x00, "Intel ICH8", 0}, 161203030Smav {0x28248086, 0x00, "Intel ICH8", 0}, 162203030Smav {0x28298086, 0x00, "Intel ICH8M", 0}, 163203030Smav {0x282a8086, 0x00, "Intel ICH8M", 0}, 164203030Smav {0x29228086, 0x00, "Intel ICH9", 0}, 165203030Smav {0x29238086, 0x00, "Intel ICH9", 0}, 166203030Smav {0x29248086, 0x00, "Intel ICH9", 0}, 167203030Smav {0x29258086, 0x00, "Intel ICH9", 0}, 168203030Smav {0x29278086, 0x00, "Intel ICH9", 0}, 169203030Smav {0x29298086, 0x00, "Intel ICH9M", 0}, 170203030Smav {0x292a8086, 0x00, "Intel ICH9M", 0}, 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{0x1f258086, 0x00, "Intel Avoton (RAID)", 0}, 205258162Smav {0x1f268086, 0x00, "Intel Avoton (RAID)", 0}, 206258162Smav {0x1f278086, 0x00, "Intel Avoton (RAID)", 0}, 207258162Smav {0x1f2e8086, 0x00, "Intel Avoton (RAID)", 0}, 208258162Smav {0x1f2f8086, 0x00, "Intel Avoton (RAID)", 0}, 209258162Smav {0x1f328086, 0x00, "Intel Avoton", 0}, 210258162Smav {0x1f338086, 0x00, "Intel Avoton", 0}, 211258162Smav {0x1f348086, 0x00, "Intel Avoton (RAID)", 0}, 212258162Smav {0x1f358086, 0x00, "Intel Avoton (RAID)", 0}, 213258162Smav {0x1f368086, 0x00, "Intel Avoton (RAID)", 0}, 214258162Smav {0x1f378086, 0x00, "Intel Avoton (RAID)", 0}, 215258162Smav {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0}, 216258162Smav {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0}, 217253475Sjfv {0x23a38086, 0x00, "Intel Coleto Creek", 0}, 218258162Smav {0x28238086, 0x00, "Intel Wellsburg (RAID)", 0}, 219258162Smav {0x28278086, 0x00, "Intel Wellsburg (RAID)", 0}, 220244983Sjfv {0x8c028086, 0x00, "Intel Lynx Point", 0}, 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237258162Smav {0x9c048086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 238258162Smav {0x9c058086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 239258162Smav {0x9c068086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 240258162Smav {0x9c078086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 241258162Smav {0x9c0e8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 242258162Smav {0x9c0f8086, 0x00, "Intel Lynx Point-LP (RAID)", 0}, 243221789Sjfv {0x23238086, 0x00, "Intel DH89xxCC", 0}, 244239907Smav {0x2360197b, 0x00, "JMicron JMB360", 0}, 245203030Smav {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 246239907Smav {0x2362197b, 0x00, "JMicron JMB362", 0}, 247203030Smav {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 248203030Smav {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 249203030Smav {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 250203030Smav {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 251232380Smav {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 252218596Smav AHCI_Q_EDGEIS}, 253232380Smav {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 254218596Smav AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 255232380Smav {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 256218596Smav AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 257232380Smav {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 258218596Smav AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 259220413Smav {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 260222304Smav {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 261203123Smav {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 262223699Smav {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 263225789Smav {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 264236242Shselasky {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 265222306Smav {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 266221504Smav {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 267254987Sgavin {0x91831b4b, 0x00, "Marvell 88SS9183", AHCI_Q_NOBSYRES}, 268253069Smav {0x91a01b4b, 0x00, "Marvell 88SE91Ax", AHCI_Q_NOBSYRES}, 269253074Smav {0x92151b4b, 0x00, "Marvell 88SE9215", AHCI_Q_NOBSYRES}, 270236737Smav {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 271236737Smav {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 272236737Smav {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 273216309Smav {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 274216309Smav {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 275216309Smav {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 276216309Smav {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 277217245Smav {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 278219341Smav {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 279217245Smav {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 280219341Smav {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 281250185Smav {0x06411103, 0x00, "HighPoint RocketRAID 640L", AHCI_Q_NOBSYRES}, 282250185Smav {0x06421103, 0x00, "HighPoint RocketRAID 642L", AHCI_Q_NOBSYRES}, 283250185Smav {0x06451103, 0x00, "HighPoint RocketRAID 644L", AHCI_Q_NOBSYRES}, 284207499Smav {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 285207499Smav {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 286207499Smav {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 287207499Smav {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 288207499Smav {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 289207499Smav {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 290207499Smav {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 291207499Smav {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 292207499Smav {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 293207499Smav {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 294207499Smav {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 295207499Smav {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 296207499Smav {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 297207499Smav {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 298207499Smav {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 299207499Smav {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 300207499Smav {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 301207499Smav {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 302207499Smav {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 303207499Smav {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 304207499Smav {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 305207499Smav {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 306207499Smav {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 307207499Smav {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 308207499Smav {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 309207499Smav {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 310207499Smav {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 311207499Smav {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 312207499Smav {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 313207499Smav {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 314207499Smav {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 315207499Smav {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 316207499Smav {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 317207499Smav {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 318207499Smav {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 319207499Smav {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 320207499Smav {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 321207499Smav {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 322207499Smav {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 323207499Smav {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 324207499Smav {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 325207499Smav {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 326207499Smav {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 327207499Smav {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 328207499Smav {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 329207499Smav {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 330207499Smav {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 331207499Smav {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 332207499Smav {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 333207499Smav {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 334207499Smav {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 335207499Smav {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 336207499Smav {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 337207499Smav {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 338207499Smav {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 339207499Smav {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 340207499Smav {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 341207499Smav {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 342224603Smav {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 343207499Smav {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 344207499Smav {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 345207499Smav {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 346207499Smav {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 347207499Smav {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 348207499Smav {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 349207499Smav {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 350207499Smav {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 351207499Smav {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 352207499Smav {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 353208907Smav {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 354208907Smav {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 355203030Smav {0x11841039, 0x00, "SiS 966", 0}, 356203030Smav {0x11851039, 0x00, "SiS 968", 0}, 357203030Smav {0x01861039, 0x00, "SiS 968", 0}, 358203030Smav {0x00000000, 0x00, NULL, 0} 359199176Smav}; 360199176Smav 361220565Smav#define recovery_type spriv_field0 362220565Smav#define RECOVERY_NONE 0 363220565Smav#define RECOVERY_READ_LOG 1 364220565Smav#define RECOVERY_REQUEST_SENSE 2 365220565Smav#define recovery_slot spriv_field1 366220565Smav 367228200Smavstatic int force_ahci = 1; 368228200SmavTUNABLE_INT("hw.ahci.force", &force_ahci); 369228200Smav 370195534Sscottlstatic int 371195534Sscottlahci_probe(device_t dev) 372195534Sscottl{ 373199176Smav char buf[64]; 374199322Smav int i, valid = 0; 375199322Smav uint32_t devid = pci_get_devid(dev); 376203030Smav uint8_t revid = pci_get_revid(dev); 377199322Smav 378199322Smav /* Is this a possible AHCI candidate? */ 379199322Smav if (pci_get_class(dev) == PCIC_STORAGE && 380199322Smav pci_get_subclass(dev) == PCIS_STORAGE_SATA && 381199322Smav pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 382199322Smav valid = 1; 383199322Smav /* Is this a known AHCI chip? */ 384199322Smav for (i = 0; ahci_ids[i].id != 0; i++) { 385199322Smav if (ahci_ids[i].id == devid && 386203030Smav ahci_ids[i].rev <= revid && 387228200Smav (valid || (force_ahci == 1 && 388228200Smav !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 389199717Smav /* Do not attach JMicrons with single PCI function. */ 390199717Smav if (pci_get_vendor(dev) == 0x197b && 391199717Smav (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 392199717Smav return (ENXIO); 393199322Smav snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 394199322Smav ahci_ids[i].name); 395199322Smav device_set_desc_copy(dev, buf); 396199322Smav return (BUS_PROBE_VENDOR); 397199322Smav } 398199322Smav } 399199322Smav if (!valid) 400199322Smav return (ENXIO); 401199322Smav device_set_desc_copy(dev, "AHCI SATA controller"); 402199322Smav return (BUS_PROBE_VENDOR); 403199322Smav} 404199322Smav 405199322Smavstatic int 406199322Smavahci_ata_probe(device_t dev) 407199322Smav{ 408199322Smav char buf[64]; 409199176Smav int i; 410199176Smav uint32_t devid = pci_get_devid(dev); 411203030Smav uint8_t revid = pci_get_revid(dev); 412195534Sscottl 413199322Smav if ((intptr_t)device_get_ivars(dev) >= 0) 414199322Smav return (ENXIO); 415199176Smav /* Is this a known AHCI chip? */ 416199176Smav for (i = 0; ahci_ids[i].id != 0; i++) { 417203030Smav if (ahci_ids[i].id == devid && 418203030Smav ahci_ids[i].rev <= revid) { 419199176Smav snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 420199176Smav ahci_ids[i].name); 421199176Smav device_set_desc_copy(dev, buf); 422199176Smav return (BUS_PROBE_VENDOR); 423199176Smav } 424199176Smav } 425199176Smav device_set_desc_copy(dev, "AHCI SATA controller"); 426195534Sscottl return (BUS_PROBE_VENDOR); 427195534Sscottl} 428195534Sscottl 429195534Sscottlstatic int 430195534Sscottlahci_attach(device_t dev) 431195534Sscottl{ 432195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 433195534Sscottl device_t child; 434199322Smav int error, unit, speed, i; 435256843Smav u_int u; 436199322Smav uint32_t devid = pci_get_devid(dev); 437203030Smav uint8_t revid = pci_get_revid(dev); 438196656Smav u_int32_t version; 439195534Sscottl 440195534Sscottl ctlr->dev = dev; 441199322Smav i = 0; 442203030Smav while (ahci_ids[i].id != 0 && 443203030Smav (ahci_ids[i].id != devid || 444203030Smav ahci_ids[i].rev > revid)) 445199322Smav i++; 446199322Smav ctlr->quirks = ahci_ids[i].quirks; 447196656Smav resource_int_value(device_get_name(dev), 448196656Smav device_get_unit(dev), "ccc", &ctlr->ccc); 449195534Sscottl /* if we have a memory BAR(5) we are likely on an AHCI part */ 450195534Sscottl ctlr->r_rid = PCIR_BAR(5); 451195534Sscottl if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 452195534Sscottl &ctlr->r_rid, RF_ACTIVE))) 453195534Sscottl return ENXIO; 454195534Sscottl /* Setup our own memory management for channels. */ 455208414Smav ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 456208414Smav ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 457195534Sscottl ctlr->sc_iomem.rm_type = RMAN_ARRAY; 458195534Sscottl ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 459195534Sscottl if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 460195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 461195534Sscottl return (error); 462195534Sscottl } 463195534Sscottl if ((error = rman_manage_region(&ctlr->sc_iomem, 464195534Sscottl rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 465195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 466195534Sscottl rman_fini(&ctlr->sc_iomem); 467195534Sscottl return (error); 468195534Sscottl } 469207511Smav pci_enable_busmaster(dev); 470195534Sscottl /* Reset controller */ 471195534Sscottl if ((error = ahci_ctlr_reset(dev)) != 0) { 472195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 473195534Sscottl rman_fini(&ctlr->sc_iomem); 474195534Sscottl return (error); 475195534Sscottl }; 476199322Smav /* Get the HW capabilities */ 477199322Smav version = ATA_INL(ctlr->r_mem, AHCI_VS); 478199322Smav ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 479240383Smav if (version >= 0x00010200) 480199322Smav ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 481203108Smav if (ctlr->caps & AHCI_CAP_EMS) 482203108Smav ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 483195534Sscottl ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 484222304Smav 485222304Smav /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 486222304Smav if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 487222304Smav (ctlr->quirks & AHCI_Q_ALTSIG) && 488222304Smav (ctlr->caps & AHCI_CAP_SPM) == 0) 489222304Smav ctlr->quirks &= ~AHCI_Q_NOBSYRES; 490222304Smav 491199322Smav if (ctlr->quirks & AHCI_Q_1CH) { 492199322Smav ctlr->caps &= ~AHCI_CAP_NPMASK; 493199322Smav ctlr->ichannels &= 0x01; 494199322Smav } 495199322Smav if (ctlr->quirks & AHCI_Q_2CH) { 496199322Smav ctlr->caps &= ~AHCI_CAP_NPMASK; 497199322Smav ctlr->caps |= 1; 498199322Smav ctlr->ichannels &= 0x03; 499199322Smav } 500199322Smav if (ctlr->quirks & AHCI_Q_4CH) { 501199322Smav ctlr->caps &= ~AHCI_CAP_NPMASK; 502199322Smav ctlr->caps |= 3; 503199322Smav ctlr->ichannels &= 0x0f; 504199322Smav } 505195534Sscottl ctlr->channels = MAX(flsl(ctlr->ichannels), 506199322Smav (ctlr->caps & AHCI_CAP_NPMASK) + 1); 507199322Smav if (ctlr->quirks & AHCI_Q_NOPMP) 508199322Smav ctlr->caps &= ~AHCI_CAP_SPM; 509199322Smav if (ctlr->quirks & AHCI_Q_NONCQ) 510199322Smav ctlr->caps &= ~AHCI_CAP_SNCQ; 511205422Smav if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 512205422Smav ctlr->ccc = 0; 513222039Smav ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 514249346Smav 515249346Smav /* Create controller-wide DMA tag. */ 516249346Smav if (bus_dma_tag_create(bus_get_dma_tag(dev), 0, 0, 517249346Smav (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 518249346Smav BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 519249346Smav BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 520249346Smav 0, NULL, NULL, &ctlr->dma_tag)) { 521249346Smav bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 522249346Smav ctlr->r_mem); 523249346Smav rman_fini(&ctlr->sc_iomem); 524249346Smav return ENXIO; 525249346Smav } 526249346Smav 527205422Smav ahci_ctlr_setup(dev); 528195534Sscottl /* Setup interrupts. */ 529195534Sscottl if (ahci_setup_interrupt(dev)) { 530249346Smav bus_dma_tag_destroy(ctlr->dma_tag); 531195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 532195534Sscottl rman_fini(&ctlr->sc_iomem); 533195534Sscottl return ENXIO; 534195534Sscottl } 535256843Smav i = 0; 536256843Smav for (u = ctlr->ichannels; u != 0; u >>= 1) 537256843Smav i += (u & 1); 538256843Smav ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 539256843Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 540256843Smav "direct", &ctlr->direct); 541195534Sscottl /* Announce HW capabilities. */ 542196656Smav speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 543195534Sscottl device_printf(dev, 544203123Smav "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 545195534Sscottl ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 546195534Sscottl ((version >> 4) & 0xf0) + (version & 0x0f), 547196656Smav (ctlr->caps & AHCI_CAP_NPMASK) + 1, 548195534Sscottl ((speed == 1) ? "1.5":((speed == 2) ? "3": 549195534Sscottl ((speed == 3) ? "6":"?"))), 550196656Smav (ctlr->caps & AHCI_CAP_SPM) ? 551203123Smav "supported" : "not supported", 552203123Smav (ctlr->caps & AHCI_CAP_FBSS) ? 553203123Smav " with FBS" : ""); 554250792Ssmh if (ctlr->quirks != 0) { 555250792Ssmh device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 556250792Ssmh AHCI_Q_BIT_STRING); 557250792Ssmh } 558195534Sscottl if (bootverbose) { 559195534Sscottl device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 560196656Smav (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 561196656Smav (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 562196656Smav (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 563196656Smav (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 564196656Smav (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 565196656Smav (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 566196656Smav (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 567196656Smav (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 568195534Sscottl ((speed == 1) ? "1.5":((speed == 2) ? "3": 569195534Sscottl ((speed == 3) ? "6":"?")))); 570195534Sscottl printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 571196656Smav (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 572196656Smav (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 573196656Smav (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 574196656Smav (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 575196656Smav (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 576196656Smav (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 577196656Smav ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 578196656Smav (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 579196656Smav (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 580196656Smav (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 581196656Smav (ctlr->caps & AHCI_CAP_NPMASK) + 1); 582195534Sscottl } 583240383Smav if (bootverbose && version >= 0x00010200) { 584253647Smav device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 585253647Smav (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 586253647Smav (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 587253647Smav (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 588196656Smav (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 589196656Smav (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 590196656Smav (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 591196656Smav } 592195534Sscottl /* Attach all channels on this controller */ 593195534Sscottl for (unit = 0; unit < ctlr->channels; unit++) { 594195534Sscottl child = device_add_child(dev, "ahcich", -1); 595227635Smav if (child == NULL) { 596195534Sscottl device_printf(dev, "failed to add channel device\n"); 597227635Smav continue; 598227635Smav } 599227635Smav device_set_ivars(child, (void *)(intptr_t)unit); 600227635Smav if ((ctlr->ichannels & (1 << unit)) == 0) 601227635Smav device_disable(child); 602195534Sscottl } 603238805Smav if (ctlr->caps & AHCI_CAP_EMS) { 604238805Smav child = device_add_child(dev, "ahciem", -1); 605238805Smav if (child == NULL) 606238805Smav device_printf(dev, "failed to add enclosure device\n"); 607238805Smav else 608238805Smav device_set_ivars(child, (void *)(intptr_t)-1); 609238805Smav } 610195534Sscottl bus_generic_attach(dev); 611195534Sscottl return 0; 612195534Sscottl} 613195534Sscottl 614195534Sscottlstatic int 615195534Sscottlahci_detach(device_t dev) 616195534Sscottl{ 617195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 618227701Shselasky int i; 619195534Sscottl 620195534Sscottl /* Detach & delete all children */ 621227849Shselasky device_delete_children(dev); 622227701Shselasky 623195534Sscottl /* Free interrupts. */ 624195534Sscottl for (i = 0; i < ctlr->numirqs; i++) { 625195534Sscottl if (ctlr->irqs[i].r_irq) { 626195534Sscottl bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 627195534Sscottl ctlr->irqs[i].handle); 628195534Sscottl bus_release_resource(dev, SYS_RES_IRQ, 629195534Sscottl ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 630195534Sscottl } 631195534Sscottl } 632195534Sscottl pci_release_msi(dev); 633249346Smav bus_dma_tag_destroy(ctlr->dma_tag); 634195534Sscottl /* Free memory. */ 635195534Sscottl rman_fini(&ctlr->sc_iomem); 636195534Sscottl if (ctlr->r_mem) 637195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 638195534Sscottl return (0); 639195534Sscottl} 640195534Sscottl 641195534Sscottlstatic int 642195534Sscottlahci_ctlr_reset(device_t dev) 643195534Sscottl{ 644195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 645195534Sscottl int timeout; 646195534Sscottl 647240693Sgavin if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 && 648195534Sscottl (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 649195534Sscottl pci_write_config(dev, 0x92, 0x01, 1); 650195534Sscottl /* Enable AHCI mode */ 651195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 652195534Sscottl /* Reset AHCI controller */ 653195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 654195534Sscottl for (timeout = 1000; timeout > 0; timeout--) { 655195534Sscottl DELAY(1000); 656195534Sscottl if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 657195534Sscottl break; 658195534Sscottl } 659195534Sscottl if (timeout == 0) { 660195534Sscottl device_printf(dev, "AHCI controller reset failure\n"); 661195534Sscottl return ENXIO; 662195534Sscottl } 663195534Sscottl /* Reenable AHCI mode */ 664195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 665205422Smav return (0); 666205422Smav} 667205422Smav 668205422Smavstatic int 669205422Smavahci_ctlr_setup(device_t dev) 670205422Smav{ 671205422Smav struct ahci_controller *ctlr = device_get_softc(dev); 672195534Sscottl /* Clear interrupts */ 673195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 674196656Smav /* Configure CCC */ 675196656Smav if (ctlr->ccc) { 676196656Smav ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 677196656Smav ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 678196656Smav (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 679196656Smav (4 << AHCI_CCCC_CC_SHIFT) | 680196656Smav AHCI_CCCC_EN); 681196656Smav ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 682196656Smav AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 683196656Smav if (bootverbose) { 684196656Smav device_printf(dev, 685196656Smav "CCC with %dms/4cmd enabled on vector %d\n", 686196656Smav ctlr->ccc, ctlr->cccv); 687196656Smav } 688196656Smav } 689195534Sscottl /* Enable AHCI interrupts */ 690195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, 691195534Sscottl ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 692195534Sscottl return (0); 693195534Sscottl} 694195534Sscottl 695195534Sscottlstatic int 696195534Sscottlahci_suspend(device_t dev) 697195534Sscottl{ 698195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 699195534Sscottl 700195534Sscottl bus_generic_suspend(dev); 701195534Sscottl /* Disable interupts, so the state change(s) doesn't trigger */ 702195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, 703195534Sscottl ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 704195534Sscottl return 0; 705195534Sscottl} 706195534Sscottl 707195534Sscottlstatic int 708195534Sscottlahci_resume(device_t dev) 709195534Sscottl{ 710195534Sscottl int res; 711195534Sscottl 712195534Sscottl if ((res = ahci_ctlr_reset(dev)) != 0) 713195534Sscottl return (res); 714205422Smav ahci_ctlr_setup(dev); 715195534Sscottl return (bus_generic_resume(dev)); 716195534Sscottl} 717195534Sscottl 718195534Sscottlstatic int 719195534Sscottlahci_setup_interrupt(device_t dev) 720195534Sscottl{ 721195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 722256843Smav int i; 723195534Sscottl 724256843Smav ctlr->msi = 2; 725195534Sscottl /* Process hints. */ 726245875Smav if (ctlr->quirks & AHCI_Q_NOMSI) 727256843Smav ctlr->msi = 0; 728195534Sscottl resource_int_value(device_get_name(dev), 729256843Smav device_get_unit(dev), "msi", &ctlr->msi); 730256843Smav ctlr->numirqs = 1; 731256843Smav if (ctlr->msi < 0) 732256843Smav ctlr->msi = 0; 733256843Smav else if (ctlr->msi == 1) 734256843Smav ctlr->msi = min(1, pci_msi_count(dev)); 735256843Smav else if (ctlr->msi > 1) { 736256843Smav ctlr->msi = 2; 737256843Smav ctlr->numirqs = pci_msi_count(dev); 738256843Smav } 739195534Sscottl /* Allocate MSI if needed/present. */ 740256843Smav if (ctlr->msi && pci_alloc_msi(dev, &ctlr->numirqs) != 0) { 741256843Smav ctlr->msi = 0; 742195534Sscottl ctlr->numirqs = 1; 743195534Sscottl } 744195534Sscottl /* Check for single MSI vector fallback. */ 745195534Sscottl if (ctlr->numirqs > 1 && 746195534Sscottl (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 747195534Sscottl device_printf(dev, "Falling back to one MSI\n"); 748195534Sscottl ctlr->numirqs = 1; 749195534Sscottl } 750195534Sscottl /* Allocate all IRQs. */ 751195534Sscottl for (i = 0; i < ctlr->numirqs; i++) { 752195534Sscottl ctlr->irqs[i].ctlr = ctlr; 753256843Smav ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 754196656Smav if (ctlr->numirqs == 1 || i >= ctlr->channels || 755196656Smav (ctlr->ccc && i == ctlr->cccv)) 756195534Sscottl ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 757195534Sscottl else if (i == ctlr->numirqs - 1) 758195534Sscottl ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 759195534Sscottl else 760195534Sscottl ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 761195534Sscottl if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 762195534Sscottl &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 763195534Sscottl device_printf(dev, "unable to map interrupt\n"); 764195534Sscottl return ENXIO; 765195534Sscottl } 766195534Sscottl if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 767256843Smav (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 768256843Smav ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 769256843Smav ahci_intr_one), 770195534Sscottl &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 771195534Sscottl /* SOS XXX release r_irq */ 772195534Sscottl device_printf(dev, "unable to setup interrupt\n"); 773195534Sscottl return ENXIO; 774195534Sscottl } 775202011Smav if (ctlr->numirqs > 1) { 776202011Smav bus_describe_intr(dev, ctlr->irqs[i].r_irq, 777202011Smav ctlr->irqs[i].handle, 778202011Smav ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 779202011Smav "ch%d" : "%d", i); 780202011Smav } 781195534Sscottl } 782195534Sscottl return (0); 783195534Sscottl} 784195534Sscottl 785195534Sscottl/* 786195534Sscottl * Common case interrupt handler. 787195534Sscottl */ 788195534Sscottlstatic void 789195534Sscottlahci_intr(void *data) 790195534Sscottl{ 791195534Sscottl struct ahci_controller_irq *irq = data; 792195534Sscottl struct ahci_controller *ctlr = irq->ctlr; 793205422Smav u_int32_t is, ise = 0; 794195534Sscottl void *arg; 795195534Sscottl int unit; 796195534Sscottl 797196656Smav if (irq->mode == AHCI_IRQ_MODE_ALL) { 798195534Sscottl unit = 0; 799196656Smav if (ctlr->ccc) 800196656Smav is = ctlr->ichannels; 801196656Smav else 802196656Smav is = ATA_INL(ctlr->r_mem, AHCI_IS); 803196656Smav } else { /* AHCI_IRQ_MODE_AFTER */ 804195534Sscottl unit = irq->r_irq_rid - 1; 805196656Smav is = ATA_INL(ctlr->r_mem, AHCI_IS); 806196656Smav } 807205422Smav /* CCC interrupt is edge triggered. */ 808205422Smav if (ctlr->ccc) 809205422Smav ise = 1 << ctlr->cccv; 810200814Smav /* Some controllers have edge triggered IS. */ 811200814Smav if (ctlr->quirks & AHCI_Q_EDGEIS) 812205422Smav ise |= is; 813205422Smav if (ise != 0) 814205422Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 815195534Sscottl for (; unit < ctlr->channels; unit++) { 816195534Sscottl if ((is & (1 << unit)) != 0 && 817195534Sscottl (arg = ctlr->interrupt[unit].argument)) { 818199322Smav ctlr->interrupt[unit].function(arg); 819195534Sscottl } 820195534Sscottl } 821200814Smav /* AHCI declares level triggered IS. */ 822200814Smav if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 823200814Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 824195534Sscottl} 825195534Sscottl 826195534Sscottl/* 827195534Sscottl * Simplified interrupt handler for multivector MSI mode. 828195534Sscottl */ 829195534Sscottlstatic void 830195534Sscottlahci_intr_one(void *data) 831195534Sscottl{ 832195534Sscottl struct ahci_controller_irq *irq = data; 833195534Sscottl struct ahci_controller *ctlr = irq->ctlr; 834195534Sscottl void *arg; 835195534Sscottl int unit; 836195534Sscottl 837195534Sscottl unit = irq->r_irq_rid - 1; 838195534Sscottl if ((arg = ctlr->interrupt[unit].argument)) 839195534Sscottl ctlr->interrupt[unit].function(arg); 840202011Smav /* AHCI declares level triggered IS. */ 841256843Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 842195534Sscottl} 843195534Sscottl 844256843Smavstatic void 845256843Smavahci_intr_one_edge(void *data) 846256843Smav{ 847256843Smav struct ahci_controller_irq *irq = data; 848256843Smav struct ahci_controller *ctlr = irq->ctlr; 849256843Smav void *arg; 850256843Smav int unit; 851256843Smav 852256843Smav unit = irq->r_irq_rid - 1; 853256843Smav /* Some controllers have edge triggered IS. */ 854256843Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 855256843Smav if ((arg = ctlr->interrupt[unit].argument)) 856256843Smav ctlr->interrupt[unit].function(arg); 857256843Smav} 858256843Smav 859195534Sscottlstatic struct resource * 860195534Sscottlahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 861195534Sscottl u_long start, u_long end, u_long count, u_int flags) 862195534Sscottl{ 863195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 864238805Smav struct resource *res; 865195534Sscottl long st; 866238805Smav int offset, size, unit; 867195534Sscottl 868238805Smav unit = (intptr_t)device_get_ivars(child); 869238805Smav res = NULL; 870195534Sscottl switch (type) { 871195534Sscottl case SYS_RES_MEMORY: 872238805Smav if (unit >= 0) { 873238805Smav offset = AHCI_OFFSET + (unit << 7); 874238805Smav size = 128; 875238805Smav } else if (*rid == 0) { 876238805Smav offset = AHCI_EM_CTL; 877238805Smav size = 4; 878238805Smav } else { 879238805Smav offset = (ctlr->emloc & 0xffff0000) >> 14; 880238805Smav size = (ctlr->emloc & 0x0000ffff) << 2; 881238805Smav if (*rid != 1) { 882238805Smav if (*rid == 2 && (ctlr->capsem & 883238805Smav (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 884238805Smav offset += size; 885238805Smav else 886238805Smav break; 887238805Smav } 888238805Smav } 889195534Sscottl st = rman_get_start(ctlr->r_mem); 890195534Sscottl res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 891238805Smav st + offset + size - 1, size, RF_ACTIVE, child); 892195534Sscottl if (res) { 893195534Sscottl bus_space_handle_t bsh; 894195534Sscottl bus_space_tag_t bst; 895195534Sscottl bsh = rman_get_bushandle(ctlr->r_mem); 896195534Sscottl bst = rman_get_bustag(ctlr->r_mem); 897195534Sscottl bus_space_subregion(bst, bsh, offset, 128, &bsh); 898195534Sscottl rman_set_bushandle(res, bsh); 899195534Sscottl rman_set_bustag(res, bst); 900195534Sscottl } 901195534Sscottl break; 902195534Sscottl case SYS_RES_IRQ: 903195534Sscottl if (*rid == ATA_IRQ_RID) 904195534Sscottl res = ctlr->irqs[0].r_irq; 905195534Sscottl break; 906195534Sscottl } 907195534Sscottl return (res); 908195534Sscottl} 909195534Sscottl 910195534Sscottlstatic int 911195534Sscottlahci_release_resource(device_t dev, device_t child, int type, int rid, 912195534Sscottl struct resource *r) 913195534Sscottl{ 914195534Sscottl 915195534Sscottl switch (type) { 916195534Sscottl case SYS_RES_MEMORY: 917195534Sscottl rman_release_resource(r); 918195534Sscottl return (0); 919195534Sscottl case SYS_RES_IRQ: 920195534Sscottl if (rid != ATA_IRQ_RID) 921195534Sscottl return ENOENT; 922195534Sscottl return (0); 923195534Sscottl } 924195534Sscottl return (EINVAL); 925195534Sscottl} 926195534Sscottl 927195534Sscottlstatic int 928195534Sscottlahci_setup_intr(device_t dev, device_t child, struct resource *irq, 929195534Sscottl int flags, driver_filter_t *filter, driver_intr_t *function, 930195534Sscottl void *argument, void **cookiep) 931195534Sscottl{ 932195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 933195534Sscottl int unit = (intptr_t)device_get_ivars(child); 934195534Sscottl 935195534Sscottl if (filter != NULL) { 936195534Sscottl printf("ahci.c: we cannot use a filter here\n"); 937195534Sscottl return (EINVAL); 938195534Sscottl } 939195534Sscottl ctlr->interrupt[unit].function = function; 940195534Sscottl ctlr->interrupt[unit].argument = argument; 941195534Sscottl return (0); 942195534Sscottl} 943195534Sscottl 944195534Sscottlstatic int 945195534Sscottlahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 946195534Sscottl void *cookie) 947195534Sscottl{ 948195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 949195534Sscottl int unit = (intptr_t)device_get_ivars(child); 950195534Sscottl 951195534Sscottl ctlr->interrupt[unit].function = NULL; 952195534Sscottl ctlr->interrupt[unit].argument = NULL; 953195534Sscottl return (0); 954195534Sscottl} 955195534Sscottl 956195534Sscottlstatic int 957195534Sscottlahci_print_child(device_t dev, device_t child) 958195534Sscottl{ 959238805Smav int retval, channel; 960195534Sscottl 961195534Sscottl retval = bus_print_child_header(dev, child); 962238805Smav channel = (int)(intptr_t)device_get_ivars(child); 963238805Smav if (channel >= 0) 964238805Smav retval += printf(" at channel %d", channel); 965195534Sscottl retval += bus_print_child_footer(dev, child); 966195534Sscottl return (retval); 967195534Sscottl} 968195534Sscottl 969208410Smavstatic int 970208410Smavahci_child_location_str(device_t dev, device_t child, char *buf, 971208410Smav size_t buflen) 972208410Smav{ 973238805Smav int channel; 974208410Smav 975238805Smav channel = (int)(intptr_t)device_get_ivars(child); 976238805Smav if (channel >= 0) 977238805Smav snprintf(buf, buflen, "channel=%d", channel); 978208410Smav return (0); 979208410Smav} 980208410Smav 981249346Smavstatic bus_dma_tag_t 982249346Smavahci_get_dma_tag(device_t dev, device_t child) 983249346Smav{ 984249346Smav struct ahci_controller *ctlr = device_get_softc(dev); 985249346Smav 986249346Smav return (ctlr->dma_tag); 987249346Smav} 988249346Smav 989195534Sscottldevclass_t ahci_devclass; 990195534Sscottlstatic device_method_t ahci_methods[] = { 991195534Sscottl DEVMETHOD(device_probe, ahci_probe), 992195534Sscottl DEVMETHOD(device_attach, ahci_attach), 993195534Sscottl DEVMETHOD(device_detach, ahci_detach), 994195534Sscottl DEVMETHOD(device_suspend, ahci_suspend), 995195534Sscottl DEVMETHOD(device_resume, ahci_resume), 996195534Sscottl DEVMETHOD(bus_print_child, ahci_print_child), 997195534Sscottl DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 998195534Sscottl DEVMETHOD(bus_release_resource, ahci_release_resource), 999195534Sscottl DEVMETHOD(bus_setup_intr, ahci_setup_intr), 1000195534Sscottl DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 1001208410Smav DEVMETHOD(bus_child_location_str, ahci_child_location_str), 1002249346Smav DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 1003195534Sscottl { 0, 0 } 1004195534Sscottl}; 1005195534Sscottlstatic driver_t ahci_driver = { 1006195534Sscottl "ahci", 1007195534Sscottl ahci_methods, 1008195534Sscottl sizeof(struct ahci_controller) 1009195534Sscottl}; 1010195534SscottlDRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 1011199322Smavstatic device_method_t ahci_ata_methods[] = { 1012199322Smav DEVMETHOD(device_probe, ahci_ata_probe), 1013199322Smav DEVMETHOD(device_attach, ahci_attach), 1014199322Smav DEVMETHOD(device_detach, ahci_detach), 1015199322Smav DEVMETHOD(device_suspend, ahci_suspend), 1016199322Smav DEVMETHOD(device_resume, ahci_resume), 1017199322Smav DEVMETHOD(bus_print_child, ahci_print_child), 1018199322Smav DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 1019199322Smav DEVMETHOD(bus_release_resource, ahci_release_resource), 1020199322Smav DEVMETHOD(bus_setup_intr, ahci_setup_intr), 1021199322Smav DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 1022208410Smav DEVMETHOD(bus_child_location_str, ahci_child_location_str), 1023199322Smav { 0, 0 } 1024199322Smav}; 1025199322Smavstatic driver_t ahci_ata_driver = { 1026199322Smav "ahci", 1027199322Smav ahci_ata_methods, 1028199322Smav sizeof(struct ahci_controller) 1029199322Smav}; 1030199322SmavDRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 1031195534SscottlMODULE_VERSION(ahci, 1); 1032195534SscottlMODULE_DEPEND(ahci, cam, 1, 1, 1); 1033195534Sscottl 1034195534Sscottlstatic int 1035195534Sscottlahci_ch_probe(device_t dev) 1036195534Sscottl{ 1037195534Sscottl 1038195534Sscottl device_set_desc_copy(dev, "AHCI channel"); 1039195534Sscottl return (0); 1040195534Sscottl} 1041195534Sscottl 1042195534Sscottlstatic int 1043195534Sscottlahci_ch_attach(device_t dev) 1044195534Sscottl{ 1045195534Sscottl struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1046195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1047195534Sscottl struct cam_devq *devq; 1048199821Smav int rid, error, i, sata_rev = 0; 1049203123Smav u_int32_t version; 1050195534Sscottl 1051195534Sscottl ch->dev = dev; 1052195534Sscottl ch->unit = (intptr_t)device_get_ivars(dev); 1053196656Smav ch->caps = ctlr->caps; 1054196656Smav ch->caps2 = ctlr->caps2; 1055199322Smav ch->quirks = ctlr->quirks; 1056215725Smav ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 1057196656Smav mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 1058195534Sscottl resource_int_value(device_get_name(dev), 1059195534Sscottl device_get_unit(dev), "pm_level", &ch->pm_level); 1060256843Smav STAILQ_INIT(&ch->doneq); 1061196656Smav if (ch->pm_level > 3) 1062196656Smav callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 1063220576Smav callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 1064195534Sscottl /* Limit speed for my onboard JMicron external port. 1065195534Sscottl * It is not eSATA really. */ 1066195534Sscottl if (pci_get_devid(ctlr->dev) == 0x2363197b && 1067195534Sscottl pci_get_subvendor(ctlr->dev) == 0x1043 && 1068195534Sscottl pci_get_subdevice(ctlr->dev) == 0x81e4 && 1069195534Sscottl ch->unit == 0) 1070199821Smav sata_rev = 1; 1071203030Smav if (ch->quirks & AHCI_Q_SATA2) 1072203030Smav sata_rev = 2; 1073195534Sscottl resource_int_value(device_get_name(dev), 1074199821Smav device_get_unit(dev), "sata_rev", &sata_rev); 1075199821Smav for (i = 0; i < 16; i++) { 1076199821Smav ch->user[i].revision = sata_rev; 1077199821Smav ch->user[i].mode = 0; 1078199821Smav ch->user[i].bytecount = 8192; 1079199821Smav ch->user[i].tags = ch->numslots; 1080207499Smav ch->user[i].caps = 0; 1081199821Smav ch->curr[i] = ch->user[i]; 1082207499Smav if (ch->pm_level) { 1083207499Smav ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 1084207499Smav CTS_SATA_CAPS_H_APST | 1085207499Smav CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 1086207499Smav } 1087220602Smav ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 1088220602Smav CTS_SATA_CAPS_H_AN; 1089199821Smav } 1090238805Smav rid = 0; 1091195534Sscottl if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1092195534Sscottl &rid, RF_ACTIVE))) 1093195534Sscottl return (ENXIO); 1094195534Sscottl ahci_dmainit(dev); 1095195534Sscottl ahci_slotsalloc(dev); 1096208375Smav ahci_ch_init(dev); 1097195534Sscottl mtx_lock(&ch->mtx); 1098195534Sscottl rid = ATA_IRQ_RID; 1099195534Sscottl if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1100195534Sscottl &rid, RF_SHAREABLE | RF_ACTIVE))) { 1101195534Sscottl device_printf(dev, "Unable to map interrupt\n"); 1102208813Smav error = ENXIO; 1103208813Smav goto err0; 1104195534Sscottl } 1105195534Sscottl if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 1106256843Smav ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 1107256843Smav dev, &ch->ih))) { 1108195534Sscottl device_printf(dev, "Unable to setup interrupt\n"); 1109195534Sscottl error = ENXIO; 1110195534Sscottl goto err1; 1111195534Sscottl } 1112203123Smav ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 1113203123Smav version = ATA_INL(ctlr->r_mem, AHCI_VS); 1114240383Smav if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 1115203123Smav ch->chcaps |= AHCI_P_CMD_FBSCP; 1116203123Smav if (bootverbose) { 1117203123Smav device_printf(dev, "Caps:%s%s%s%s%s\n", 1118203123Smav (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 1119203123Smav (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 1120203123Smav (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 1121203123Smav (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 1122203123Smav (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 1123203123Smav } 1124195534Sscottl /* Create the device queue for our SIM. */ 1125195534Sscottl devq = cam_simq_alloc(ch->numslots); 1126195534Sscottl if (devq == NULL) { 1127195534Sscottl device_printf(dev, "Unable to allocate simq\n"); 1128195534Sscottl error = ENOMEM; 1129195534Sscottl goto err1; 1130195534Sscottl } 1131195534Sscottl /* Construct SIM entry */ 1132195534Sscottl ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1133199178Smav device_get_unit(dev), &ch->mtx, 1134199278Smav min(2, ch->numslots), 1135199278Smav (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1136199278Smav devq); 1137195534Sscottl if (ch->sim == NULL) { 1138208813Smav cam_simq_free(devq); 1139195534Sscottl device_printf(dev, "unable to allocate sim\n"); 1140195534Sscottl error = ENOMEM; 1141208813Smav goto err1; 1142195534Sscottl } 1143195534Sscottl if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1144195534Sscottl device_printf(dev, "unable to register xpt bus\n"); 1145195534Sscottl error = ENXIO; 1146195534Sscottl goto err2; 1147195534Sscottl } 1148195534Sscottl if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1149195534Sscottl CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1150195534Sscottl device_printf(dev, "unable to create path\n"); 1151195534Sscottl error = ENXIO; 1152195534Sscottl goto err3; 1153195534Sscottl } 1154196656Smav if (ch->pm_level > 3) { 1155196656Smav callout_reset(&ch->pm_timer, 1156196656Smav (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1157196656Smav ahci_ch_pm, dev); 1158196656Smav } 1159195534Sscottl mtx_unlock(&ch->mtx); 1160195534Sscottl return (0); 1161195534Sscottl 1162195534Sscottlerr3: 1163195534Sscottl xpt_bus_deregister(cam_sim_path(ch->sim)); 1164195534Sscottlerr2: 1165195534Sscottl cam_sim_free(ch->sim, /*free_devq*/TRUE); 1166195534Sscottlerr1: 1167195534Sscottl bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1168208813Smaverr0: 1169195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1170195534Sscottl mtx_unlock(&ch->mtx); 1171214325Smav mtx_destroy(&ch->mtx); 1172195534Sscottl return (error); 1173195534Sscottl} 1174195534Sscottl 1175195534Sscottlstatic int 1176195534Sscottlahci_ch_detach(device_t dev) 1177195534Sscottl{ 1178195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1179195534Sscottl 1180195534Sscottl mtx_lock(&ch->mtx); 1181195534Sscottl xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1182220576Smav /* Forget about reset. */ 1183220576Smav if (ch->resetting) { 1184220576Smav ch->resetting = 0; 1185220576Smav xpt_release_simq(ch->sim, TRUE); 1186220576Smav } 1187195534Sscottl xpt_free_path(ch->path); 1188195534Sscottl xpt_bus_deregister(cam_sim_path(ch->sim)); 1189195534Sscottl cam_sim_free(ch->sim, /*free_devq*/TRUE); 1190195534Sscottl mtx_unlock(&ch->mtx); 1191195534Sscottl 1192196656Smav if (ch->pm_level > 3) 1193196656Smav callout_drain(&ch->pm_timer); 1194220576Smav callout_drain(&ch->reset_timer); 1195195534Sscottl bus_teardown_intr(dev, ch->r_irq, ch->ih); 1196195534Sscottl bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1197195534Sscottl 1198208375Smav ahci_ch_deinit(dev); 1199195534Sscottl ahci_slotsfree(dev); 1200195534Sscottl ahci_dmafini(dev); 1201195534Sscottl 1202195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1203195534Sscottl mtx_destroy(&ch->mtx); 1204195534Sscottl return (0); 1205195534Sscottl} 1206195534Sscottl 1207195534Sscottlstatic int 1208208375Smavahci_ch_init(device_t dev) 1209195534Sscottl{ 1210195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1211208375Smav uint64_t work; 1212195534Sscottl 1213208375Smav /* Disable port interrupts */ 1214208375Smav ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1215208375Smav /* Setup work areas */ 1216208375Smav work = ch->dma.work_bus + AHCI_CL_OFFSET; 1217208375Smav ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1218208375Smav ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1219208375Smav work = ch->dma.rfis_bus; 1220208375Smav ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1221208375Smav ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1222208375Smav /* Activate the channel and power/spin up device */ 1223208375Smav ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1224208375Smav (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1225208375Smav ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1226208375Smav ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1227208375Smav ahci_start_fr(dev); 1228208375Smav ahci_start(dev, 1); 1229208375Smav return (0); 1230208375Smav} 1231208375Smav 1232208375Smavstatic int 1233208375Smavahci_ch_deinit(device_t dev) 1234208375Smav{ 1235208375Smav struct ahci_channel *ch = device_get_softc(dev); 1236208375Smav 1237195534Sscottl /* Disable port interrupts. */ 1238195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1239195534Sscottl /* Reset command register. */ 1240195534Sscottl ahci_stop(dev); 1241195534Sscottl ahci_stop_fr(dev); 1242195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1243195534Sscottl /* Allow everything, including partial and slumber modes. */ 1244195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1245195534Sscottl /* Request slumber mode transition and give some time to get there. */ 1246195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1247195534Sscottl DELAY(100); 1248195534Sscottl /* Disable PHY. */ 1249195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1250195534Sscottl return (0); 1251195534Sscottl} 1252195534Sscottl 1253195534Sscottlstatic int 1254208375Smavahci_ch_suspend(device_t dev) 1255208375Smav{ 1256208375Smav struct ahci_channel *ch = device_get_softc(dev); 1257208375Smav 1258208375Smav mtx_lock(&ch->mtx); 1259208375Smav xpt_freeze_simq(ch->sim, 1); 1260220576Smav /* Forget about reset. */ 1261220576Smav if (ch->resetting) { 1262220576Smav ch->resetting = 0; 1263220576Smav callout_stop(&ch->reset_timer); 1264220576Smav xpt_release_simq(ch->sim, TRUE); 1265220576Smav } 1266208375Smav while (ch->oslots) 1267208375Smav msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1268208375Smav ahci_ch_deinit(dev); 1269208375Smav mtx_unlock(&ch->mtx); 1270208375Smav return (0); 1271208375Smav} 1272208375Smav 1273208375Smavstatic int 1274195534Sscottlahci_ch_resume(device_t dev) 1275195534Sscottl{ 1276195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1277195534Sscottl 1278208375Smav mtx_lock(&ch->mtx); 1279208375Smav ahci_ch_init(dev); 1280208375Smav ahci_reset(dev); 1281208375Smav xpt_release_simq(ch->sim, TRUE); 1282208375Smav mtx_unlock(&ch->mtx); 1283195534Sscottl return (0); 1284195534Sscottl} 1285195534Sscottl 1286195534Sscottldevclass_t ahcich_devclass; 1287195534Sscottlstatic device_method_t ahcich_methods[] = { 1288195534Sscottl DEVMETHOD(device_probe, ahci_ch_probe), 1289195534Sscottl DEVMETHOD(device_attach, ahci_ch_attach), 1290195534Sscottl DEVMETHOD(device_detach, ahci_ch_detach), 1291195534Sscottl DEVMETHOD(device_suspend, ahci_ch_suspend), 1292195534Sscottl DEVMETHOD(device_resume, ahci_ch_resume), 1293195534Sscottl { 0, 0 } 1294195534Sscottl}; 1295195534Sscottlstatic driver_t ahcich_driver = { 1296195534Sscottl "ahcich", 1297195534Sscottl ahcich_methods, 1298195534Sscottl sizeof(struct ahci_channel) 1299195534Sscottl}; 1300199322SmavDRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1301195534Sscottl 1302195534Sscottlstruct ahci_dc_cb_args { 1303195534Sscottl bus_addr_t maddr; 1304195534Sscottl int error; 1305195534Sscottl}; 1306195534Sscottl 1307195534Sscottlstatic void 1308195534Sscottlahci_dmainit(device_t dev) 1309195534Sscottl{ 1310195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1311195534Sscottl struct ahci_dc_cb_args dcba; 1312203123Smav size_t rfsize; 1313195534Sscottl 1314195534Sscottl /* Command area. */ 1315195534Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1316249346Smav BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1317195534Sscottl NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1318195534Sscottl 0, NULL, NULL, &ch->dma.work_tag)) 1319195534Sscottl goto error; 1320248687Smav if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1321248687Smav BUS_DMA_ZERO, &ch->dma.work_map)) 1322195534Sscottl goto error; 1323195534Sscottl if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1324195534Sscottl AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1325195534Sscottl bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1326195534Sscottl goto error; 1327195534Sscottl } 1328195534Sscottl ch->dma.work_bus = dcba.maddr; 1329195534Sscottl /* FIS receive area. */ 1330203123Smav if (ch->chcaps & AHCI_P_CMD_FBSCP) 1331203123Smav rfsize = 4096; 1332203123Smav else 1333203123Smav rfsize = 256; 1334203123Smav if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1335249346Smav BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1336203123Smav NULL, NULL, rfsize, 1, rfsize, 1337195534Sscottl 0, NULL, NULL, &ch->dma.rfis_tag)) 1338195534Sscottl goto error; 1339195534Sscottl if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1340195534Sscottl &ch->dma.rfis_map)) 1341195534Sscottl goto error; 1342195534Sscottl if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1343203123Smav rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1344195534Sscottl bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1345195534Sscottl goto error; 1346195534Sscottl } 1347195534Sscottl ch->dma.rfis_bus = dcba.maddr; 1348195534Sscottl /* Data area. */ 1349195534Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1350249346Smav BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1351195534Sscottl NULL, NULL, 1352195534Sscottl AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1353195534Sscottl AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1354195534Sscottl 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1355195534Sscottl goto error; 1356195534Sscottl } 1357195534Sscottl return; 1358195534Sscottl 1359195534Sscottlerror: 1360195534Sscottl device_printf(dev, "WARNING - DMA initialization failed\n"); 1361195534Sscottl ahci_dmafini(dev); 1362195534Sscottl} 1363195534Sscottl 1364195534Sscottlstatic void 1365195534Sscottlahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1366195534Sscottl{ 1367195534Sscottl struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1368195534Sscottl 1369195534Sscottl if (!(dcba->error = error)) 1370195534Sscottl dcba->maddr = segs[0].ds_addr; 1371195534Sscottl} 1372195534Sscottl 1373195534Sscottlstatic void 1374195534Sscottlahci_dmafini(device_t dev) 1375195534Sscottl{ 1376195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1377195534Sscottl 1378195534Sscottl if (ch->dma.data_tag) { 1379195534Sscottl bus_dma_tag_destroy(ch->dma.data_tag); 1380195534Sscottl ch->dma.data_tag = NULL; 1381195534Sscottl } 1382195534Sscottl if (ch->dma.rfis_bus) { 1383195534Sscottl bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1384195534Sscottl bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1385195534Sscottl ch->dma.rfis_bus = 0; 1386195534Sscottl ch->dma.rfis_map = NULL; 1387195534Sscottl ch->dma.rfis = NULL; 1388195534Sscottl } 1389195534Sscottl if (ch->dma.work_bus) { 1390195534Sscottl bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1391195534Sscottl bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1392195534Sscottl ch->dma.work_bus = 0; 1393195534Sscottl ch->dma.work_map = NULL; 1394195534Sscottl ch->dma.work = NULL; 1395195534Sscottl } 1396195534Sscottl if (ch->dma.work_tag) { 1397195534Sscottl bus_dma_tag_destroy(ch->dma.work_tag); 1398195534Sscottl ch->dma.work_tag = NULL; 1399195534Sscottl } 1400195534Sscottl} 1401195534Sscottl 1402195534Sscottlstatic void 1403195534Sscottlahci_slotsalloc(device_t dev) 1404195534Sscottl{ 1405195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1406195534Sscottl int i; 1407195534Sscottl 1408195534Sscottl /* Alloc and setup command/dma slots */ 1409195534Sscottl bzero(ch->slot, sizeof(ch->slot)); 1410195534Sscottl for (i = 0; i < ch->numslots; i++) { 1411195534Sscottl struct ahci_slot *slot = &ch->slot[i]; 1412195534Sscottl 1413195534Sscottl slot->dev = dev; 1414195534Sscottl slot->slot = i; 1415195534Sscottl slot->state = AHCI_SLOT_EMPTY; 1416195534Sscottl slot->ccb = NULL; 1417195534Sscottl callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1418195534Sscottl 1419195534Sscottl if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1420195534Sscottl device_printf(ch->dev, "FAILURE - create data_map\n"); 1421195534Sscottl } 1422195534Sscottl} 1423195534Sscottl 1424195534Sscottlstatic void 1425195534Sscottlahci_slotsfree(device_t dev) 1426195534Sscottl{ 1427195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1428195534Sscottl int i; 1429195534Sscottl 1430195534Sscottl /* Free all dma slots */ 1431195534Sscottl for (i = 0; i < ch->numslots; i++) { 1432195534Sscottl struct ahci_slot *slot = &ch->slot[i]; 1433195534Sscottl 1434196656Smav callout_drain(&slot->timeout); 1435195534Sscottl if (slot->dma.data_map) { 1436195534Sscottl bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1437195534Sscottl slot->dma.data_map = NULL; 1438195534Sscottl } 1439195534Sscottl } 1440195534Sscottl} 1441195534Sscottl 1442220657Smavstatic int 1443198319Smavahci_phy_check_events(device_t dev, u_int32_t serr) 1444195534Sscottl{ 1445195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1446195534Sscottl 1447220657Smav if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1448220657Smav ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1449195534Sscottl u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1450203108Smav union ccb *ccb; 1451203108Smav 1452203165Smav if (bootverbose) { 1453220657Smav if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1454195534Sscottl device_printf(dev, "CONNECT requested\n"); 1455220657Smav else 1456195534Sscottl device_printf(dev, "DISCONNECT requested\n"); 1457195534Sscottl } 1458203165Smav ahci_reset(dev); 1459203108Smav if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1460220657Smav return (0); 1461203108Smav if (xpt_create_path(&ccb->ccb_h.path, NULL, 1462203108Smav cam_sim_path(ch->sim), 1463203108Smav CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1464203108Smav xpt_free_ccb(ccb); 1465220657Smav return (0); 1466203108Smav } 1467203108Smav xpt_rescan(ccb); 1468220657Smav return (1); 1469195534Sscottl } 1470220657Smav return (0); 1471195534Sscottl} 1472195534Sscottl 1473195534Sscottlstatic void 1474220657Smavahci_cpd_check_events(device_t dev) 1475220657Smav{ 1476220657Smav struct ahci_channel *ch = device_get_softc(dev); 1477220657Smav u_int32_t status; 1478220657Smav union ccb *ccb; 1479220657Smav 1480220657Smav if (ch->pm_level == 0) 1481220657Smav return; 1482220657Smav 1483220657Smav status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1484220657Smav if ((status & AHCI_P_CMD_CPD) == 0) 1485220657Smav return; 1486220657Smav 1487220657Smav if (bootverbose) { 1488220657Smav if (status & AHCI_P_CMD_CPS) { 1489220657Smav device_printf(dev, "COLD CONNECT requested\n"); 1490220657Smav } else 1491220657Smav device_printf(dev, "COLD DISCONNECT requested\n"); 1492220657Smav } 1493220657Smav ahci_reset(dev); 1494220657Smav if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1495220657Smav return; 1496220657Smav if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1497220657Smav CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1498220657Smav xpt_free_ccb(ccb); 1499220657Smav return; 1500220657Smav } 1501220657Smav xpt_rescan(ccb); 1502220657Smav} 1503220657Smav 1504220657Smavstatic void 1505196907Smavahci_notify_events(device_t dev, u_int32_t status) 1506196656Smav{ 1507196656Smav struct ahci_channel *ch = device_get_softc(dev); 1508196656Smav struct cam_path *dpath; 1509196656Smav int i; 1510196656Smav 1511200196Smav if (ch->caps & AHCI_CAP_SSNTF) 1512200196Smav ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1513196656Smav if (bootverbose) 1514196656Smav device_printf(dev, "SNTF 0x%04x\n", status); 1515196656Smav for (i = 0; i < 16; i++) { 1516196656Smav if ((status & (1 << i)) == 0) 1517196656Smav continue; 1518196656Smav if (xpt_create_path(&dpath, NULL, 1519196656Smav xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1520196656Smav xpt_async(AC_SCSI_AEN, dpath, NULL); 1521196656Smav xpt_free_path(dpath); 1522196656Smav } 1523196656Smav } 1524196656Smav} 1525196656Smav 1526196656Smavstatic void 1527256843Smavahci_done(struct ahci_channel *ch, union ccb *ccb) 1528195534Sscottl{ 1529256843Smav 1530256843Smav mtx_assert(&ch->mtx, MA_OWNED); 1531256843Smav if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1532256843Smav ch->batch == 0) { 1533256843Smav xpt_done(ccb); 1534256843Smav return; 1535256843Smav } 1536256843Smav 1537256843Smav STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1538256843Smav} 1539256843Smav 1540256843Smavstatic void 1541256843Smavahci_ch_intr(void *arg) 1542256843Smav{ 1543256843Smav device_t dev = (device_t)arg; 1544195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1545256843Smav uint32_t istatus; 1546195534Sscottl 1547256843Smav /* Read interrupt statuses. */ 1548256843Smav istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1549256843Smav if (istatus == 0) 1550256843Smav return; 1551256843Smav 1552195534Sscottl mtx_lock(&ch->mtx); 1553256843Smav ahci_ch_intr_main(ch, istatus); 1554195534Sscottl mtx_unlock(&ch->mtx); 1555195534Sscottl} 1556195534Sscottl 1557195534Sscottlstatic void 1558256843Smavahci_ch_intr_direct(void *arg) 1559256843Smav{ 1560256843Smav device_t dev = (device_t)arg; 1561256843Smav struct ahci_channel *ch = device_get_softc(dev); 1562256843Smav struct ccb_hdr *ccb_h; 1563256843Smav uint32_t istatus; 1564256843Smav 1565256843Smav /* Read interrupt statuses. */ 1566256843Smav istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1567256843Smav if (istatus == 0) 1568256843Smav return; 1569256843Smav 1570256843Smav mtx_lock(&ch->mtx); 1571256843Smav ch->batch = 1; 1572256843Smav ahci_ch_intr_main(ch, istatus); 1573256843Smav ch->batch = 0; 1574256843Smav mtx_unlock(&ch->mtx); 1575256843Smav while ((ccb_h = STAILQ_FIRST(&ch->doneq)) != NULL) { 1576256843Smav STAILQ_REMOVE_HEAD(&ch->doneq, sim_links.stqe); 1577256843Smav xpt_done_direct((union ccb *)ccb_h); 1578256843Smav } 1579256843Smav} 1580256843Smav 1581256843Smavstatic void 1582196656Smavahci_ch_pm(void *arg) 1583196656Smav{ 1584196656Smav device_t dev = (device_t)arg; 1585196656Smav struct ahci_channel *ch = device_get_softc(dev); 1586196656Smav uint32_t work; 1587196656Smav 1588196656Smav if (ch->numrslots != 0) 1589196656Smav return; 1590196656Smav work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1591196656Smav if (ch->pm_level == 4) 1592196656Smav work |= AHCI_P_CMD_PARTIAL; 1593196656Smav else 1594196656Smav work |= AHCI_P_CMD_SLUMBER; 1595196656Smav ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1596196656Smav} 1597196656Smav 1598196656Smavstatic void 1599256843Smavahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1600195534Sscottl{ 1601256843Smav device_t dev = ch->dev; 1602256843Smav uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1603195534Sscottl enum ahci_err_type et; 1604220657Smav int i, ccs, port, reset = 0; 1605195534Sscottl 1606256843Smav /* Clear interrupt statuses. */ 1607195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1608195534Sscottl /* Read command statuses. */ 1609248698Smav if (ch->numtslots != 0) 1610248698Smav cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1611248698Smav else 1612248698Smav cstatus = 0; 1613248698Smav if (ch->numrslots != ch->numtslots) 1614248698Smav cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1615248698Smav /* Read SNTF in one of possible ways. */ 1616248704Smav if ((istatus & AHCI_P_IX_SDB) && 1617248704Smav (ch->pm_present || ch->curr[0].atapi != 0)) { 1618200196Smav if (ch->caps & AHCI_CAP_SSNTF) 1619200196Smav sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1620203123Smav else if (ch->fbs_enabled) { 1621200196Smav u_int8_t *fis = ch->dma.rfis + 0x58; 1622200196Smav 1623203123Smav for (i = 0; i < 16; i++) { 1624203123Smav if (fis[1] & 0x80) { 1625203123Smav fis[1] &= 0x7f; 1626203123Smav sntf |= 1 << i; 1627203123Smav } 1628203123Smav fis += 256; 1629203123Smav } 1630203123Smav } else { 1631203123Smav u_int8_t *fis = ch->dma.rfis + 0x58; 1632203123Smav 1633200196Smav if (fis[1] & 0x80) 1634200196Smav sntf = (1 << (fis[1] & 0x0f)); 1635200196Smav } 1636200196Smav } 1637195534Sscottl /* Process PHY events */ 1638198319Smav if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1639198319Smav AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1640198319Smav serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1641198319Smav if (serr) { 1642198319Smav ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1643220657Smav reset = ahci_phy_check_events(dev, serr); 1644198319Smav } 1645198319Smav } 1646220657Smav /* Process cold presence detection events */ 1647220657Smav if ((istatus & AHCI_P_IX_CPD) && !reset) 1648220657Smav ahci_cpd_check_events(dev); 1649195534Sscottl /* Process command errors */ 1650198319Smav if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1651198319Smav AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1652195534Sscottl ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1653195534Sscottl >> AHCI_P_CMD_CCS_SHIFT; 1654203123Smav//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1655203123Smav// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1656203123Smav// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1657203123Smav port = -1; 1658203123Smav if (ch->fbs_enabled) { 1659203123Smav uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1660203123Smav if (fbs & AHCI_P_FBS_SDE) { 1661203123Smav port = (fbs & AHCI_P_FBS_DWE) 1662203123Smav >> AHCI_P_FBS_DWE_SHIFT; 1663203123Smav } else { 1664203123Smav for (i = 0; i < 16; i++) { 1665203123Smav if (ch->numrslotspd[i] == 0) 1666203123Smav continue; 1667203123Smav if (port == -1) 1668203123Smav port = i; 1669203123Smav else if (port != i) { 1670203123Smav port = -2; 1671203123Smav break; 1672203123Smav } 1673203123Smav } 1674203123Smav } 1675203123Smav } 1676248698Smav err = ch->rslots & cstatus; 1677195534Sscottl } else { 1678195534Sscottl ccs = 0; 1679195534Sscottl err = 0; 1680203123Smav port = -1; 1681195534Sscottl } 1682195534Sscottl /* Complete all successfull commands. */ 1683248698Smav ok = ch->rslots & ~cstatus; 1684195534Sscottl for (i = 0; i < ch->numslots; i++) { 1685195534Sscottl if ((ok >> i) & 1) 1686195534Sscottl ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1687195534Sscottl } 1688195534Sscottl /* On error, complete the rest of commands with error statuses. */ 1689195534Sscottl if (err) { 1690195534Sscottl if (ch->frozen) { 1691195534Sscottl union ccb *fccb = ch->frozen; 1692195534Sscottl ch->frozen = NULL; 1693195534Sscottl fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1694198319Smav if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1695198319Smav xpt_freeze_devq(fccb->ccb_h.path, 1); 1696198319Smav fccb->ccb_h.status |= CAM_DEV_QFRZN; 1697198319Smav } 1698256843Smav ahci_done(ch, fccb); 1699195534Sscottl } 1700195534Sscottl for (i = 0; i < ch->numslots; i++) { 1701195534Sscottl /* XXX: reqests in loading state. */ 1702195534Sscottl if (((err >> i) & 1) == 0) 1703195534Sscottl continue; 1704203123Smav if (port >= 0 && 1705203123Smav ch->slot[i].ccb->ccb_h.target_id != port) 1706203123Smav continue; 1707198390Smav if (istatus & AHCI_P_IX_TFE) { 1708203123Smav if (port != -2) { 1709195534Sscottl /* Task File Error */ 1710203123Smav if (ch->numtslotspd[ 1711203123Smav ch->slot[i].ccb->ccb_h.target_id] == 0) { 1712195534Sscottl /* Untagged operation. */ 1713195534Sscottl if (i == ccs) 1714195534Sscottl et = AHCI_ERR_TFE; 1715195534Sscottl else 1716195534Sscottl et = AHCI_ERR_INNOCENT; 1717195534Sscottl } else { 1718195534Sscottl /* Tagged operation. */ 1719195534Sscottl et = AHCI_ERR_NCQ; 1720195534Sscottl } 1721203123Smav } else { 1722203123Smav et = AHCI_ERR_TFE; 1723203123Smav ch->fatalerr = 1; 1724203123Smav } 1725198390Smav } else if (istatus & AHCI_P_IX_IF) { 1726203123Smav if (ch->numtslots == 0 && i != ccs && port != -2) 1727198390Smav et = AHCI_ERR_INNOCENT; 1728198390Smav else 1729198390Smav et = AHCI_ERR_SATA; 1730195534Sscottl } else 1731195534Sscottl et = AHCI_ERR_INVALID; 1732195534Sscottl ahci_end_transaction(&ch->slot[i], et); 1733195534Sscottl } 1734203123Smav /* 1735203123Smav * We can't reinit port if there are some other 1736203123Smav * commands active, use resume to complete them. 1737203123Smav */ 1738220565Smav if (ch->rslots != 0 && !ch->recoverycmd) 1739203123Smav ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1740195534Sscottl } 1741196656Smav /* Process NOTIFY events */ 1742196907Smav if (sntf) 1743196907Smav ahci_notify_events(dev, sntf); 1744195534Sscottl} 1745195534Sscottl 1746195534Sscottl/* Must be called with channel locked. */ 1747195534Sscottlstatic int 1748195534Sscottlahci_check_collision(device_t dev, union ccb *ccb) 1749195534Sscottl{ 1750195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1751203123Smav int t = ccb->ccb_h.target_id; 1752195534Sscottl 1753195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1754195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1755199747Smav /* Tagged command while we have no supported tag free. */ 1756199747Smav if (((~ch->oslots) & (0xffffffff >> (32 - 1757203123Smav ch->curr[t].tags))) == 0) 1758199747Smav return (1); 1759203123Smav /* If we have FBS */ 1760203123Smav if (ch->fbs_enabled) { 1761203123Smav /* Tagged command while untagged are active. */ 1762203123Smav if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1763203123Smav return (1); 1764203123Smav } else { 1765203123Smav /* Tagged command while untagged are active. */ 1766203123Smav if (ch->numrslots != 0 && ch->numtslots == 0) 1767203123Smav return (1); 1768203123Smav /* Tagged command while tagged to other target is active. */ 1769203123Smav if (ch->numtslots != 0 && 1770203123Smav ch->taggedtarget != ccb->ccb_h.target_id) 1771203123Smav return (1); 1772203123Smav } 1773195534Sscottl } else { 1774203123Smav /* If we have FBS */ 1775203123Smav if (ch->fbs_enabled) { 1776203123Smav /* Untagged command while tagged are active. */ 1777203123Smav if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1778203123Smav return (1); 1779203123Smav } else { 1780203123Smav /* Untagged command while tagged are active. */ 1781203123Smav if (ch->numrslots != 0 && ch->numtslots != 0) 1782203123Smav return (1); 1783203123Smav } 1784195534Sscottl } 1785195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1786195534Sscottl (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1787195534Sscottl /* Atomic command while anything active. */ 1788195534Sscottl if (ch->numrslots != 0) 1789195534Sscottl return (1); 1790195534Sscottl } 1791195534Sscottl /* We have some atomic command running. */ 1792195534Sscottl if (ch->aslots != 0) 1793195534Sscottl return (1); 1794195534Sscottl return (0); 1795195534Sscottl} 1796195534Sscottl 1797195534Sscottl/* Must be called with channel locked. */ 1798195534Sscottlstatic void 1799195534Sscottlahci_begin_transaction(device_t dev, union ccb *ccb) 1800195534Sscottl{ 1801195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1802195534Sscottl struct ahci_slot *slot; 1803199747Smav int tag, tags; 1804195534Sscottl 1805195534Sscottl /* Choose empty slot. */ 1806199747Smav tags = ch->numslots; 1807199747Smav if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1808199747Smav (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1809199747Smav tags = ch->curr[ccb->ccb_h.target_id].tags; 1810195534Sscottl tag = ch->lastslot; 1811199747Smav while (1) { 1812199747Smav if (tag >= tags) 1813195534Sscottl tag = 0; 1814199747Smav if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1815199747Smav break; 1816199747Smav tag++; 1817199747Smav }; 1818195534Sscottl ch->lastslot = tag; 1819195534Sscottl /* Occupy chosen slot. */ 1820195534Sscottl slot = &ch->slot[tag]; 1821195534Sscottl slot->ccb = ccb; 1822196656Smav /* Stop PM timer. */ 1823196656Smav if (ch->numrslots == 0 && ch->pm_level > 3) 1824196656Smav callout_stop(&ch->pm_timer); 1825195534Sscottl /* Update channel stats. */ 1826199747Smav ch->oslots |= (1 << slot->slot); 1827195534Sscottl ch->numrslots++; 1828203123Smav ch->numrslotspd[ccb->ccb_h.target_id]++; 1829195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1830195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1831195534Sscottl ch->numtslots++; 1832203123Smav ch->numtslotspd[ccb->ccb_h.target_id]++; 1833195534Sscottl ch->taggedtarget = ccb->ccb_h.target_id; 1834195534Sscottl } 1835195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1836195534Sscottl (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1837195534Sscottl ch->aslots |= (1 << slot->slot); 1838195534Sscottl slot->dma.nsegs = 0; 1839195534Sscottl if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1840195534Sscottl slot->state = AHCI_SLOT_LOADING; 1841246713Skib bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1842246713Skib ahci_dmasetprd, slot, 0); 1843195534Sscottl } else 1844195534Sscottl ahci_execute_transaction(slot); 1845195534Sscottl} 1846195534Sscottl 1847195534Sscottl/* Locked by busdma engine. */ 1848195534Sscottlstatic void 1849195534Sscottlahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1850195534Sscottl{ 1851195534Sscottl struct ahci_slot *slot = arg; 1852195534Sscottl struct ahci_channel *ch = device_get_softc(slot->dev); 1853195534Sscottl struct ahci_cmd_tab *ctp; 1854195534Sscottl struct ahci_dma_prd *prd; 1855195534Sscottl int i; 1856195534Sscottl 1857195534Sscottl if (error) { 1858195534Sscottl device_printf(slot->dev, "DMA load error\n"); 1859195534Sscottl ahci_end_transaction(slot, AHCI_ERR_INVALID); 1860195534Sscottl return; 1861195534Sscottl } 1862195534Sscottl KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1863195534Sscottl /* Get a piece of the workspace for this request */ 1864195534Sscottl ctp = (struct ahci_cmd_tab *) 1865195534Sscottl (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1866195534Sscottl /* Fill S/G table */ 1867195534Sscottl prd = &ctp->prd_tab[0]; 1868195534Sscottl for (i = 0; i < nsegs; i++) { 1869195534Sscottl prd[i].dba = htole64(segs[i].ds_addr); 1870195534Sscottl prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1871195534Sscottl } 1872195534Sscottl slot->dma.nsegs = nsegs; 1873195534Sscottl bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1874195534Sscottl ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1875195534Sscottl BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1876195534Sscottl ahci_execute_transaction(slot); 1877195534Sscottl} 1878195534Sscottl 1879195534Sscottl/* Must be called with channel locked. */ 1880195534Sscottlstatic void 1881195534Sscottlahci_execute_transaction(struct ahci_slot *slot) 1882195534Sscottl{ 1883195534Sscottl device_t dev = slot->dev; 1884195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1885195534Sscottl struct ahci_cmd_tab *ctp; 1886195534Sscottl struct ahci_cmd_list *clp; 1887195534Sscottl union ccb *ccb = slot->ccb; 1888195534Sscottl int port = ccb->ccb_h.target_id & 0x0f; 1889222304Smav int fis_size, i, softreset; 1890203123Smav uint8_t *fis = ch->dma.rfis + 0x40; 1891203123Smav uint8_t val; 1892195534Sscottl 1893195534Sscottl /* Get a piece of the workspace for this request */ 1894195534Sscottl ctp = (struct ahci_cmd_tab *) 1895195534Sscottl (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1896195534Sscottl /* Setup the FIS for this request */ 1897199821Smav if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1898195534Sscottl device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1899195534Sscottl ahci_end_transaction(slot, AHCI_ERR_INVALID); 1900195534Sscottl return; 1901195534Sscottl } 1902195534Sscottl /* Setup the command list entry */ 1903195534Sscottl clp = (struct ahci_cmd_list *) 1904195534Sscottl (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1905214988Smav clp->cmd_flags = htole16( 1906214988Smav (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1907214988Smav (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1908214988Smav (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1909214988Smav (fis_size / sizeof(u_int32_t)) | 1910214988Smav (port << 12)); 1911214988Smav clp->prd_length = htole16(slot->dma.nsegs); 1912195534Sscottl /* Special handling for Soft Reset command. */ 1913195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1914203123Smav (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1915203123Smav if (ccb->ataio.cmd.control & ATA_A_RESET) { 1916222304Smav softreset = 1; 1917203123Smav /* Kick controller into sane state */ 1918203123Smav ahci_stop(dev); 1919203123Smav ahci_clo(dev); 1920203123Smav ahci_start(dev, 0); 1921203123Smav clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1922203123Smav } else { 1923222304Smav softreset = 2; 1924203123Smav /* Prepare FIS receive area for check. */ 1925203123Smav for (i = 0; i < 20; i++) 1926203123Smav fis[i] = 0xff; 1927203123Smav } 1928222304Smav } else 1929222304Smav softreset = 0; 1930195534Sscottl clp->bytecount = 0; 1931195534Sscottl clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1932195534Sscottl (AHCI_CT_SIZE * slot->slot)); 1933195534Sscottl bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1934214988Smav BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1935195534Sscottl bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1936195534Sscottl BUS_DMASYNC_PREREAD); 1937195534Sscottl /* Set ACTIVE bit for NCQ commands. */ 1938195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1939195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1940195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1941195534Sscottl } 1942203123Smav /* If FBS is enabled, set PMP port. */ 1943203123Smav if (ch->fbs_enabled) { 1944203123Smav ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1945203123Smav (port << AHCI_P_FBS_DEV_SHIFT)); 1946203123Smav } 1947195534Sscottl /* Issue command to the controller. */ 1948195534Sscottl slot->state = AHCI_SLOT_RUNNING; 1949195534Sscottl ch->rslots |= (1 << slot->slot); 1950195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1951195534Sscottl /* Device reset commands doesn't interrupt. Poll them. */ 1952195534Sscottl if (ccb->ccb_h.func_code == XPT_ATA_IO && 1953222304Smav (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1954220777Smav int count, timeout = ccb->ccb_h.timeout * 100; 1955195534Sscottl enum ahci_err_type et = AHCI_ERR_NONE; 1956195534Sscottl 1957195534Sscottl for (count = 0; count < timeout; count++) { 1958220777Smav DELAY(10); 1959195534Sscottl if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1960195534Sscottl break; 1961222304Smav if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1962222304Smav softreset != 1) { 1963222285Smav#if 0 1964195534Sscottl device_printf(ch->dev, 1965195534Sscottl "Poll error on slot %d, TFD: %04x\n", 1966195534Sscottl slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1967222285Smav#endif 1968195534Sscottl et = AHCI_ERR_TFE; 1969195534Sscottl break; 1970195534Sscottl } 1971198851Smav /* Workaround for ATI SB600/SB700 chipsets. */ 1972198851Smav if (ccb->ccb_h.target_id == 15 && 1973198851Smav pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1974198851Smav (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1975198851Smav et = AHCI_ERR_TIMEOUT; 1976198851Smav break; 1977198851Smav } 1978195534Sscottl } 1979222304Smav 1980222304Smav /* Marvell controllers do not wait for readyness. */ 1981222304Smav if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1982222304Smav et == AHCI_ERR_NONE) { 1983222304Smav while ((val = fis[2]) & ATA_S_BUSY) { 1984222304Smav DELAY(10); 1985222304Smav if (count++ >= timeout) 1986222304Smav break; 1987222304Smav } 1988222304Smav } 1989222304Smav 1990195534Sscottl if (timeout && (count >= timeout)) { 1991222304Smav device_printf(dev, "Poll timeout on slot %d port %d\n", 1992222304Smav slot->slot, port); 1993203108Smav device_printf(dev, "is %08x cs %08x ss %08x " 1994224498Smav "rs %08x tfd %02x serr %08x cmd %08x\n", 1995203108Smav ATA_INL(ch->r_mem, AHCI_P_IS), 1996203108Smav ATA_INL(ch->r_mem, AHCI_P_CI), 1997203108Smav ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1998203108Smav ATA_INL(ch->r_mem, AHCI_P_TFD), 1999224498Smav ATA_INL(ch->r_mem, AHCI_P_SERR), 2000224498Smav ATA_INL(ch->r_mem, AHCI_P_CMD)); 2001195534Sscottl et = AHCI_ERR_TIMEOUT; 2002195534Sscottl } 2003222304Smav 2004203123Smav /* Kick controller into sane state and enable FBS. */ 2005222304Smav if (softreset == 2) 2006222285Smav ch->eslots |= (1 << slot->slot); 2007222285Smav ahci_end_transaction(slot, et); 2008195534Sscottl return; 2009195534Sscottl } 2010195534Sscottl /* Start command execution timeout */ 2011198319Smav callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 2012195534Sscottl (timeout_t*)ahci_timeout, slot); 2013195534Sscottl return; 2014195534Sscottl} 2015195534Sscottl 2016203873Smav/* Must be called with channel locked. */ 2017203873Smavstatic void 2018203873Smavahci_process_timeout(device_t dev) 2019203873Smav{ 2020203873Smav struct ahci_channel *ch = device_get_softc(dev); 2021203873Smav int i; 2022203873Smav 2023203873Smav mtx_assert(&ch->mtx, MA_OWNED); 2024203873Smav /* Handle the rest of commands. */ 2025203873Smav for (i = 0; i < ch->numslots; i++) { 2026203873Smav /* Do we have a running request on slot? */ 2027203873Smav if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2028203873Smav continue; 2029203873Smav ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 2030203873Smav } 2031203873Smav} 2032203873Smav 2033203873Smav/* Must be called with channel locked. */ 2034203873Smavstatic void 2035203873Smavahci_rearm_timeout(device_t dev) 2036203873Smav{ 2037203873Smav struct ahci_channel *ch = device_get_softc(dev); 2038203873Smav int i; 2039203873Smav 2040203873Smav mtx_assert(&ch->mtx, MA_OWNED); 2041203873Smav for (i = 0; i < ch->numslots; i++) { 2042203873Smav struct ahci_slot *slot = &ch->slot[i]; 2043203873Smav 2044203873Smav /* Do we have a running request on slot? */ 2045203873Smav if (slot->state < AHCI_SLOT_RUNNING) 2046203873Smav continue; 2047203873Smav if ((ch->toslots & (1 << i)) == 0) 2048203873Smav continue; 2049203873Smav callout_reset(&slot->timeout, 2050203873Smav (int)slot->ccb->ccb_h.timeout * hz / 2000, 2051203873Smav (timeout_t*)ahci_timeout, slot); 2052203873Smav } 2053203873Smav} 2054203873Smav 2055195534Sscottl/* Locked by callout mechanism. */ 2056195534Sscottlstatic void 2057195534Sscottlahci_timeout(struct ahci_slot *slot) 2058195534Sscottl{ 2059195534Sscottl device_t dev = slot->dev; 2060195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2061198319Smav uint32_t sstatus; 2062198319Smav int ccs; 2063195534Sscottl int i; 2064195534Sscottl 2065196656Smav /* Check for stale timeout. */ 2066198319Smav if (slot->state < AHCI_SLOT_RUNNING) 2067196656Smav return; 2068196656Smav 2069198319Smav /* Check if slot was not being executed last time we checked. */ 2070198319Smav if (slot->state < AHCI_SLOT_EXECUTING) { 2071198319Smav /* Check if slot started executing. */ 2072198319Smav sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 2073198319Smav ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 2074198319Smav >> AHCI_P_CMD_CCS_SHIFT; 2075203123Smav if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 2076224498Smav ch->fbs_enabled || ch->wrongccs) 2077198319Smav slot->state = AHCI_SLOT_EXECUTING; 2078224498Smav else if ((ch->rslots & (1 << ccs)) == 0) { 2079224498Smav ch->wrongccs = 1; 2080224498Smav slot->state = AHCI_SLOT_EXECUTING; 2081224498Smav } 2082198319Smav 2083198319Smav callout_reset(&slot->timeout, 2084198319Smav (int)slot->ccb->ccb_h.timeout * hz / 2000, 2085198319Smav (timeout_t*)ahci_timeout, slot); 2086198319Smav return; 2087198319Smav } 2088198319Smav 2089222304Smav device_printf(dev, "Timeout on slot %d port %d\n", 2090222304Smav slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 2091224498Smav device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 2092224498Smav "serr %08x cmd %08x\n", 2093198319Smav ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 2094198319Smav ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 2095224498Smav ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 2096224498Smav ATA_INL(ch->r_mem, AHCI_P_CMD)); 2097195534Sscottl 2098197838Smav /* Handle frozen command. */ 2099195534Sscottl if (ch->frozen) { 2100195534Sscottl union ccb *fccb = ch->frozen; 2101195534Sscottl ch->frozen = NULL; 2102195534Sscottl fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2103198319Smav if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2104198319Smav xpt_freeze_devq(fccb->ccb_h.path, 1); 2105198319Smav fccb->ccb_h.status |= CAM_DEV_QFRZN; 2106198319Smav } 2107256843Smav ahci_done(ch, fccb); 2108195534Sscottl } 2109224498Smav if (!ch->fbs_enabled && !ch->wrongccs) { 2110203873Smav /* Without FBS we know real timeout source. */ 2111203873Smav ch->fatalerr = 1; 2112203873Smav /* Handle command with timeout. */ 2113203873Smav ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 2114203873Smav /* Handle the rest of commands. */ 2115203873Smav for (i = 0; i < ch->numslots; i++) { 2116203873Smav /* Do we have a running request on slot? */ 2117203873Smav if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2118203873Smav continue; 2119203873Smav ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2120203873Smav } 2121203873Smav } else { 2122203873Smav /* With FBS we wait for other commands timeout and pray. */ 2123203873Smav if (ch->toslots == 0) 2124203873Smav xpt_freeze_simq(ch->sim, 1); 2125203873Smav ch->toslots |= (1 << slot->slot); 2126203873Smav if ((ch->rslots & ~ch->toslots) == 0) 2127203873Smav ahci_process_timeout(dev); 2128203873Smav else 2129203873Smav device_printf(dev, " ... waiting for slots %08x\n", 2130203873Smav ch->rslots & ~ch->toslots); 2131195534Sscottl } 2132195534Sscottl} 2133195534Sscottl 2134195534Sscottl/* Must be called with channel locked. */ 2135195534Sscottlstatic void 2136195534Sscottlahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 2137195534Sscottl{ 2138195534Sscottl device_t dev = slot->dev; 2139195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2140195534Sscottl union ccb *ccb = slot->ccb; 2141214988Smav struct ahci_cmd_list *clp; 2142212732Smav int lastto; 2143222304Smav uint32_t sig; 2144195534Sscottl 2145195534Sscottl bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 2146214988Smav BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2147214988Smav clp = (struct ahci_cmd_list *) 2148214988Smav (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 2149195534Sscottl /* Read result registers to the result struct 2150195534Sscottl * May be incorrect if several commands finished same time, 2151195534Sscottl * so read only when sure or have to. 2152195534Sscottl */ 2153195534Sscottl if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2154195534Sscottl struct ata_res *res = &ccb->ataio.res; 2155195534Sscottl 2156195534Sscottl if ((et == AHCI_ERR_TFE) || 2157195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 2158195534Sscottl u_int8_t *fis = ch->dma.rfis + 0x40; 2159195534Sscottl 2160195534Sscottl bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2161195534Sscottl BUS_DMASYNC_POSTREAD); 2162203123Smav if (ch->fbs_enabled) { 2163203123Smav fis += ccb->ccb_h.target_id * 256; 2164203123Smav res->status = fis[2]; 2165203123Smav res->error = fis[3]; 2166203123Smav } else { 2167203123Smav uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2168203123Smav 2169203123Smav res->status = tfd; 2170203123Smav res->error = tfd >> 8; 2171203123Smav } 2172195534Sscottl res->lba_low = fis[4]; 2173195534Sscottl res->lba_mid = fis[5]; 2174195534Sscottl res->lba_high = fis[6]; 2175195534Sscottl res->device = fis[7]; 2176195534Sscottl res->lba_low_exp = fis[8]; 2177195534Sscottl res->lba_mid_exp = fis[9]; 2178195534Sscottl res->lba_high_exp = fis[10]; 2179195534Sscottl res->sector_count = fis[12]; 2180195534Sscottl res->sector_count_exp = fis[13]; 2181222304Smav 2182222304Smav /* 2183222304Smav * Some weird controllers do not return signature in 2184222304Smav * FIS receive area. Read it from PxSIG register. 2185222304Smav */ 2186222304Smav if ((ch->quirks & AHCI_Q_ALTSIG) && 2187222304Smav (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2188222304Smav (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2189222304Smav sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2190222304Smav res->lba_high = sig >> 24; 2191222304Smav res->lba_mid = sig >> 16; 2192222304Smav res->lba_low = sig >> 8; 2193222304Smav res->sector_count = sig; 2194222304Smav } 2195195534Sscottl } else 2196195534Sscottl bzero(res, sizeof(*res)); 2197214988Smav if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2198218596Smav (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2199218596Smav (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2200214988Smav ccb->ataio.resid = 2201214988Smav ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2202214988Smav } 2203214988Smav } else { 2204218596Smav if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2205218596Smav (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2206214988Smav ccb->csio.resid = 2207214988Smav ccb->csio.dxfer_len - le32toh(clp->bytecount); 2208214988Smav } 2209195534Sscottl } 2210195534Sscottl if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2211195534Sscottl bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2212195534Sscottl (ccb->ccb_h.flags & CAM_DIR_IN) ? 2213195534Sscottl BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2214195534Sscottl bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2215195534Sscottl } 2216203123Smav if (et != AHCI_ERR_NONE) 2217203123Smav ch->eslots |= (1 << slot->slot); 2218198319Smav /* In case of error, freeze device for proper recovery. */ 2219220565Smav if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2220198319Smav !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2221198319Smav xpt_freeze_devq(ccb->ccb_h.path, 1); 2222198319Smav ccb->ccb_h.status |= CAM_DEV_QFRZN; 2223198319Smav } 2224195534Sscottl /* Set proper result status. */ 2225195534Sscottl ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2226195534Sscottl switch (et) { 2227195534Sscottl case AHCI_ERR_NONE: 2228195534Sscottl ccb->ccb_h.status |= CAM_REQ_CMP; 2229195534Sscottl if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2230195534Sscottl ccb->csio.scsi_status = SCSI_STATUS_OK; 2231195534Sscottl break; 2232195534Sscottl case AHCI_ERR_INVALID: 2233198851Smav ch->fatalerr = 1; 2234195534Sscottl ccb->ccb_h.status |= CAM_REQ_INVALID; 2235195534Sscottl break; 2236195534Sscottl case AHCI_ERR_INNOCENT: 2237195534Sscottl ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2238195534Sscottl break; 2239195534Sscottl case AHCI_ERR_TFE: 2240198319Smav case AHCI_ERR_NCQ: 2241195534Sscottl if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2242195534Sscottl ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2243195534Sscottl ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2244195534Sscottl } else { 2245195534Sscottl ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2246195534Sscottl } 2247195534Sscottl break; 2248195534Sscottl case AHCI_ERR_SATA: 2249198851Smav ch->fatalerr = 1; 2250220565Smav if (!ch->recoverycmd) { 2251198319Smav xpt_freeze_simq(ch->sim, 1); 2252198319Smav ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2253198319Smav ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2254198319Smav } 2255198319Smav ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2256195534Sscottl break; 2257195534Sscottl case AHCI_ERR_TIMEOUT: 2258220565Smav if (!ch->recoverycmd) { 2259198319Smav xpt_freeze_simq(ch->sim, 1); 2260198319Smav ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2261198319Smav ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2262198319Smav } 2263195534Sscottl ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2264195534Sscottl break; 2265195534Sscottl default: 2266198851Smav ch->fatalerr = 1; 2267195534Sscottl ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2268195534Sscottl } 2269195534Sscottl /* Free slot. */ 2270199747Smav ch->oslots &= ~(1 << slot->slot); 2271195534Sscottl ch->rslots &= ~(1 << slot->slot); 2272195534Sscottl ch->aslots &= ~(1 << slot->slot); 2273195534Sscottl slot->state = AHCI_SLOT_EMPTY; 2274195534Sscottl slot->ccb = NULL; 2275195534Sscottl /* Update channel stats. */ 2276195534Sscottl ch->numrslots--; 2277203123Smav ch->numrslotspd[ccb->ccb_h.target_id]--; 2278195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2279195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2280195534Sscottl ch->numtslots--; 2281203123Smav ch->numtslotspd[ccb->ccb_h.target_id]--; 2282195534Sscottl } 2283212732Smav /* Cancel timeout state if request completed normally. */ 2284212732Smav if (et != AHCI_ERR_TIMEOUT) { 2285212732Smav lastto = (ch->toslots == (1 << slot->slot)); 2286212732Smav ch->toslots &= ~(1 << slot->slot); 2287212732Smav if (lastto) 2288212732Smav xpt_release_simq(ch->sim, TRUE); 2289212732Smav } 2290195534Sscottl /* If it was first request of reset sequence and there is no error, 2291195534Sscottl * proceed to second request. */ 2292195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2293195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2294195534Sscottl (ccb->ataio.cmd.control & ATA_A_RESET) && 2295195534Sscottl et == AHCI_ERR_NONE) { 2296195534Sscottl ccb->ataio.cmd.control &= ~ATA_A_RESET; 2297195534Sscottl ahci_begin_transaction(dev, ccb); 2298195534Sscottl return; 2299195534Sscottl } 2300198851Smav /* If it was our READ LOG command - process it. */ 2301220565Smav if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2302198851Smav ahci_process_read_log(dev, ccb); 2303220565Smav /* If it was our REQUEST SENSE command - process it. */ 2304220565Smav } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2305220565Smav ahci_process_request_sense(dev, ccb); 2306220565Smav /* If it was NCQ or ATAPI command error, put result on hold. */ 2307220565Smav } else if (et == AHCI_ERR_NCQ || 2308220565Smav ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2309220565Smav (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2310195534Sscottl ch->hold[slot->slot] = ccb; 2311203123Smav ch->numhslots++; 2312198851Smav } else 2313256843Smav ahci_done(ch, ccb); 2314198851Smav /* If we have no other active commands, ... */ 2315198851Smav if (ch->rslots == 0) { 2316198851Smav /* if there was fatal error - reset port. */ 2317203873Smav if (ch->toslots != 0 || ch->fatalerr) { 2318198851Smav ahci_reset(dev); 2319203123Smav } else { 2320203123Smav /* if we have slots in error, we can reinit port. */ 2321203123Smav if (ch->eslots != 0) { 2322203123Smav ahci_stop(dev); 2323222285Smav ahci_clo(dev); 2324203123Smav ahci_start(dev, 1); 2325203123Smav } 2326203123Smav /* if there commands on hold, we can do READ LOG. */ 2327220565Smav if (!ch->recoverycmd && ch->numhslots) 2328220565Smav ahci_issue_recovery(dev); 2329198851Smav } 2330203873Smav /* If all the rest of commands are in timeout - give them chance. */ 2331203873Smav } else if ((ch->rslots & ~ch->toslots) == 0 && 2332203873Smav et != AHCI_ERR_TIMEOUT) 2333203873Smav ahci_rearm_timeout(dev); 2334222285Smav /* Unfreeze frozen command. */ 2335222285Smav if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2336222285Smav union ccb *fccb = ch->frozen; 2337222285Smav ch->frozen = NULL; 2338222285Smav ahci_begin_transaction(dev, fccb); 2339222285Smav xpt_release_simq(ch->sim, TRUE); 2340222285Smav } 2341196656Smav /* Start PM timer. */ 2342207499Smav if (ch->numrslots == 0 && ch->pm_level > 3 && 2343207499Smav (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2344196656Smav callout_schedule(&ch->pm_timer, 2345196656Smav (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2346196656Smav } 2347195534Sscottl} 2348195534Sscottl 2349195534Sscottlstatic void 2350220565Smavahci_issue_recovery(device_t dev) 2351195534Sscottl{ 2352195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2353195534Sscottl union ccb *ccb; 2354195534Sscottl struct ccb_ataio *ataio; 2355220565Smav struct ccb_scsiio *csio; 2356195534Sscottl int i; 2357195534Sscottl 2358220830Smav /* Find some held command. */ 2359195534Sscottl for (i = 0; i < ch->numslots; i++) { 2360195534Sscottl if (ch->hold[i]) 2361195534Sscottl break; 2362195534Sscottl } 2363195534Sscottl ccb = xpt_alloc_ccb_nowait(); 2364195534Sscottl if (ccb == NULL) { 2365220830Smav device_printf(dev, "Unable to allocate recovery command\n"); 2366220822Smavcompleteall: 2367220830Smav /* We can't do anything -- complete held commands. */ 2368220822Smav for (i = 0; i < ch->numslots; i++) { 2369220822Smav if (ch->hold[i] == NULL) 2370220822Smav continue; 2371220822Smav ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2372220822Smav ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2373256843Smav ahci_done(ch, ch->hold[i]); 2374220822Smav ch->hold[i] = NULL; 2375220822Smav ch->numhslots--; 2376220822Smav } 2377220822Smav ahci_reset(dev); 2378220822Smav return; 2379195534Sscottl } 2380195534Sscottl ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2381220565Smav if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2382220565Smav /* READ LOG */ 2383220565Smav ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2384220565Smav ccb->ccb_h.func_code = XPT_ATA_IO; 2385220565Smav ccb->ccb_h.flags = CAM_DIR_IN; 2386220565Smav ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2387220565Smav ataio = &ccb->ataio; 2388220565Smav ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2389220565Smav if (ataio->data_ptr == NULL) { 2390220565Smav xpt_free_ccb(ccb); 2391220822Smav device_printf(dev, 2392220830Smav "Unable to allocate memory for READ LOG command\n"); 2393220822Smav goto completeall; 2394220565Smav } 2395220565Smav ataio->dxfer_len = 512; 2396220565Smav bzero(&ataio->cmd, sizeof(ataio->cmd)); 2397220565Smav ataio->cmd.flags = CAM_ATAIO_48BIT; 2398220565Smav ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2399220565Smav ataio->cmd.sector_count = 1; 2400220565Smav ataio->cmd.sector_count_exp = 0; 2401220565Smav ataio->cmd.lba_low = 0x10; 2402220565Smav ataio->cmd.lba_mid = 0; 2403220565Smav ataio->cmd.lba_mid_exp = 0; 2404220565Smav } else { 2405220565Smav /* REQUEST SENSE */ 2406220565Smav ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2407220565Smav ccb->ccb_h.recovery_slot = i; 2408220565Smav ccb->ccb_h.func_code = XPT_SCSI_IO; 2409220565Smav ccb->ccb_h.flags = CAM_DIR_IN; 2410220565Smav ccb->ccb_h.status = 0; 2411220565Smav ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2412220565Smav csio = &ccb->csio; 2413220565Smav csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2414220565Smav csio->dxfer_len = ch->hold[i]->csio.sense_len; 2415220565Smav csio->cdb_len = 6; 2416220565Smav bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2417220565Smav csio->cdb_io.cdb_bytes[0] = 0x03; 2418220565Smav csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2419195534Sscottl } 2420220565Smav /* Freeze SIM while doing recovery. */ 2421220822Smav ch->recoverycmd = 1; 2422198319Smav xpt_freeze_simq(ch->sim, 1); 2423195534Sscottl ahci_begin_transaction(dev, ccb); 2424195534Sscottl} 2425195534Sscottl 2426195534Sscottlstatic void 2427195534Sscottlahci_process_read_log(device_t dev, union ccb *ccb) 2428195534Sscottl{ 2429195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2430195534Sscottl uint8_t *data; 2431195534Sscottl struct ata_res *res; 2432195534Sscottl int i; 2433195534Sscottl 2434220565Smav ch->recoverycmd = 0; 2435195534Sscottl 2436195534Sscottl data = ccb->ataio.data_ptr; 2437195534Sscottl if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2438195534Sscottl (data[0] & 0x80) == 0) { 2439195534Sscottl for (i = 0; i < ch->numslots; i++) { 2440195534Sscottl if (!ch->hold[i]) 2441195534Sscottl continue; 2442220565Smav if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2443220565Smav continue; 2444195534Sscottl if ((data[0] & 0x1F) == i) { 2445195534Sscottl res = &ch->hold[i]->ataio.res; 2446195534Sscottl res->status = data[2]; 2447195534Sscottl res->error = data[3]; 2448195534Sscottl res->lba_low = data[4]; 2449195534Sscottl res->lba_mid = data[5]; 2450195534Sscottl res->lba_high = data[6]; 2451195534Sscottl res->device = data[7]; 2452195534Sscottl res->lba_low_exp = data[8]; 2453195534Sscottl res->lba_mid_exp = data[9]; 2454195534Sscottl res->lba_high_exp = data[10]; 2455195534Sscottl res->sector_count = data[12]; 2456195534Sscottl res->sector_count_exp = data[13]; 2457195534Sscottl } else { 2458195534Sscottl ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2459195534Sscottl ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2460195534Sscottl } 2461256843Smav ahci_done(ch, ch->hold[i]); 2462195534Sscottl ch->hold[i] = NULL; 2463203123Smav ch->numhslots--; 2464195534Sscottl } 2465195534Sscottl } else { 2466195534Sscottl if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2467195534Sscottl device_printf(dev, "Error while READ LOG EXT\n"); 2468195534Sscottl else if ((data[0] & 0x80) == 0) { 2469195534Sscottl device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2470195534Sscottl } 2471195534Sscottl for (i = 0; i < ch->numslots; i++) { 2472195534Sscottl if (!ch->hold[i]) 2473195534Sscottl continue; 2474220565Smav if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2475220565Smav continue; 2476256843Smav ahci_done(ch, ch->hold[i]); 2477195534Sscottl ch->hold[i] = NULL; 2478203123Smav ch->numhslots--; 2479195534Sscottl } 2480195534Sscottl } 2481195534Sscottl free(ccb->ataio.data_ptr, M_AHCI); 2482195534Sscottl xpt_free_ccb(ccb); 2483198319Smav xpt_release_simq(ch->sim, TRUE); 2484195534Sscottl} 2485195534Sscottl 2486195534Sscottlstatic void 2487220565Smavahci_process_request_sense(device_t dev, union ccb *ccb) 2488220565Smav{ 2489220565Smav struct ahci_channel *ch = device_get_softc(dev); 2490220565Smav int i; 2491220565Smav 2492220565Smav ch->recoverycmd = 0; 2493220565Smav 2494220565Smav i = ccb->ccb_h.recovery_slot; 2495220565Smav if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2496220565Smav ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2497220565Smav } else { 2498220565Smav ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2499220565Smav ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2500220565Smav } 2501256843Smav ahci_done(ch, ch->hold[i]); 2502220565Smav ch->hold[i] = NULL; 2503220565Smav ch->numhslots--; 2504220565Smav xpt_free_ccb(ccb); 2505220565Smav xpt_release_simq(ch->sim, TRUE); 2506220565Smav} 2507220565Smav 2508220565Smavstatic void 2509203123Smavahci_start(device_t dev, int fbs) 2510195534Sscottl{ 2511195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2512195534Sscottl u_int32_t cmd; 2513195534Sscottl 2514195534Sscottl /* Clear SATA error register */ 2515195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2516195534Sscottl /* Clear any interrupts pending on this channel */ 2517195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2518203123Smav /* Configure FIS-based switching if supported. */ 2519203123Smav if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2520203123Smav ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2521203123Smav ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2522203123Smav ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2523203123Smav } 2524195534Sscottl /* Start operations on this channel */ 2525195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2526207430Smav cmd &= ~AHCI_P_CMD_PMA; 2527195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2528195534Sscottl (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2529195534Sscottl} 2530195534Sscottl 2531195534Sscottlstatic void 2532195534Sscottlahci_stop(device_t dev) 2533195534Sscottl{ 2534195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2535195534Sscottl u_int32_t cmd; 2536195534Sscottl int timeout; 2537195534Sscottl 2538195534Sscottl /* Kill all activity on this channel */ 2539195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2540195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2541195534Sscottl /* Wait for activity stop. */ 2542195534Sscottl timeout = 0; 2543195534Sscottl do { 2544220777Smav DELAY(10); 2545220777Smav if (timeout++ > 50000) { 2546195534Sscottl device_printf(dev, "stopping AHCI engine failed\n"); 2547195534Sscottl break; 2548195534Sscottl } 2549195534Sscottl } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2550203123Smav ch->eslots = 0; 2551195534Sscottl} 2552195534Sscottl 2553195534Sscottlstatic void 2554195534Sscottlahci_clo(device_t dev) 2555195534Sscottl{ 2556195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2557195534Sscottl u_int32_t cmd; 2558195534Sscottl int timeout; 2559195534Sscottl 2560195534Sscottl /* Issue Command List Override if supported */ 2561195534Sscottl if (ch->caps & AHCI_CAP_SCLO) { 2562195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2563195534Sscottl cmd |= AHCI_P_CMD_CLO; 2564195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2565195534Sscottl timeout = 0; 2566195534Sscottl do { 2567220777Smav DELAY(10); 2568220777Smav if (timeout++ > 50000) { 2569195534Sscottl device_printf(dev, "executing CLO failed\n"); 2570195534Sscottl break; 2571195534Sscottl } 2572195534Sscottl } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2573195534Sscottl } 2574195534Sscottl} 2575195534Sscottl 2576195534Sscottlstatic void 2577195534Sscottlahci_stop_fr(device_t dev) 2578195534Sscottl{ 2579195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2580195534Sscottl u_int32_t cmd; 2581195534Sscottl int timeout; 2582195534Sscottl 2583195534Sscottl /* Kill all FIS reception on this channel */ 2584195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2585195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2586195534Sscottl /* Wait for FIS reception stop. */ 2587195534Sscottl timeout = 0; 2588195534Sscottl do { 2589220777Smav DELAY(10); 2590220777Smav if (timeout++ > 50000) { 2591195534Sscottl device_printf(dev, "stopping AHCI FR engine failed\n"); 2592195534Sscottl break; 2593195534Sscottl } 2594195534Sscottl } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2595195534Sscottl} 2596195534Sscottl 2597195534Sscottlstatic void 2598195534Sscottlahci_start_fr(device_t dev) 2599195534Sscottl{ 2600195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2601195534Sscottl u_int32_t cmd; 2602195534Sscottl 2603195534Sscottl /* Start FIS reception on this channel */ 2604195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2605195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2606195534Sscottl} 2607195534Sscottl 2608195534Sscottlstatic int 2609220576Smavahci_wait_ready(device_t dev, int t, int t0) 2610195534Sscottl{ 2611195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2612195534Sscottl int timeout = 0; 2613195534Sscottl uint32_t val; 2614195534Sscottl 2615195534Sscottl while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2616195534Sscottl (ATA_S_BUSY | ATA_S_DRQ)) { 2617220576Smav if (timeout > t) { 2618220576Smav if (t != 0) { 2619220576Smav device_printf(dev, 2620220576Smav "AHCI reset: device not ready after %dms " 2621220576Smav "(tfd = %08x)\n", 2622220576Smav MAX(t, 0) + t0, val); 2623220576Smav } 2624195534Sscottl return (EBUSY); 2625195534Sscottl } 2626220576Smav DELAY(1000); 2627220576Smav timeout++; 2628220576Smav } 2629195534Sscottl if (bootverbose) 2630220576Smav device_printf(dev, "AHCI reset: device ready after %dms\n", 2631220576Smav timeout + t0); 2632195534Sscottl return (0); 2633195534Sscottl} 2634195534Sscottl 2635195534Sscottlstatic void 2636220576Smavahci_reset_to(void *arg) 2637220576Smav{ 2638220576Smav device_t dev = arg; 2639220576Smav struct ahci_channel *ch = device_get_softc(dev); 2640220576Smav 2641220576Smav if (ch->resetting == 0) 2642220576Smav return; 2643220576Smav ch->resetting--; 2644220576Smav if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2645220576Smav (310 - ch->resetting) * 100) == 0) { 2646220576Smav ch->resetting = 0; 2647220777Smav ahci_start(dev, 1); 2648220576Smav xpt_release_simq(ch->sim, TRUE); 2649220576Smav return; 2650220576Smav } 2651220576Smav if (ch->resetting == 0) { 2652220576Smav ahci_clo(dev); 2653220576Smav ahci_start(dev, 1); 2654220576Smav xpt_release_simq(ch->sim, TRUE); 2655220576Smav return; 2656220576Smav } 2657220576Smav callout_schedule(&ch->reset_timer, hz / 10); 2658220576Smav} 2659220576Smav 2660220576Smavstatic void 2661195534Sscottlahci_reset(device_t dev) 2662195534Sscottl{ 2663195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2664196656Smav struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2665195534Sscottl int i; 2666195534Sscottl 2667203108Smav xpt_freeze_simq(ch->sim, 1); 2668195534Sscottl if (bootverbose) 2669195534Sscottl device_printf(dev, "AHCI reset...\n"); 2670220576Smav /* Forget about previous reset. */ 2671220576Smav if (ch->resetting) { 2672220576Smav ch->resetting = 0; 2673220576Smav callout_stop(&ch->reset_timer); 2674220576Smav xpt_release_simq(ch->sim, TRUE); 2675220576Smav } 2676195534Sscottl /* Requeue freezed command. */ 2677195534Sscottl if (ch->frozen) { 2678195534Sscottl union ccb *fccb = ch->frozen; 2679195534Sscottl ch->frozen = NULL; 2680195534Sscottl fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2681198319Smav if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2682198319Smav xpt_freeze_devq(fccb->ccb_h.path, 1); 2683198319Smav fccb->ccb_h.status |= CAM_DEV_QFRZN; 2684198319Smav } 2685256843Smav ahci_done(ch, fccb); 2686195534Sscottl } 2687195534Sscottl /* Kill the engine and requeue all running commands. */ 2688195534Sscottl ahci_stop(dev); 2689195534Sscottl for (i = 0; i < ch->numslots; i++) { 2690195534Sscottl /* Do we have a running request on slot? */ 2691195534Sscottl if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2692195534Sscottl continue; 2693195534Sscottl /* XXX; Commands in loading state. */ 2694195534Sscottl ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2695195534Sscottl } 2696198851Smav for (i = 0; i < ch->numslots; i++) { 2697198851Smav if (!ch->hold[i]) 2698198851Smav continue; 2699256843Smav ahci_done(ch, ch->hold[i]); 2700198851Smav ch->hold[i] = NULL; 2701203123Smav ch->numhslots--; 2702198851Smav } 2703203873Smav if (ch->toslots != 0) 2704203873Smav xpt_release_simq(ch->sim, TRUE); 2705203123Smav ch->eslots = 0; 2706203873Smav ch->toslots = 0; 2707224498Smav ch->wrongccs = 0; 2708198851Smav ch->fatalerr = 0; 2709198319Smav /* Tell the XPT about the event */ 2710198319Smav xpt_async(AC_BUS_RESET, ch->path, NULL); 2711195534Sscottl /* Disable port interrupts */ 2712195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2713195534Sscottl /* Reset and reconnect PHY, */ 2714203108Smav if (!ahci_sata_phy_reset(dev)) { 2715195534Sscottl if (bootverbose) 2716195534Sscottl device_printf(dev, 2717220576Smav "AHCI reset: device not found\n"); 2718195534Sscottl ch->devices = 0; 2719195534Sscottl /* Enable wanted port interrupts */ 2720195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 2721220657Smav (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2722220657Smav AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2723203108Smav xpt_release_simq(ch->sim, TRUE); 2724195534Sscottl return; 2725195534Sscottl } 2726220576Smav if (bootverbose) 2727220576Smav device_printf(dev, "AHCI reset: device found\n"); 2728195534Sscottl /* Wait for clearing busy status. */ 2729220576Smav if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2730220576Smav if (dumping) 2731220576Smav ahci_clo(dev); 2732220576Smav else 2733220576Smav ch->resetting = 310; 2734220576Smav } 2735195534Sscottl ch->devices = 1; 2736195534Sscottl /* Enable wanted port interrupts */ 2737195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 2738220657Smav (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2739220657Smav AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2740195534Sscottl AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2741220657Smav ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2742196656Smav AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2743196656Smav AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2744220576Smav if (ch->resetting) 2745220576Smav callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2746220777Smav else { 2747220777Smav ahci_start(dev, 1); 2748220576Smav xpt_release_simq(ch->sim, TRUE); 2749220777Smav } 2750195534Sscottl} 2751195534Sscottl 2752195534Sscottlstatic int 2753199821Smavahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2754195534Sscottl{ 2755199821Smav struct ahci_channel *ch = device_get_softc(dev); 2756195534Sscottl u_int8_t *fis = &ctp->cfis[0]; 2757195534Sscottl 2758248687Smav bzero(ctp->cfis, 16); 2759195534Sscottl fis[0] = 0x27; /* host to device */ 2760195534Sscottl fis[1] = (ccb->ccb_h.target_id & 0x0f); 2761195534Sscottl if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2762195534Sscottl fis[1] |= 0x80; 2763195534Sscottl fis[2] = ATA_PACKET_CMD; 2764199821Smav if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2765199821Smav ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2766195534Sscottl fis[3] = ATA_F_DMA; 2767195534Sscottl else { 2768195534Sscottl fis[5] = ccb->csio.dxfer_len; 2769195534Sscottl fis[6] = ccb->csio.dxfer_len >> 8; 2770195534Sscottl } 2771195534Sscottl fis[7] = ATA_D_LBA; 2772195534Sscottl fis[15] = ATA_A_4BIT; 2773195534Sscottl bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2774195534Sscottl ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2775195534Sscottl ctp->acmd, ccb->csio.cdb_len); 2776248687Smav bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2777195534Sscottl } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2778195534Sscottl fis[1] |= 0x80; 2779195534Sscottl fis[2] = ccb->ataio.cmd.command; 2780195534Sscottl fis[3] = ccb->ataio.cmd.features; 2781195534Sscottl fis[4] = ccb->ataio.cmd.lba_low; 2782195534Sscottl fis[5] = ccb->ataio.cmd.lba_mid; 2783195534Sscottl fis[6] = ccb->ataio.cmd.lba_high; 2784195534Sscottl fis[7] = ccb->ataio.cmd.device; 2785195534Sscottl fis[8] = ccb->ataio.cmd.lba_low_exp; 2786195534Sscottl fis[9] = ccb->ataio.cmd.lba_mid_exp; 2787195534Sscottl fis[10] = ccb->ataio.cmd.lba_high_exp; 2788195534Sscottl fis[11] = ccb->ataio.cmd.features_exp; 2789195534Sscottl if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2790195534Sscottl fis[12] = tag << 3; 2791195534Sscottl fis[13] = 0; 2792195534Sscottl } else { 2793195534Sscottl fis[12] = ccb->ataio.cmd.sector_count; 2794195534Sscottl fis[13] = ccb->ataio.cmd.sector_count_exp; 2795195534Sscottl } 2796195534Sscottl fis[15] = ATA_A_4BIT; 2797195534Sscottl } else { 2798195534Sscottl fis[15] = ccb->ataio.cmd.control; 2799195534Sscottl } 2800195534Sscottl return (20); 2801195534Sscottl} 2802195534Sscottl 2803195534Sscottlstatic int 2804195534Sscottlahci_sata_connect(struct ahci_channel *ch) 2805195534Sscottl{ 2806195534Sscottl u_int32_t status; 2807220829Smav int timeout, found = 0; 2808195534Sscottl 2809195534Sscottl /* Wait up to 100ms for "connect well" */ 2810220777Smav for (timeout = 0; timeout < 1000 ; timeout++) { 2811195534Sscottl status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2812220829Smav if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2813220829Smav found = 1; 2814195534Sscottl if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2815195534Sscottl ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2816195534Sscottl ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2817195534Sscottl break; 2818196656Smav if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2819196656Smav if (bootverbose) { 2820196656Smav device_printf(ch->dev, "SATA offline status=%08x\n", 2821196656Smav status); 2822196656Smav } 2823196656Smav return (0); 2824196656Smav } 2825220829Smav if (found == 0 && timeout >= 100) 2826220829Smav break; 2827220777Smav DELAY(100); 2828195534Sscottl } 2829220829Smav if (timeout >= 1000 || !found) { 2830195534Sscottl if (bootverbose) { 2831220829Smav device_printf(ch->dev, 2832220829Smav "SATA connect timeout time=%dus status=%08x\n", 2833220829Smav timeout * 100, status); 2834195534Sscottl } 2835195534Sscottl return (0); 2836195534Sscottl } 2837195534Sscottl if (bootverbose) { 2838220777Smav device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2839220777Smav timeout * 100, status); 2840195534Sscottl } 2841195534Sscottl /* Clear SATA error register */ 2842195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2843195534Sscottl return (1); 2844195534Sscottl} 2845195534Sscottl 2846195534Sscottlstatic int 2847203108Smavahci_sata_phy_reset(device_t dev) 2848195534Sscottl{ 2849195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2850199821Smav int sata_rev; 2851195534Sscottl uint32_t val; 2852195534Sscottl 2853220657Smav if (ch->listening) { 2854220657Smav val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2855220657Smav val |= AHCI_P_CMD_SUD; 2856220657Smav ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2857220657Smav ch->listening = 0; 2858220657Smav } 2859199821Smav sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2860199821Smav if (sata_rev == 1) 2861195534Sscottl val = ATA_SC_SPD_SPEED_GEN1; 2862199821Smav else if (sata_rev == 2) 2863195534Sscottl val = ATA_SC_SPD_SPEED_GEN2; 2864199821Smav else if (sata_rev == 3) 2865195534Sscottl val = ATA_SC_SPD_SPEED_GEN3; 2866195534Sscottl else 2867195534Sscottl val = 0; 2868195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2869196656Smav ATA_SC_DET_RESET | val | 2870196656Smav ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2871220777Smav DELAY(1000); 2872196656Smav ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2873195534Sscottl ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2874195534Sscottl (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2875203426Smav if (!ahci_sata_connect(ch)) { 2876220657Smav if (ch->caps & AHCI_CAP_SSS) { 2877220657Smav val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2878220657Smav val &= ~AHCI_P_CMD_SUD; 2879220657Smav ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2880220657Smav ch->listening = 1; 2881220657Smav } else if (ch->pm_level > 0) 2882203426Smav ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2883203426Smav return (0); 2884203426Smav } 2885203426Smav return (1); 2886195534Sscottl} 2887195534Sscottl 2888207430Smavstatic int 2889207430Smavahci_check_ids(device_t dev, union ccb *ccb) 2890207430Smav{ 2891207430Smav struct ahci_channel *ch = device_get_softc(dev); 2892207430Smav 2893207430Smav if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2894207430Smav ccb->ccb_h.status = CAM_TID_INVALID; 2895256843Smav ahci_done(ch, ccb); 2896207430Smav return (-1); 2897207430Smav } 2898207430Smav if (ccb->ccb_h.target_lun != 0) { 2899207430Smav ccb->ccb_h.status = CAM_LUN_INVALID; 2900256843Smav ahci_done(ch, ccb); 2901207430Smav return (-1); 2902207430Smav } 2903207430Smav return (0); 2904207430Smav} 2905207430Smav 2906195534Sscottlstatic void 2907195534Sscottlahciaction(struct cam_sim *sim, union ccb *ccb) 2908195534Sscottl{ 2909210471Smav device_t dev, parent; 2910195534Sscottl struct ahci_channel *ch; 2911195534Sscottl 2912195534Sscottl CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2913195534Sscottl ccb->ccb_h.func_code)); 2914195534Sscottl 2915195534Sscottl ch = (struct ahci_channel *)cam_sim_softc(sim); 2916195534Sscottl dev = ch->dev; 2917195534Sscottl switch (ccb->ccb_h.func_code) { 2918195534Sscottl /* Common cases first */ 2919195534Sscottl case XPT_ATA_IO: /* Execute the requested I/O operation */ 2920195534Sscottl case XPT_SCSI_IO: 2921207430Smav if (ahci_check_ids(dev, ccb)) 2922207430Smav return; 2923207430Smav if (ch->devices == 0 || 2924207430Smav (ch->pm_present == 0 && 2925207430Smav ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2926195534Sscottl ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2927195534Sscottl break; 2928195534Sscottl } 2929220565Smav ccb->ccb_h.recovery_type = RECOVERY_NONE; 2930195534Sscottl /* Check for command collision. */ 2931195534Sscottl if (ahci_check_collision(dev, ccb)) { 2932195534Sscottl /* Freeze command. */ 2933195534Sscottl ch->frozen = ccb; 2934195534Sscottl /* We have only one frozen slot, so freeze simq also. */ 2935195534Sscottl xpt_freeze_simq(ch->sim, 1); 2936195534Sscottl return; 2937195534Sscottl } 2938195534Sscottl ahci_begin_transaction(dev, ccb); 2939207430Smav return; 2940195534Sscottl case XPT_EN_LUN: /* Enable LUN as a target */ 2941195534Sscottl case XPT_TARGET_IO: /* Execute target I/O request */ 2942195534Sscottl case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2943195534Sscottl case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2944195534Sscottl case XPT_ABORT: /* Abort the specified CCB */ 2945195534Sscottl /* XXX Implement */ 2946195534Sscottl ccb->ccb_h.status = CAM_REQ_INVALID; 2947195534Sscottl break; 2948195534Sscottl case XPT_SET_TRAN_SETTINGS: 2949195534Sscottl { 2950195534Sscottl struct ccb_trans_settings *cts = &ccb->cts; 2951199747Smav struct ahci_device *d; 2952195534Sscottl 2953207430Smav if (ahci_check_ids(dev, ccb)) 2954207430Smav return; 2955199747Smav if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2956199747Smav d = &ch->curr[ccb->ccb_h.target_id]; 2957199747Smav else 2958199747Smav d = &ch->user[ccb->ccb_h.target_id]; 2959199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2960199747Smav d->revision = cts->xport_specific.sata.revision; 2961199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2962199747Smav d->mode = cts->xport_specific.sata.mode; 2963199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2964199747Smav d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2965199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2966199747Smav d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2967199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2968195534Sscottl ch->pm_present = cts->xport_specific.sata.pm_present; 2969203376Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2970203376Smav d->atapi = cts->xport_specific.sata.atapi; 2971207499Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2972207499Smav d->caps = cts->xport_specific.sata.caps; 2973195534Sscottl ccb->ccb_h.status = CAM_REQ_CMP; 2974195534Sscottl break; 2975195534Sscottl } 2976195534Sscottl case XPT_GET_TRAN_SETTINGS: 2977195534Sscottl /* Get default/user set transfer settings for the target */ 2978195534Sscottl { 2979195534Sscottl struct ccb_trans_settings *cts = &ccb->cts; 2980199747Smav struct ahci_device *d; 2981195534Sscottl uint32_t status; 2982195534Sscottl 2983207430Smav if (ahci_check_ids(dev, ccb)) 2984207430Smav return; 2985199747Smav if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2986199747Smav d = &ch->curr[ccb->ccb_h.target_id]; 2987199747Smav else 2988199747Smav d = &ch->user[ccb->ccb_h.target_id]; 2989236666Smav cts->protocol = PROTO_UNSPECIFIED; 2990196656Smav cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2991195534Sscottl cts->transport = XPORT_SATA; 2992196656Smav cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2993195534Sscottl cts->proto_specific.valid = 0; 2994195534Sscottl cts->xport_specific.sata.valid = 0; 2995199747Smav if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2996199747Smav (ccb->ccb_h.target_id == 15 || 2997199747Smav (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2998195534Sscottl status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2999199747Smav if (status & 0x0f0) { 3000199747Smav cts->xport_specific.sata.revision = 3001199747Smav (status & 0x0f0) >> 4; 3002199747Smav cts->xport_specific.sata.valid |= 3003199747Smav CTS_SATA_VALID_REVISION; 3004199747Smav } 3005207499Smav cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 3006207499Smav if (ch->pm_level) { 3007207499Smav if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 3008207499Smav cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 3009207499Smav if (ch->caps2 & AHCI_CAP2_APST) 3010207499Smav cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 3011207499Smav } 3012207499Smav if ((ch->caps & AHCI_CAP_SNCQ) && 3013207499Smav (ch->quirks & AHCI_Q_NOAA) == 0) 3014207499Smav cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 3015220602Smav cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 3016207499Smav cts->xport_specific.sata.caps &= 3017207499Smav ch->user[ccb->ccb_h.target_id].caps; 3018207499Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3019195534Sscottl } else { 3020199747Smav cts->xport_specific.sata.revision = d->revision; 3021199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 3022207499Smav cts->xport_specific.sata.caps = d->caps; 3023207499Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 3024195534Sscottl } 3025199747Smav cts->xport_specific.sata.mode = d->mode; 3026199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 3027199747Smav cts->xport_specific.sata.bytecount = d->bytecount; 3028199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 3029199747Smav cts->xport_specific.sata.pm_present = ch->pm_present; 3030195534Sscottl cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 3031199747Smav cts->xport_specific.sata.tags = d->tags; 3032199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 3033203376Smav cts->xport_specific.sata.atapi = d->atapi; 3034203376Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 3035195534Sscottl ccb->ccb_h.status = CAM_REQ_CMP; 3036195534Sscottl break; 3037195534Sscottl } 3038195534Sscottl case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 3039195534Sscottl case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 3040195534Sscottl ahci_reset(dev); 3041195534Sscottl ccb->ccb_h.status = CAM_REQ_CMP; 3042195534Sscottl break; 3043195534Sscottl case XPT_TERM_IO: /* Terminate the I/O process */ 3044195534Sscottl /* XXX Implement */ 3045195534Sscottl ccb->ccb_h.status = CAM_REQ_INVALID; 3046195534Sscottl break; 3047195534Sscottl case XPT_PATH_INQ: /* Path routing inquiry */ 3048195534Sscottl { 3049195534Sscottl struct ccb_pathinq *cpi = &ccb->cpi; 3050195534Sscottl 3051210471Smav parent = device_get_parent(dev); 3052195534Sscottl cpi->version_num = 1; /* XXX??? */ 3053199278Smav cpi->hba_inquiry = PI_SDTR_ABLE; 3054199278Smav if (ch->caps & AHCI_CAP_SNCQ) 3055199278Smav cpi->hba_inquiry |= PI_TAG_ABLE; 3056195534Sscottl if (ch->caps & AHCI_CAP_SPM) 3057195534Sscottl cpi->hba_inquiry |= PI_SATAPM; 3058195534Sscottl cpi->target_sprt = 0; 3059248522Skib cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 3060195534Sscottl cpi->hba_eng_cnt = 0; 3061195534Sscottl if (ch->caps & AHCI_CAP_SPM) 3062198322Smav cpi->max_target = 15; 3063195534Sscottl else 3064195534Sscottl cpi->max_target = 0; 3065195534Sscottl cpi->max_lun = 0; 3066195534Sscottl cpi->initiator_id = 0; 3067195534Sscottl cpi->bus_id = cam_sim_bus(sim); 3068195534Sscottl cpi->base_transfer_speed = 150000; 3069195534Sscottl strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3070195534Sscottl strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 3071195534Sscottl strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3072195534Sscottl cpi->unit_number = cam_sim_unit(sim); 3073195534Sscottl cpi->transport = XPORT_SATA; 3074196656Smav cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 3075236847Smav cpi->protocol = PROTO_ATA; 3076196656Smav cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 3077195534Sscottl cpi->maxio = MAXPHYS; 3078196777Smav /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 3079210471Smav if (pci_get_devid(parent) == 0x43801002) 3080196796Smav cpi->maxio = min(cpi->maxio, 128 * 512); 3081210471Smav cpi->hba_vendor = pci_get_vendor(parent); 3082210471Smav cpi->hba_device = pci_get_device(parent); 3083210471Smav cpi->hba_subvendor = pci_get_subvendor(parent); 3084210471Smav cpi->hba_subdevice = pci_get_subdevice(parent); 3085195534Sscottl cpi->ccb_h.status = CAM_REQ_CMP; 3086195534Sscottl break; 3087195534Sscottl } 3088195534Sscottl default: 3089195534Sscottl ccb->ccb_h.status = CAM_REQ_INVALID; 3090195534Sscottl break; 3091195534Sscottl } 3092256843Smav ahci_done(ch, ccb); 3093195534Sscottl} 3094195534Sscottl 3095195534Sscottlstatic void 3096195534Sscottlahcipoll(struct cam_sim *sim) 3097195534Sscottl{ 3098195534Sscottl struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 3099256843Smav uint32_t istatus; 3100195534Sscottl 3101256843Smav /* Read interrupt statuses and process if any. */ 3102256843Smav istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 3103256843Smav if (istatus != 0) 3104256843Smav ahci_ch_intr_main(ch, istatus); 3105220789Smav if (ch->resetting != 0 && 3106220789Smav (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 3107220789Smav ch->resetpolldiv = 1000; 3108220789Smav ahci_reset_to(ch->dev); 3109220789Smav } 3110195534Sscottl} 3111