ahci_pci.c revision 211922
1195534Sscottl/*- 2195534Sscottl * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3195534Sscottl * All rights reserved. 4195534Sscottl * 5195534Sscottl * Redistribution and use in source and binary forms, with or without 6195534Sscottl * modification, are permitted provided that the following conditions 7195534Sscottl * are met: 8195534Sscottl * 1. Redistributions of source code must retain the above copyright 9195534Sscottl * notice, this list of conditions and the following disclaimer, 10195534Sscottl * without modification, immediately at the beginning of the file. 11195534Sscottl * 2. Redistributions in binary form must reproduce the above copyright 12195534Sscottl * notice, this list of conditions and the following disclaimer in the 13195534Sscottl * documentation and/or other materials provided with the distribution. 14195534Sscottl * 15195534Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16195534Sscottl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17195534Sscottl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18195534Sscottl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19195534Sscottl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20195534Sscottl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21195534Sscottl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22195534Sscottl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23195534Sscottl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24195534Sscottl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25195534Sscottl */ 26195534Sscottl 27195534Sscottl#include <sys/cdefs.h> 28195534Sscottl__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 211922 2010-08-28 07:24:45Z mav $"); 29195534Sscottl 30195534Sscottl#include <sys/param.h> 31195534Sscottl#include <sys/module.h> 32195534Sscottl#include <sys/systm.h> 33195534Sscottl#include <sys/kernel.h> 34195534Sscottl#include <sys/ata.h> 35195534Sscottl#include <sys/bus.h> 36195534Sscottl#include <sys/endian.h> 37195534Sscottl#include <sys/malloc.h> 38195534Sscottl#include <sys/lock.h> 39195534Sscottl#include <sys/mutex.h> 40195534Sscottl#include <sys/sema.h> 41195534Sscottl#include <sys/taskqueue.h> 42195534Sscottl#include <vm/uma.h> 43195534Sscottl#include <machine/stdarg.h> 44195534Sscottl#include <machine/resource.h> 45195534Sscottl#include <machine/bus.h> 46195534Sscottl#include <sys/rman.h> 47195534Sscottl#include <dev/pci/pcivar.h> 48195534Sscottl#include <dev/pci/pcireg.h> 49195534Sscottl#include "ahci.h" 50195534Sscottl 51195534Sscottl#include <cam/cam.h> 52195534Sscottl#include <cam/cam_ccb.h> 53195534Sscottl#include <cam/cam_sim.h> 54195534Sscottl#include <cam/cam_xpt_sim.h> 55195534Sscottl#include <cam/cam_debug.h> 56195534Sscottl 57195534Sscottl/* local prototypes */ 58195534Sscottlstatic int ahci_setup_interrupt(device_t dev); 59195534Sscottlstatic void ahci_intr(void *data); 60195534Sscottlstatic void ahci_intr_one(void *data); 61195534Sscottlstatic int ahci_suspend(device_t dev); 62195534Sscottlstatic int ahci_resume(device_t dev); 63208375Smavstatic int ahci_ch_init(device_t dev); 64208375Smavstatic int ahci_ch_deinit(device_t dev); 65195534Sscottlstatic int ahci_ch_suspend(device_t dev); 66195534Sscottlstatic int ahci_ch_resume(device_t dev); 67196656Smavstatic void ahci_ch_pm(void *arg); 68195534Sscottlstatic void ahci_ch_intr_locked(void *data); 69195534Sscottlstatic void ahci_ch_intr(void *data); 70195534Sscottlstatic int ahci_ctlr_reset(device_t dev); 71205422Smavstatic int ahci_ctlr_setup(device_t dev); 72195534Sscottlstatic void ahci_begin_transaction(device_t dev, union ccb *ccb); 73195534Sscottlstatic void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 74195534Sscottlstatic void ahci_execute_transaction(struct ahci_slot *slot); 75195534Sscottlstatic void ahci_timeout(struct ahci_slot *slot); 76195534Sscottlstatic void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 77199821Smavstatic int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 78195534Sscottlstatic void ahci_dmainit(device_t dev); 79195534Sscottlstatic void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 80195534Sscottlstatic void ahci_dmafini(device_t dev); 81195534Sscottlstatic void ahci_slotsalloc(device_t dev); 82195534Sscottlstatic void ahci_slotsfree(device_t dev); 83195534Sscottlstatic void ahci_reset(device_t dev); 84203123Smavstatic void ahci_start(device_t dev, int fbs); 85195534Sscottlstatic void ahci_stop(device_t dev); 86195534Sscottlstatic void ahci_clo(device_t dev); 87195534Sscottlstatic void ahci_start_fr(device_t dev); 88195534Sscottlstatic void ahci_stop_fr(device_t dev); 89195534Sscottl 90195534Sscottlstatic int ahci_sata_connect(struct ahci_channel *ch); 91203108Smavstatic int ahci_sata_phy_reset(device_t dev); 92203123Smavstatic int ahci_wait_ready(device_t dev, int t); 93195534Sscottl 94195534Sscottlstatic void ahci_issue_read_log(device_t dev); 95195534Sscottlstatic void ahci_process_read_log(device_t dev, union ccb *ccb); 96195534Sscottl 97195534Sscottlstatic void ahciaction(struct cam_sim *sim, union ccb *ccb); 98195534Sscottlstatic void ahcipoll(struct cam_sim *sim); 99195534Sscottl 100195534SscottlMALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 101195534Sscottl 102199176Smavstatic struct { 103199176Smav uint32_t id; 104203030Smav uint8_t rev; 105199176Smav const char *name; 106199322Smav int quirks; 107199322Smav#define AHCI_Q_NOFORCE 1 108199322Smav#define AHCI_Q_NOPMP 2 109199322Smav#define AHCI_Q_NONCQ 4 110199322Smav#define AHCI_Q_1CH 8 111199322Smav#define AHCI_Q_2CH 16 112199322Smav#define AHCI_Q_4CH 32 113199322Smav#define AHCI_Q_EDGEIS 64 114203030Smav#define AHCI_Q_SATA2 128 115203123Smav#define AHCI_Q_NOBSYRES 256 116207499Smav#define AHCI_Q_NOAA 512 117199176Smav} ahci_ids[] = { 118203030Smav {0x43801002, 0x00, "ATI IXP600", 0}, 119203030Smav {0x43901002, 0x00, "ATI IXP700", 0}, 120203030Smav {0x43911002, 0x00, "ATI IXP700", 0}, 121203030Smav {0x43921002, 0x00, "ATI IXP700", 0}, 122203030Smav {0x43931002, 0x00, "ATI IXP700", 0}, 123203030Smav {0x43941002, 0x00, "ATI IXP800", 0}, 124203030Smav {0x43951002, 0x00, "ATI IXP800", 0}, 125203030Smav {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 126203030Smav {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 127203030Smav {0x26818086, 0x00, "Intel ESB2", 0}, 128203030Smav {0x26828086, 0x00, "Intel ESB2", 0}, 129203030Smav {0x26838086, 0x00, "Intel ESB2", 0}, 130203030Smav {0x27c18086, 0x00, "Intel ICH7", 0}, 131203030Smav {0x27c38086, 0x00, "Intel ICH7", 0}, 132203030Smav {0x27c58086, 0x00, "Intel ICH7M", 0}, 133203030Smav {0x27c68086, 0x00, "Intel ICH7M", 0}, 134203030Smav {0x28218086, 0x00, "Intel ICH8", 0}, 135203030Smav {0x28228086, 0x00, "Intel ICH8", 0}, 136203030Smav {0x28248086, 0x00, "Intel ICH8", 0}, 137203030Smav {0x28298086, 0x00, "Intel ICH8M", 0}, 138203030Smav {0x282a8086, 0x00, "Intel ICH8M", 0}, 139203030Smav {0x29228086, 0x00, "Intel ICH9", 0}, 140203030Smav {0x29238086, 0x00, "Intel ICH9", 0}, 141203030Smav {0x29248086, 0x00, "Intel ICH9", 0}, 142203030Smav {0x29258086, 0x00, "Intel ICH9", 0}, 143203030Smav {0x29278086, 0x00, "Intel ICH9", 0}, 144203030Smav {0x29298086, 0x00, "Intel ICH9M", 0}, 145203030Smav {0x292a8086, 0x00, "Intel ICH9M", 0}, 146203030Smav {0x292b8086, 0x00, "Intel ICH9M", 0}, 147203030Smav {0x292c8086, 0x00, "Intel ICH9M", 0}, 148203030Smav {0x292f8086, 0x00, "Intel ICH9M", 0}, 149203030Smav {0x294d8086, 0x00, "Intel ICH9", 0}, 150203030Smav {0x294e8086, 0x00, "Intel ICH9M", 0}, 151203030Smav {0x3a058086, 0x00, "Intel ICH10", 0}, 152203030Smav {0x3a228086, 0x00, "Intel ICH10", 0}, 153203030Smav {0x3a258086, 0x00, "Intel ICH10", 0}, 154211922Smav {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 155211922Smav {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 156211922Smav {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 157211922Smav {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 158211922Smav {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 159211922Smav {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 160211922Smav {0x1c028086, 0x00, "Intel Cougar Point", 0}, 161211922Smav {0x1c038086, 0x00, "Intel Cougar Point", 0}, 162211922Smav {0x1c048086, 0x00, "Intel Cougar Point", 0}, 163211922Smav {0x1c058086, 0x00, "Intel Cougar Point", 0}, 164203030Smav {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 165203030Smav {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 166203030Smav {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 167203030Smav {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 168203030Smav {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 169203030Smav {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS}, 170203030Smav {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS}, 171203030Smav {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 172203030Smav {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 173203123Smav {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES}, 174203123Smav {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 175207499Smav {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 176207499Smav {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 177207499Smav {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 178207499Smav {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 179207499Smav {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 180207499Smav {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 181207499Smav {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 182207499Smav {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 183207499Smav {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 184207499Smav {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 185207499Smav {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 186207499Smav {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 187207499Smav {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 188207499Smav {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 189207499Smav {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 190207499Smav {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 191207499Smav {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 192207499Smav {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 193207499Smav {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 194207499Smav {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 195207499Smav {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 196207499Smav {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 197207499Smav {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 198207499Smav {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 199207499Smav {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 200207499Smav {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 201207499Smav {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 202207499Smav {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 203207499Smav {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 204207499Smav {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 205207499Smav {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 206207499Smav {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 207207499Smav {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 208207499Smav {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 209207499Smav {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 210207499Smav {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 211207499Smav {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 212207499Smav {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 213207499Smav {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 214207499Smav {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 215207499Smav {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 216207499Smav {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 217207499Smav {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 218207499Smav {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 219207499Smav {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 220207499Smav {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 221207499Smav {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 222207499Smav {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 223207499Smav {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 224207499Smav {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 225207499Smav {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 226207499Smav {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 227207499Smav {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 228207499Smav {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 229207499Smav {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 230207499Smav {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 231207499Smav {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 232207499Smav {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 233207499Smav {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 234207499Smav {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 235207499Smav {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 236207499Smav {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 237207499Smav {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 238207499Smav {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 239207499Smav {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 240207499Smav {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 241207499Smav {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 242207499Smav {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 243207499Smav {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 244208907Smav {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 245208907Smav {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 246203030Smav {0x11841039, 0x00, "SiS 966", 0}, 247203030Smav {0x11851039, 0x00, "SiS 968", 0}, 248203030Smav {0x01861039, 0x00, "SiS 968", 0}, 249203030Smav {0x00000000, 0x00, NULL, 0} 250199176Smav}; 251199176Smav 252195534Sscottlstatic int 253195534Sscottlahci_probe(device_t dev) 254195534Sscottl{ 255199176Smav char buf[64]; 256199322Smav int i, valid = 0; 257199322Smav uint32_t devid = pci_get_devid(dev); 258203030Smav uint8_t revid = pci_get_revid(dev); 259199322Smav 260199322Smav /* Is this a possible AHCI candidate? */ 261199322Smav if (pci_get_class(dev) == PCIC_STORAGE && 262199322Smav pci_get_subclass(dev) == PCIS_STORAGE_SATA && 263199322Smav pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 264199322Smav valid = 1; 265199322Smav /* Is this a known AHCI chip? */ 266199322Smav for (i = 0; ahci_ids[i].id != 0; i++) { 267199322Smav if (ahci_ids[i].id == devid && 268203030Smav ahci_ids[i].rev <= revid && 269199322Smav (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 270199717Smav /* Do not attach JMicrons with single PCI function. */ 271199717Smav if (pci_get_vendor(dev) == 0x197b && 272199717Smav (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 273199717Smav return (ENXIO); 274199322Smav snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 275199322Smav ahci_ids[i].name); 276199322Smav device_set_desc_copy(dev, buf); 277199322Smav return (BUS_PROBE_VENDOR); 278199322Smav } 279199322Smav } 280199322Smav if (!valid) 281199322Smav return (ENXIO); 282199322Smav device_set_desc_copy(dev, "AHCI SATA controller"); 283199322Smav return (BUS_PROBE_VENDOR); 284199322Smav} 285199322Smav 286199322Smavstatic int 287199322Smavahci_ata_probe(device_t dev) 288199322Smav{ 289199322Smav char buf[64]; 290199176Smav int i; 291199176Smav uint32_t devid = pci_get_devid(dev); 292203030Smav uint8_t revid = pci_get_revid(dev); 293195534Sscottl 294199322Smav if ((intptr_t)device_get_ivars(dev) >= 0) 295199322Smav return (ENXIO); 296199176Smav /* Is this a known AHCI chip? */ 297199176Smav for (i = 0; ahci_ids[i].id != 0; i++) { 298203030Smav if (ahci_ids[i].id == devid && 299203030Smav ahci_ids[i].rev <= revid) { 300199176Smav snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 301199176Smav ahci_ids[i].name); 302199176Smav device_set_desc_copy(dev, buf); 303199176Smav return (BUS_PROBE_VENDOR); 304199176Smav } 305199176Smav } 306199176Smav device_set_desc_copy(dev, "AHCI SATA controller"); 307195534Sscottl return (BUS_PROBE_VENDOR); 308195534Sscottl} 309195534Sscottl 310195534Sscottlstatic int 311195534Sscottlahci_attach(device_t dev) 312195534Sscottl{ 313195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 314195534Sscottl device_t child; 315199322Smav int error, unit, speed, i; 316199322Smav uint32_t devid = pci_get_devid(dev); 317203030Smav uint8_t revid = pci_get_revid(dev); 318196656Smav u_int32_t version; 319195534Sscottl 320195534Sscottl ctlr->dev = dev; 321199322Smav i = 0; 322203030Smav while (ahci_ids[i].id != 0 && 323203030Smav (ahci_ids[i].id != devid || 324203030Smav ahci_ids[i].rev > revid)) 325199322Smav i++; 326199322Smav ctlr->quirks = ahci_ids[i].quirks; 327196656Smav resource_int_value(device_get_name(dev), 328196656Smav device_get_unit(dev), "ccc", &ctlr->ccc); 329195534Sscottl /* if we have a memory BAR(5) we are likely on an AHCI part */ 330195534Sscottl ctlr->r_rid = PCIR_BAR(5); 331195534Sscottl if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 332195534Sscottl &ctlr->r_rid, RF_ACTIVE))) 333195534Sscottl return ENXIO; 334195534Sscottl /* Setup our own memory management for channels. */ 335208414Smav ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 336208414Smav ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 337195534Sscottl ctlr->sc_iomem.rm_type = RMAN_ARRAY; 338195534Sscottl ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 339195534Sscottl if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 340195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 341195534Sscottl return (error); 342195534Sscottl } 343195534Sscottl if ((error = rman_manage_region(&ctlr->sc_iomem, 344195534Sscottl rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 345195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 346195534Sscottl rman_fini(&ctlr->sc_iomem); 347195534Sscottl return (error); 348195534Sscottl } 349207511Smav pci_enable_busmaster(dev); 350195534Sscottl /* Reset controller */ 351195534Sscottl if ((error = ahci_ctlr_reset(dev)) != 0) { 352195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 353195534Sscottl rman_fini(&ctlr->sc_iomem); 354195534Sscottl return (error); 355195534Sscottl }; 356199322Smav /* Get the HW capabilities */ 357199322Smav version = ATA_INL(ctlr->r_mem, AHCI_VS); 358199322Smav ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 359199322Smav if (version >= 0x00010020) 360199322Smav ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 361203108Smav if (ctlr->caps & AHCI_CAP_EMS) 362203108Smav ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 363195534Sscottl ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 364199322Smav if (ctlr->quirks & AHCI_Q_1CH) { 365199322Smav ctlr->caps &= ~AHCI_CAP_NPMASK; 366199322Smav ctlr->ichannels &= 0x01; 367199322Smav } 368199322Smav if (ctlr->quirks & AHCI_Q_2CH) { 369199322Smav ctlr->caps &= ~AHCI_CAP_NPMASK; 370199322Smav ctlr->caps |= 1; 371199322Smav ctlr->ichannels &= 0x03; 372199322Smav } 373199322Smav if (ctlr->quirks & AHCI_Q_4CH) { 374199322Smav ctlr->caps &= ~AHCI_CAP_NPMASK; 375199322Smav ctlr->caps |= 3; 376199322Smav ctlr->ichannels &= 0x0f; 377199322Smav } 378195534Sscottl ctlr->channels = MAX(flsl(ctlr->ichannels), 379199322Smav (ctlr->caps & AHCI_CAP_NPMASK) + 1); 380199322Smav if (ctlr->quirks & AHCI_Q_NOPMP) 381199322Smav ctlr->caps &= ~AHCI_CAP_SPM; 382199322Smav if (ctlr->quirks & AHCI_Q_NONCQ) 383199322Smav ctlr->caps &= ~AHCI_CAP_SNCQ; 384205422Smav if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 385205422Smav ctlr->ccc = 0; 386205422Smav ahci_ctlr_setup(dev); 387195534Sscottl /* Setup interrupts. */ 388195534Sscottl if (ahci_setup_interrupt(dev)) { 389195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 390195534Sscottl rman_fini(&ctlr->sc_iomem); 391195534Sscottl return ENXIO; 392195534Sscottl } 393195534Sscottl /* Announce HW capabilities. */ 394196656Smav speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 395195534Sscottl device_printf(dev, 396203123Smav "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 397195534Sscottl ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 398195534Sscottl ((version >> 4) & 0xf0) + (version & 0x0f), 399196656Smav (ctlr->caps & AHCI_CAP_NPMASK) + 1, 400195534Sscottl ((speed == 1) ? "1.5":((speed == 2) ? "3": 401195534Sscottl ((speed == 3) ? "6":"?"))), 402196656Smav (ctlr->caps & AHCI_CAP_SPM) ? 403203123Smav "supported" : "not supported", 404203123Smav (ctlr->caps & AHCI_CAP_FBSS) ? 405203123Smav " with FBS" : ""); 406195534Sscottl if (bootverbose) { 407195534Sscottl device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 408196656Smav (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 409196656Smav (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 410196656Smav (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 411196656Smav (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 412196656Smav (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 413196656Smav (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 414196656Smav (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 415196656Smav (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 416195534Sscottl ((speed == 1) ? "1.5":((speed == 2) ? "3": 417195534Sscottl ((speed == 3) ? "6":"?")))); 418195534Sscottl printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 419196656Smav (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 420196656Smav (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 421196656Smav (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 422196656Smav (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 423196656Smav (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 424196656Smav (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 425196656Smav ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 426196656Smav (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 427196656Smav (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 428196656Smav (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 429196656Smav (ctlr->caps & AHCI_CAP_NPMASK) + 1); 430195534Sscottl } 431196656Smav if (bootverbose && version >= 0x00010020) { 432196656Smav device_printf(dev, "Caps2:%s%s%s\n", 433196656Smav (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 434196656Smav (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 435196656Smav (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 436196656Smav } 437203108Smav if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 438203123Smav device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 439203108Smav (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 440203108Smav (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 441203108Smav (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 442203108Smav (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 443203108Smav (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 444203108Smav (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 445203108Smav (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 446203108Smav (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 447203108Smav } 448195534Sscottl /* Attach all channels on this controller */ 449195534Sscottl for (unit = 0; unit < ctlr->channels; unit++) { 450195534Sscottl if ((ctlr->ichannels & (1 << unit)) == 0) 451195534Sscottl continue; 452195534Sscottl child = device_add_child(dev, "ahcich", -1); 453195534Sscottl if (child == NULL) 454195534Sscottl device_printf(dev, "failed to add channel device\n"); 455195534Sscottl else 456195534Sscottl device_set_ivars(child, (void *)(intptr_t)unit); 457195534Sscottl } 458195534Sscottl bus_generic_attach(dev); 459195534Sscottl return 0; 460195534Sscottl} 461195534Sscottl 462195534Sscottlstatic int 463195534Sscottlahci_detach(device_t dev) 464195534Sscottl{ 465195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 466195534Sscottl device_t *children; 467195534Sscottl int nchildren, i; 468195534Sscottl 469195534Sscottl /* Detach & delete all children */ 470195534Sscottl if (!device_get_children(dev, &children, &nchildren)) { 471195534Sscottl for (i = 0; i < nchildren; i++) 472195534Sscottl device_delete_child(dev, children[i]); 473195534Sscottl free(children, M_TEMP); 474195534Sscottl } 475195534Sscottl /* Free interrupts. */ 476195534Sscottl for (i = 0; i < ctlr->numirqs; i++) { 477195534Sscottl if (ctlr->irqs[i].r_irq) { 478195534Sscottl bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 479195534Sscottl ctlr->irqs[i].handle); 480195534Sscottl bus_release_resource(dev, SYS_RES_IRQ, 481195534Sscottl ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 482195534Sscottl } 483195534Sscottl } 484195534Sscottl pci_release_msi(dev); 485195534Sscottl /* Free memory. */ 486195534Sscottl rman_fini(&ctlr->sc_iomem); 487195534Sscottl if (ctlr->r_mem) 488195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 489195534Sscottl return (0); 490195534Sscottl} 491195534Sscottl 492195534Sscottlstatic int 493195534Sscottlahci_ctlr_reset(device_t dev) 494195534Sscottl{ 495195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 496195534Sscottl int timeout; 497195534Sscottl 498195534Sscottl if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 499195534Sscottl (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 500195534Sscottl pci_write_config(dev, 0x92, 0x01, 1); 501195534Sscottl /* Enable AHCI mode */ 502195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 503195534Sscottl /* Reset AHCI controller */ 504195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 505195534Sscottl for (timeout = 1000; timeout > 0; timeout--) { 506195534Sscottl DELAY(1000); 507195534Sscottl if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 508195534Sscottl break; 509195534Sscottl } 510195534Sscottl if (timeout == 0) { 511195534Sscottl device_printf(dev, "AHCI controller reset failure\n"); 512195534Sscottl return ENXIO; 513195534Sscottl } 514195534Sscottl /* Reenable AHCI mode */ 515195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 516205422Smav return (0); 517205422Smav} 518205422Smav 519205422Smavstatic int 520205422Smavahci_ctlr_setup(device_t dev) 521205422Smav{ 522205422Smav struct ahci_controller *ctlr = device_get_softc(dev); 523195534Sscottl /* Clear interrupts */ 524195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 525196656Smav /* Configure CCC */ 526196656Smav if (ctlr->ccc) { 527196656Smav ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 528196656Smav ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 529196656Smav (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 530196656Smav (4 << AHCI_CCCC_CC_SHIFT) | 531196656Smav AHCI_CCCC_EN); 532196656Smav ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 533196656Smav AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 534196656Smav if (bootverbose) { 535196656Smav device_printf(dev, 536196656Smav "CCC with %dms/4cmd enabled on vector %d\n", 537196656Smav ctlr->ccc, ctlr->cccv); 538196656Smav } 539196656Smav } 540195534Sscottl /* Enable AHCI interrupts */ 541195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, 542195534Sscottl ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 543195534Sscottl return (0); 544195534Sscottl} 545195534Sscottl 546195534Sscottlstatic int 547195534Sscottlahci_suspend(device_t dev) 548195534Sscottl{ 549195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 550195534Sscottl 551195534Sscottl bus_generic_suspend(dev); 552195534Sscottl /* Disable interupts, so the state change(s) doesn't trigger */ 553195534Sscottl ATA_OUTL(ctlr->r_mem, AHCI_GHC, 554195534Sscottl ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 555195534Sscottl return 0; 556195534Sscottl} 557195534Sscottl 558195534Sscottlstatic int 559195534Sscottlahci_resume(device_t dev) 560195534Sscottl{ 561195534Sscottl int res; 562195534Sscottl 563195534Sscottl if ((res = ahci_ctlr_reset(dev)) != 0) 564195534Sscottl return (res); 565205422Smav ahci_ctlr_setup(dev); 566195534Sscottl return (bus_generic_resume(dev)); 567195534Sscottl} 568195534Sscottl 569195534Sscottlstatic int 570195534Sscottlahci_setup_interrupt(device_t dev) 571195534Sscottl{ 572195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 573195534Sscottl int i, msi = 1; 574195534Sscottl 575195534Sscottl /* Process hints. */ 576195534Sscottl resource_int_value(device_get_name(dev), 577195534Sscottl device_get_unit(dev), "msi", &msi); 578195534Sscottl if (msi < 0) 579195534Sscottl msi = 0; 580195534Sscottl else if (msi == 1) 581195534Sscottl msi = min(1, pci_msi_count(dev)); 582195534Sscottl else if (msi > 1) 583195534Sscottl msi = pci_msi_count(dev); 584195534Sscottl /* Allocate MSI if needed/present. */ 585195534Sscottl if (msi && pci_alloc_msi(dev, &msi) == 0) { 586195534Sscottl ctlr->numirqs = msi; 587195534Sscottl } else { 588195534Sscottl msi = 0; 589195534Sscottl ctlr->numirqs = 1; 590195534Sscottl } 591195534Sscottl /* Check for single MSI vector fallback. */ 592195534Sscottl if (ctlr->numirqs > 1 && 593195534Sscottl (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 594195534Sscottl device_printf(dev, "Falling back to one MSI\n"); 595195534Sscottl ctlr->numirqs = 1; 596195534Sscottl } 597195534Sscottl /* Allocate all IRQs. */ 598195534Sscottl for (i = 0; i < ctlr->numirqs; i++) { 599195534Sscottl ctlr->irqs[i].ctlr = ctlr; 600195534Sscottl ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 601196656Smav if (ctlr->numirqs == 1 || i >= ctlr->channels || 602196656Smav (ctlr->ccc && i == ctlr->cccv)) 603195534Sscottl ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 604195534Sscottl else if (i == ctlr->numirqs - 1) 605195534Sscottl ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 606195534Sscottl else 607195534Sscottl ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 608195534Sscottl if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 609195534Sscottl &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 610195534Sscottl device_printf(dev, "unable to map interrupt\n"); 611195534Sscottl return ENXIO; 612195534Sscottl } 613195534Sscottl if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 614195534Sscottl (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 615195534Sscottl &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 616195534Sscottl /* SOS XXX release r_irq */ 617195534Sscottl device_printf(dev, "unable to setup interrupt\n"); 618195534Sscottl return ENXIO; 619195534Sscottl } 620202011Smav if (ctlr->numirqs > 1) { 621202011Smav bus_describe_intr(dev, ctlr->irqs[i].r_irq, 622202011Smav ctlr->irqs[i].handle, 623202011Smav ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 624202011Smav "ch%d" : "%d", i); 625202011Smav } 626195534Sscottl } 627195534Sscottl return (0); 628195534Sscottl} 629195534Sscottl 630195534Sscottl/* 631195534Sscottl * Common case interrupt handler. 632195534Sscottl */ 633195534Sscottlstatic void 634195534Sscottlahci_intr(void *data) 635195534Sscottl{ 636195534Sscottl struct ahci_controller_irq *irq = data; 637195534Sscottl struct ahci_controller *ctlr = irq->ctlr; 638205422Smav u_int32_t is, ise = 0; 639195534Sscottl void *arg; 640195534Sscottl int unit; 641195534Sscottl 642196656Smav if (irq->mode == AHCI_IRQ_MODE_ALL) { 643195534Sscottl unit = 0; 644196656Smav if (ctlr->ccc) 645196656Smav is = ctlr->ichannels; 646196656Smav else 647196656Smav is = ATA_INL(ctlr->r_mem, AHCI_IS); 648196656Smav } else { /* AHCI_IRQ_MODE_AFTER */ 649195534Sscottl unit = irq->r_irq_rid - 1; 650196656Smav is = ATA_INL(ctlr->r_mem, AHCI_IS); 651196656Smav } 652205422Smav /* CCC interrupt is edge triggered. */ 653205422Smav if (ctlr->ccc) 654205422Smav ise = 1 << ctlr->cccv; 655200814Smav /* Some controllers have edge triggered IS. */ 656200814Smav if (ctlr->quirks & AHCI_Q_EDGEIS) 657205422Smav ise |= is; 658205422Smav if (ise != 0) 659205422Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 660195534Sscottl for (; unit < ctlr->channels; unit++) { 661195534Sscottl if ((is & (1 << unit)) != 0 && 662195534Sscottl (arg = ctlr->interrupt[unit].argument)) { 663199322Smav ctlr->interrupt[unit].function(arg); 664195534Sscottl } 665195534Sscottl } 666200814Smav /* AHCI declares level triggered IS. */ 667200814Smav if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 668200814Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 669195534Sscottl} 670195534Sscottl 671195534Sscottl/* 672195534Sscottl * Simplified interrupt handler for multivector MSI mode. 673195534Sscottl */ 674195534Sscottlstatic void 675195534Sscottlahci_intr_one(void *data) 676195534Sscottl{ 677195534Sscottl struct ahci_controller_irq *irq = data; 678195534Sscottl struct ahci_controller *ctlr = irq->ctlr; 679195534Sscottl void *arg; 680195534Sscottl int unit; 681195534Sscottl 682195534Sscottl unit = irq->r_irq_rid - 1; 683202011Smav /* Some controllers have edge triggered IS. */ 684202011Smav if (ctlr->quirks & AHCI_Q_EDGEIS) 685202011Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 686195534Sscottl if ((arg = ctlr->interrupt[unit].argument)) 687195534Sscottl ctlr->interrupt[unit].function(arg); 688202011Smav /* AHCI declares level triggered IS. */ 689202011Smav if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 690202011Smav ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 691195534Sscottl} 692195534Sscottl 693195534Sscottlstatic struct resource * 694195534Sscottlahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 695195534Sscottl u_long start, u_long end, u_long count, u_int flags) 696195534Sscottl{ 697195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 698195534Sscottl int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 699195534Sscottl struct resource *res = NULL; 700195534Sscottl int offset = AHCI_OFFSET + (unit << 7); 701195534Sscottl long st; 702195534Sscottl 703195534Sscottl switch (type) { 704195534Sscottl case SYS_RES_MEMORY: 705195534Sscottl st = rman_get_start(ctlr->r_mem); 706195534Sscottl res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 707195534Sscottl st + offset + 127, 128, RF_ACTIVE, child); 708195534Sscottl if (res) { 709195534Sscottl bus_space_handle_t bsh; 710195534Sscottl bus_space_tag_t bst; 711195534Sscottl bsh = rman_get_bushandle(ctlr->r_mem); 712195534Sscottl bst = rman_get_bustag(ctlr->r_mem); 713195534Sscottl bus_space_subregion(bst, bsh, offset, 128, &bsh); 714195534Sscottl rman_set_bushandle(res, bsh); 715195534Sscottl rman_set_bustag(res, bst); 716195534Sscottl } 717195534Sscottl break; 718195534Sscottl case SYS_RES_IRQ: 719195534Sscottl if (*rid == ATA_IRQ_RID) 720195534Sscottl res = ctlr->irqs[0].r_irq; 721195534Sscottl break; 722195534Sscottl } 723195534Sscottl return (res); 724195534Sscottl} 725195534Sscottl 726195534Sscottlstatic int 727195534Sscottlahci_release_resource(device_t dev, device_t child, int type, int rid, 728195534Sscottl struct resource *r) 729195534Sscottl{ 730195534Sscottl 731195534Sscottl switch (type) { 732195534Sscottl case SYS_RES_MEMORY: 733195534Sscottl rman_release_resource(r); 734195534Sscottl return (0); 735195534Sscottl case SYS_RES_IRQ: 736195534Sscottl if (rid != ATA_IRQ_RID) 737195534Sscottl return ENOENT; 738195534Sscottl return (0); 739195534Sscottl } 740195534Sscottl return (EINVAL); 741195534Sscottl} 742195534Sscottl 743195534Sscottlstatic int 744195534Sscottlahci_setup_intr(device_t dev, device_t child, struct resource *irq, 745195534Sscottl int flags, driver_filter_t *filter, driver_intr_t *function, 746195534Sscottl void *argument, void **cookiep) 747195534Sscottl{ 748195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 749195534Sscottl int unit = (intptr_t)device_get_ivars(child); 750195534Sscottl 751195534Sscottl if (filter != NULL) { 752195534Sscottl printf("ahci.c: we cannot use a filter here\n"); 753195534Sscottl return (EINVAL); 754195534Sscottl } 755195534Sscottl ctlr->interrupt[unit].function = function; 756195534Sscottl ctlr->interrupt[unit].argument = argument; 757195534Sscottl return (0); 758195534Sscottl} 759195534Sscottl 760195534Sscottlstatic int 761195534Sscottlahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 762195534Sscottl void *cookie) 763195534Sscottl{ 764195534Sscottl struct ahci_controller *ctlr = device_get_softc(dev); 765195534Sscottl int unit = (intptr_t)device_get_ivars(child); 766195534Sscottl 767195534Sscottl ctlr->interrupt[unit].function = NULL; 768195534Sscottl ctlr->interrupt[unit].argument = NULL; 769195534Sscottl return (0); 770195534Sscottl} 771195534Sscottl 772195534Sscottlstatic int 773195534Sscottlahci_print_child(device_t dev, device_t child) 774195534Sscottl{ 775195534Sscottl int retval; 776195534Sscottl 777195534Sscottl retval = bus_print_child_header(dev, child); 778195534Sscottl retval += printf(" at channel %d", 779195534Sscottl (int)(intptr_t)device_get_ivars(child)); 780195534Sscottl retval += bus_print_child_footer(dev, child); 781195534Sscottl 782195534Sscottl return (retval); 783195534Sscottl} 784195534Sscottl 785208410Smavstatic int 786208410Smavahci_child_location_str(device_t dev, device_t child, char *buf, 787208410Smav size_t buflen) 788208410Smav{ 789208410Smav 790208410Smav snprintf(buf, buflen, "channel=%d", 791208410Smav (int)(intptr_t)device_get_ivars(child)); 792208410Smav return (0); 793208410Smav} 794208410Smav 795195534Sscottldevclass_t ahci_devclass; 796195534Sscottlstatic device_method_t ahci_methods[] = { 797195534Sscottl DEVMETHOD(device_probe, ahci_probe), 798195534Sscottl DEVMETHOD(device_attach, ahci_attach), 799195534Sscottl DEVMETHOD(device_detach, ahci_detach), 800195534Sscottl DEVMETHOD(device_suspend, ahci_suspend), 801195534Sscottl DEVMETHOD(device_resume, ahci_resume), 802195534Sscottl DEVMETHOD(bus_print_child, ahci_print_child), 803195534Sscottl DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 804195534Sscottl DEVMETHOD(bus_release_resource, ahci_release_resource), 805195534Sscottl DEVMETHOD(bus_setup_intr, ahci_setup_intr), 806195534Sscottl DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 807208410Smav DEVMETHOD(bus_child_location_str, ahci_child_location_str), 808195534Sscottl { 0, 0 } 809195534Sscottl}; 810195534Sscottlstatic driver_t ahci_driver = { 811195534Sscottl "ahci", 812195534Sscottl ahci_methods, 813195534Sscottl sizeof(struct ahci_controller) 814195534Sscottl}; 815195534SscottlDRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 816199322Smavstatic device_method_t ahci_ata_methods[] = { 817199322Smav DEVMETHOD(device_probe, ahci_ata_probe), 818199322Smav DEVMETHOD(device_attach, ahci_attach), 819199322Smav DEVMETHOD(device_detach, ahci_detach), 820199322Smav DEVMETHOD(device_suspend, ahci_suspend), 821199322Smav DEVMETHOD(device_resume, ahci_resume), 822199322Smav DEVMETHOD(bus_print_child, ahci_print_child), 823199322Smav DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 824199322Smav DEVMETHOD(bus_release_resource, ahci_release_resource), 825199322Smav DEVMETHOD(bus_setup_intr, ahci_setup_intr), 826199322Smav DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 827208410Smav DEVMETHOD(bus_child_location_str, ahci_child_location_str), 828199322Smav { 0, 0 } 829199322Smav}; 830199322Smavstatic driver_t ahci_ata_driver = { 831199322Smav "ahci", 832199322Smav ahci_ata_methods, 833199322Smav sizeof(struct ahci_controller) 834199322Smav}; 835199322SmavDRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 836195534SscottlMODULE_VERSION(ahci, 1); 837195534SscottlMODULE_DEPEND(ahci, cam, 1, 1, 1); 838195534Sscottl 839195534Sscottlstatic int 840195534Sscottlahci_ch_probe(device_t dev) 841195534Sscottl{ 842195534Sscottl 843195534Sscottl device_set_desc_copy(dev, "AHCI channel"); 844195534Sscottl return (0); 845195534Sscottl} 846195534Sscottl 847195534Sscottlstatic int 848195534Sscottlahci_ch_attach(device_t dev) 849195534Sscottl{ 850195534Sscottl struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 851195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 852195534Sscottl struct cam_devq *devq; 853199821Smav int rid, error, i, sata_rev = 0; 854203123Smav u_int32_t version; 855195534Sscottl 856195534Sscottl ch->dev = dev; 857195534Sscottl ch->unit = (intptr_t)device_get_ivars(dev); 858196656Smav ch->caps = ctlr->caps; 859196656Smav ch->caps2 = ctlr->caps2; 860199322Smav ch->quirks = ctlr->quirks; 861195534Sscottl ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 862196656Smav mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 863195534Sscottl resource_int_value(device_get_name(dev), 864195534Sscottl device_get_unit(dev), "pm_level", &ch->pm_level); 865196656Smav if (ch->pm_level > 3) 866196656Smav callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 867195534Sscottl /* Limit speed for my onboard JMicron external port. 868195534Sscottl * It is not eSATA really. */ 869195534Sscottl if (pci_get_devid(ctlr->dev) == 0x2363197b && 870195534Sscottl pci_get_subvendor(ctlr->dev) == 0x1043 && 871195534Sscottl pci_get_subdevice(ctlr->dev) == 0x81e4 && 872195534Sscottl ch->unit == 0) 873199821Smav sata_rev = 1; 874203030Smav if (ch->quirks & AHCI_Q_SATA2) 875203030Smav sata_rev = 2; 876195534Sscottl resource_int_value(device_get_name(dev), 877199821Smav device_get_unit(dev), "sata_rev", &sata_rev); 878199821Smav for (i = 0; i < 16; i++) { 879199821Smav ch->user[i].revision = sata_rev; 880199821Smav ch->user[i].mode = 0; 881199821Smav ch->user[i].bytecount = 8192; 882199821Smav ch->user[i].tags = ch->numslots; 883207499Smav ch->user[i].caps = 0; 884199821Smav ch->curr[i] = ch->user[i]; 885207499Smav if (ch->pm_level) { 886207499Smav ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 887207499Smav CTS_SATA_CAPS_H_APST | 888207499Smav CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 889207499Smav } 890207499Smav ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA; 891199821Smav } 892195534Sscottl rid = ch->unit; 893195534Sscottl if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 894195534Sscottl &rid, RF_ACTIVE))) 895195534Sscottl return (ENXIO); 896195534Sscottl ahci_dmainit(dev); 897195534Sscottl ahci_slotsalloc(dev); 898208375Smav ahci_ch_init(dev); 899195534Sscottl mtx_lock(&ch->mtx); 900195534Sscottl rid = ATA_IRQ_RID; 901195534Sscottl if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 902195534Sscottl &rid, RF_SHAREABLE | RF_ACTIVE))) { 903195534Sscottl device_printf(dev, "Unable to map interrupt\n"); 904208813Smav error = ENXIO; 905208813Smav goto err0; 906195534Sscottl } 907195534Sscottl if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 908195534Sscottl ahci_ch_intr_locked, dev, &ch->ih))) { 909195534Sscottl device_printf(dev, "Unable to setup interrupt\n"); 910195534Sscottl error = ENXIO; 911195534Sscottl goto err1; 912195534Sscottl } 913203123Smav ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 914203123Smav version = ATA_INL(ctlr->r_mem, AHCI_VS); 915203123Smav if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 916203123Smav ch->chcaps |= AHCI_P_CMD_FBSCP; 917203123Smav if (bootverbose) { 918203123Smav device_printf(dev, "Caps:%s%s%s%s%s\n", 919203123Smav (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 920203123Smav (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 921203123Smav (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 922203123Smav (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 923203123Smav (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 924203123Smav } 925195534Sscottl /* Create the device queue for our SIM. */ 926195534Sscottl devq = cam_simq_alloc(ch->numslots); 927195534Sscottl if (devq == NULL) { 928195534Sscottl device_printf(dev, "Unable to allocate simq\n"); 929195534Sscottl error = ENOMEM; 930195534Sscottl goto err1; 931195534Sscottl } 932195534Sscottl /* Construct SIM entry */ 933195534Sscottl ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 934199178Smav device_get_unit(dev), &ch->mtx, 935199278Smav min(2, ch->numslots), 936199278Smav (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 937199278Smav devq); 938195534Sscottl if (ch->sim == NULL) { 939208813Smav cam_simq_free(devq); 940195534Sscottl device_printf(dev, "unable to allocate sim\n"); 941195534Sscottl error = ENOMEM; 942208813Smav goto err1; 943195534Sscottl } 944195534Sscottl if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 945195534Sscottl device_printf(dev, "unable to register xpt bus\n"); 946195534Sscottl error = ENXIO; 947195534Sscottl goto err2; 948195534Sscottl } 949195534Sscottl if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 950195534Sscottl CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 951195534Sscottl device_printf(dev, "unable to create path\n"); 952195534Sscottl error = ENXIO; 953195534Sscottl goto err3; 954195534Sscottl } 955196656Smav if (ch->pm_level > 3) { 956196656Smav callout_reset(&ch->pm_timer, 957196656Smav (ch->pm_level == 4) ? hz / 1000 : hz / 8, 958196656Smav ahci_ch_pm, dev); 959196656Smav } 960195534Sscottl mtx_unlock(&ch->mtx); 961195534Sscottl return (0); 962195534Sscottl 963195534Sscottlerr3: 964195534Sscottl xpt_bus_deregister(cam_sim_path(ch->sim)); 965195534Sscottlerr2: 966195534Sscottl cam_sim_free(ch->sim, /*free_devq*/TRUE); 967195534Sscottlerr1: 968195534Sscottl bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 969208813Smaverr0: 970195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 971195534Sscottl mtx_unlock(&ch->mtx); 972195534Sscottl return (error); 973195534Sscottl} 974195534Sscottl 975195534Sscottlstatic int 976195534Sscottlahci_ch_detach(device_t dev) 977195534Sscottl{ 978195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 979195534Sscottl 980195534Sscottl mtx_lock(&ch->mtx); 981195534Sscottl xpt_async(AC_LOST_DEVICE, ch->path, NULL); 982195534Sscottl xpt_free_path(ch->path); 983195534Sscottl xpt_bus_deregister(cam_sim_path(ch->sim)); 984195534Sscottl cam_sim_free(ch->sim, /*free_devq*/TRUE); 985195534Sscottl mtx_unlock(&ch->mtx); 986195534Sscottl 987196656Smav if (ch->pm_level > 3) 988196656Smav callout_drain(&ch->pm_timer); 989195534Sscottl bus_teardown_intr(dev, ch->r_irq, ch->ih); 990195534Sscottl bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 991195534Sscottl 992208375Smav ahci_ch_deinit(dev); 993195534Sscottl ahci_slotsfree(dev); 994195534Sscottl ahci_dmafini(dev); 995195534Sscottl 996195534Sscottl bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 997195534Sscottl mtx_destroy(&ch->mtx); 998195534Sscottl return (0); 999195534Sscottl} 1000195534Sscottl 1001195534Sscottlstatic int 1002208375Smavahci_ch_init(device_t dev) 1003195534Sscottl{ 1004195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1005208375Smav uint64_t work; 1006195534Sscottl 1007208375Smav /* Disable port interrupts */ 1008208375Smav ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1009208375Smav /* Setup work areas */ 1010208375Smav work = ch->dma.work_bus + AHCI_CL_OFFSET; 1011208375Smav ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1012208375Smav ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1013208375Smav work = ch->dma.rfis_bus; 1014208375Smav ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1015208375Smav ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1016208375Smav /* Activate the channel and power/spin up device */ 1017208375Smav ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1018208375Smav (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1019208375Smav ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1020208375Smav ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1021208375Smav ahci_start_fr(dev); 1022208375Smav ahci_start(dev, 1); 1023208375Smav return (0); 1024208375Smav} 1025208375Smav 1026208375Smavstatic int 1027208375Smavahci_ch_deinit(device_t dev) 1028208375Smav{ 1029208375Smav struct ahci_channel *ch = device_get_softc(dev); 1030208375Smav 1031195534Sscottl /* Disable port interrupts. */ 1032195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1033195534Sscottl /* Reset command register. */ 1034195534Sscottl ahci_stop(dev); 1035195534Sscottl ahci_stop_fr(dev); 1036195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1037195534Sscottl /* Allow everything, including partial and slumber modes. */ 1038195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1039195534Sscottl /* Request slumber mode transition and give some time to get there. */ 1040195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1041195534Sscottl DELAY(100); 1042195534Sscottl /* Disable PHY. */ 1043195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1044195534Sscottl return (0); 1045195534Sscottl} 1046195534Sscottl 1047195534Sscottlstatic int 1048208375Smavahci_ch_suspend(device_t dev) 1049208375Smav{ 1050208375Smav struct ahci_channel *ch = device_get_softc(dev); 1051208375Smav 1052208375Smav mtx_lock(&ch->mtx); 1053208375Smav xpt_freeze_simq(ch->sim, 1); 1054208375Smav while (ch->oslots) 1055208375Smav msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1056208375Smav ahci_ch_deinit(dev); 1057208375Smav mtx_unlock(&ch->mtx); 1058208375Smav return (0); 1059208375Smav} 1060208375Smav 1061208375Smavstatic int 1062195534Sscottlahci_ch_resume(device_t dev) 1063195534Sscottl{ 1064195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1065195534Sscottl 1066208375Smav mtx_lock(&ch->mtx); 1067208375Smav ahci_ch_init(dev); 1068208375Smav ahci_reset(dev); 1069208375Smav xpt_release_simq(ch->sim, TRUE); 1070208375Smav mtx_unlock(&ch->mtx); 1071195534Sscottl return (0); 1072195534Sscottl} 1073195534Sscottl 1074195534Sscottldevclass_t ahcich_devclass; 1075195534Sscottlstatic device_method_t ahcich_methods[] = { 1076195534Sscottl DEVMETHOD(device_probe, ahci_ch_probe), 1077195534Sscottl DEVMETHOD(device_attach, ahci_ch_attach), 1078195534Sscottl DEVMETHOD(device_detach, ahci_ch_detach), 1079195534Sscottl DEVMETHOD(device_suspend, ahci_ch_suspend), 1080195534Sscottl DEVMETHOD(device_resume, ahci_ch_resume), 1081195534Sscottl { 0, 0 } 1082195534Sscottl}; 1083195534Sscottlstatic driver_t ahcich_driver = { 1084195534Sscottl "ahcich", 1085195534Sscottl ahcich_methods, 1086195534Sscottl sizeof(struct ahci_channel) 1087195534Sscottl}; 1088199322SmavDRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1089195534Sscottl 1090195534Sscottlstruct ahci_dc_cb_args { 1091195534Sscottl bus_addr_t maddr; 1092195534Sscottl int error; 1093195534Sscottl}; 1094195534Sscottl 1095195534Sscottlstatic void 1096195534Sscottlahci_dmainit(device_t dev) 1097195534Sscottl{ 1098195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1099195534Sscottl struct ahci_dc_cb_args dcba; 1100203123Smav size_t rfsize; 1101195534Sscottl 1102195534Sscottl if (ch->caps & AHCI_CAP_64BIT) 1103195534Sscottl ch->dma.max_address = BUS_SPACE_MAXADDR; 1104195534Sscottl else 1105195534Sscottl ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1106195534Sscottl /* Command area. */ 1107195534Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1108195534Sscottl ch->dma.max_address, BUS_SPACE_MAXADDR, 1109195534Sscottl NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1110195534Sscottl 0, NULL, NULL, &ch->dma.work_tag)) 1111195534Sscottl goto error; 1112195534Sscottl if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1113195534Sscottl &ch->dma.work_map)) 1114195534Sscottl goto error; 1115195534Sscottl if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1116195534Sscottl AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1117195534Sscottl bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1118195534Sscottl goto error; 1119195534Sscottl } 1120195534Sscottl ch->dma.work_bus = dcba.maddr; 1121195534Sscottl /* FIS receive area. */ 1122203123Smav if (ch->chcaps & AHCI_P_CMD_FBSCP) 1123203123Smav rfsize = 4096; 1124203123Smav else 1125203123Smav rfsize = 256; 1126203123Smav if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1127195534Sscottl ch->dma.max_address, BUS_SPACE_MAXADDR, 1128203123Smav NULL, NULL, rfsize, 1, rfsize, 1129195534Sscottl 0, NULL, NULL, &ch->dma.rfis_tag)) 1130195534Sscottl goto error; 1131195534Sscottl if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1132195534Sscottl &ch->dma.rfis_map)) 1133195534Sscottl goto error; 1134195534Sscottl if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1135203123Smav rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1136195534Sscottl bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1137195534Sscottl goto error; 1138195534Sscottl } 1139195534Sscottl ch->dma.rfis_bus = dcba.maddr; 1140195534Sscottl /* Data area. */ 1141195534Sscottl if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1142195534Sscottl ch->dma.max_address, BUS_SPACE_MAXADDR, 1143195534Sscottl NULL, NULL, 1144195534Sscottl AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1145195534Sscottl AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1146195534Sscottl 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1147195534Sscottl goto error; 1148195534Sscottl } 1149195534Sscottl return; 1150195534Sscottl 1151195534Sscottlerror: 1152195534Sscottl device_printf(dev, "WARNING - DMA initialization failed\n"); 1153195534Sscottl ahci_dmafini(dev); 1154195534Sscottl} 1155195534Sscottl 1156195534Sscottlstatic void 1157195534Sscottlahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1158195534Sscottl{ 1159195534Sscottl struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1160195534Sscottl 1161195534Sscottl if (!(dcba->error = error)) 1162195534Sscottl dcba->maddr = segs[0].ds_addr; 1163195534Sscottl} 1164195534Sscottl 1165195534Sscottlstatic void 1166195534Sscottlahci_dmafini(device_t dev) 1167195534Sscottl{ 1168195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1169195534Sscottl 1170195534Sscottl if (ch->dma.data_tag) { 1171195534Sscottl bus_dma_tag_destroy(ch->dma.data_tag); 1172195534Sscottl ch->dma.data_tag = NULL; 1173195534Sscottl } 1174195534Sscottl if (ch->dma.rfis_bus) { 1175195534Sscottl bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1176195534Sscottl bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1177195534Sscottl ch->dma.rfis_bus = 0; 1178195534Sscottl ch->dma.rfis_map = NULL; 1179195534Sscottl ch->dma.rfis = NULL; 1180195534Sscottl } 1181195534Sscottl if (ch->dma.work_bus) { 1182195534Sscottl bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1183195534Sscottl bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1184195534Sscottl ch->dma.work_bus = 0; 1185195534Sscottl ch->dma.work_map = NULL; 1186195534Sscottl ch->dma.work = NULL; 1187195534Sscottl } 1188195534Sscottl if (ch->dma.work_tag) { 1189195534Sscottl bus_dma_tag_destroy(ch->dma.work_tag); 1190195534Sscottl ch->dma.work_tag = NULL; 1191195534Sscottl } 1192195534Sscottl} 1193195534Sscottl 1194195534Sscottlstatic void 1195195534Sscottlahci_slotsalloc(device_t dev) 1196195534Sscottl{ 1197195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1198195534Sscottl int i; 1199195534Sscottl 1200195534Sscottl /* Alloc and setup command/dma slots */ 1201195534Sscottl bzero(ch->slot, sizeof(ch->slot)); 1202195534Sscottl for (i = 0; i < ch->numslots; i++) { 1203195534Sscottl struct ahci_slot *slot = &ch->slot[i]; 1204195534Sscottl 1205195534Sscottl slot->dev = dev; 1206195534Sscottl slot->slot = i; 1207195534Sscottl slot->state = AHCI_SLOT_EMPTY; 1208195534Sscottl slot->ccb = NULL; 1209195534Sscottl callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1210195534Sscottl 1211195534Sscottl if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1212195534Sscottl device_printf(ch->dev, "FAILURE - create data_map\n"); 1213195534Sscottl } 1214195534Sscottl} 1215195534Sscottl 1216195534Sscottlstatic void 1217195534Sscottlahci_slotsfree(device_t dev) 1218195534Sscottl{ 1219195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1220195534Sscottl int i; 1221195534Sscottl 1222195534Sscottl /* Free all dma slots */ 1223195534Sscottl for (i = 0; i < ch->numslots; i++) { 1224195534Sscottl struct ahci_slot *slot = &ch->slot[i]; 1225195534Sscottl 1226196656Smav callout_drain(&slot->timeout); 1227195534Sscottl if (slot->dma.data_map) { 1228195534Sscottl bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1229195534Sscottl slot->dma.data_map = NULL; 1230195534Sscottl } 1231195534Sscottl } 1232195534Sscottl} 1233195534Sscottl 1234195534Sscottlstatic void 1235198319Smavahci_phy_check_events(device_t dev, u_int32_t serr) 1236195534Sscottl{ 1237195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1238195534Sscottl 1239198319Smav if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1240195534Sscottl u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1241203108Smav union ccb *ccb; 1242203108Smav 1243203165Smav if (bootverbose) { 1244203165Smav if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1245203165Smav ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1246203165Smav ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1247195534Sscottl device_printf(dev, "CONNECT requested\n"); 1248203165Smav } else 1249195534Sscottl device_printf(dev, "DISCONNECT requested\n"); 1250195534Sscottl } 1251203165Smav ahci_reset(dev); 1252203108Smav if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1253203108Smav return; 1254203108Smav if (xpt_create_path(&ccb->ccb_h.path, NULL, 1255203108Smav cam_sim_path(ch->sim), 1256203108Smav CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1257203108Smav xpt_free_ccb(ccb); 1258203108Smav return; 1259203108Smav } 1260203108Smav xpt_rescan(ccb); 1261195534Sscottl } 1262195534Sscottl} 1263195534Sscottl 1264195534Sscottlstatic void 1265196907Smavahci_notify_events(device_t dev, u_int32_t status) 1266196656Smav{ 1267196656Smav struct ahci_channel *ch = device_get_softc(dev); 1268196656Smav struct cam_path *dpath; 1269196656Smav int i; 1270196656Smav 1271200196Smav if (ch->caps & AHCI_CAP_SSNTF) 1272200196Smav ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1273196656Smav if (bootverbose) 1274196656Smav device_printf(dev, "SNTF 0x%04x\n", status); 1275196656Smav for (i = 0; i < 16; i++) { 1276196656Smav if ((status & (1 << i)) == 0) 1277196656Smav continue; 1278196656Smav if (xpt_create_path(&dpath, NULL, 1279196656Smav xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1280196656Smav xpt_async(AC_SCSI_AEN, dpath, NULL); 1281196656Smav xpt_free_path(dpath); 1282196656Smav } 1283196656Smav } 1284196656Smav} 1285196656Smav 1286196656Smavstatic void 1287195534Sscottlahci_ch_intr_locked(void *data) 1288195534Sscottl{ 1289195534Sscottl device_t dev = (device_t)data; 1290195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1291195534Sscottl 1292195534Sscottl mtx_lock(&ch->mtx); 1293195534Sscottl ahci_ch_intr(data); 1294195534Sscottl mtx_unlock(&ch->mtx); 1295195534Sscottl} 1296195534Sscottl 1297195534Sscottlstatic void 1298196656Smavahci_ch_pm(void *arg) 1299196656Smav{ 1300196656Smav device_t dev = (device_t)arg; 1301196656Smav struct ahci_channel *ch = device_get_softc(dev); 1302196656Smav uint32_t work; 1303196656Smav 1304196656Smav if (ch->numrslots != 0) 1305196656Smav return; 1306196656Smav work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1307196656Smav if (ch->pm_level == 4) 1308196656Smav work |= AHCI_P_CMD_PARTIAL; 1309196656Smav else 1310196656Smav work |= AHCI_P_CMD_SLUMBER; 1311196656Smav ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1312196656Smav} 1313196656Smav 1314196656Smavstatic void 1315195534Sscottlahci_ch_intr(void *data) 1316195534Sscottl{ 1317195534Sscottl device_t dev = (device_t)data; 1318195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1319198319Smav uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1320195534Sscottl enum ahci_err_type et; 1321203123Smav int i, ccs, port; 1322195534Sscottl 1323195534Sscottl /* Read and clear interrupt statuses. */ 1324195534Sscottl istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1325196656Smav if (istatus == 0) 1326196656Smav return; 1327195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1328195534Sscottl /* Read command statuses. */ 1329196907Smav sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1330195534Sscottl cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1331200196Smav if (istatus & AHCI_P_IX_SDB) { 1332200196Smav if (ch->caps & AHCI_CAP_SSNTF) 1333200196Smav sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1334203123Smav else if (ch->fbs_enabled) { 1335200196Smav u_int8_t *fis = ch->dma.rfis + 0x58; 1336200196Smav 1337203123Smav for (i = 0; i < 16; i++) { 1338203123Smav if (fis[1] & 0x80) { 1339203123Smav fis[1] &= 0x7f; 1340203123Smav sntf |= 1 << i; 1341203123Smav } 1342203123Smav fis += 256; 1343203123Smav } 1344203123Smav } else { 1345203123Smav u_int8_t *fis = ch->dma.rfis + 0x58; 1346203123Smav 1347200196Smav if (fis[1] & 0x80) 1348200196Smav sntf = (1 << (fis[1] & 0x0f)); 1349200196Smav } 1350200196Smav } 1351195534Sscottl /* Process PHY events */ 1352198319Smav if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1353198319Smav AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1354198319Smav serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1355198319Smav if (serr) { 1356198319Smav ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1357198319Smav ahci_phy_check_events(dev, serr); 1358198319Smav } 1359198319Smav } 1360195534Sscottl /* Process command errors */ 1361198319Smav if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1362198319Smav AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1363195534Sscottl ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1364195534Sscottl >> AHCI_P_CMD_CCS_SHIFT; 1365203123Smav//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1366203123Smav// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1367203123Smav// serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1368203123Smav port = -1; 1369203123Smav if (ch->fbs_enabled) { 1370203123Smav uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1371203123Smav if (fbs & AHCI_P_FBS_SDE) { 1372203123Smav port = (fbs & AHCI_P_FBS_DWE) 1373203123Smav >> AHCI_P_FBS_DWE_SHIFT; 1374203123Smav } else { 1375203123Smav for (i = 0; i < 16; i++) { 1376203123Smav if (ch->numrslotspd[i] == 0) 1377203123Smav continue; 1378203123Smav if (port == -1) 1379203123Smav port = i; 1380203123Smav else if (port != i) { 1381203123Smav port = -2; 1382203123Smav break; 1383203123Smav } 1384203123Smav } 1385203123Smav } 1386203123Smav } 1387196656Smav err = ch->rslots & (cstatus | sstatus); 1388195534Sscottl } else { 1389195534Sscottl ccs = 0; 1390195534Sscottl err = 0; 1391203123Smav port = -1; 1392195534Sscottl } 1393195534Sscottl /* Complete all successfull commands. */ 1394196656Smav ok = ch->rslots & ~(cstatus | sstatus); 1395195534Sscottl for (i = 0; i < ch->numslots; i++) { 1396195534Sscottl if ((ok >> i) & 1) 1397195534Sscottl ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1398195534Sscottl } 1399195534Sscottl /* On error, complete the rest of commands with error statuses. */ 1400195534Sscottl if (err) { 1401195534Sscottl if (ch->frozen) { 1402195534Sscottl union ccb *fccb = ch->frozen; 1403195534Sscottl ch->frozen = NULL; 1404195534Sscottl fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1405198319Smav if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1406198319Smav xpt_freeze_devq(fccb->ccb_h.path, 1); 1407198319Smav fccb->ccb_h.status |= CAM_DEV_QFRZN; 1408198319Smav } 1409195534Sscottl xpt_done(fccb); 1410195534Sscottl } 1411195534Sscottl for (i = 0; i < ch->numslots; i++) { 1412195534Sscottl /* XXX: reqests in loading state. */ 1413195534Sscottl if (((err >> i) & 1) == 0) 1414195534Sscottl continue; 1415203123Smav if (port >= 0 && 1416203123Smav ch->slot[i].ccb->ccb_h.target_id != port) 1417203123Smav continue; 1418198390Smav if (istatus & AHCI_P_IX_TFE) { 1419203123Smav if (port != -2) { 1420195534Sscottl /* Task File Error */ 1421203123Smav if (ch->numtslotspd[ 1422203123Smav ch->slot[i].ccb->ccb_h.target_id] == 0) { 1423195534Sscottl /* Untagged operation. */ 1424195534Sscottl if (i == ccs) 1425195534Sscottl et = AHCI_ERR_TFE; 1426195534Sscottl else 1427195534Sscottl et = AHCI_ERR_INNOCENT; 1428195534Sscottl } else { 1429195534Sscottl /* Tagged operation. */ 1430195534Sscottl et = AHCI_ERR_NCQ; 1431195534Sscottl } 1432203123Smav } else { 1433203123Smav et = AHCI_ERR_TFE; 1434203123Smav ch->fatalerr = 1; 1435203123Smav } 1436198390Smav } else if (istatus & AHCI_P_IX_IF) { 1437203123Smav if (ch->numtslots == 0 && i != ccs && port != -2) 1438198390Smav et = AHCI_ERR_INNOCENT; 1439198390Smav else 1440198390Smav et = AHCI_ERR_SATA; 1441195534Sscottl } else 1442195534Sscottl et = AHCI_ERR_INVALID; 1443195534Sscottl ahci_end_transaction(&ch->slot[i], et); 1444195534Sscottl } 1445203123Smav /* 1446203123Smav * We can't reinit port if there are some other 1447203123Smav * commands active, use resume to complete them. 1448203123Smav */ 1449203123Smav if (ch->rslots != 0) 1450203123Smav ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1451195534Sscottl } 1452196656Smav /* Process NOTIFY events */ 1453196907Smav if (sntf) 1454196907Smav ahci_notify_events(dev, sntf); 1455195534Sscottl} 1456195534Sscottl 1457195534Sscottl/* Must be called with channel locked. */ 1458195534Sscottlstatic int 1459195534Sscottlahci_check_collision(device_t dev, union ccb *ccb) 1460195534Sscottl{ 1461195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1462203123Smav int t = ccb->ccb_h.target_id; 1463195534Sscottl 1464195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1465195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1466199747Smav /* Tagged command while we have no supported tag free. */ 1467199747Smav if (((~ch->oslots) & (0xffffffff >> (32 - 1468203123Smav ch->curr[t].tags))) == 0) 1469199747Smav return (1); 1470203123Smav /* If we have FBS */ 1471203123Smav if (ch->fbs_enabled) { 1472203123Smav /* Tagged command while untagged are active. */ 1473203123Smav if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1474203123Smav return (1); 1475203123Smav } else { 1476203123Smav /* Tagged command while untagged are active. */ 1477203123Smav if (ch->numrslots != 0 && ch->numtslots == 0) 1478203123Smav return (1); 1479203123Smav /* Tagged command while tagged to other target is active. */ 1480203123Smav if (ch->numtslots != 0 && 1481203123Smav ch->taggedtarget != ccb->ccb_h.target_id) 1482203123Smav return (1); 1483203123Smav } 1484195534Sscottl } else { 1485203123Smav /* If we have FBS */ 1486203123Smav if (ch->fbs_enabled) { 1487203123Smav /* Untagged command while tagged are active. */ 1488203123Smav if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1489203123Smav return (1); 1490203123Smav } else { 1491203123Smav /* Untagged command while tagged are active. */ 1492203123Smav if (ch->numrslots != 0 && ch->numtslots != 0) 1493203123Smav return (1); 1494203123Smav } 1495195534Sscottl } 1496195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1497195534Sscottl (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1498195534Sscottl /* Atomic command while anything active. */ 1499195534Sscottl if (ch->numrslots != 0) 1500195534Sscottl return (1); 1501195534Sscottl } 1502195534Sscottl /* We have some atomic command running. */ 1503195534Sscottl if (ch->aslots != 0) 1504195534Sscottl return (1); 1505195534Sscottl return (0); 1506195534Sscottl} 1507195534Sscottl 1508195534Sscottl/* Must be called with channel locked. */ 1509195534Sscottlstatic void 1510195534Sscottlahci_begin_transaction(device_t dev, union ccb *ccb) 1511195534Sscottl{ 1512195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1513195534Sscottl struct ahci_slot *slot; 1514199747Smav int tag, tags; 1515195534Sscottl 1516195534Sscottl /* Choose empty slot. */ 1517199747Smav tags = ch->numslots; 1518199747Smav if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1519199747Smav (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1520199747Smav tags = ch->curr[ccb->ccb_h.target_id].tags; 1521195534Sscottl tag = ch->lastslot; 1522199747Smav while (1) { 1523199747Smav if (tag >= tags) 1524195534Sscottl tag = 0; 1525199747Smav if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1526199747Smav break; 1527199747Smav tag++; 1528199747Smav }; 1529195534Sscottl ch->lastslot = tag; 1530195534Sscottl /* Occupy chosen slot. */ 1531195534Sscottl slot = &ch->slot[tag]; 1532195534Sscottl slot->ccb = ccb; 1533196656Smav /* Stop PM timer. */ 1534196656Smav if (ch->numrslots == 0 && ch->pm_level > 3) 1535196656Smav callout_stop(&ch->pm_timer); 1536195534Sscottl /* Update channel stats. */ 1537199747Smav ch->oslots |= (1 << slot->slot); 1538195534Sscottl ch->numrslots++; 1539203123Smav ch->numrslotspd[ccb->ccb_h.target_id]++; 1540195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1541195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1542195534Sscottl ch->numtslots++; 1543203123Smav ch->numtslotspd[ccb->ccb_h.target_id]++; 1544195534Sscottl ch->taggedtarget = ccb->ccb_h.target_id; 1545195534Sscottl } 1546195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1547195534Sscottl (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1548195534Sscottl ch->aslots |= (1 << slot->slot); 1549195534Sscottl slot->dma.nsegs = 0; 1550195534Sscottl /* If request moves data, setup and load SG list */ 1551195534Sscottl if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1552195534Sscottl void *buf; 1553195534Sscottl bus_size_t size; 1554195534Sscottl 1555195534Sscottl slot->state = AHCI_SLOT_LOADING; 1556195534Sscottl if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1557195534Sscottl buf = ccb->ataio.data_ptr; 1558195534Sscottl size = ccb->ataio.dxfer_len; 1559195534Sscottl } else { 1560195534Sscottl buf = ccb->csio.data_ptr; 1561195534Sscottl size = ccb->csio.dxfer_len; 1562195534Sscottl } 1563195534Sscottl bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1564195534Sscottl buf, size, ahci_dmasetprd, slot, 0); 1565195534Sscottl } else 1566195534Sscottl ahci_execute_transaction(slot); 1567195534Sscottl} 1568195534Sscottl 1569195534Sscottl/* Locked by busdma engine. */ 1570195534Sscottlstatic void 1571195534Sscottlahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1572195534Sscottl{ 1573195534Sscottl struct ahci_slot *slot = arg; 1574195534Sscottl struct ahci_channel *ch = device_get_softc(slot->dev); 1575195534Sscottl struct ahci_cmd_tab *ctp; 1576195534Sscottl struct ahci_dma_prd *prd; 1577195534Sscottl int i; 1578195534Sscottl 1579195534Sscottl if (error) { 1580195534Sscottl device_printf(slot->dev, "DMA load error\n"); 1581195534Sscottl ahci_end_transaction(slot, AHCI_ERR_INVALID); 1582195534Sscottl return; 1583195534Sscottl } 1584195534Sscottl KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1585195534Sscottl /* Get a piece of the workspace for this request */ 1586195534Sscottl ctp = (struct ahci_cmd_tab *) 1587195534Sscottl (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1588195534Sscottl /* Fill S/G table */ 1589195534Sscottl prd = &ctp->prd_tab[0]; 1590195534Sscottl for (i = 0; i < nsegs; i++) { 1591195534Sscottl prd[i].dba = htole64(segs[i].ds_addr); 1592195534Sscottl prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1593195534Sscottl } 1594195534Sscottl slot->dma.nsegs = nsegs; 1595195534Sscottl bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1596195534Sscottl ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1597195534Sscottl BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1598195534Sscottl ahci_execute_transaction(slot); 1599195534Sscottl} 1600195534Sscottl 1601195534Sscottl/* Must be called with channel locked. */ 1602195534Sscottlstatic void 1603195534Sscottlahci_execute_transaction(struct ahci_slot *slot) 1604195534Sscottl{ 1605195534Sscottl device_t dev = slot->dev; 1606195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1607195534Sscottl struct ahci_cmd_tab *ctp; 1608195534Sscottl struct ahci_cmd_list *clp; 1609195534Sscottl union ccb *ccb = slot->ccb; 1610195534Sscottl int port = ccb->ccb_h.target_id & 0x0f; 1611203123Smav int fis_size, i; 1612203123Smav uint8_t *fis = ch->dma.rfis + 0x40; 1613203123Smav uint8_t val; 1614195534Sscottl 1615195534Sscottl /* Get a piece of the workspace for this request */ 1616195534Sscottl ctp = (struct ahci_cmd_tab *) 1617195534Sscottl (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1618195534Sscottl /* Setup the FIS for this request */ 1619199821Smav if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1620195534Sscottl device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1621195534Sscottl ahci_end_transaction(slot, AHCI_ERR_INVALID); 1622195534Sscottl return; 1623195534Sscottl } 1624195534Sscottl /* Setup the command list entry */ 1625195534Sscottl clp = (struct ahci_cmd_list *) 1626195534Sscottl (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1627195534Sscottl clp->prd_length = slot->dma.nsegs; 1628195534Sscottl clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1629195534Sscottl (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1630195534Sscottl (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1631195534Sscottl (fis_size / sizeof(u_int32_t)) | 1632195534Sscottl (port << 12); 1633195534Sscottl /* Special handling for Soft Reset command. */ 1634195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1635203123Smav (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1636203123Smav if (ccb->ataio.cmd.control & ATA_A_RESET) { 1637203123Smav /* Kick controller into sane state */ 1638203123Smav ahci_stop(dev); 1639203123Smav ahci_clo(dev); 1640203123Smav ahci_start(dev, 0); 1641203123Smav clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1642203123Smav } else { 1643203123Smav /* Prepare FIS receive area for check. */ 1644203123Smav for (i = 0; i < 20; i++) 1645203123Smav fis[i] = 0xff; 1646203123Smav } 1647195534Sscottl } 1648195534Sscottl clp->bytecount = 0; 1649195534Sscottl clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1650195534Sscottl (AHCI_CT_SIZE * slot->slot)); 1651195534Sscottl bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1652195534Sscottl BUS_DMASYNC_PREWRITE); 1653195534Sscottl bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1654195534Sscottl BUS_DMASYNC_PREREAD); 1655195534Sscottl /* Set ACTIVE bit for NCQ commands. */ 1656195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1657195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1658195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1659195534Sscottl } 1660203123Smav /* If FBS is enabled, set PMP port. */ 1661203123Smav if (ch->fbs_enabled) { 1662203123Smav ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1663203123Smav (port << AHCI_P_FBS_DEV_SHIFT)); 1664203123Smav } 1665195534Sscottl /* Issue command to the controller. */ 1666195534Sscottl slot->state = AHCI_SLOT_RUNNING; 1667195534Sscottl ch->rslots |= (1 << slot->slot); 1668195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1669195534Sscottl /* Device reset commands doesn't interrupt. Poll them. */ 1670195534Sscottl if (ccb->ccb_h.func_code == XPT_ATA_IO && 1671195534Sscottl (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1672195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1673195534Sscottl int count, timeout = ccb->ccb_h.timeout; 1674195534Sscottl enum ahci_err_type et = AHCI_ERR_NONE; 1675195534Sscottl 1676195534Sscottl for (count = 0; count < timeout; count++) { 1677195534Sscottl DELAY(1000); 1678195534Sscottl if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1679195534Sscottl break; 1680195534Sscottl if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1681195534Sscottl device_printf(ch->dev, 1682195534Sscottl "Poll error on slot %d, TFD: %04x\n", 1683195534Sscottl slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1684195534Sscottl et = AHCI_ERR_TFE; 1685195534Sscottl break; 1686195534Sscottl } 1687198851Smav /* Workaround for ATI SB600/SB700 chipsets. */ 1688198851Smav if (ccb->ccb_h.target_id == 15 && 1689198851Smav pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1690198851Smav (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1691198851Smav et = AHCI_ERR_TIMEOUT; 1692198851Smav break; 1693198851Smav } 1694195534Sscottl } 1695195534Sscottl if (timeout && (count >= timeout)) { 1696195534Sscottl device_printf(ch->dev, 1697195534Sscottl "Poll timeout on slot %d\n", slot->slot); 1698203108Smav device_printf(dev, "is %08x cs %08x ss %08x " 1699203108Smav "rs %08x tfd %02x serr %08x\n", 1700203108Smav ATA_INL(ch->r_mem, AHCI_P_IS), 1701203108Smav ATA_INL(ch->r_mem, AHCI_P_CI), 1702203108Smav ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1703203108Smav ATA_INL(ch->r_mem, AHCI_P_TFD), 1704203108Smav ATA_INL(ch->r_mem, AHCI_P_SERR)); 1705195534Sscottl et = AHCI_ERR_TIMEOUT; 1706195534Sscottl } 1707203123Smav /* Marvell controllers do not wait for readyness. */ 1708203123Smav if ((ch->quirks & AHCI_Q_NOBSYRES) && 1709203123Smav (ccb->ccb_h.func_code == XPT_ATA_IO) && 1710203123Smav (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1711203123Smav (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1712203123Smav while ((val = fis[2]) & (ATA_S_BUSY | ATA_S_DRQ)) { 1713203123Smav DELAY(1000); 1714203123Smav if (count++ >= timeout) { 1715203123Smav device_printf(dev, "device is not " 1716203123Smav "ready after soft-reset: " 1717203123Smav "tfd = %08x\n", val); 1718203123Smav et = AHCI_ERR_TIMEOUT; 1719203123Smav break; 1720203123Smav } 1721203123Smav } 1722203123Smav } 1723203123Smav ahci_end_transaction(slot, et); 1724203123Smav /* Kick controller into sane state and enable FBS. */ 1725203123Smav if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1726203123Smav (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1727203123Smav (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1728195534Sscottl ahci_stop(ch->dev); 1729203123Smav ahci_start(ch->dev, 1); 1730195534Sscottl } 1731195534Sscottl return; 1732195534Sscottl } 1733195534Sscottl /* Start command execution timeout */ 1734198319Smav callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1735195534Sscottl (timeout_t*)ahci_timeout, slot); 1736195534Sscottl return; 1737195534Sscottl} 1738195534Sscottl 1739203873Smav/* Must be called with channel locked. */ 1740203873Smavstatic void 1741203873Smavahci_process_timeout(device_t dev) 1742203873Smav{ 1743203873Smav struct ahci_channel *ch = device_get_softc(dev); 1744203873Smav int i; 1745203873Smav 1746203873Smav mtx_assert(&ch->mtx, MA_OWNED); 1747203873Smav /* Handle the rest of commands. */ 1748203873Smav for (i = 0; i < ch->numslots; i++) { 1749203873Smav /* Do we have a running request on slot? */ 1750203873Smav if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1751203873Smav continue; 1752203873Smav ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1753203873Smav } 1754203873Smav} 1755203873Smav 1756203873Smav/* Must be called with channel locked. */ 1757203873Smavstatic void 1758203873Smavahci_rearm_timeout(device_t dev) 1759203873Smav{ 1760203873Smav struct ahci_channel *ch = device_get_softc(dev); 1761203873Smav int i; 1762203873Smav 1763203873Smav mtx_assert(&ch->mtx, MA_OWNED); 1764203873Smav for (i = 0; i < ch->numslots; i++) { 1765203873Smav struct ahci_slot *slot = &ch->slot[i]; 1766203873Smav 1767203873Smav /* Do we have a running request on slot? */ 1768203873Smav if (slot->state < AHCI_SLOT_RUNNING) 1769203873Smav continue; 1770203873Smav if ((ch->toslots & (1 << i)) == 0) 1771203873Smav continue; 1772203873Smav callout_reset(&slot->timeout, 1773203873Smav (int)slot->ccb->ccb_h.timeout * hz / 2000, 1774203873Smav (timeout_t*)ahci_timeout, slot); 1775203873Smav } 1776203873Smav} 1777203873Smav 1778195534Sscottl/* Locked by callout mechanism. */ 1779195534Sscottlstatic void 1780195534Sscottlahci_timeout(struct ahci_slot *slot) 1781195534Sscottl{ 1782195534Sscottl device_t dev = slot->dev; 1783195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1784198319Smav uint32_t sstatus; 1785198319Smav int ccs; 1786195534Sscottl int i; 1787195534Sscottl 1788196656Smav /* Check for stale timeout. */ 1789198319Smav if (slot->state < AHCI_SLOT_RUNNING) 1790196656Smav return; 1791196656Smav 1792198319Smav /* Check if slot was not being executed last time we checked. */ 1793198319Smav if (slot->state < AHCI_SLOT_EXECUTING) { 1794198319Smav /* Check if slot started executing. */ 1795198319Smav sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1796198319Smav ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1797198319Smav >> AHCI_P_CMD_CCS_SHIFT; 1798203123Smav if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1799203123Smav ch->fbs_enabled) 1800198319Smav slot->state = AHCI_SLOT_EXECUTING; 1801198319Smav 1802198319Smav callout_reset(&slot->timeout, 1803198319Smav (int)slot->ccb->ccb_h.timeout * hz / 2000, 1804198319Smav (timeout_t*)ahci_timeout, slot); 1805198319Smav return; 1806198319Smav } 1807198319Smav 1808195534Sscottl device_printf(dev, "Timeout on slot %d\n", slot->slot); 1809198319Smav device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1810198319Smav ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1811198319Smav ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1812198319Smav ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1813195534Sscottl 1814197838Smav /* Handle frozen command. */ 1815195534Sscottl if (ch->frozen) { 1816195534Sscottl union ccb *fccb = ch->frozen; 1817195534Sscottl ch->frozen = NULL; 1818195534Sscottl fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1819198319Smav if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1820198319Smav xpt_freeze_devq(fccb->ccb_h.path, 1); 1821198319Smav fccb->ccb_h.status |= CAM_DEV_QFRZN; 1822198319Smav } 1823195534Sscottl xpt_done(fccb); 1824195534Sscottl } 1825203873Smav if (!ch->fbs_enabled) { 1826203873Smav /* Without FBS we know real timeout source. */ 1827203873Smav ch->fatalerr = 1; 1828203873Smav /* Handle command with timeout. */ 1829203873Smav ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1830203873Smav /* Handle the rest of commands. */ 1831203873Smav for (i = 0; i < ch->numslots; i++) { 1832203873Smav /* Do we have a running request on slot? */ 1833203873Smav if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1834203873Smav continue; 1835203873Smav ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1836203873Smav } 1837203873Smav } else { 1838203873Smav /* With FBS we wait for other commands timeout and pray. */ 1839203873Smav if (ch->toslots == 0) 1840203873Smav xpt_freeze_simq(ch->sim, 1); 1841203873Smav ch->toslots |= (1 << slot->slot); 1842203873Smav if ((ch->rslots & ~ch->toslots) == 0) 1843203873Smav ahci_process_timeout(dev); 1844203873Smav else 1845203873Smav device_printf(dev, " ... waiting for slots %08x\n", 1846203873Smav ch->rslots & ~ch->toslots); 1847195534Sscottl } 1848195534Sscottl} 1849195534Sscottl 1850195534Sscottl/* Must be called with channel locked. */ 1851195534Sscottlstatic void 1852195534Sscottlahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1853195534Sscottl{ 1854195534Sscottl device_t dev = slot->dev; 1855195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 1856195534Sscottl union ccb *ccb = slot->ccb; 1857195534Sscottl 1858195534Sscottl bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1859195534Sscottl BUS_DMASYNC_POSTWRITE); 1860195534Sscottl /* Read result registers to the result struct 1861195534Sscottl * May be incorrect if several commands finished same time, 1862195534Sscottl * so read only when sure or have to. 1863195534Sscottl */ 1864195534Sscottl if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1865195534Sscottl struct ata_res *res = &ccb->ataio.res; 1866195534Sscottl 1867195534Sscottl if ((et == AHCI_ERR_TFE) || 1868195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1869195534Sscottl u_int8_t *fis = ch->dma.rfis + 0x40; 1870195534Sscottl 1871195534Sscottl bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1872195534Sscottl BUS_DMASYNC_POSTREAD); 1873203123Smav if (ch->fbs_enabled) { 1874203123Smav fis += ccb->ccb_h.target_id * 256; 1875203123Smav res->status = fis[2]; 1876203123Smav res->error = fis[3]; 1877203123Smav } else { 1878203123Smav uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1879203123Smav 1880203123Smav res->status = tfd; 1881203123Smav res->error = tfd >> 8; 1882203123Smav } 1883195534Sscottl res->lba_low = fis[4]; 1884195534Sscottl res->lba_mid = fis[5]; 1885195534Sscottl res->lba_high = fis[6]; 1886195534Sscottl res->device = fis[7]; 1887195534Sscottl res->lba_low_exp = fis[8]; 1888195534Sscottl res->lba_mid_exp = fis[9]; 1889195534Sscottl res->lba_high_exp = fis[10]; 1890195534Sscottl res->sector_count = fis[12]; 1891195534Sscottl res->sector_count_exp = fis[13]; 1892195534Sscottl } else 1893195534Sscottl bzero(res, sizeof(*res)); 1894195534Sscottl } 1895195534Sscottl if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1896195534Sscottl bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1897195534Sscottl (ccb->ccb_h.flags & CAM_DIR_IN) ? 1898195534Sscottl BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1899195534Sscottl bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1900195534Sscottl } 1901203123Smav if (et != AHCI_ERR_NONE) 1902203123Smav ch->eslots |= (1 << slot->slot); 1903198319Smav /* In case of error, freeze device for proper recovery. */ 1904198319Smav if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1905198319Smav !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1906198319Smav xpt_freeze_devq(ccb->ccb_h.path, 1); 1907198319Smav ccb->ccb_h.status |= CAM_DEV_QFRZN; 1908198319Smav } 1909195534Sscottl /* Set proper result status. */ 1910195534Sscottl ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1911195534Sscottl switch (et) { 1912195534Sscottl case AHCI_ERR_NONE: 1913195534Sscottl ccb->ccb_h.status |= CAM_REQ_CMP; 1914195534Sscottl if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1915195534Sscottl ccb->csio.scsi_status = SCSI_STATUS_OK; 1916195534Sscottl break; 1917195534Sscottl case AHCI_ERR_INVALID: 1918198851Smav ch->fatalerr = 1; 1919195534Sscottl ccb->ccb_h.status |= CAM_REQ_INVALID; 1920195534Sscottl break; 1921195534Sscottl case AHCI_ERR_INNOCENT: 1922195534Sscottl ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1923195534Sscottl break; 1924195534Sscottl case AHCI_ERR_TFE: 1925198319Smav case AHCI_ERR_NCQ: 1926195534Sscottl if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1927195534Sscottl ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1928195534Sscottl ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1929195534Sscottl } else { 1930195534Sscottl ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1931195534Sscottl } 1932195534Sscottl break; 1933195534Sscottl case AHCI_ERR_SATA: 1934198851Smav ch->fatalerr = 1; 1935198319Smav if (!ch->readlog) { 1936198319Smav xpt_freeze_simq(ch->sim, 1); 1937198319Smav ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1938198319Smav ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1939198319Smav } 1940198319Smav ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1941195534Sscottl break; 1942195534Sscottl case AHCI_ERR_TIMEOUT: 1943198319Smav if (!ch->readlog) { 1944198319Smav xpt_freeze_simq(ch->sim, 1); 1945198319Smav ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1946198319Smav ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1947198319Smav } 1948195534Sscottl ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1949195534Sscottl break; 1950195534Sscottl default: 1951198851Smav ch->fatalerr = 1; 1952195534Sscottl ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1953195534Sscottl } 1954195534Sscottl /* Free slot. */ 1955199747Smav ch->oslots &= ~(1 << slot->slot); 1956195534Sscottl ch->rslots &= ~(1 << slot->slot); 1957195534Sscottl ch->aslots &= ~(1 << slot->slot); 1958203873Smav if (et != AHCI_ERR_TIMEOUT) { 1959203873Smav if (ch->toslots == (1 << slot->slot)) 1960203873Smav xpt_release_simq(ch->sim, TRUE); 1961203873Smav ch->toslots &= ~(1 << slot->slot); 1962203873Smav } 1963195534Sscottl slot->state = AHCI_SLOT_EMPTY; 1964195534Sscottl slot->ccb = NULL; 1965195534Sscottl /* Update channel stats. */ 1966195534Sscottl ch->numrslots--; 1967203123Smav ch->numrslotspd[ccb->ccb_h.target_id]--; 1968195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1969195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1970195534Sscottl ch->numtslots--; 1971203123Smav ch->numtslotspd[ccb->ccb_h.target_id]--; 1972195534Sscottl } 1973195534Sscottl /* If it was first request of reset sequence and there is no error, 1974195534Sscottl * proceed to second request. */ 1975195534Sscottl if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1976195534Sscottl (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1977195534Sscottl (ccb->ataio.cmd.control & ATA_A_RESET) && 1978195534Sscottl et == AHCI_ERR_NONE) { 1979195534Sscottl ccb->ataio.cmd.control &= ~ATA_A_RESET; 1980195534Sscottl ahci_begin_transaction(dev, ccb); 1981195534Sscottl return; 1982195534Sscottl } 1983198851Smav /* If it was our READ LOG command - process it. */ 1984198851Smav if (ch->readlog) { 1985198851Smav ahci_process_read_log(dev, ccb); 1986195534Sscottl /* If it was NCQ command error, put result on hold. */ 1987198851Smav } else if (et == AHCI_ERR_NCQ) { 1988195534Sscottl ch->hold[slot->slot] = ccb; 1989203123Smav ch->numhslots++; 1990198851Smav } else 1991195534Sscottl xpt_done(ccb); 1992195534Sscottl /* Unfreeze frozen command. */ 1993199747Smav if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 1994195534Sscottl union ccb *fccb = ch->frozen; 1995195534Sscottl ch->frozen = NULL; 1996195534Sscottl ahci_begin_transaction(dev, fccb); 1997195534Sscottl xpt_release_simq(ch->sim, TRUE); 1998195534Sscottl } 1999198851Smav /* If we have no other active commands, ... */ 2000198851Smav if (ch->rslots == 0) { 2001198851Smav /* if there was fatal error - reset port. */ 2002203873Smav if (ch->toslots != 0 || ch->fatalerr) { 2003198851Smav ahci_reset(dev); 2004203123Smav } else { 2005203123Smav /* if we have slots in error, we can reinit port. */ 2006203123Smav if (ch->eslots != 0) { 2007203123Smav ahci_stop(dev); 2008203123Smav ahci_start(dev, 1); 2009203123Smav } 2010203123Smav /* if there commands on hold, we can do READ LOG. */ 2011203123Smav if (!ch->readlog && ch->numhslots) 2012203123Smav ahci_issue_read_log(dev); 2013198851Smav } 2014203873Smav /* If all the rest of commands are in timeout - give them chance. */ 2015203873Smav } else if ((ch->rslots & ~ch->toslots) == 0 && 2016203873Smav et != AHCI_ERR_TIMEOUT) 2017203873Smav ahci_rearm_timeout(dev); 2018196656Smav /* Start PM timer. */ 2019207499Smav if (ch->numrslots == 0 && ch->pm_level > 3 && 2020207499Smav (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2021196656Smav callout_schedule(&ch->pm_timer, 2022196656Smav (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2023196656Smav } 2024195534Sscottl} 2025195534Sscottl 2026195534Sscottlstatic void 2027195534Sscottlahci_issue_read_log(device_t dev) 2028195534Sscottl{ 2029195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2030195534Sscottl union ccb *ccb; 2031195534Sscottl struct ccb_ataio *ataio; 2032195534Sscottl int i; 2033195534Sscottl 2034195534Sscottl ch->readlog = 1; 2035195534Sscottl /* Find some holden command. */ 2036195534Sscottl for (i = 0; i < ch->numslots; i++) { 2037195534Sscottl if (ch->hold[i]) 2038195534Sscottl break; 2039195534Sscottl } 2040195534Sscottl ccb = xpt_alloc_ccb_nowait(); 2041195534Sscottl if (ccb == NULL) { 2042195534Sscottl device_printf(dev, "Unable allocate READ LOG command"); 2043195534Sscottl return; /* XXX */ 2044195534Sscottl } 2045195534Sscottl ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2046195534Sscottl ccb->ccb_h.func_code = XPT_ATA_IO; 2047195534Sscottl ccb->ccb_h.flags = CAM_DIR_IN; 2048195534Sscottl ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2049195534Sscottl ataio = &ccb->ataio; 2050195534Sscottl ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2051195534Sscottl if (ataio->data_ptr == NULL) { 2052208814Smav xpt_free_ccb(ccb); 2053195534Sscottl device_printf(dev, "Unable allocate memory for READ LOG command"); 2054195534Sscottl return; /* XXX */ 2055195534Sscottl } 2056195534Sscottl ataio->dxfer_len = 512; 2057195534Sscottl bzero(&ataio->cmd, sizeof(ataio->cmd)); 2058195534Sscottl ataio->cmd.flags = CAM_ATAIO_48BIT; 2059195534Sscottl ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2060195534Sscottl ataio->cmd.sector_count = 1; 2061195534Sscottl ataio->cmd.sector_count_exp = 0; 2062195534Sscottl ataio->cmd.lba_low = 0x10; 2063195534Sscottl ataio->cmd.lba_mid = 0; 2064195534Sscottl ataio->cmd.lba_mid_exp = 0; 2065198319Smav /* Freeze SIM while doing READ LOG EXT. */ 2066198319Smav xpt_freeze_simq(ch->sim, 1); 2067195534Sscottl ahci_begin_transaction(dev, ccb); 2068195534Sscottl} 2069195534Sscottl 2070195534Sscottlstatic void 2071195534Sscottlahci_process_read_log(device_t dev, union ccb *ccb) 2072195534Sscottl{ 2073195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2074195534Sscottl uint8_t *data; 2075195534Sscottl struct ata_res *res; 2076195534Sscottl int i; 2077195534Sscottl 2078195534Sscottl ch->readlog = 0; 2079195534Sscottl 2080195534Sscottl data = ccb->ataio.data_ptr; 2081195534Sscottl if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2082195534Sscottl (data[0] & 0x80) == 0) { 2083195534Sscottl for (i = 0; i < ch->numslots; i++) { 2084195534Sscottl if (!ch->hold[i]) 2085195534Sscottl continue; 2086195534Sscottl if ((data[0] & 0x1F) == i) { 2087195534Sscottl res = &ch->hold[i]->ataio.res; 2088195534Sscottl res->status = data[2]; 2089195534Sscottl res->error = data[3]; 2090195534Sscottl res->lba_low = data[4]; 2091195534Sscottl res->lba_mid = data[5]; 2092195534Sscottl res->lba_high = data[6]; 2093195534Sscottl res->device = data[7]; 2094195534Sscottl res->lba_low_exp = data[8]; 2095195534Sscottl res->lba_mid_exp = data[9]; 2096195534Sscottl res->lba_high_exp = data[10]; 2097195534Sscottl res->sector_count = data[12]; 2098195534Sscottl res->sector_count_exp = data[13]; 2099195534Sscottl } else { 2100195534Sscottl ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2101195534Sscottl ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2102195534Sscottl } 2103195534Sscottl xpt_done(ch->hold[i]); 2104195534Sscottl ch->hold[i] = NULL; 2105203123Smav ch->numhslots--; 2106195534Sscottl } 2107195534Sscottl } else { 2108195534Sscottl if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2109195534Sscottl device_printf(dev, "Error while READ LOG EXT\n"); 2110195534Sscottl else if ((data[0] & 0x80) == 0) { 2111195534Sscottl device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2112195534Sscottl } 2113195534Sscottl for (i = 0; i < ch->numslots; i++) { 2114195534Sscottl if (!ch->hold[i]) 2115195534Sscottl continue; 2116195534Sscottl xpt_done(ch->hold[i]); 2117195534Sscottl ch->hold[i] = NULL; 2118203123Smav ch->numhslots--; 2119195534Sscottl } 2120195534Sscottl } 2121195534Sscottl free(ccb->ataio.data_ptr, M_AHCI); 2122195534Sscottl xpt_free_ccb(ccb); 2123198319Smav xpt_release_simq(ch->sim, TRUE); 2124195534Sscottl} 2125195534Sscottl 2126195534Sscottlstatic void 2127203123Smavahci_start(device_t dev, int fbs) 2128195534Sscottl{ 2129195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2130195534Sscottl u_int32_t cmd; 2131195534Sscottl 2132195534Sscottl /* Clear SATA error register */ 2133195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2134195534Sscottl /* Clear any interrupts pending on this channel */ 2135195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2136203123Smav /* Configure FIS-based switching if supported. */ 2137203123Smav if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2138203123Smav ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2139203123Smav ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2140203123Smav ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2141203123Smav } 2142195534Sscottl /* Start operations on this channel */ 2143195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2144207430Smav cmd &= ~AHCI_P_CMD_PMA; 2145195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2146195534Sscottl (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2147195534Sscottl} 2148195534Sscottl 2149195534Sscottlstatic void 2150195534Sscottlahci_stop(device_t dev) 2151195534Sscottl{ 2152195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2153195534Sscottl u_int32_t cmd; 2154195534Sscottl int timeout; 2155195534Sscottl 2156195534Sscottl /* Kill all activity on this channel */ 2157195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2158195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2159195534Sscottl /* Wait for activity stop. */ 2160195534Sscottl timeout = 0; 2161195534Sscottl do { 2162195534Sscottl DELAY(1000); 2163195534Sscottl if (timeout++ > 1000) { 2164195534Sscottl device_printf(dev, "stopping AHCI engine failed\n"); 2165195534Sscottl break; 2166195534Sscottl } 2167195534Sscottl } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2168203123Smav ch->eslots = 0; 2169195534Sscottl} 2170195534Sscottl 2171195534Sscottlstatic void 2172195534Sscottlahci_clo(device_t dev) 2173195534Sscottl{ 2174195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2175195534Sscottl u_int32_t cmd; 2176195534Sscottl int timeout; 2177195534Sscottl 2178195534Sscottl /* Issue Command List Override if supported */ 2179195534Sscottl if (ch->caps & AHCI_CAP_SCLO) { 2180195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2181195534Sscottl cmd |= AHCI_P_CMD_CLO; 2182195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2183195534Sscottl timeout = 0; 2184195534Sscottl do { 2185195534Sscottl DELAY(1000); 2186195534Sscottl if (timeout++ > 1000) { 2187195534Sscottl device_printf(dev, "executing CLO failed\n"); 2188195534Sscottl break; 2189195534Sscottl } 2190195534Sscottl } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2191195534Sscottl } 2192195534Sscottl} 2193195534Sscottl 2194195534Sscottlstatic void 2195195534Sscottlahci_stop_fr(device_t dev) 2196195534Sscottl{ 2197195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2198195534Sscottl u_int32_t cmd; 2199195534Sscottl int timeout; 2200195534Sscottl 2201195534Sscottl /* Kill all FIS reception on this channel */ 2202195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2203195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2204195534Sscottl /* Wait for FIS reception stop. */ 2205195534Sscottl timeout = 0; 2206195534Sscottl do { 2207195534Sscottl DELAY(1000); 2208195534Sscottl if (timeout++ > 1000) { 2209195534Sscottl device_printf(dev, "stopping AHCI FR engine failed\n"); 2210195534Sscottl break; 2211195534Sscottl } 2212195534Sscottl } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2213195534Sscottl} 2214195534Sscottl 2215195534Sscottlstatic void 2216195534Sscottlahci_start_fr(device_t dev) 2217195534Sscottl{ 2218195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2219195534Sscottl u_int32_t cmd; 2220195534Sscottl 2221195534Sscottl /* Start FIS reception on this channel */ 2222195534Sscottl cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2223195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2224195534Sscottl} 2225195534Sscottl 2226195534Sscottlstatic int 2227195534Sscottlahci_wait_ready(device_t dev, int t) 2228195534Sscottl{ 2229195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2230195534Sscottl int timeout = 0; 2231195534Sscottl uint32_t val; 2232195534Sscottl 2233195534Sscottl while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2234195534Sscottl (ATA_S_BUSY | ATA_S_DRQ)) { 2235195534Sscottl DELAY(1000); 2236195534Sscottl if (timeout++ > t) { 2237203108Smav device_printf(dev, "device is not ready (timeout %dms) " 2238195534Sscottl "tfd = %08x\n", t, val); 2239195534Sscottl return (EBUSY); 2240195534Sscottl } 2241195534Sscottl } 2242195534Sscottl if (bootverbose) 2243195534Sscottl device_printf(dev, "ready wait time=%dms\n", timeout); 2244195534Sscottl return (0); 2245195534Sscottl} 2246195534Sscottl 2247195534Sscottlstatic void 2248195534Sscottlahci_reset(device_t dev) 2249195534Sscottl{ 2250195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2251196656Smav struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2252195534Sscottl int i; 2253195534Sscottl 2254203108Smav xpt_freeze_simq(ch->sim, 1); 2255195534Sscottl if (bootverbose) 2256195534Sscottl device_printf(dev, "AHCI reset...\n"); 2257195534Sscottl /* Requeue freezed command. */ 2258195534Sscottl if (ch->frozen) { 2259195534Sscottl union ccb *fccb = ch->frozen; 2260195534Sscottl ch->frozen = NULL; 2261195534Sscottl fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2262198319Smav if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2263198319Smav xpt_freeze_devq(fccb->ccb_h.path, 1); 2264198319Smav fccb->ccb_h.status |= CAM_DEV_QFRZN; 2265198319Smav } 2266195534Sscottl xpt_done(fccb); 2267195534Sscottl } 2268195534Sscottl /* Kill the engine and requeue all running commands. */ 2269195534Sscottl ahci_stop(dev); 2270195534Sscottl for (i = 0; i < ch->numslots; i++) { 2271195534Sscottl /* Do we have a running request on slot? */ 2272195534Sscottl if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2273195534Sscottl continue; 2274195534Sscottl /* XXX; Commands in loading state. */ 2275195534Sscottl ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2276195534Sscottl } 2277198851Smav for (i = 0; i < ch->numslots; i++) { 2278198851Smav if (!ch->hold[i]) 2279198851Smav continue; 2280198851Smav xpt_done(ch->hold[i]); 2281198851Smav ch->hold[i] = NULL; 2282203123Smav ch->numhslots--; 2283198851Smav } 2284203873Smav if (ch->toslots != 0) 2285203873Smav xpt_release_simq(ch->sim, TRUE); 2286203123Smav ch->eslots = 0; 2287203873Smav ch->toslots = 0; 2288198851Smav ch->fatalerr = 0; 2289198319Smav /* Tell the XPT about the event */ 2290198319Smav xpt_async(AC_BUS_RESET, ch->path, NULL); 2291195534Sscottl /* Disable port interrupts */ 2292195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2293195534Sscottl /* Reset and reconnect PHY, */ 2294203108Smav if (!ahci_sata_phy_reset(dev)) { 2295195534Sscottl if (bootverbose) 2296195534Sscottl device_printf(dev, 2297195534Sscottl "AHCI reset done: phy reset found no device\n"); 2298195534Sscottl ch->devices = 0; 2299195534Sscottl /* Enable wanted port interrupts */ 2300195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 2301195534Sscottl (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2302203108Smav xpt_release_simq(ch->sim, TRUE); 2303195534Sscottl return; 2304195534Sscottl } 2305195534Sscottl /* Wait for clearing busy status. */ 2306203108Smav if (ahci_wait_ready(dev, 15000)) 2307195534Sscottl ahci_clo(dev); 2308203123Smav ahci_start(dev, 1); 2309195534Sscottl ch->devices = 1; 2310195534Sscottl /* Enable wanted port interrupts */ 2311195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_IE, 2312195534Sscottl (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2313195534Sscottl AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2314195534Sscottl ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 2315196656Smav AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2316196656Smav AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2317195534Sscottl if (bootverbose) 2318196656Smav device_printf(dev, "AHCI reset done: device found\n"); 2319203108Smav xpt_release_simq(ch->sim, TRUE); 2320195534Sscottl} 2321195534Sscottl 2322195534Sscottlstatic int 2323199821Smavahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2324195534Sscottl{ 2325199821Smav struct ahci_channel *ch = device_get_softc(dev); 2326195534Sscottl u_int8_t *fis = &ctp->cfis[0]; 2327195534Sscottl 2328195534Sscottl bzero(ctp->cfis, 64); 2329195534Sscottl fis[0] = 0x27; /* host to device */ 2330195534Sscottl fis[1] = (ccb->ccb_h.target_id & 0x0f); 2331195534Sscottl if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2332195534Sscottl fis[1] |= 0x80; 2333195534Sscottl fis[2] = ATA_PACKET_CMD; 2334199821Smav if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2335199821Smav ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2336195534Sscottl fis[3] = ATA_F_DMA; 2337195534Sscottl else { 2338195534Sscottl fis[5] = ccb->csio.dxfer_len; 2339195534Sscottl fis[6] = ccb->csio.dxfer_len >> 8; 2340195534Sscottl } 2341195534Sscottl fis[7] = ATA_D_LBA; 2342195534Sscottl fis[15] = ATA_A_4BIT; 2343195534Sscottl bzero(ctp->acmd, 32); 2344195534Sscottl bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2345195534Sscottl ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2346195534Sscottl ctp->acmd, ccb->csio.cdb_len); 2347195534Sscottl } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2348195534Sscottl fis[1] |= 0x80; 2349195534Sscottl fis[2] = ccb->ataio.cmd.command; 2350195534Sscottl fis[3] = ccb->ataio.cmd.features; 2351195534Sscottl fis[4] = ccb->ataio.cmd.lba_low; 2352195534Sscottl fis[5] = ccb->ataio.cmd.lba_mid; 2353195534Sscottl fis[6] = ccb->ataio.cmd.lba_high; 2354195534Sscottl fis[7] = ccb->ataio.cmd.device; 2355195534Sscottl fis[8] = ccb->ataio.cmd.lba_low_exp; 2356195534Sscottl fis[9] = ccb->ataio.cmd.lba_mid_exp; 2357195534Sscottl fis[10] = ccb->ataio.cmd.lba_high_exp; 2358195534Sscottl fis[11] = ccb->ataio.cmd.features_exp; 2359195534Sscottl if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2360195534Sscottl fis[12] = tag << 3; 2361195534Sscottl fis[13] = 0; 2362195534Sscottl } else { 2363195534Sscottl fis[12] = ccb->ataio.cmd.sector_count; 2364195534Sscottl fis[13] = ccb->ataio.cmd.sector_count_exp; 2365195534Sscottl } 2366195534Sscottl fis[15] = ATA_A_4BIT; 2367195534Sscottl } else { 2368195534Sscottl fis[15] = ccb->ataio.cmd.control; 2369195534Sscottl } 2370195534Sscottl return (20); 2371195534Sscottl} 2372195534Sscottl 2373195534Sscottlstatic int 2374195534Sscottlahci_sata_connect(struct ahci_channel *ch) 2375195534Sscottl{ 2376195534Sscottl u_int32_t status; 2377195534Sscottl int timeout; 2378195534Sscottl 2379195534Sscottl /* Wait up to 100ms for "connect well" */ 2380195534Sscottl for (timeout = 0; timeout < 100 ; timeout++) { 2381195534Sscottl status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2382195534Sscottl if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2383195534Sscottl ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2384195534Sscottl ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2385195534Sscottl break; 2386196656Smav if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2387196656Smav if (bootverbose) { 2388196656Smav device_printf(ch->dev, "SATA offline status=%08x\n", 2389196656Smav status); 2390196656Smav } 2391196656Smav return (0); 2392196656Smav } 2393195534Sscottl DELAY(1000); 2394195534Sscottl } 2395195534Sscottl if (timeout >= 100) { 2396195534Sscottl if (bootverbose) { 2397195534Sscottl device_printf(ch->dev, "SATA connect timeout status=%08x\n", 2398195534Sscottl status); 2399195534Sscottl } 2400195534Sscottl return (0); 2401195534Sscottl } 2402195534Sscottl if (bootverbose) { 2403195534Sscottl device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 2404195534Sscottl timeout, status); 2405195534Sscottl } 2406195534Sscottl /* Clear SATA error register */ 2407195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2408195534Sscottl return (1); 2409195534Sscottl} 2410195534Sscottl 2411195534Sscottlstatic int 2412203108Smavahci_sata_phy_reset(device_t dev) 2413195534Sscottl{ 2414195534Sscottl struct ahci_channel *ch = device_get_softc(dev); 2415199821Smav int sata_rev; 2416195534Sscottl uint32_t val; 2417195534Sscottl 2418199821Smav sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2419199821Smav if (sata_rev == 1) 2420195534Sscottl val = ATA_SC_SPD_SPEED_GEN1; 2421199821Smav else if (sata_rev == 2) 2422195534Sscottl val = ATA_SC_SPD_SPEED_GEN2; 2423199821Smav else if (sata_rev == 3) 2424195534Sscottl val = ATA_SC_SPD_SPEED_GEN3; 2425195534Sscottl else 2426195534Sscottl val = 0; 2427195534Sscottl ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2428196656Smav ATA_SC_DET_RESET | val | 2429196656Smav ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2430196656Smav DELAY(5000); 2431196656Smav ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2432195534Sscottl ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2433195534Sscottl (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2434196656Smav DELAY(5000); 2435203426Smav if (!ahci_sata_connect(ch)) { 2436203426Smav if (ch->pm_level > 0) 2437203426Smav ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2438203426Smav return (0); 2439203426Smav } 2440203426Smav return (1); 2441195534Sscottl} 2442195534Sscottl 2443207430Smavstatic int 2444207430Smavahci_check_ids(device_t dev, union ccb *ccb) 2445207430Smav{ 2446207430Smav struct ahci_channel *ch = device_get_softc(dev); 2447207430Smav 2448207430Smav if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2449207430Smav ccb->ccb_h.status = CAM_TID_INVALID; 2450207430Smav xpt_done(ccb); 2451207430Smav return (-1); 2452207430Smav } 2453207430Smav if (ccb->ccb_h.target_lun != 0) { 2454207430Smav ccb->ccb_h.status = CAM_LUN_INVALID; 2455207430Smav xpt_done(ccb); 2456207430Smav return (-1); 2457207430Smav } 2458207430Smav return (0); 2459207430Smav} 2460207430Smav 2461195534Sscottlstatic void 2462195534Sscottlahciaction(struct cam_sim *sim, union ccb *ccb) 2463195534Sscottl{ 2464210471Smav device_t dev, parent; 2465195534Sscottl struct ahci_channel *ch; 2466195534Sscottl 2467195534Sscottl CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2468195534Sscottl ccb->ccb_h.func_code)); 2469195534Sscottl 2470195534Sscottl ch = (struct ahci_channel *)cam_sim_softc(sim); 2471195534Sscottl dev = ch->dev; 2472195534Sscottl switch (ccb->ccb_h.func_code) { 2473195534Sscottl /* Common cases first */ 2474195534Sscottl case XPT_ATA_IO: /* Execute the requested I/O operation */ 2475195534Sscottl case XPT_SCSI_IO: 2476207430Smav if (ahci_check_ids(dev, ccb)) 2477207430Smav return; 2478207430Smav if (ch->devices == 0 || 2479207430Smav (ch->pm_present == 0 && 2480207430Smav ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2481195534Sscottl ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2482195534Sscottl break; 2483195534Sscottl } 2484195534Sscottl /* Check for command collision. */ 2485195534Sscottl if (ahci_check_collision(dev, ccb)) { 2486195534Sscottl /* Freeze command. */ 2487195534Sscottl ch->frozen = ccb; 2488195534Sscottl /* We have only one frozen slot, so freeze simq also. */ 2489195534Sscottl xpt_freeze_simq(ch->sim, 1); 2490195534Sscottl return; 2491195534Sscottl } 2492195534Sscottl ahci_begin_transaction(dev, ccb); 2493207430Smav return; 2494195534Sscottl case XPT_EN_LUN: /* Enable LUN as a target */ 2495195534Sscottl case XPT_TARGET_IO: /* Execute target I/O request */ 2496195534Sscottl case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2497195534Sscottl case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2498195534Sscottl case XPT_ABORT: /* Abort the specified CCB */ 2499195534Sscottl /* XXX Implement */ 2500195534Sscottl ccb->ccb_h.status = CAM_REQ_INVALID; 2501195534Sscottl break; 2502195534Sscottl case XPT_SET_TRAN_SETTINGS: 2503195534Sscottl { 2504195534Sscottl struct ccb_trans_settings *cts = &ccb->cts; 2505199747Smav struct ahci_device *d; 2506195534Sscottl 2507207430Smav if (ahci_check_ids(dev, ccb)) 2508207430Smav return; 2509199747Smav if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2510199747Smav d = &ch->curr[ccb->ccb_h.target_id]; 2511199747Smav else 2512199747Smav d = &ch->user[ccb->ccb_h.target_id]; 2513199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2514199747Smav d->revision = cts->xport_specific.sata.revision; 2515199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2516199747Smav d->mode = cts->xport_specific.sata.mode; 2517199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2518199747Smav d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2519199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2520199747Smav d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2521199747Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2522195534Sscottl ch->pm_present = cts->xport_specific.sata.pm_present; 2523203376Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2524203376Smav d->atapi = cts->xport_specific.sata.atapi; 2525207499Smav if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2526207499Smav d->caps = cts->xport_specific.sata.caps; 2527195534Sscottl ccb->ccb_h.status = CAM_REQ_CMP; 2528195534Sscottl break; 2529195534Sscottl } 2530195534Sscottl case XPT_GET_TRAN_SETTINGS: 2531195534Sscottl /* Get default/user set transfer settings for the target */ 2532195534Sscottl { 2533195534Sscottl struct ccb_trans_settings *cts = &ccb->cts; 2534199747Smav struct ahci_device *d; 2535195534Sscottl uint32_t status; 2536195534Sscottl 2537207430Smav if (ahci_check_ids(dev, ccb)) 2538207430Smav return; 2539199747Smav if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2540199747Smav d = &ch->curr[ccb->ccb_h.target_id]; 2541199747Smav else 2542199747Smav d = &ch->user[ccb->ccb_h.target_id]; 2543195534Sscottl cts->protocol = PROTO_ATA; 2544196656Smav cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2545195534Sscottl cts->transport = XPORT_SATA; 2546196656Smav cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2547195534Sscottl cts->proto_specific.valid = 0; 2548195534Sscottl cts->xport_specific.sata.valid = 0; 2549199747Smav if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2550199747Smav (ccb->ccb_h.target_id == 15 || 2551199747Smav (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2552195534Sscottl status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2553199747Smav if (status & 0x0f0) { 2554199747Smav cts->xport_specific.sata.revision = 2555199747Smav (status & 0x0f0) >> 4; 2556199747Smav cts->xport_specific.sata.valid |= 2557199747Smav CTS_SATA_VALID_REVISION; 2558199747Smav } 2559207499Smav cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2560207499Smav if (ch->pm_level) { 2561207499Smav if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2562207499Smav cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2563207499Smav if (ch->caps2 & AHCI_CAP2_APST) 2564207499Smav cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2565207499Smav } 2566207499Smav if ((ch->caps & AHCI_CAP_SNCQ) && 2567207499Smav (ch->quirks & AHCI_Q_NOAA) == 0) 2568207499Smav cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2569207499Smav cts->xport_specific.sata.caps &= 2570207499Smav ch->user[ccb->ccb_h.target_id].caps; 2571207499Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2572195534Sscottl } else { 2573199747Smav cts->xport_specific.sata.revision = d->revision; 2574199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2575207499Smav cts->xport_specific.sata.caps = d->caps; 2576207499Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2577195534Sscottl } 2578199747Smav cts->xport_specific.sata.mode = d->mode; 2579199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2580199747Smav cts->xport_specific.sata.bytecount = d->bytecount; 2581199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2582199747Smav cts->xport_specific.sata.pm_present = ch->pm_present; 2583195534Sscottl cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2584199747Smav cts->xport_specific.sata.tags = d->tags; 2585199747Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2586203376Smav cts->xport_specific.sata.atapi = d->atapi; 2587203376Smav cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2588195534Sscottl ccb->ccb_h.status = CAM_REQ_CMP; 2589195534Sscottl break; 2590195534Sscottl } 2591195534Sscottl case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2592195534Sscottl case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2593195534Sscottl ahci_reset(dev); 2594195534Sscottl ccb->ccb_h.status = CAM_REQ_CMP; 2595195534Sscottl break; 2596195534Sscottl case XPT_TERM_IO: /* Terminate the I/O process */ 2597195534Sscottl /* XXX Implement */ 2598195534Sscottl ccb->ccb_h.status = CAM_REQ_INVALID; 2599195534Sscottl break; 2600195534Sscottl case XPT_PATH_INQ: /* Path routing inquiry */ 2601195534Sscottl { 2602195534Sscottl struct ccb_pathinq *cpi = &ccb->cpi; 2603195534Sscottl 2604210471Smav parent = device_get_parent(dev); 2605195534Sscottl cpi->version_num = 1; /* XXX??? */ 2606199278Smav cpi->hba_inquiry = PI_SDTR_ABLE; 2607199278Smav if (ch->caps & AHCI_CAP_SNCQ) 2608199278Smav cpi->hba_inquiry |= PI_TAG_ABLE; 2609195534Sscottl if (ch->caps & AHCI_CAP_SPM) 2610195534Sscottl cpi->hba_inquiry |= PI_SATAPM; 2611195534Sscottl cpi->target_sprt = 0; 2612195534Sscottl cpi->hba_misc = PIM_SEQSCAN; 2613195534Sscottl cpi->hba_eng_cnt = 0; 2614195534Sscottl if (ch->caps & AHCI_CAP_SPM) 2615198322Smav cpi->max_target = 15; 2616195534Sscottl else 2617195534Sscottl cpi->max_target = 0; 2618195534Sscottl cpi->max_lun = 0; 2619195534Sscottl cpi->initiator_id = 0; 2620195534Sscottl cpi->bus_id = cam_sim_bus(sim); 2621195534Sscottl cpi->base_transfer_speed = 150000; 2622195534Sscottl strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2623195534Sscottl strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2624195534Sscottl strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2625195534Sscottl cpi->unit_number = cam_sim_unit(sim); 2626195534Sscottl cpi->transport = XPORT_SATA; 2627196656Smav cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2628195534Sscottl cpi->protocol = PROTO_ATA; 2629196656Smav cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2630195534Sscottl cpi->maxio = MAXPHYS; 2631196777Smav /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2632210471Smav if (pci_get_devid(parent) == 0x43801002) 2633196796Smav cpi->maxio = min(cpi->maxio, 128 * 512); 2634210471Smav cpi->hba_vendor = pci_get_vendor(parent); 2635210471Smav cpi->hba_device = pci_get_device(parent); 2636210471Smav cpi->hba_subvendor = pci_get_subvendor(parent); 2637210471Smav cpi->hba_subdevice = pci_get_subdevice(parent); 2638195534Sscottl cpi->ccb_h.status = CAM_REQ_CMP; 2639195534Sscottl break; 2640195534Sscottl } 2641195534Sscottl default: 2642195534Sscottl ccb->ccb_h.status = CAM_REQ_INVALID; 2643195534Sscottl break; 2644195534Sscottl } 2645207430Smav xpt_done(ccb); 2646195534Sscottl} 2647195534Sscottl 2648195534Sscottlstatic void 2649195534Sscottlahcipoll(struct cam_sim *sim) 2650195534Sscottl{ 2651195534Sscottl struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2652195534Sscottl 2653195534Sscottl ahci_ch_intr(ch->dev); 2654195534Sscottl} 2655