ahci_pci.c revision 195534
1/*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ahci/ahci.c 195534 2009-07-10 08:18:08Z scottl $"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include "ahci.h" 50 51#include <cam/cam.h> 52#include <cam/cam_ccb.h> 53#include <cam/cam_sim.h> 54#include <cam/cam_xpt_sim.h> 55#include <cam/cam_xpt_periph.h> 56#include <cam/cam_debug.h> 57 58/* local prototypes */ 59static int ahci_setup_interrupt(device_t dev); 60static void ahci_intr(void *data); 61static void ahci_intr_one(void *data); 62static int ahci_suspend(device_t dev); 63static int ahci_resume(device_t dev); 64static int ahci_ch_suspend(device_t dev); 65static int ahci_ch_resume(device_t dev); 66static void ahci_ch_intr_locked(void *data); 67static void ahci_ch_intr(void *data); 68static int ahci_ctlr_reset(device_t dev); 69static void ahci_begin_transaction(device_t dev, union ccb *ccb); 70static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 71static void ahci_execute_transaction(struct ahci_slot *slot); 72static void ahci_timeout(struct ahci_slot *slot); 73static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 74static int ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 75static void ahci_dmainit(device_t dev); 76static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 77static void ahci_dmafini(device_t dev); 78static void ahci_slotsalloc(device_t dev); 79static void ahci_slotsfree(device_t dev); 80static void ahci_reset(device_t dev); 81static void ahci_start(device_t dev); 82static void ahci_stop(device_t dev); 83static void ahci_clo(device_t dev); 84static void ahci_start_fr(device_t dev); 85static void ahci_stop_fr(device_t dev); 86 87static int ahci_sata_connect(struct ahci_channel *ch); 88static int ahci_sata_phy_reset(device_t dev, int quick); 89 90static void ahci_issue_read_log(device_t dev); 91static void ahci_process_read_log(device_t dev, union ccb *ccb); 92 93static void ahciaction(struct cam_sim *sim, union ccb *ccb); 94static void ahcipoll(struct cam_sim *sim); 95 96MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 97 98/* 99 * AHCI v1.x compliant SATA chipset support functions 100 */ 101static int 102ahci_probe(device_t dev) 103{ 104 105 /* is this a possible AHCI candidate ? */ 106 if (pci_get_class(dev) != PCIC_STORAGE || 107 pci_get_subclass(dev) != PCIS_STORAGE_SATA) 108 return (ENXIO); 109 110 /* is this PCI device flagged as an AHCI compliant chip ? */ 111 if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0) 112 return (ENXIO); 113 114 device_set_desc_copy(dev, "AHCI controller"); 115 return (BUS_PROBE_VENDOR); 116} 117 118static int 119ahci_attach(device_t dev) 120{ 121 struct ahci_controller *ctlr = device_get_softc(dev); 122 device_t child; 123 int error, unit, speed; 124 u_int32_t version, caps; 125 126 ctlr->dev = dev; 127 /* if we have a memory BAR(5) we are likely on an AHCI part */ 128 ctlr->r_rid = PCIR_BAR(5); 129 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 130 &ctlr->r_rid, RF_ACTIVE))) 131 return ENXIO; 132 /* Setup our own memory management for channels. */ 133 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 134 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 135 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 136 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 137 return (error); 138 } 139 if ((error = rman_manage_region(&ctlr->sc_iomem, 140 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 141 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 142 rman_fini(&ctlr->sc_iomem); 143 return (error); 144 } 145 /* Reset controller */ 146 if ((error = ahci_ctlr_reset(dev)) != 0) { 147 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 148 rman_fini(&ctlr->sc_iomem); 149 return (error); 150 }; 151 /* Get the number of HW channels */ 152 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 153 ctlr->channels = MAX(flsl(ctlr->ichannels), 154 (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_NPMASK) + 1); 155 /* Setup interrupts. */ 156 if (ahci_setup_interrupt(dev)) { 157 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 158 rman_fini(&ctlr->sc_iomem); 159 return ENXIO; 160 } 161 /* Announce HW capabilities. */ 162 version = ATA_INL(ctlr->r_mem, AHCI_VS); 163 caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 164 speed = (caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 165 device_printf(dev, 166 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n", 167 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 168 ((version >> 4) & 0xf0) + (version & 0x0f), 169 (caps & AHCI_CAP_NPMASK) + 1, 170 ((speed == 1) ? "1.5":((speed == 2) ? "3": 171 ((speed == 3) ? "6":"?"))), 172 (caps & AHCI_CAP_SPM) ? 173 "supported" : "not supported"); 174 if (bootverbose) { 175 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 176 (caps & AHCI_CAP_64BIT) ? " 64bit":"", 177 (caps & AHCI_CAP_SNCQ) ? " NCQ":"", 178 (caps & AHCI_CAP_SSNTF) ? " SNTF":"", 179 (caps & AHCI_CAP_SMPS) ? " MPS":"", 180 (caps & AHCI_CAP_SSS) ? " SS":"", 181 (caps & AHCI_CAP_SALP) ? " ALP":"", 182 (caps & AHCI_CAP_SAL) ? " AL":"", 183 (caps & AHCI_CAP_SCLO) ? " CLO":"", 184 ((speed == 1) ? "1.5":((speed == 2) ? "3": 185 ((speed == 3) ? "6":"?")))); 186 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 187 (caps & AHCI_CAP_SAM) ? " AM":"", 188 (caps & AHCI_CAP_SPM) ? " PM":"", 189 (caps & AHCI_CAP_FBSS) ? " FBS":"", 190 (caps & AHCI_CAP_PMD) ? " PMD":"", 191 (caps & AHCI_CAP_SSC) ? " SSC":"", 192 (caps & AHCI_CAP_PSC) ? " PSC":"", 193 ((caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 194 (caps & AHCI_CAP_CCCS) ? " CCC":"", 195 (caps & AHCI_CAP_EMS) ? " EM":"", 196 (caps & AHCI_CAP_SXS) ? " eSATA":"", 197 (caps & AHCI_CAP_NPMASK) + 1); 198 } 199 /* Attach all channels on this controller */ 200 for (unit = 0; unit < ctlr->channels; unit++) { 201 if ((ctlr->ichannels & (1 << unit)) == 0) 202 continue; 203 child = device_add_child(dev, "ahcich", -1); 204 if (child == NULL) 205 device_printf(dev, "failed to add channel device\n"); 206 else 207 device_set_ivars(child, (void *)(intptr_t)unit); 208 } 209 bus_generic_attach(dev); 210 return 0; 211} 212 213static int 214ahci_detach(device_t dev) 215{ 216 struct ahci_controller *ctlr = device_get_softc(dev); 217 device_t *children; 218 int nchildren, i; 219 220 /* Detach & delete all children */ 221 if (!device_get_children(dev, &children, &nchildren)) { 222 for (i = 0; i < nchildren; i++) 223 device_delete_child(dev, children[i]); 224 free(children, M_TEMP); 225 } 226 /* Free interrupts. */ 227 for (i = 0; i < ctlr->numirqs; i++) { 228 if (ctlr->irqs[i].r_irq) { 229 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 230 ctlr->irqs[i].handle); 231 bus_release_resource(dev, SYS_RES_IRQ, 232 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 233 } 234 } 235 pci_release_msi(dev); 236 /* Free memory. */ 237 rman_fini(&ctlr->sc_iomem); 238 if (ctlr->r_mem) 239 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 240 return (0); 241} 242 243static int 244ahci_ctlr_reset(device_t dev) 245{ 246 struct ahci_controller *ctlr = device_get_softc(dev); 247 int timeout; 248 249 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 250 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 251 pci_write_config(dev, 0x92, 0x01, 1); 252 /* Enable AHCI mode */ 253 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 254 /* Reset AHCI controller */ 255 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 256 for (timeout = 1000; timeout > 0; timeout--) { 257 DELAY(1000); 258 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 259 break; 260 } 261 if (timeout == 0) { 262 device_printf(dev, "AHCI controller reset failure\n"); 263 return ENXIO; 264 } 265 /* Reenable AHCI mode */ 266 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 267 /* Clear interrupts */ 268 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 269 /* Enable AHCI interrupts */ 270 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 271 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 272 return (0); 273} 274 275static int 276ahci_suspend(device_t dev) 277{ 278 struct ahci_controller *ctlr = device_get_softc(dev); 279 280 bus_generic_suspend(dev); 281 /* Disable interupts, so the state change(s) doesn't trigger */ 282 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 283 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 284 return 0; 285} 286 287static int 288ahci_resume(device_t dev) 289{ 290 int res; 291 292 if ((res = ahci_ctlr_reset(dev)) != 0) 293 return (res); 294 return (bus_generic_resume(dev)); 295} 296 297static int 298ahci_setup_interrupt(device_t dev) 299{ 300 struct ahci_controller *ctlr = device_get_softc(dev); 301 int i, msi = 1; 302 303 /* Process hints. */ 304 resource_int_value(device_get_name(dev), 305 device_get_unit(dev), "msi", &msi); 306 if (msi < 0) 307 msi = 0; 308 else if (msi == 1) 309 msi = min(1, pci_msi_count(dev)); 310 else if (msi > 1) 311 msi = pci_msi_count(dev); 312 /* Allocate MSI if needed/present. */ 313 if (msi && pci_alloc_msi(dev, &msi) == 0) { 314 ctlr->numirqs = msi; 315 } else { 316 msi = 0; 317 ctlr->numirqs = 1; 318 } 319 /* Check for single MSI vector fallback. */ 320 if (ctlr->numirqs > 1 && 321 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 322 device_printf(dev, "Falling back to one MSI\n"); 323 ctlr->numirqs = 1; 324 } 325 /* Allocate all IRQs. */ 326 for (i = 0; i < ctlr->numirqs; i++) { 327 ctlr->irqs[i].ctlr = ctlr; 328 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 329 if (ctlr->numirqs == 1 || i >= ctlr->channels) 330 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 331 else if (i == ctlr->numirqs - 1) 332 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 333 else 334 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 335 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 336 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 337 device_printf(dev, "unable to map interrupt\n"); 338 return ENXIO; 339 } 340 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 341 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 342 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 343 /* SOS XXX release r_irq */ 344 device_printf(dev, "unable to setup interrupt\n"); 345 return ENXIO; 346 } 347 } 348 return (0); 349} 350 351/* 352 * Common case interrupt handler. 353 */ 354static void 355ahci_intr(void *data) 356{ 357 struct ahci_controller_irq *irq = data; 358 struct ahci_controller *ctlr = irq->ctlr; 359 u_int32_t is; 360 void *arg; 361 int unit; 362 363 is = ATA_INL(ctlr->r_mem, AHCI_IS); 364 if (irq->mode == AHCI_IRQ_MODE_ALL) 365 unit = 0; 366 else /* AHCI_IRQ_MODE_AFTER */ 367 unit = irq->r_irq_rid - 1; 368 for (; unit < ctlr->channels; unit++) { 369 if ((is & (1 << unit)) != 0 && 370 (arg = ctlr->interrupt[unit].argument)) { 371 ctlr->interrupt[unit].function(arg); 372 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 373 } 374 } 375} 376 377/* 378 * Simplified interrupt handler for multivector MSI mode. 379 */ 380static void 381ahci_intr_one(void *data) 382{ 383 struct ahci_controller_irq *irq = data; 384 struct ahci_controller *ctlr = irq->ctlr; 385 void *arg; 386 int unit; 387 388 unit = irq->r_irq_rid - 1; 389 if ((arg = ctlr->interrupt[unit].argument)) 390 ctlr->interrupt[unit].function(arg); 391} 392 393static struct resource * 394ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 395 u_long start, u_long end, u_long count, u_int flags) 396{ 397 struct ahci_controller *ctlr = device_get_softc(dev); 398 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 399 struct resource *res = NULL; 400 int offset = AHCI_OFFSET + (unit << 7); 401 long st; 402 403 switch (type) { 404 case SYS_RES_MEMORY: 405 st = rman_get_start(ctlr->r_mem); 406 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 407 st + offset + 127, 128, RF_ACTIVE, child); 408 if (res) { 409 bus_space_handle_t bsh; 410 bus_space_tag_t bst; 411 bsh = rman_get_bushandle(ctlr->r_mem); 412 bst = rman_get_bustag(ctlr->r_mem); 413 bus_space_subregion(bst, bsh, offset, 128, &bsh); 414 rman_set_bushandle(res, bsh); 415 rman_set_bustag(res, bst); 416 } 417 break; 418 case SYS_RES_IRQ: 419 if (*rid == ATA_IRQ_RID) 420 res = ctlr->irqs[0].r_irq; 421 break; 422 } 423 return (res); 424} 425 426static int 427ahci_release_resource(device_t dev, device_t child, int type, int rid, 428 struct resource *r) 429{ 430 431 switch (type) { 432 case SYS_RES_MEMORY: 433 rman_release_resource(r); 434 return (0); 435 case SYS_RES_IRQ: 436 if (rid != ATA_IRQ_RID) 437 return ENOENT; 438 return (0); 439 } 440 return (EINVAL); 441} 442 443static int 444ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 445 int flags, driver_filter_t *filter, driver_intr_t *function, 446 void *argument, void **cookiep) 447{ 448 struct ahci_controller *ctlr = device_get_softc(dev); 449 int unit = (intptr_t)device_get_ivars(child); 450 451 if (filter != NULL) { 452 printf("ahci.c: we cannot use a filter here\n"); 453 return (EINVAL); 454 } 455 ctlr->interrupt[unit].function = function; 456 ctlr->interrupt[unit].argument = argument; 457 return (0); 458} 459 460static int 461ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 462 void *cookie) 463{ 464 struct ahci_controller *ctlr = device_get_softc(dev); 465 int unit = (intptr_t)device_get_ivars(child); 466 467 ctlr->interrupt[unit].function = NULL; 468 ctlr->interrupt[unit].argument = NULL; 469 return (0); 470} 471 472static int 473ahci_print_child(device_t dev, device_t child) 474{ 475 int retval; 476 477 retval = bus_print_child_header(dev, child); 478 retval += printf(" at channel %d", 479 (int)(intptr_t)device_get_ivars(child)); 480 retval += bus_print_child_footer(dev, child); 481 482 return (retval); 483} 484 485devclass_t ahci_devclass; 486static device_method_t ahci_methods[] = { 487 DEVMETHOD(device_probe, ahci_probe), 488 DEVMETHOD(device_attach, ahci_attach), 489 DEVMETHOD(device_detach, ahci_detach), 490 DEVMETHOD(device_suspend, ahci_suspend), 491 DEVMETHOD(device_resume, ahci_resume), 492 DEVMETHOD(bus_print_child, ahci_print_child), 493 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 494 DEVMETHOD(bus_release_resource, ahci_release_resource), 495 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 496 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 497 { 0, 0 } 498}; 499static driver_t ahci_driver = { 500 "ahci", 501 ahci_methods, 502 sizeof(struct ahci_controller) 503}; 504DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 505MODULE_VERSION(ahci, 1); 506MODULE_DEPEND(ahci, cam, 1, 1, 1); 507 508static int 509ahci_ch_probe(device_t dev) 510{ 511 512 device_set_desc_copy(dev, "AHCI channel"); 513 return (0); 514} 515 516static int 517ahci_ch_attach(device_t dev) 518{ 519 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 520 struct ahci_channel *ch = device_get_softc(dev); 521 struct cam_devq *devq; 522 int rid, error; 523 524 ch->dev = dev; 525 ch->unit = (intptr_t)device_get_ivars(dev); 526 ch->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 527 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 528 resource_int_value(device_get_name(dev), 529 device_get_unit(dev), "pm_level", &ch->pm_level); 530 /* Limit speed for my onboard JMicron external port. 531 * It is not eSATA really. */ 532 if (pci_get_devid(ctlr->dev) == 0x2363197b && 533 pci_get_subvendor(ctlr->dev) == 0x1043 && 534 pci_get_subdevice(ctlr->dev) == 0x81e4 && 535 ch->unit == 0) 536 ch->sata_rev = 1; 537 resource_int_value(device_get_name(dev), 538 device_get_unit(dev), "sata_rev", &ch->sata_rev); 539 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 540 rid = ch->unit; 541 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 542 &rid, RF_ACTIVE))) 543 return (ENXIO); 544 ahci_dmainit(dev); 545 ahci_slotsalloc(dev); 546 ahci_ch_resume(dev); 547 mtx_lock(&ch->mtx); 548 rid = ATA_IRQ_RID; 549 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 550 &rid, RF_SHAREABLE | RF_ACTIVE))) { 551 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 552 device_printf(dev, "Unable to map interrupt\n"); 553 return (ENXIO); 554 } 555 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 556 ahci_ch_intr_locked, dev, &ch->ih))) { 557 device_printf(dev, "Unable to setup interrupt\n"); 558 error = ENXIO; 559 goto err1; 560 } 561 /* Create the device queue for our SIM. */ 562 devq = cam_simq_alloc(ch->numslots); 563 if (devq == NULL) { 564 device_printf(dev, "Unable to allocate simq\n"); 565 error = ENOMEM; 566 goto err1; 567 } 568 /* Construct SIM entry */ 569 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 570 device_get_unit(dev), &ch->mtx, ch->numslots, 0, devq); 571 if (ch->sim == NULL) { 572 device_printf(dev, "unable to allocate sim\n"); 573 error = ENOMEM; 574 goto err2; 575 } 576 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 577 device_printf(dev, "unable to register xpt bus\n"); 578 error = ENXIO; 579 goto err2; 580 } 581 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 582 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 583 device_printf(dev, "unable to create path\n"); 584 error = ENXIO; 585 goto err3; 586 } 587 mtx_unlock(&ch->mtx); 588 return (0); 589 590err3: 591 xpt_bus_deregister(cam_sim_path(ch->sim)); 592err2: 593 cam_sim_free(ch->sim, /*free_devq*/TRUE); 594err1: 595 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 596 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 597 mtx_unlock(&ch->mtx); 598 return (error); 599} 600 601static int 602ahci_ch_detach(device_t dev) 603{ 604 struct ahci_channel *ch = device_get_softc(dev); 605 606 mtx_lock(&ch->mtx); 607 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 608 xpt_free_path(ch->path); 609 xpt_bus_deregister(cam_sim_path(ch->sim)); 610 cam_sim_free(ch->sim, /*free_devq*/TRUE); 611 mtx_unlock(&ch->mtx); 612 613 bus_teardown_intr(dev, ch->r_irq, ch->ih); 614 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 615 616 ahci_ch_suspend(dev); 617 ahci_slotsfree(dev); 618 ahci_dmafini(dev); 619 620 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 621 mtx_destroy(&ch->mtx); 622 return (0); 623} 624 625static int 626ahci_ch_suspend(device_t dev) 627{ 628 struct ahci_channel *ch = device_get_softc(dev); 629 630 /* Disable port interrupts. */ 631 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 632 /* Reset command register. */ 633 ahci_stop(dev); 634 ahci_stop_fr(dev); 635 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 636 /* Allow everything, including partial and slumber modes. */ 637 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 638 /* Request slumber mode transition and give some time to get there. */ 639 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 640 DELAY(100); 641 /* Disable PHY. */ 642 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 643 return (0); 644} 645 646static int 647ahci_ch_resume(device_t dev) 648{ 649 struct ahci_channel *ch = device_get_softc(dev); 650 uint64_t work; 651 652 /* Disable port interrupts */ 653 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 654 /* Setup work areas */ 655 work = ch->dma.work_bus + AHCI_CL_OFFSET; 656 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 657 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 658 work = ch->dma.rfis_bus; 659 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 660 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 661 /* Activate the channel and power/spin up device */ 662 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 663 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 664 ((ch->pm_level > 1) ? AHCI_P_CMD_ALPE : 0) | 665 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 666 ahci_start_fr(dev); 667 ahci_start(dev); 668 return (0); 669} 670 671devclass_t ahcich_devclass; 672static device_method_t ahcich_methods[] = { 673 DEVMETHOD(device_probe, ahci_ch_probe), 674 DEVMETHOD(device_attach, ahci_ch_attach), 675 DEVMETHOD(device_detach, ahci_ch_detach), 676 DEVMETHOD(device_suspend, ahci_ch_suspend), 677 DEVMETHOD(device_resume, ahci_ch_resume), 678 { 0, 0 } 679}; 680static driver_t ahcich_driver = { 681 "ahcich", 682 ahcich_methods, 683 sizeof(struct ahci_channel) 684}; 685DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahci_devclass, 0, 0); 686 687struct ahci_dc_cb_args { 688 bus_addr_t maddr; 689 int error; 690}; 691 692static void 693ahci_dmainit(device_t dev) 694{ 695 struct ahci_channel *ch = device_get_softc(dev); 696 struct ahci_dc_cb_args dcba; 697 698 if (ch->caps & AHCI_CAP_64BIT) 699 ch->dma.max_address = BUS_SPACE_MAXADDR; 700 else 701 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 702 /* Command area. */ 703 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 704 ch->dma.max_address, BUS_SPACE_MAXADDR, 705 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 706 0, NULL, NULL, &ch->dma.work_tag)) 707 goto error; 708 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 709 &ch->dma.work_map)) 710 goto error; 711 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 712 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 713 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 714 goto error; 715 } 716 ch->dma.work_bus = dcba.maddr; 717 /* FIS receive area. */ 718 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, 719 ch->dma.max_address, BUS_SPACE_MAXADDR, 720 NULL, NULL, 4096, 1, 4096, 721 0, NULL, NULL, &ch->dma.rfis_tag)) 722 goto error; 723 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 724 &ch->dma.rfis_map)) 725 goto error; 726 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 727 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 728 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 729 goto error; 730 } 731 ch->dma.rfis_bus = dcba.maddr; 732 /* Data area. */ 733 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 734 ch->dma.max_address, BUS_SPACE_MAXADDR, 735 NULL, NULL, 736 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 737 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 738 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 739 goto error; 740 } 741 return; 742 743error: 744 device_printf(dev, "WARNING - DMA initialization failed\n"); 745 ahci_dmafini(dev); 746} 747 748static void 749ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 750{ 751 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 752 753 if (!(dcba->error = error)) 754 dcba->maddr = segs[0].ds_addr; 755} 756 757static void 758ahci_dmafini(device_t dev) 759{ 760 struct ahci_channel *ch = device_get_softc(dev); 761 762 if (ch->dma.data_tag) { 763 bus_dma_tag_destroy(ch->dma.data_tag); 764 ch->dma.data_tag = NULL; 765 } 766 if (ch->dma.rfis_bus) { 767 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 768 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 769 ch->dma.rfis_bus = 0; 770 ch->dma.rfis_map = NULL; 771 ch->dma.rfis = NULL; 772 } 773 if (ch->dma.work_bus) { 774 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 775 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 776 ch->dma.work_bus = 0; 777 ch->dma.work_map = NULL; 778 ch->dma.work = NULL; 779 } 780 if (ch->dma.work_tag) { 781 bus_dma_tag_destroy(ch->dma.work_tag); 782 ch->dma.work_tag = NULL; 783 } 784} 785 786static void 787ahci_slotsalloc(device_t dev) 788{ 789 struct ahci_channel *ch = device_get_softc(dev); 790 int i; 791 792 /* Alloc and setup command/dma slots */ 793 bzero(ch->slot, sizeof(ch->slot)); 794 for (i = 0; i < ch->numslots; i++) { 795 struct ahci_slot *slot = &ch->slot[i]; 796 797 slot->dev = dev; 798 slot->slot = i; 799 slot->state = AHCI_SLOT_EMPTY; 800 slot->ccb = NULL; 801 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 802 803 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 804 device_printf(ch->dev, "FAILURE - create data_map\n"); 805 } 806} 807 808static void 809ahci_slotsfree(device_t dev) 810{ 811 struct ahci_channel *ch = device_get_softc(dev); 812 int i; 813 814 /* Free all dma slots */ 815 for (i = 0; i < ch->numslots; i++) { 816 struct ahci_slot *slot = &ch->slot[i]; 817 818 if (slot->dma.data_map) { 819 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 820 slot->dma.data_map = NULL; 821 } 822 } 823} 824 825static void 826ahci_phy_check_events(device_t dev) 827{ 828 struct ahci_channel *ch = device_get_softc(dev); 829 u_int32_t error = ATA_INL(ch->r_mem, AHCI_P_SERR); 830 831 /* Clear error bits/interrupt */ 832 ATA_OUTL(ch->r_mem, AHCI_P_SERR, error); 833 /* If we have a connection event, deal with it */ 834 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 835 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 836 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 837 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 838 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 839 if (bootverbose) 840 device_printf(dev, "CONNECT requested\n"); 841 ahci_reset(dev); 842 } else { 843 if (bootverbose) 844 device_printf(dev, "DISCONNECT requested\n"); 845 ch->devices = 0; 846 } 847 } 848} 849 850static void 851ahci_ch_intr_locked(void *data) 852{ 853 device_t dev = (device_t)data; 854 struct ahci_channel *ch = device_get_softc(dev); 855 856 mtx_lock(&ch->mtx); 857 ahci_ch_intr(data); 858 mtx_unlock(&ch->mtx); 859} 860 861static void 862ahci_ch_intr(void *data) 863{ 864 device_t dev = (device_t)data; 865 struct ahci_channel *ch = device_get_softc(dev); 866 uint32_t istatus, cstatus, sstatus, ok, err; 867 enum ahci_err_type et; 868 int i, ccs, ncq_err = 0; 869 870 /* Read and clear interrupt statuses. */ 871 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 872 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 873 /* Read command statuses. */ 874 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 875 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 876 /* Process PHY events */ 877 if (istatus & (AHCI_P_IX_PRC | AHCI_P_IX_PC)) 878 ahci_phy_check_events(dev); 879 /* Process command errors */ 880 if (istatus & (AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | 881 AHCI_P_IX_TFE | AHCI_P_IX_OF)) { 882//device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 883// __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 884// ATA_INL(ch->r_mem, AHCI_P_SERR)); 885 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 886 >> AHCI_P_CMD_CCS_SHIFT; 887 /* Kick controller into sane state */ 888 ahci_stop(dev); 889 ahci_start(dev); 890 ok = ch->rslots & ~(cstatus | sstatus); 891 err = ch->rslots & (cstatus | sstatus); 892 } else { 893 ccs = 0; 894 ok = ch->rslots & ~(cstatus | sstatus); 895 err = 0; 896 } 897 /* Complete all successfull commands. */ 898 for (i = 0; i < ch->numslots; i++) { 899 if ((ok >> i) & 1) 900 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 901 } 902 /* On error, complete the rest of commands with error statuses. */ 903 if (err) { 904 if (!ch->readlog) 905 xpt_freeze_simq(ch->sim, ch->numrslots); 906 if (ch->frozen) { 907 union ccb *fccb = ch->frozen; 908 ch->frozen = NULL; 909 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 910 xpt_done(fccb); 911 } 912 for (i = 0; i < ch->numslots; i++) { 913 /* XXX: reqests in loading state. */ 914 if (((err >> i) & 1) == 0) 915 continue; 916 if (istatus & AHCI_P_IX_TFE) { 917 /* Task File Error */ 918 if (ch->numtslots == 0) { 919 /* Untagged operation. */ 920 if (i == ccs) 921 et = AHCI_ERR_TFE; 922 else 923 et = AHCI_ERR_INNOCENT; 924 } else { 925 /* Tagged operation. */ 926 et = AHCI_ERR_NCQ; 927 ncq_err = 1; 928 } 929 } else if (istatus & AHCI_P_IX_IF) { 930 /* SATA error */ 931 et = AHCI_ERR_SATA; 932 } else 933 et = AHCI_ERR_INVALID; 934 ahci_end_transaction(&ch->slot[i], et); 935 } 936 if (ncq_err) 937 ahci_issue_read_log(dev); 938 } 939} 940 941/* Must be called with channel locked. */ 942static int 943ahci_check_collision(device_t dev, union ccb *ccb) 944{ 945 struct ahci_channel *ch = device_get_softc(dev); 946 947 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 948 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 949 /* Tagged command while untagged are active. */ 950 if (ch->numrslots != 0 && ch->numtslots == 0) 951 return (1); 952 /* Tagged command while tagged to other target is active. */ 953 if (ch->numtslots != 0 && 954 ch->taggedtarget != ccb->ccb_h.target_id) 955 return (1); 956 } else { 957 /* Untagged command while tagged are active. */ 958 if (ch->numrslots != 0 && ch->numtslots != 0) 959 return (1); 960 } 961 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 962 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 963 /* Atomic command while anything active. */ 964 if (ch->numrslots != 0) 965 return (1); 966 } 967 /* We have some atomic command running. */ 968 if (ch->aslots != 0) 969 return (1); 970 return (0); 971} 972 973/* Must be called with channel locked. */ 974static void 975ahci_begin_transaction(device_t dev, union ccb *ccb) 976{ 977 struct ahci_channel *ch = device_get_softc(dev); 978 struct ahci_slot *slot; 979 int tag; 980 981 /* Choose empty slot. */ 982 tag = ch->lastslot; 983 do { 984 tag++; 985 if (tag >= ch->numslots) 986 tag = 0; 987 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 988 break; 989 } while (tag != ch->lastslot); 990 if (ch->slot[tag].state != AHCI_SLOT_EMPTY) 991 device_printf(ch->dev, "ALL SLOTS BUSY!\n"); 992 ch->lastslot = tag; 993 /* Occupy chosen slot. */ 994 slot = &ch->slot[tag]; 995 slot->ccb = ccb; 996 /* Update channel stats. */ 997 ch->numrslots++; 998 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 999 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1000 ch->numtslots++; 1001 ch->taggedtarget = ccb->ccb_h.target_id; 1002 } 1003 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1004 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1005 ch->aslots |= (1 << slot->slot); 1006 slot->dma.nsegs = 0; 1007 /* If request moves data, setup and load SG list */ 1008 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1009 void *buf; 1010 bus_size_t size; 1011 1012 slot->state = AHCI_SLOT_LOADING; 1013 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1014 buf = ccb->ataio.data_ptr; 1015 size = ccb->ataio.dxfer_len; 1016 } else { 1017 buf = ccb->csio.data_ptr; 1018 size = ccb->csio.dxfer_len; 1019 } 1020 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1021 buf, size, ahci_dmasetprd, slot, 0); 1022 } else 1023 ahci_execute_transaction(slot); 1024} 1025 1026/* Locked by busdma engine. */ 1027static void 1028ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1029{ 1030 struct ahci_slot *slot = arg; 1031 struct ahci_channel *ch = device_get_softc(slot->dev); 1032 struct ahci_cmd_tab *ctp; 1033 struct ahci_dma_prd *prd; 1034 int i; 1035 1036 if (error) { 1037 device_printf(slot->dev, "DMA load error\n"); 1038 if (!ch->readlog) 1039 xpt_freeze_simq(ch->sim, 1); 1040 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1041 return; 1042 } 1043 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1044 /* Get a piece of the workspace for this request */ 1045 ctp = (struct ahci_cmd_tab *) 1046 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1047 /* Fill S/G table */ 1048 prd = &ctp->prd_tab[0]; 1049 for (i = 0; i < nsegs; i++) { 1050 prd[i].dba = htole64(segs[i].ds_addr); 1051 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1052 } 1053 slot->dma.nsegs = nsegs; 1054 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1055 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1056 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1057 ahci_execute_transaction(slot); 1058} 1059 1060/* Must be called with channel locked. */ 1061static void 1062ahci_execute_transaction(struct ahci_slot *slot) 1063{ 1064 device_t dev = slot->dev; 1065 struct ahci_channel *ch = device_get_softc(dev); 1066 struct ahci_cmd_tab *ctp; 1067 struct ahci_cmd_list *clp; 1068 union ccb *ccb = slot->ccb; 1069 int port = ccb->ccb_h.target_id & 0x0f; 1070 int fis_size; 1071 1072 /* Get a piece of the workspace for this request */ 1073 ctp = (struct ahci_cmd_tab *) 1074 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1075 /* Setup the FIS for this request */ 1076 if (!(fis_size = ahci_setup_fis(ctp, ccb, slot->slot))) { 1077 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1078 if (!ch->readlog) 1079 xpt_freeze_simq(ch->sim, 1); 1080 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1081 return; 1082 } 1083 /* Setup the command list entry */ 1084 clp = (struct ahci_cmd_list *) 1085 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1086 clp->prd_length = slot->dma.nsegs; 1087 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1088 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1089 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1090 (fis_size / sizeof(u_int32_t)) | 1091 (port << 12); 1092 /* Special handling for Soft Reset command. */ 1093 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1094 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1095 (ccb->ataio.cmd.control & ATA_A_RESET)) { 1096 /* Kick controller into sane state */ 1097 ahci_stop(dev); 1098 ahci_clo(dev); 1099 ahci_start(dev); 1100 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1101 } 1102 clp->bytecount = 0; 1103 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1104 (AHCI_CT_SIZE * slot->slot)); 1105 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1106 BUS_DMASYNC_PREWRITE); 1107 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1108 BUS_DMASYNC_PREREAD); 1109 /* Set ACTIVE bit for NCQ commands. */ 1110 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1111 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1112 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1113 } 1114 /* Issue command to the controller. */ 1115 slot->state = AHCI_SLOT_RUNNING; 1116 ch->rslots |= (1 << slot->slot); 1117 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1118 /* Device reset commands doesn't interrupt. Poll them. */ 1119 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1120 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1121 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1122 int count, timeout = ccb->ccb_h.timeout; 1123 enum ahci_err_type et = AHCI_ERR_NONE; 1124 1125 for (count = 0; count < timeout; count++) { 1126 DELAY(1000); 1127 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1128 break; 1129 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1130 device_printf(ch->dev, 1131 "Poll error on slot %d, TFD: %04x\n", 1132 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1133 et = AHCI_ERR_TFE; 1134 break; 1135 } 1136 } 1137 if (timeout && (count >= timeout)) { 1138 device_printf(ch->dev, 1139 "Poll timeout on slot %d\n", slot->slot); 1140 et = AHCI_ERR_TIMEOUT; 1141 } 1142 if (et != AHCI_ERR_NONE) { 1143 /* Kick controller into sane state */ 1144 ahci_stop(ch->dev); 1145 ahci_start(ch->dev); 1146 xpt_freeze_simq(ch->sim, 1); 1147 } 1148 ahci_end_transaction(slot, et); 1149 return; 1150 } 1151 /* Start command execution timeout */ 1152 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1153 (timeout_t*)ahci_timeout, slot); 1154 return; 1155} 1156 1157/* Locked by callout mechanism. */ 1158static void 1159ahci_timeout(struct ahci_slot *slot) 1160{ 1161 device_t dev = slot->dev; 1162 struct ahci_channel *ch = device_get_softc(dev); 1163 int i; 1164 1165 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1166 /* Kick controller into sane state. */ 1167 ahci_stop(ch->dev); 1168 ahci_start(ch->dev); 1169 1170 if (!ch->readlog) 1171 xpt_freeze_simq(ch->sim, ch->numrslots); 1172 /* Handle command with timeout. */ 1173 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1174 /* Handle the rest of commands. */ 1175 if (ch->frozen) { 1176 union ccb *fccb = ch->frozen; 1177 ch->frozen = NULL; 1178 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1179 xpt_done(fccb); 1180 } 1181 for (i = 0; i < ch->numslots; i++) { 1182 /* Do we have a running request on slot? */ 1183 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1184 continue; 1185 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1186 } 1187} 1188 1189/* Must be called with channel locked. */ 1190static void 1191ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1192{ 1193 device_t dev = slot->dev; 1194 struct ahci_channel *ch = device_get_softc(dev); 1195 union ccb *ccb = slot->ccb; 1196 1197 /* Cancel command execution timeout */ 1198 callout_stop(&slot->timeout); 1199 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1200 BUS_DMASYNC_POSTWRITE); 1201 /* Read result registers to the result struct 1202 * May be incorrect if several commands finished same time, 1203 * so read only when sure or have to. 1204 */ 1205 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1206 struct ata_res *res = &ccb->ataio.res; 1207 1208 if ((et == AHCI_ERR_TFE) || 1209 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1210 u_int8_t *fis = ch->dma.rfis + 0x40; 1211 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1212 1213 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1214 BUS_DMASYNC_POSTREAD); 1215 res->status = tfd; 1216 res->error = tfd >> 8; 1217 res->lba_low = fis[4]; 1218 res->lba_mid = fis[5]; 1219 res->lba_high = fis[6]; 1220 res->device = fis[7]; 1221 res->lba_low_exp = fis[8]; 1222 res->lba_mid_exp = fis[9]; 1223 res->lba_high_exp = fis[10]; 1224 res->sector_count = fis[12]; 1225 res->sector_count_exp = fis[13]; 1226 } else 1227 bzero(res, sizeof(*res)); 1228 } 1229 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1230 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1231 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1232 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1233 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1234 } 1235 /* Set proper result status. */ 1236 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1237 if (et != AHCI_ERR_NONE) 1238 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1239 switch (et) { 1240 case AHCI_ERR_NONE: 1241 ccb->ccb_h.status |= CAM_REQ_CMP; 1242 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1243 ccb->csio.scsi_status = SCSI_STATUS_OK; 1244 break; 1245 case AHCI_ERR_INVALID: 1246 ccb->ccb_h.status |= CAM_REQ_INVALID; 1247 break; 1248 case AHCI_ERR_INNOCENT: 1249 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1250 break; 1251 case AHCI_ERR_TFE: 1252 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1253 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1254 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1255 } else { 1256 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1257 } 1258 break; 1259 case AHCI_ERR_SATA: 1260 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1261 break; 1262 case AHCI_ERR_TIMEOUT: 1263 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1264 break; 1265 case AHCI_ERR_NCQ: 1266 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1267 default: 1268 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1269 } 1270 /* Free slot. */ 1271 ch->rslots &= ~(1 << slot->slot); 1272 ch->aslots &= ~(1 << slot->slot); 1273 slot->state = AHCI_SLOT_EMPTY; 1274 slot->ccb = NULL; 1275 /* Update channel stats. */ 1276 ch->numrslots--; 1277 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1278 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1279 ch->numtslots--; 1280 } 1281 /* If it was first request of reset sequence and there is no error, 1282 * proceed to second request. */ 1283 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1284 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1285 (ccb->ataio.cmd.control & ATA_A_RESET) && 1286 et == AHCI_ERR_NONE) { 1287 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1288 ahci_begin_transaction(dev, ccb); 1289 return; 1290 } 1291 /* If it was NCQ command error, put result on hold. */ 1292 if (et == AHCI_ERR_NCQ) { 1293 ch->hold[slot->slot] = ccb; 1294 } else if (ch->readlog) /* If it was our READ LOG command - process it. */ 1295 ahci_process_read_log(dev, ccb); 1296 else 1297 xpt_done(ccb); 1298 /* Unfreeze frozen command. */ 1299 if (ch->frozen && ch->numrslots == 0) { 1300 union ccb *fccb = ch->frozen; 1301 ch->frozen = NULL; 1302 ahci_begin_transaction(dev, fccb); 1303 xpt_release_simq(ch->sim, TRUE); 1304 } 1305} 1306 1307static void 1308ahci_issue_read_log(device_t dev) 1309{ 1310 struct ahci_channel *ch = device_get_softc(dev); 1311 union ccb *ccb; 1312 struct ccb_ataio *ataio; 1313 int i; 1314 1315 ch->readlog = 1; 1316 /* Find some holden command. */ 1317 for (i = 0; i < ch->numslots; i++) { 1318 if (ch->hold[i]) 1319 break; 1320 } 1321 ccb = xpt_alloc_ccb_nowait(); 1322 if (ccb == NULL) { 1323 device_printf(dev, "Unable allocate READ LOG command"); 1324 return; /* XXX */ 1325 } 1326 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1327 ccb->ccb_h.func_code = XPT_ATA_IO; 1328 ccb->ccb_h.flags = CAM_DIR_IN; 1329 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1330 ataio = &ccb->ataio; 1331 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1332 if (ataio->data_ptr == NULL) { 1333 device_printf(dev, "Unable allocate memory for READ LOG command"); 1334 return; /* XXX */ 1335 } 1336 ataio->dxfer_len = 512; 1337 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1338 ataio->cmd.flags = CAM_ATAIO_48BIT; 1339 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1340 ataio->cmd.sector_count = 1; 1341 ataio->cmd.sector_count_exp = 0; 1342 ataio->cmd.lba_low = 0x10; 1343 ataio->cmd.lba_mid = 0; 1344 ataio->cmd.lba_mid_exp = 0; 1345 1346 ahci_begin_transaction(dev, ccb); 1347} 1348 1349static void 1350ahci_process_read_log(device_t dev, union ccb *ccb) 1351{ 1352 struct ahci_channel *ch = device_get_softc(dev); 1353 uint8_t *data; 1354 struct ata_res *res; 1355 int i; 1356 1357 ch->readlog = 0; 1358 1359 data = ccb->ataio.data_ptr; 1360 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1361 (data[0] & 0x80) == 0) { 1362 for (i = 0; i < ch->numslots; i++) { 1363 if (!ch->hold[i]) 1364 continue; 1365 if ((data[0] & 0x1F) == i) { 1366 res = &ch->hold[i]->ataio.res; 1367 res->status = data[2]; 1368 res->error = data[3]; 1369 res->lba_low = data[4]; 1370 res->lba_mid = data[5]; 1371 res->lba_high = data[6]; 1372 res->device = data[7]; 1373 res->lba_low_exp = data[8]; 1374 res->lba_mid_exp = data[9]; 1375 res->lba_high_exp = data[10]; 1376 res->sector_count = data[12]; 1377 res->sector_count_exp = data[13]; 1378 } else { 1379 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1380 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1381 } 1382 xpt_done(ch->hold[i]); 1383 ch->hold[i] = NULL; 1384 } 1385 } else { 1386 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1387 device_printf(dev, "Error while READ LOG EXT\n"); 1388 else if ((data[0] & 0x80) == 0) { 1389 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1390 } 1391 for (i = 0; i < ch->numslots; i++) { 1392 if (!ch->hold[i]) 1393 continue; 1394 xpt_done(ch->hold[i]); 1395 ch->hold[i] = NULL; 1396 } 1397 } 1398 free(ccb->ataio.data_ptr, M_AHCI); 1399 xpt_free_ccb(ccb); 1400} 1401 1402static void 1403ahci_start(device_t dev) 1404{ 1405 struct ahci_channel *ch = device_get_softc(dev); 1406 u_int32_t cmd; 1407 1408 /* Clear SATA error register */ 1409 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 1410 /* Clear any interrupts pending on this channel */ 1411 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 1412 /* Start operations on this channel */ 1413 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1414 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 1415 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 1416} 1417 1418static void 1419ahci_stop(device_t dev) 1420{ 1421 struct ahci_channel *ch = device_get_softc(dev); 1422 u_int32_t cmd; 1423 int timeout; 1424 1425 /* Kill all activity on this channel */ 1426 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1427 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 1428 /* Wait for activity stop. */ 1429 timeout = 0; 1430 do { 1431 DELAY(1000); 1432 if (timeout++ > 1000) { 1433 device_printf(dev, "stopping AHCI engine failed\n"); 1434 break; 1435 } 1436 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 1437} 1438 1439static void 1440ahci_clo(device_t dev) 1441{ 1442 struct ahci_channel *ch = device_get_softc(dev); 1443 u_int32_t cmd; 1444 int timeout; 1445 1446 /* Issue Command List Override if supported */ 1447 if (ch->caps & AHCI_CAP_SCLO) { 1448 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1449 cmd |= AHCI_P_CMD_CLO; 1450 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 1451 timeout = 0; 1452 do { 1453 DELAY(1000); 1454 if (timeout++ > 1000) { 1455 device_printf(dev, "executing CLO failed\n"); 1456 break; 1457 } 1458 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 1459 } 1460} 1461 1462static void 1463ahci_stop_fr(device_t dev) 1464{ 1465 struct ahci_channel *ch = device_get_softc(dev); 1466 u_int32_t cmd; 1467 int timeout; 1468 1469 /* Kill all FIS reception on this channel */ 1470 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1471 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 1472 /* Wait for FIS reception stop. */ 1473 timeout = 0; 1474 do { 1475 DELAY(1000); 1476 if (timeout++ > 1000) { 1477 device_printf(dev, "stopping AHCI FR engine failed\n"); 1478 break; 1479 } 1480 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 1481} 1482 1483static void 1484ahci_start_fr(device_t dev) 1485{ 1486 struct ahci_channel *ch = device_get_softc(dev); 1487 u_int32_t cmd; 1488 1489 /* Start FIS reception on this channel */ 1490 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 1491 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 1492} 1493 1494static int 1495ahci_wait_ready(device_t dev, int t) 1496{ 1497 struct ahci_channel *ch = device_get_softc(dev); 1498 int timeout = 0; 1499 uint32_t val; 1500 1501 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 1502 (ATA_S_BUSY | ATA_S_DRQ)) { 1503 DELAY(1000); 1504 if (timeout++ > t) { 1505 device_printf(dev, "port is not ready (timeout %dms) " 1506 "tfd = %08x\n", t, val); 1507 return (EBUSY); 1508 } 1509 } 1510 if (bootverbose) 1511 device_printf(dev, "ready wait time=%dms\n", timeout); 1512 return (0); 1513} 1514 1515static void 1516ahci_reset(device_t dev) 1517{ 1518 struct ahci_channel *ch = device_get_softc(dev); 1519 int i; 1520 1521 if (bootverbose) 1522 device_printf(dev, "AHCI reset...\n"); 1523 xpt_freeze_simq(ch->sim, ch->numrslots); 1524 /* Requeue freezed command. */ 1525 if (ch->frozen) { 1526 union ccb *fccb = ch->frozen; 1527 ch->frozen = NULL; 1528 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1529 xpt_done(fccb); 1530 } 1531 /* Kill the engine and requeue all running commands. */ 1532 ahci_stop(dev); 1533 for (i = 0; i < ch->numslots; i++) { 1534 /* Do we have a running request on slot? */ 1535 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1536 continue; 1537 /* XXX; Commands in loading state. */ 1538 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1539 } 1540 /* Disable port interrupts */ 1541 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1542 /* Reset and reconnect PHY, */ 1543 if (!ahci_sata_phy_reset(dev, 0)) { 1544 if (bootverbose) 1545 device_printf(dev, 1546 "AHCI reset done: phy reset found no device\n"); 1547 ch->devices = 0; 1548 /* Enable wanted port interrupts */ 1549 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1550 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 1551 return; 1552 } 1553 /* Wait for clearing busy status. */ 1554 if (ahci_wait_ready(dev, 10000)) { 1555 device_printf(dev, "device ready timeout\n"); 1556 ahci_clo(dev); 1557 } 1558 ahci_start(dev); 1559 ch->devices = 1; 1560 /* Enable wanted port interrupts */ 1561 ATA_OUTL(ch->r_mem, AHCI_P_IE, 1562 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 1563 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 1564 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 1565 AHCI_P_IX_DP | AHCI_P_IX_UF | AHCI_P_IX_SDB | 1566 AHCI_P_IX_DS | AHCI_P_IX_PS | AHCI_P_IX_DHR)); 1567 if (bootverbose) 1568 device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices); 1569 /* Tell the XPT about the event */ 1570 xpt_async(AC_BUS_RESET, ch->path, NULL); 1571} 1572 1573static int 1574ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 1575{ 1576 u_int8_t *fis = &ctp->cfis[0]; 1577 1578 bzero(ctp->cfis, 64); 1579 fis[0] = 0x27; /* host to device */ 1580 fis[1] = (ccb->ccb_h.target_id & 0x0f); 1581 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1582 fis[1] |= 0x80; 1583 fis[2] = ATA_PACKET_CMD; 1584 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1585 fis[3] = ATA_F_DMA; 1586 else { 1587 fis[5] = ccb->csio.dxfer_len; 1588 fis[6] = ccb->csio.dxfer_len >> 8; 1589 } 1590 fis[7] = ATA_D_LBA; 1591 fis[15] = ATA_A_4BIT; 1592 bzero(ctp->acmd, 32); 1593 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1594 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 1595 ctp->acmd, ccb->csio.cdb_len); 1596 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 1597 fis[1] |= 0x80; 1598 fis[2] = ccb->ataio.cmd.command; 1599 fis[3] = ccb->ataio.cmd.features; 1600 fis[4] = ccb->ataio.cmd.lba_low; 1601 fis[5] = ccb->ataio.cmd.lba_mid; 1602 fis[6] = ccb->ataio.cmd.lba_high; 1603 fis[7] = ccb->ataio.cmd.device; 1604 fis[8] = ccb->ataio.cmd.lba_low_exp; 1605 fis[9] = ccb->ataio.cmd.lba_mid_exp; 1606 fis[10] = ccb->ataio.cmd.lba_high_exp; 1607 fis[11] = ccb->ataio.cmd.features_exp; 1608 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1609 fis[12] = tag << 3; 1610 fis[13] = 0; 1611 } else { 1612 fis[12] = ccb->ataio.cmd.sector_count; 1613 fis[13] = ccb->ataio.cmd.sector_count_exp; 1614 } 1615 fis[15] = ATA_A_4BIT; 1616 } else { 1617 fis[15] = ccb->ataio.cmd.control; 1618 } 1619 return (20); 1620} 1621 1622static int 1623ahci_sata_connect(struct ahci_channel *ch) 1624{ 1625 u_int32_t status; 1626 int timeout; 1627 1628 /* Wait up to 100ms for "connect well" */ 1629 for (timeout = 0; timeout < 100 ; timeout++) { 1630 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1631 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1632 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1633 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 1634 break; 1635 DELAY(1000); 1636 } 1637 if (timeout >= 100) { 1638 if (bootverbose) { 1639 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 1640 status); 1641 } 1642 return (0); 1643 } 1644 if (bootverbose) { 1645 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 1646 timeout, status); 1647 } 1648 /* Clear SATA error register */ 1649 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 1650 return (1); 1651} 1652 1653static int 1654ahci_sata_phy_reset(device_t dev, int quick) 1655{ 1656 struct ahci_channel *ch = device_get_softc(dev); 1657 uint32_t val; 1658 1659 if (quick) { 1660 val = ATA_INL(ch->r_mem, AHCI_P_SCTL); 1661 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) 1662 return (ahci_sata_connect(ch)); 1663 } 1664 1665 if (bootverbose) 1666 device_printf(dev, "hardware reset ...\n"); 1667 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_IPM_DIS_PARTIAL | 1668 ATA_SC_IPM_DIS_SLUMBER | ATA_SC_DET_RESET); 1669 DELAY(50000); 1670 if (ch->sata_rev == 1) 1671 val = ATA_SC_SPD_SPEED_GEN1; 1672 else if (ch->sata_rev == 2) 1673 val = ATA_SC_SPD_SPEED_GEN2; 1674 else if (ch->sata_rev == 3) 1675 val = ATA_SC_SPD_SPEED_GEN3; 1676 else 1677 val = 0; 1678 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 1679 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 1680 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 1681 DELAY(50000); 1682 return (ahci_sata_connect(ch)); 1683} 1684 1685static void 1686ahciaction(struct cam_sim *sim, union ccb *ccb) 1687{ 1688 device_t dev; 1689 struct ahci_channel *ch; 1690 1691 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 1692 ccb->ccb_h.func_code)); 1693 1694 ch = (struct ahci_channel *)cam_sim_softc(sim); 1695 dev = ch->dev; 1696 switch (ccb->ccb_h.func_code) { 1697 /* Common cases first */ 1698 case XPT_ATA_IO: /* Execute the requested I/O operation */ 1699 case XPT_SCSI_IO: 1700 if (ch->devices == 0) { 1701 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1702 xpt_done(ccb); 1703 break; 1704 } 1705 /* Check for command collision. */ 1706 if (ahci_check_collision(dev, ccb)) { 1707 /* Freeze command. */ 1708 ch->frozen = ccb; 1709 /* We have only one frozen slot, so freeze simq also. */ 1710 xpt_freeze_simq(ch->sim, 1); 1711 return; 1712 } 1713 ahci_begin_transaction(dev, ccb); 1714 break; 1715 case XPT_EN_LUN: /* Enable LUN as a target */ 1716 case XPT_TARGET_IO: /* Execute target I/O request */ 1717 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 1718 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 1719 case XPT_ABORT: /* Abort the specified CCB */ 1720 /* XXX Implement */ 1721 ccb->ccb_h.status = CAM_REQ_INVALID; 1722 xpt_done(ccb); 1723 break; 1724 case XPT_SET_TRAN_SETTINGS: 1725 { 1726 struct ccb_trans_settings *cts = &ccb->cts; 1727 1728 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) { 1729 ch->pm_present = cts->xport_specific.sata.pm_present; 1730 } 1731 ccb->ccb_h.status = CAM_REQ_CMP; 1732 xpt_done(ccb); 1733 break; 1734 } 1735 case XPT_GET_TRAN_SETTINGS: 1736 /* Get default/user set transfer settings for the target */ 1737 { 1738 struct ccb_trans_settings *cts = &ccb->cts; 1739 uint32_t status; 1740 1741 cts->protocol = PROTO_ATA; 1742 cts->protocol_version = SCSI_REV_2; 1743 cts->transport = XPORT_SATA; 1744 cts->transport_version = 2; 1745 cts->proto_specific.valid = 0; 1746 cts->xport_specific.sata.valid = 0; 1747 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 1748 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 1749 else 1750 status = ATA_INL(ch->r_mem, AHCI_P_SCTL) & ATA_SC_SPD_MASK; 1751 if (status & ATA_SS_SPD_GEN3) { 1752 cts->xport_specific.sata.bitrate = 600000; 1753 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 1754 } else if (status & ATA_SS_SPD_GEN2) { 1755 cts->xport_specific.sata.bitrate = 300000; 1756 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 1757 } else if (status & ATA_SS_SPD_GEN1) { 1758 cts->xport_specific.sata.bitrate = 150000; 1759 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED; 1760 } 1761 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 1762 cts->xport_specific.sata.pm_present = 1763 (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_PMA) ? 1764 1 : 0; 1765 } else { 1766 cts->xport_specific.sata.pm_present = ch->pm_present; 1767 } 1768 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 1769 ccb->ccb_h.status = CAM_REQ_CMP; 1770 xpt_done(ccb); 1771 break; 1772 } 1773#if 0 1774 case XPT_CALC_GEOMETRY: 1775 { 1776 struct ccb_calc_geometry *ccg; 1777 uint32_t size_mb; 1778 uint32_t secs_per_cylinder; 1779 1780 ccg = &ccb->ccg; 1781 size_mb = ccg->volume_size 1782 / ((1024L * 1024L) / ccg->block_size); 1783 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 1784 if (size_mb >= 2048) { 1785 ccg->heads = 255; 1786 ccg->secs_per_track = 63; 1787 } else { 1788 ccg->heads = 128; 1789 ccg->secs_per_track = 32; 1790 } 1791 } else { 1792 ccg->heads = 64; 1793 ccg->secs_per_track = 32; 1794 } 1795 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 1796 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 1797 ccb->ccb_h.status = CAM_REQ_CMP; 1798 xpt_done(ccb); 1799 break; 1800 } 1801#endif 1802 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 1803 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 1804 ahci_reset(dev); 1805 ccb->ccb_h.status = CAM_REQ_CMP; 1806 xpt_done(ccb); 1807 break; 1808 case XPT_TERM_IO: /* Terminate the I/O process */ 1809 /* XXX Implement */ 1810 ccb->ccb_h.status = CAM_REQ_INVALID; 1811 xpt_done(ccb); 1812 break; 1813 case XPT_PATH_INQ: /* Path routing inquiry */ 1814 { 1815 struct ccb_pathinq *cpi = &ccb->cpi; 1816 1817 cpi->version_num = 1; /* XXX??? */ 1818 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 1819 if (ch->caps & AHCI_CAP_SPM) 1820 cpi->hba_inquiry |= PI_SATAPM; 1821 cpi->target_sprt = 0; 1822 cpi->hba_misc = PIM_SEQSCAN; 1823 cpi->hba_eng_cnt = 0; 1824 if (ch->caps & AHCI_CAP_SPM) 1825 cpi->max_target = 14; 1826 else 1827 cpi->max_target = 0; 1828 cpi->max_lun = 0; 1829 cpi->initiator_id = 0; 1830 cpi->bus_id = cam_sim_bus(sim); 1831 cpi->base_transfer_speed = 150000; 1832 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1833 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 1834 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1835 cpi->unit_number = cam_sim_unit(sim); 1836 cpi->transport = XPORT_SATA; 1837 cpi->transport_version = 2; 1838 cpi->protocol = PROTO_ATA; 1839 cpi->protocol_version = SCSI_REV_2; 1840 cpi->maxio = MAXPHYS; 1841 cpi->ccb_h.status = CAM_REQ_CMP; 1842 xpt_done(ccb); 1843 break; 1844 } 1845 default: 1846 ccb->ccb_h.status = CAM_REQ_INVALID; 1847 xpt_done(ccb); 1848 break; 1849 } 1850} 1851 1852static void 1853ahcipoll(struct cam_sim *sim) 1854{ 1855 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 1856 1857 ahci_ch_intr(ch->dev); 1858} 1859