agp_i810.c revision 177115
1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * Copyright (c) 2000 Ruslan Ermilov 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org> 30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org> 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/agp/agp_i810.c 177115 2008-03-12 18:23:39Z remko $"); 35 36#include "opt_bus.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46#include <sys/proc.h> 47 48#include <dev/agp/agppriv.h> 49#include <dev/agp/agpreg.h> 50#include <dev/pci/pcivar.h> 51#include <dev/pci/pcireg.h> 52 53#include <vm/vm.h> 54#include <vm/vm_object.h> 55#include <vm/vm_page.h> 56#include <vm/vm_pageout.h> 57#include <vm/pmap.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <machine/md_var.h> 62#include <sys/rman.h> 63 64MALLOC_DECLARE(M_AGP); 65 66enum { 67 CHIP_I810, /* i810/i815 */ 68 CHIP_I830, /* 830M/845G */ 69 CHIP_I855, /* 852GM/855GM/865G */ 70 CHIP_I915, /* 915G/915GM */ 71 CHIP_I965, /* G965 */ 72 CHIP_G33, /* G33/Q33/Q35 */ 73}; 74 75/* The i810 through i855 have the registers at BAR 1, and the GATT gets 76 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the 77 * start of the stolen memory, and should only be accessed by the OS through 78 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB 79 * is registers, second 512KB is GATT. 80 */ 81static struct resource_spec agp_i810_res_spec[] = { 82 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE }, 83 { -1, 0 } 84}; 85 86static struct resource_spec agp_i915_res_spec[] = { 87 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE }, 88 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE }, 89 { -1, 0 } 90}; 91 92static struct resource_spec agp_i965_res_spec[] = { 93 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE }, 94 { -1, 0 } 95}; 96 97struct agp_i810_softc { 98 struct agp_softc agp; 99 u_int32_t initial_aperture; /* aperture size at startup */ 100 struct agp_gatt *gatt; 101 int chiptype; /* i810-like or i830 */ 102 u_int32_t dcache_size; /* i810 only */ 103 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */ 104 device_t bdev; /* bridge device */ 105 106 void *argb_cursor; /* contigmalloc area for ARGB cursor */ 107 108 struct resource_spec * sc_res_spec; 109 struct resource *sc_res[2]; 110}; 111 112/* For adding new devices, devid is the id of the graphics controller 113 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the 114 * second head should never be added. The bridge_offset is the offset to 115 * subtract from devid to get the id of the hostb that the device is on. 116 */ 117static const struct agp_i810_match { 118 int devid; 119 int chiptype; 120 int bridge_offset; 121 char *name; 122} agp_i810_matches[] = { 123 {0x71218086, CHIP_I810, 0x00010000, 124 "Intel 82810 (i810 GMCH) SVGA controller"}, 125 {0x71238086, CHIP_I810, 0x00010000, 126 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"}, 127 {0x71258086, CHIP_I810, 0x00010000, 128 "Intel 82810E (i810E GMCH) SVGA controller"}, 129 {0x11328086, CHIP_I810, 0x00020000, 130 "Intel 82815 (i815 GMCH) SVGA controller"}, 131 {0x35778086, CHIP_I830, 0x00020000, 132 "Intel 82830M (830M GMCH) SVGA controller"}, 133 {0x25628086, CHIP_I830, 0x00020000, 134 "Intel 82845M (845M GMCH) SVGA controller"}, 135 {0x35828086, CHIP_I855, 0x00020000, 136 "Intel 82852/5"}, 137 {0x25728086, CHIP_I855, 0x00020000, 138 "Intel 82865G (865G GMCH) SVGA controller"}, 139 {0x25828086, CHIP_I915, 0x00020000, 140 "Intel 82915G (915G GMCH) SVGA controller"}, 141 {0x258A8086, CHIP_I915, 0x00020000, 142 "Intel E7221 SVGA controller"}, 143 {0x25928086, CHIP_I915, 0x00020000, 144 "Intel 82915GM (915GM GMCH) SVGA controller"}, 145 {0x27728086, CHIP_I915, 0x00020000, 146 "Intel 82945G (945G GMCH) SVGA controller"}, 147 {0x27A28086, CHIP_I915, 0x00020000, 148 "Intel 82945GM (945GM GMCH) SVGA controller"}, 149 {0x27A28086, CHIP_I915, 0x00020000, 150 "Intel 945GME SVGA controller"}, 151 {0x29728086, CHIP_I965, 0x00020000, 152 "Intel 946GZ SVGA controller"}, 153 {0x29828086, CHIP_I965, 0x00020000, 154 "Intel G965 SVGA controller"}, 155 {0x29928086, CHIP_I965, 0x00020000, 156 "Intel Q965 SVGA controller"}, 157 {0x29a28086, CHIP_I965, 0x00020000, 158 "Intel G965 SVGA controller"}, 159/* 160 {0x29b28086, CHIP_G33, 0x00020000, 161 "Intel Q35 SVGA controller"}, 162 {0x29c28086, CHIP_G33, 0x00020000, 163 "Intel G33 SVGA controller"}, 164 {0x29d28086, CHIP_G33, 0x00020000, 165 "Intel Q33 SVGA controller"}, 166*/ 167 {0x2a028086, CHIP_I965, 0x00020000, 168 "Intel GM965 SVGA controller"}, 169 {0x2a128086, CHIP_I965, 0x00020000, 170 "Intel GME965 SVGA controller"}, 171 {0, 0, 0, NULL} 172}; 173 174static const struct agp_i810_match* 175agp_i810_match(device_t dev) 176{ 177 int i, devid; 178 179 if (pci_get_class(dev) != PCIC_DISPLAY 180 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA) 181 return NULL; 182 183 devid = pci_get_devid(dev); 184 for (i = 0; agp_i810_matches[i].devid != 0; i++) { 185 if (agp_i810_matches[i].devid == devid) 186 break; 187 } 188 if (agp_i810_matches[i].devid == 0) 189 return NULL; 190 else 191 return &agp_i810_matches[i]; 192} 193 194/* 195 * Find bridge device. 196 */ 197static device_t 198agp_i810_find_bridge(device_t dev) 199{ 200 device_t *children, child; 201 int nchildren, i; 202 u_int32_t devid; 203 const struct agp_i810_match *match; 204 205 match = agp_i810_match(dev); 206 devid = match->devid - match->bridge_offset; 207 208 if (device_get_children(device_get_parent(device_get_parent(dev)), 209 &children, &nchildren)) 210 return 0; 211 212 for (i = 0; i < nchildren; i++) { 213 child = children[i]; 214 215 if (pci_get_devid(child) == devid) { 216 free(children, M_TEMP); 217 return child; 218 } 219 } 220 free(children, M_TEMP); 221 return 0; 222} 223 224static void 225agp_i810_identify(driver_t *driver, device_t parent) 226{ 227 228 if (device_find_child(parent, "agp", -1) == NULL && 229 agp_i810_match(parent)) 230 device_add_child(parent, "agp", -1); 231} 232 233static int 234agp_i810_probe(device_t dev) 235{ 236 device_t bdev; 237 const struct agp_i810_match *match; 238 u_int8_t smram; 239 int gcc1, deven; 240 241 if (resource_disabled("agp", device_get_unit(dev))) 242 return (ENXIO); 243 match = agp_i810_match(dev); 244 if (match == NULL) 245 return ENXIO; 246 247 bdev = agp_i810_find_bridge(dev); 248 if (!bdev) { 249 if (bootverbose) 250 printf("I810: can't find bridge device\n"); 251 return ENXIO; 252 } 253 254 /* 255 * checking whether internal graphics device has been activated. 256 */ 257 switch (match->chiptype) { 258 case CHIP_I810: 259 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1); 260 if ((smram & AGP_I810_SMRAM_GMS) == 261 AGP_I810_SMRAM_GMS_DISABLED) { 262 if (bootverbose) 263 printf("I810: disabled, not probing\n"); 264 return ENXIO; 265 } 266 break; 267 case CHIP_I830: 268 case CHIP_I855: 269 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1); 270 if ((gcc1 & AGP_I830_GCC1_DEV2) == 271 AGP_I830_GCC1_DEV2_DISABLED) { 272 if (bootverbose) 273 printf("I830: disabled, not probing\n"); 274 return ENXIO; 275 } 276 break; 277 case CHIP_I915: 278 case CHIP_I965: 279 case CHIP_G33: 280 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4); 281 if ((deven & AGP_I915_DEVEN_D2F0) == 282 AGP_I915_DEVEN_D2F0_DISABLED) { 283 if (bootverbose) 284 printf("I915: disabled, not probing\n"); 285 return ENXIO; 286 } 287 break; 288 } 289 290 if (match->devid == 0x35828086) { 291 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { 292 case AGP_I855_GME: 293 device_set_desc(dev, 294 "Intel 82855GME (855GME GMCH) SVGA controller"); 295 break; 296 case AGP_I855_GM: 297 device_set_desc(dev, 298 "Intel 82855GM (855GM GMCH) SVGA controller"); 299 break; 300 case AGP_I852_GME: 301 device_set_desc(dev, 302 "Intel 82852GME (852GME GMCH) SVGA controller"); 303 break; 304 case AGP_I852_GM: 305 device_set_desc(dev, 306 "Intel 82852GM (852GM GMCH) SVGA controller"); 307 break; 308 default: 309 device_set_desc(dev, 310 "Intel 8285xM (85xGM GMCH) SVGA controller"); 311 break; 312 } 313 } else { 314 device_set_desc(dev, match->name); 315 } 316 317 return BUS_PROBE_DEFAULT; 318} 319 320static void 321agp_i810_dump_regs(device_t dev) 322{ 323 struct agp_i810_softc *sc = device_get_softc(dev); 324 325 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", 326 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); 327 328 switch (sc->chiptype) { 329 case CHIP_I810: 330 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n", 331 pci_read_config(sc->bdev, AGP_I810_MISCC, 2)); 332 break; 333 case CHIP_I830: 334 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n", 335 pci_read_config(sc->bdev, AGP_I830_GCC1, 1)); 336 break; 337 case CHIP_I855: 338 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", 339 pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); 340 break; 341 case CHIP_I915: 342 case CHIP_I965: 343 case CHIP_G33: 344 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", 345 pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); 346 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n", 347 pci_read_config(sc->bdev, AGP_I915_MSAC, 1)); 348 break; 349 } 350 device_printf(dev, "Aperture resource size: %d bytes\n", 351 AGP_GET_APERTURE(dev)); 352} 353 354static int 355agp_i810_attach(device_t dev) 356{ 357 struct agp_i810_softc *sc = device_get_softc(dev); 358 struct agp_gatt *gatt; 359 const struct agp_i810_match *match; 360 int error; 361 362 sc->bdev = agp_i810_find_bridge(dev); 363 if (!sc->bdev) 364 return ENOENT; 365 366 match = agp_i810_match(dev); 367 sc->chiptype = match->chiptype; 368 369 switch (sc->chiptype) { 370 case CHIP_I810: 371 case CHIP_I830: 372 case CHIP_I855: 373 sc->sc_res_spec = agp_i810_res_spec; 374 agp_set_aperture_resource(dev, AGP_APBASE); 375 break; 376 case CHIP_I915: 377 case CHIP_G33: 378 sc->sc_res_spec = agp_i915_res_spec; 379 agp_set_aperture_resource(dev, AGP_I915_GMADR); 380 break; 381 case CHIP_I965: 382 sc->sc_res_spec = agp_i965_res_spec; 383 agp_set_aperture_resource(dev, AGP_I915_GMADR); 384 break; 385 } 386 387 error = agp_generic_attach(dev); 388 if (error) 389 return error; 390 391 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 && 392 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful) 393 { 394 device_printf(dev, "agp_i810.c does not support physical " 395 "memory above 4GB.\n"); 396 return ENOENT; 397 } 398 399 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) { 400 agp_generic_detach(dev); 401 return ENODEV; 402 } 403 404 sc->initial_aperture = AGP_GET_APERTURE(dev); 405 406 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 407 if (!gatt) { 408 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res); 409 agp_generic_detach(dev); 410 return ENOMEM; 411 } 412 sc->gatt = gatt; 413 414 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; 415 416 if ( sc->chiptype == CHIP_I810 ) { 417 /* Some i810s have on-chip memory called dcache */ 418 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) & 419 AGP_I810_DRT_POPULATED) 420 sc->dcache_size = 4 * 1024 * 1024; 421 else 422 sc->dcache_size = 0; 423 424 /* According to the specs the gatt on the i810 must be 64k */ 425 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0, 426 0, ~0, PAGE_SIZE, 0); 427 if (!gatt->ag_virtual) { 428 if (bootverbose) 429 device_printf(dev, "contiguous allocation failed\n"); 430 bus_release_resources(dev, sc->sc_res_spec, 431 sc->sc_res); 432 free(gatt, M_AGP); 433 agp_generic_detach(dev); 434 return ENOMEM; 435 } 436 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t)); 437 438 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); 439 agp_flush_cache(); 440 /* Install the GATT. */ 441 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 442 gatt->ag_physical | 1); 443 } else if ( sc->chiptype == CHIP_I830 ) { 444 /* The i830 automatically initializes the 128k gatt on boot. */ 445 unsigned int gcc1, pgtblctl; 446 447 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); 448 switch (gcc1 & AGP_I830_GCC1_GMS) { 449 case AGP_I830_GCC1_GMS_STOLEN_512: 450 sc->stolen = (512 - 132) * 1024 / 4096; 451 break; 452 case AGP_I830_GCC1_GMS_STOLEN_1024: 453 sc->stolen = (1024 - 132) * 1024 / 4096; 454 break; 455 case AGP_I830_GCC1_GMS_STOLEN_8192: 456 sc->stolen = (8192 - 132) * 1024 / 4096; 457 break; 458 default: 459 sc->stolen = 0; 460 device_printf(dev, "unknown memory configuration, disabling\n"); 461 bus_release_resources(dev, sc->sc_res_spec, 462 sc->sc_res); 463 free(gatt, M_AGP); 464 agp_generic_detach(dev); 465 return EINVAL; 466 } 467 if (sc->stolen > 0) { 468 device_printf(dev, "detected %dk stolen memory\n", 469 sc->stolen * 4); 470 } 471 device_printf(dev, "aperture size is %dM\n", 472 sc->initial_aperture / 1024 / 1024); 473 474 /* GATT address is already in there, make sure it's enabled */ 475 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 476 pgtblctl |= 1; 477 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 478 479 gatt->ag_physical = pgtblctl & ~1; 480 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 || 481 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) { 482 unsigned int gcc1, pgtblctl, stolen, gtt_size; 483 484 /* Stolen memory is set up at the beginning of the aperture by 485 * the BIOS, consisting of the GATT followed by 4kb for the 486 * BIOS display. 487 */ 488 switch (sc->chiptype) { 489 case CHIP_I855: 490 gtt_size = 128; 491 break; 492 case CHIP_I915: 493 gtt_size = 256; 494 break; 495 case CHIP_I965: 496 case CHIP_G33: 497 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) & 498 AGP_I810_PGTBL_SIZE_MASK) { 499 case AGP_I810_PGTBL_SIZE_128KB: 500 gtt_size = 128; 501 break; 502 case AGP_I810_PGTBL_SIZE_256KB: 503 gtt_size = 256; 504 break; 505 case AGP_I810_PGTBL_SIZE_512KB: 506 gtt_size = 512; 507 break; 508 default: 509 device_printf(dev, "Bad PGTBL size\n"); 510 bus_release_resources(dev, sc->sc_res_spec, 511 sc->sc_res); 512 free(gatt, M_AGP); 513 agp_generic_detach(dev); 514 return EINVAL; 515 } 516 break; 517 default: 518 device_printf(dev, "Bad chiptype\n"); 519 bus_release_resources(dev, sc->sc_res_spec, 520 sc->sc_res); 521 free(gatt, M_AGP); 522 agp_generic_detach(dev); 523 return EINVAL; 524 } 525 526 /* GCC1 is called MGGC on i915+ */ 527 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); 528 switch (gcc1 & AGP_I855_GCC1_GMS) { 529 case AGP_I855_GCC1_GMS_STOLEN_1M: 530 stolen = 1024; 531 break; 532 case AGP_I855_GCC1_GMS_STOLEN_4M: 533 stolen = 4096; 534 break; 535 case AGP_I855_GCC1_GMS_STOLEN_8M: 536 stolen = 8192; 537 break; 538 case AGP_I855_GCC1_GMS_STOLEN_16M: 539 stolen = 16384; 540 break; 541 case AGP_I855_GCC1_GMS_STOLEN_32M: 542 stolen = 32768; 543 break; 544 case AGP_I915_GCC1_GMS_STOLEN_48M: 545 stolen = 49152; 546 break; 547 case AGP_I915_GCC1_GMS_STOLEN_64M: 548 stolen = 65536; 549 break; 550 case AGP_G33_GCC1_GMS_STOLEN_128M: 551 stolen = 128 * 1024; 552 break; 553 case AGP_G33_GCC1_GMS_STOLEN_256M: 554 stolen = 256 * 1024; 555 break; 556 default: 557 device_printf(dev, "unknown memory configuration, " 558 "disabling\n"); 559 bus_release_resources(dev, sc->sc_res_spec, 560 sc->sc_res); 561 free(gatt, M_AGP); 562 agp_generic_detach(dev); 563 return EINVAL; 564 } 565 sc->stolen = (stolen - gtt_size - 4) * 1024 / 4096; 566 if (sc->stolen > 0) 567 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 568 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 569 570 /* GATT address is already in there, make sure it's enabled */ 571 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 572 pgtblctl |= 1; 573 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 574 575 gatt->ag_physical = pgtblctl & ~1; 576 } 577 578 if (0) 579 agp_i810_dump_regs(dev); 580 581 return 0; 582} 583 584static int 585agp_i810_detach(device_t dev) 586{ 587 struct agp_i810_softc *sc = device_get_softc(dev); 588 589 agp_free_cdev(dev); 590 591 /* Clear the GATT base. */ 592 if ( sc->chiptype == CHIP_I810 ) { 593 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0); 594 } else { 595 unsigned int pgtblctl; 596 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 597 pgtblctl &= ~1; 598 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 599 } 600 601 /* Put the aperture back the way it started. */ 602 AGP_SET_APERTURE(dev, sc->initial_aperture); 603 604 if ( sc->chiptype == CHIP_I810 ) { 605 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP); 606 } 607 free(sc->gatt, M_AGP); 608 609 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res); 610 agp_free_res(dev); 611 612 return 0; 613} 614 615static int 616agp_i810_resume(device_t dev) 617{ 618 struct agp_i810_softc *sc; 619 sc = device_get_softc(dev); 620 621 AGP_SET_APERTURE(dev, sc->initial_aperture); 622 623 /* Install the GATT. */ 624 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 625 sc->gatt->ag_physical | 1); 626 627 return (bus_generic_resume(dev)); 628} 629 630/** 631 * Sets the PCI resource size of the aperture on i830-class and below chipsets, 632 * while returning failure on later chipsets when an actual change is 633 * requested. 634 * 635 * This whole function is likely bogus, as the kernel would probably need to 636 * reconfigure the placement of the AGP aperture if a larger size is requested, 637 * which doesn't happen currently. 638 */ 639static int 640agp_i810_set_aperture(device_t dev, u_int32_t aperture) 641{ 642 struct agp_i810_softc *sc = device_get_softc(dev); 643 u_int16_t miscc, gcc1; 644 645 switch (sc->chiptype) { 646 case CHIP_I810: 647 /* 648 * Double check for sanity. 649 */ 650 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { 651 device_printf(dev, "bad aperture size %d\n", aperture); 652 return EINVAL; 653 } 654 655 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 656 miscc &= ~AGP_I810_MISCC_WINSIZE; 657 if (aperture == 32 * 1024 * 1024) 658 miscc |= AGP_I810_MISCC_WINSIZE_32; 659 else 660 miscc |= AGP_I810_MISCC_WINSIZE_64; 661 662 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); 663 break; 664 case CHIP_I830: 665 if (aperture != 64 * 1024 * 1024 && 666 aperture != 128 * 1024 * 1024) { 667 device_printf(dev, "bad aperture size %d\n", aperture); 668 return EINVAL; 669 } 670 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 671 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 672 if (aperture == 64 * 1024 * 1024) 673 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 674 else 675 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 676 677 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); 678 break; 679 case CHIP_I855: 680 case CHIP_I915: 681 case CHIP_I965: 682 case CHIP_G33: 683 return agp_generic_set_aperture(dev, aperture); 684 } 685 686 return 0; 687} 688 689/** 690 * Writes a GTT entry mapping the page at the given offset from the beginning 691 * of the aperture to the given physical address. 692 */ 693static void 694agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical, 695 int enabled) 696{ 697 struct agp_i810_softc *sc = device_get_softc(dev); 698 u_int32_t pte; 699 700 pte = (u_int32_t)physical | 1; 701 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) { 702 pte |= (physical & 0x0000000f00000000ull) >> 28; 703 } else { 704 /* If we do actually have memory above 4GB on an older system, 705 * crash cleanly rather than scribble on system memory, 706 * so we know we need to fix it. 707 */ 708 KASSERT((pte & 0x0000000f00000000ull) == 0, 709 (">4GB physical address in agp")); 710 } 711 712 switch (sc->chiptype) { 713 case CHIP_I810: 714 case CHIP_I830: 715 case CHIP_I855: 716 bus_write_4(sc->sc_res[0], 717 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte); 718 break; 719 case CHIP_I915: 720 case CHIP_G33: 721 bus_write_4(sc->sc_res[1], 722 (offset >> AGP_PAGE_SHIFT) * 4, pte); 723 break; 724 case CHIP_I965: 725 bus_write_4(sc->sc_res[0], 726 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte); 727 break; 728 } 729} 730 731static int 732agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical) 733{ 734 struct agp_i810_softc *sc = device_get_softc(dev); 735 736 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 737 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries); 738 return EINVAL; 739 } 740 741 if ( sc->chiptype != CHIP_I810 ) { 742 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 743 device_printf(dev, "trying to bind into stolen memory"); 744 return EINVAL; 745 } 746 } 747 748 agp_i810_write_gtt_entry(dev, offset, physical, 1); 749 750 return 0; 751} 752 753static int 754agp_i810_unbind_page(device_t dev, int offset) 755{ 756 struct agp_i810_softc *sc = device_get_softc(dev); 757 758 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 759 return EINVAL; 760 761 if ( sc->chiptype != CHIP_I810 ) { 762 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 763 device_printf(dev, "trying to unbind from stolen memory"); 764 return EINVAL; 765 } 766 } 767 768 agp_i810_write_gtt_entry(dev, offset, 0, 0); 769 770 return 0; 771} 772 773/* 774 * Writing via memory mapped registers already flushes all TLBs. 775 */ 776static void 777agp_i810_flush_tlb(device_t dev) 778{ 779} 780 781static int 782agp_i810_enable(device_t dev, u_int32_t mode) 783{ 784 785 return 0; 786} 787 788static struct agp_memory * 789agp_i810_alloc_memory(device_t dev, int type, vm_size_t size) 790{ 791 struct agp_i810_softc *sc = device_get_softc(dev); 792 struct agp_memory *mem; 793 794 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 795 return 0; 796 797 if (sc->agp.as_allocated + size > sc->agp.as_maxmem) 798 return 0; 799 800 if (type == 1) { 801 /* 802 * Mapping local DRAM into GATT. 803 */ 804 if ( sc->chiptype != CHIP_I810 ) 805 return 0; 806 if (size != sc->dcache_size) 807 return 0; 808 } else if (type == 2) { 809 /* 810 * Type 2 is the contiguous physical memory type, that hands 811 * back a physical address. This is used for cursors on i810. 812 * Hand back as many single pages with physical as the user 813 * wants, but only allow one larger allocation (ARGB cursor) 814 * for simplicity. 815 */ 816 if (size != AGP_PAGE_SIZE) { 817 if (sc->argb_cursor != NULL) 818 return 0; 819 820 /* Allocate memory for ARGB cursor, if we can. */ 821 sc->argb_cursor = contigmalloc(size, M_AGP, 822 0, 0, ~0, PAGE_SIZE, 0); 823 if (sc->argb_cursor == NULL) 824 return 0; 825 } 826 } 827 828 mem = malloc(sizeof *mem, M_AGP, M_WAITOK); 829 mem->am_id = sc->agp.as_nextid++; 830 mem->am_size = size; 831 mem->am_type = type; 832 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE)) 833 mem->am_obj = vm_object_allocate(OBJT_DEFAULT, 834 atop(round_page(size))); 835 else 836 mem->am_obj = 0; 837 838 if (type == 2) { 839 if (size == AGP_PAGE_SIZE) { 840 /* 841 * Allocate and wire down the page now so that we can 842 * get its physical address. 843 */ 844 vm_page_t m; 845 846 VM_OBJECT_LOCK(mem->am_obj); 847 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY | 848 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY); 849 VM_OBJECT_UNLOCK(mem->am_obj); 850 mem->am_physical = VM_PAGE_TO_PHYS(m); 851 } else { 852 /* Our allocation is already nicely wired down for us. 853 * Just grab the physical address. 854 */ 855 mem->am_physical = vtophys(sc->argb_cursor); 856 } 857 } else { 858 mem->am_physical = 0; 859 } 860 861 mem->am_offset = 0; 862 mem->am_is_bound = 0; 863 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link); 864 sc->agp.as_allocated += size; 865 866 return mem; 867} 868 869static int 870agp_i810_free_memory(device_t dev, struct agp_memory *mem) 871{ 872 struct agp_i810_softc *sc = device_get_softc(dev); 873 874 if (mem->am_is_bound) 875 return EBUSY; 876 877 if (mem->am_type == 2) { 878 if (mem->am_size == AGP_PAGE_SIZE) { 879 /* 880 * Unwire the page which we wired in alloc_memory. 881 */ 882 vm_page_t m; 883 884 VM_OBJECT_LOCK(mem->am_obj); 885 m = vm_page_lookup(mem->am_obj, 0); 886 VM_OBJECT_UNLOCK(mem->am_obj); 887 vm_page_lock_queues(); 888 vm_page_unwire(m, 0); 889 vm_page_unlock_queues(); 890 } else { 891 contigfree(sc->argb_cursor, mem->am_size, M_AGP); 892 sc->argb_cursor = NULL; 893 } 894 } 895 896 sc->agp.as_allocated -= mem->am_size; 897 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link); 898 if (mem->am_obj) 899 vm_object_deallocate(mem->am_obj); 900 free(mem, M_AGP); 901 return 0; 902} 903 904static int 905agp_i810_bind_memory(device_t dev, struct agp_memory *mem, 906 vm_offset_t offset) 907{ 908 struct agp_i810_softc *sc = device_get_softc(dev); 909 vm_offset_t i; 910 911 /* Do some sanity checks first. */ 912 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 || 913 offset + mem->am_size > AGP_GET_APERTURE(dev)) { 914 device_printf(dev, "binding memory at bad offset %#x\n", 915 (int)offset); 916 return EINVAL; 917 } 918 919 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 920 mtx_lock(&sc->agp.as_lock); 921 if (mem->am_is_bound) { 922 mtx_unlock(&sc->agp.as_lock); 923 return EINVAL; 924 } 925 /* The memory's already wired down, just stick it in the GTT. */ 926 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 927 agp_i810_write_gtt_entry(dev, offset + i, 928 mem->am_physical + i, 1); 929 } 930 agp_flush_cache(); 931 mem->am_offset = offset; 932 mem->am_is_bound = 1; 933 mtx_unlock(&sc->agp.as_lock); 934 return 0; 935 } 936 937 if (mem->am_type != 1) 938 return agp_generic_bind_memory(dev, mem, offset); 939 940 if ( sc->chiptype != CHIP_I810 ) 941 return EINVAL; 942 943 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 944 bus_write_4(sc->sc_res[0], 945 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3); 946 } 947 948 return 0; 949} 950 951static int 952agp_i810_unbind_memory(device_t dev, struct agp_memory *mem) 953{ 954 struct agp_i810_softc *sc = device_get_softc(dev); 955 vm_offset_t i; 956 957 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 958 mtx_lock(&sc->agp.as_lock); 959 if (!mem->am_is_bound) { 960 mtx_unlock(&sc->agp.as_lock); 961 return EINVAL; 962 } 963 964 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 965 agp_i810_write_gtt_entry(dev, mem->am_offset + i, 966 0, 0); 967 } 968 agp_flush_cache(); 969 mem->am_is_bound = 0; 970 mtx_unlock(&sc->agp.as_lock); 971 return 0; 972 } 973 974 if (mem->am_type != 1) 975 return agp_generic_unbind_memory(dev, mem); 976 977 if ( sc->chiptype != CHIP_I810 ) 978 return EINVAL; 979 980 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 981 bus_write_4(sc->sc_res[0], 982 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0); 983 } 984 985 return 0; 986} 987 988static device_method_t agp_i810_methods[] = { 989 /* Device interface */ 990 DEVMETHOD(device_identify, agp_i810_identify), 991 DEVMETHOD(device_probe, agp_i810_probe), 992 DEVMETHOD(device_attach, agp_i810_attach), 993 DEVMETHOD(device_detach, agp_i810_detach), 994 DEVMETHOD(device_suspend, bus_generic_suspend), 995 DEVMETHOD(device_resume, agp_i810_resume), 996 997 /* AGP interface */ 998 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture), 999 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture), 1000 DEVMETHOD(agp_bind_page, agp_i810_bind_page), 1001 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page), 1002 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb), 1003 DEVMETHOD(agp_enable, agp_i810_enable), 1004 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory), 1005 DEVMETHOD(agp_free_memory, agp_i810_free_memory), 1006 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory), 1007 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory), 1008 1009 { 0, 0 } 1010}; 1011 1012static driver_t agp_i810_driver = { 1013 "agp", 1014 agp_i810_methods, 1015 sizeof(struct agp_i810_softc), 1016}; 1017 1018static devclass_t agp_devclass; 1019 1020DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0); 1021MODULE_DEPEND(agp_i810, agp, 1, 1, 1); 1022MODULE_DEPEND(agp_i810, pci, 1, 1, 1); 1023