agp_i810.c revision 172187
1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * Copyright (c) 2000 Ruslan Ermilov 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org> 30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org> 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/agp/agp_i810.c 172187 2007-09-15 18:16:35Z alc $"); 35 36#include "opt_bus.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46#include <sys/proc.h> 47 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <pci/agppriv.h> 51#include <pci/agpreg.h> 52 53#include <vm/vm.h> 54#include <vm/vm_object.h> 55#include <vm/vm_page.h> 56#include <vm/vm_pageout.h> 57#include <vm/pmap.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <machine/md_var.h> 62#include <sys/rman.h> 63 64MALLOC_DECLARE(M_AGP); 65 66enum { 67 CHIP_I810, /* i810/i815 */ 68 CHIP_I830, /* 830M/845G */ 69 CHIP_I855, /* 852GM/855GM/865G */ 70 CHIP_I915, /* 915G/915GM */ 71 CHIP_I965, /* G965 */ 72 CHIP_G33, /* G33/Q33/Q35 */ 73}; 74 75/* The i810 through i855 have the registers at BAR 1, and the GATT gets 76 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the 77 * start of the stolen memory, and should only be accessed by the OS through 78 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB 79 * is registers, second 512KB is GATT. 80 */ 81static struct resource_spec agp_i810_res_spec[] = { 82 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE }, 83 { -1, 0 } 84}; 85 86static struct resource_spec agp_i915_res_spec[] = { 87 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE }, 88 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE }, 89 { -1, 0 } 90}; 91 92static struct resource_spec agp_i965_res_spec[] = { 93 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE }, 94 { -1, 0 } 95}; 96 97struct agp_i810_softc { 98 struct agp_softc agp; 99 u_int32_t initial_aperture; /* aperture size at startup */ 100 struct agp_gatt *gatt; 101 int chiptype; /* i810-like or i830 */ 102 u_int32_t dcache_size; /* i810 only */ 103 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */ 104 device_t bdev; /* bridge device */ 105 106 void *argb_cursor; /* contigmalloc area for ARGB cursor */ 107 108 struct resource_spec * sc_res_spec; 109 struct resource *sc_res[2]; 110}; 111 112/* For adding new devices, devid is the id of the graphics controller 113 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the 114 * second head should never be added. The bridge_offset is the offset to 115 * subtract from devid to get the id of the hostb that the device is on. 116 */ 117static const struct agp_i810_match { 118 int devid; 119 int chiptype; 120 int bridge_offset; 121 char *name; 122} agp_i810_matches[] = { 123 {0x71218086, CHIP_I810, 0x00010000, 124 "Intel 82810 (i810 GMCH) SVGA controller"}, 125 {0x71238086, CHIP_I810, 0x00010000, 126 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"}, 127 {0x71258086, CHIP_I810, 0x00010000, 128 "Intel 82810E (i810E GMCH) SVGA controller"}, 129 {0x11328086, CHIP_I810, 0x00020000, 130 "Intel 82815 (i815 GMCH) SVGA controller"}, 131 {0x35778086, CHIP_I830, 0x00020000, 132 "Intel 82830M (830M GMCH) SVGA controller"}, 133 {0x35828086, CHIP_I855, 0x00020000, 134 "Intel 82852/5"}, 135 {0x25728086, CHIP_I855, 0x00020000, 136 "Intel 82865G (865G GMCH) SVGA controller"}, 137 {0x25828086, CHIP_I915, 0x00020000, 138 "Intel 82915G (915G GMCH) SVGA controller"}, 139 {0x258A8086, CHIP_I915, 0x00020000, 140 "Intel E7221 SVGA controller"}, 141 {0x25928086, CHIP_I915, 0x00020000, 142 "Intel 82915GM (915GM GMCH) SVGA controller"}, 143 {0x27728086, CHIP_I915, 0x00020000, 144 "Intel 82945G (945G GMCH) SVGA controller"}, 145 {0x27A28086, CHIP_I915, 0x00020000, 146 "Intel 82945GM (945GM GMCH) SVGA controller"}, 147 {0x27A28086, CHIP_I915, 0x00020000, 148 "Intel 945GME SVGA controller"}, 149 {0x29728086, CHIP_I965, 0x00020000, 150 "Intel 946GZ SVGA controller"}, 151 {0x29828086, CHIP_I965, 0x00020000, 152 "Intel G965 SVGA controller"}, 153 {0x29928086, CHIP_I965, 0x00020000, 154 "Intel Q965 SVGA controller"}, 155 {0x29a28086, CHIP_I965, 0x00020000, 156 "Intel G965 SVGA controller"}, 157/* 158 {0x29b28086, CHIP_G33, 0x00020000, 159 "Intel Q35 SVGA controller"}, 160 {0x29c28086, CHIP_G33, 0x00020000, 161 "Intel G33 SVGA controller"}, 162 {0x29d28086, CHIP_G33, 0x00020000, 163 "Intel Q33 SVGA controller"}, 164*/ 165 {0x2a028086, CHIP_I965, 0x00020000, 166 "Intel GM965 SVGA controller"}, 167 {0x2a128086, CHIP_I965, 0x00020000, 168 "Intel GME965 SVGA controller"}, 169 {0, 0, 0, NULL} 170}; 171 172static const struct agp_i810_match* 173agp_i810_match(device_t dev) 174{ 175 int i, devid; 176 177 if (pci_get_class(dev) != PCIC_DISPLAY 178 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA) 179 return NULL; 180 181 devid = pci_get_devid(dev); 182 for (i = 0; agp_i810_matches[i].devid != 0; i++) { 183 if (agp_i810_matches[i].devid == devid) 184 break; 185 } 186 if (agp_i810_matches[i].devid == 0) 187 return NULL; 188 else 189 return &agp_i810_matches[i]; 190} 191 192/* 193 * Find bridge device. 194 */ 195static device_t 196agp_i810_find_bridge(device_t dev) 197{ 198 device_t *children, child; 199 int nchildren, i; 200 u_int32_t devid; 201 const struct agp_i810_match *match; 202 203 match = agp_i810_match(dev); 204 devid = match->devid - match->bridge_offset; 205 206 if (device_get_children(device_get_parent(device_get_parent(dev)), 207 &children, &nchildren)) 208 return 0; 209 210 for (i = 0; i < nchildren; i++) { 211 child = children[i]; 212 213 if (pci_get_devid(child) == devid) { 214 free(children, M_TEMP); 215 return child; 216 } 217 } 218 free(children, M_TEMP); 219 return 0; 220} 221 222static void 223agp_i810_identify(driver_t *driver, device_t parent) 224{ 225 226 if (device_find_child(parent, "agp", -1) == NULL && 227 agp_i810_match(parent)) 228 device_add_child(parent, "agp", -1); 229} 230 231static int 232agp_i810_probe(device_t dev) 233{ 234 device_t bdev; 235 const struct agp_i810_match *match; 236 u_int8_t smram; 237 int gcc1, deven; 238 239 if (resource_disabled("agp", device_get_unit(dev))) 240 return (ENXIO); 241 match = agp_i810_match(dev); 242 if (match == NULL) 243 return ENXIO; 244 245 bdev = agp_i810_find_bridge(dev); 246 if (!bdev) { 247 if (bootverbose) 248 printf("I810: can't find bridge device\n"); 249 return ENXIO; 250 } 251 252 /* 253 * checking whether internal graphics device has been activated. 254 */ 255 switch (match->chiptype) { 256 case CHIP_I810: 257 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1); 258 if ((smram & AGP_I810_SMRAM_GMS) == 259 AGP_I810_SMRAM_GMS_DISABLED) { 260 if (bootverbose) 261 printf("I810: disabled, not probing\n"); 262 return ENXIO; 263 } 264 break; 265 case CHIP_I830: 266 case CHIP_I855: 267 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1); 268 if ((gcc1 & AGP_I830_GCC1_DEV2) == 269 AGP_I830_GCC1_DEV2_DISABLED) { 270 if (bootverbose) 271 printf("I830: disabled, not probing\n"); 272 return ENXIO; 273 } 274 break; 275 case CHIP_I915: 276 case CHIP_I965: 277 case CHIP_G33: 278 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4); 279 if ((deven & AGP_I915_DEVEN_D2F0) == 280 AGP_I915_DEVEN_D2F0_DISABLED) { 281 if (bootverbose) 282 printf("I915: disabled, not probing\n"); 283 return ENXIO; 284 } 285 break; 286 } 287 288 if (match->devid == 0x35828086) { 289 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { 290 case AGP_I855_GME: 291 device_set_desc(dev, 292 "Intel 82855GME (855GME GMCH) SVGA controller"); 293 break; 294 case AGP_I855_GM: 295 device_set_desc(dev, 296 "Intel 82855GM (855GM GMCH) SVGA controller"); 297 break; 298 case AGP_I852_GME: 299 device_set_desc(dev, 300 "Intel 82852GME (852GME GMCH) SVGA controller"); 301 break; 302 case AGP_I852_GM: 303 device_set_desc(dev, 304 "Intel 82852GM (852GM GMCH) SVGA controller"); 305 break; 306 default: 307 device_set_desc(dev, 308 "Intel 8285xM (85xGM GMCH) SVGA controller"); 309 break; 310 } 311 } else { 312 device_set_desc(dev, match->name); 313 } 314 315 return BUS_PROBE_DEFAULT; 316} 317 318static void 319agp_i810_dump_regs(device_t dev) 320{ 321 struct agp_i810_softc *sc = device_get_softc(dev); 322 323 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", 324 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); 325 326 switch (sc->chiptype) { 327 case CHIP_I810: 328 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n", 329 pci_read_config(sc->bdev, AGP_I810_MISCC, 2)); 330 break; 331 case CHIP_I830: 332 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n", 333 pci_read_config(sc->bdev, AGP_I830_GCC1, 1)); 334 break; 335 case CHIP_I855: 336 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", 337 pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); 338 break; 339 case CHIP_I915: 340 case CHIP_I965: 341 case CHIP_G33: 342 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", 343 pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); 344 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n", 345 pci_read_config(sc->bdev, AGP_I915_MSAC, 1)); 346 break; 347 } 348 device_printf(dev, "Aperture resource size: %d bytes\n", 349 AGP_GET_APERTURE(dev)); 350} 351 352static int 353agp_i810_attach(device_t dev) 354{ 355 struct agp_i810_softc *sc = device_get_softc(dev); 356 struct agp_gatt *gatt; 357 const struct agp_i810_match *match; 358 int error; 359 360 sc->bdev = agp_i810_find_bridge(dev); 361 if (!sc->bdev) 362 return ENOENT; 363 364 match = agp_i810_match(dev); 365 sc->chiptype = match->chiptype; 366 367 switch (sc->chiptype) { 368 case CHIP_I810: 369 case CHIP_I830: 370 case CHIP_I855: 371 sc->sc_res_spec = agp_i810_res_spec; 372 agp_set_aperture_resource(dev, AGP_APBASE); 373 break; 374 case CHIP_I915: 375 case CHIP_G33: 376 sc->sc_res_spec = agp_i915_res_spec; 377 agp_set_aperture_resource(dev, AGP_I915_GMADR); 378 break; 379 case CHIP_I965: 380 sc->sc_res_spec = agp_i965_res_spec; 381 agp_set_aperture_resource(dev, AGP_I915_GMADR); 382 break; 383 } 384 385 error = agp_generic_attach(dev); 386 if (error) 387 return error; 388 389 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 && 390 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful) 391 { 392 device_printf(dev, "agp_i810.c does not support physical " 393 "memory above 4GB.\n"); 394 return ENOENT; 395 } 396 397 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) { 398 agp_generic_detach(dev); 399 return ENODEV; 400 } 401 402 sc->initial_aperture = AGP_GET_APERTURE(dev); 403 404 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 405 if (!gatt) { 406 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res); 407 agp_generic_detach(dev); 408 return ENOMEM; 409 } 410 sc->gatt = gatt; 411 412 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; 413 414 if ( sc->chiptype == CHIP_I810 ) { 415 /* Some i810s have on-chip memory called dcache */ 416 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) & 417 AGP_I810_DRT_POPULATED) 418 sc->dcache_size = 4 * 1024 * 1024; 419 else 420 sc->dcache_size = 0; 421 422 /* According to the specs the gatt on the i810 must be 64k */ 423 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0, 424 0, ~0, PAGE_SIZE, 0); 425 if (!gatt->ag_virtual) { 426 if (bootverbose) 427 device_printf(dev, "contiguous allocation failed\n"); 428 bus_release_resources(dev, sc->sc_res_spec, 429 sc->sc_res); 430 free(gatt, M_AGP); 431 agp_generic_detach(dev); 432 return ENOMEM; 433 } 434 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t)); 435 436 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); 437 agp_flush_cache(); 438 /* Install the GATT. */ 439 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 440 gatt->ag_physical | 1); 441 } else if ( sc->chiptype == CHIP_I830 ) { 442 /* The i830 automatically initializes the 128k gatt on boot. */ 443 unsigned int gcc1, pgtblctl; 444 445 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); 446 switch (gcc1 & AGP_I830_GCC1_GMS) { 447 case AGP_I830_GCC1_GMS_STOLEN_512: 448 sc->stolen = (512 - 132) * 1024 / 4096; 449 break; 450 case AGP_I830_GCC1_GMS_STOLEN_1024: 451 sc->stolen = (1024 - 132) * 1024 / 4096; 452 break; 453 case AGP_I830_GCC1_GMS_STOLEN_8192: 454 sc->stolen = (8192 - 132) * 1024 / 4096; 455 break; 456 default: 457 sc->stolen = 0; 458 device_printf(dev, "unknown memory configuration, disabling\n"); 459 bus_release_resources(dev, sc->sc_res_spec, 460 sc->sc_res); 461 free(gatt, M_AGP); 462 agp_generic_detach(dev); 463 return EINVAL; 464 } 465 if (sc->stolen > 0) { 466 device_printf(dev, "detected %dk stolen memory\n", 467 sc->stolen * 4); 468 } 469 device_printf(dev, "aperture size is %dM\n", 470 sc->initial_aperture / 1024 / 1024); 471 472 /* GATT address is already in there, make sure it's enabled */ 473 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 474 pgtblctl |= 1; 475 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 476 477 gatt->ag_physical = pgtblctl & ~1; 478 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 || 479 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) { 480 unsigned int gcc1, pgtblctl, stolen, gtt_size; 481 482 /* Stolen memory is set up at the beginning of the aperture by 483 * the BIOS, consisting of the GATT followed by 4kb for the 484 * BIOS display. 485 */ 486 switch (sc->chiptype) { 487 case CHIP_I855: 488 gtt_size = 128; 489 break; 490 case CHIP_I915: 491 gtt_size = 256; 492 break; 493 case CHIP_I965: 494 case CHIP_G33: 495 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) & 496 AGP_I810_PGTBL_SIZE_MASK) { 497 case AGP_I810_PGTBL_SIZE_128KB: 498 gtt_size = 128; 499 break; 500 case AGP_I810_PGTBL_SIZE_256KB: 501 gtt_size = 256; 502 break; 503 case AGP_I810_PGTBL_SIZE_512KB: 504 gtt_size = 512; 505 break; 506 default: 507 device_printf(dev, "Bad PGTBL size\n"); 508 bus_release_resources(dev, sc->sc_res_spec, 509 sc->sc_res); 510 free(gatt, M_AGP); 511 agp_generic_detach(dev); 512 return EINVAL; 513 } 514 break; 515 default: 516 device_printf(dev, "Bad chiptype\n"); 517 bus_release_resources(dev, sc->sc_res_spec, 518 sc->sc_res); 519 free(gatt, M_AGP); 520 agp_generic_detach(dev); 521 return EINVAL; 522 } 523 524 /* GCC1 is called MGGC on i915+ */ 525 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); 526 switch (gcc1 & AGP_I855_GCC1_GMS) { 527 case AGP_I855_GCC1_GMS_STOLEN_1M: 528 stolen = 1024; 529 break; 530 case AGP_I855_GCC1_GMS_STOLEN_4M: 531 stolen = 4096; 532 break; 533 case AGP_I855_GCC1_GMS_STOLEN_8M: 534 stolen = 8192; 535 break; 536 case AGP_I855_GCC1_GMS_STOLEN_16M: 537 stolen = 16384; 538 break; 539 case AGP_I855_GCC1_GMS_STOLEN_32M: 540 stolen = 32768; 541 break; 542 case AGP_I915_GCC1_GMS_STOLEN_48M: 543 stolen = 49152; 544 break; 545 case AGP_I915_GCC1_GMS_STOLEN_64M: 546 stolen = 65536; 547 break; 548 case AGP_G33_GCC1_GMS_STOLEN_128M: 549 stolen = 128 * 1024; 550 break; 551 case AGP_G33_GCC1_GMS_STOLEN_256M: 552 stolen = 256 * 1024; 553 break; 554 default: 555 device_printf(dev, "unknown memory configuration, " 556 "disabling\n"); 557 bus_release_resources(dev, sc->sc_res_spec, 558 sc->sc_res); 559 free(gatt, M_AGP); 560 agp_generic_detach(dev); 561 return EINVAL; 562 } 563 sc->stolen = (stolen - gtt_size - 4) * 1024 / 4096; 564 if (sc->stolen > 0) 565 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 566 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 567 568 /* GATT address is already in there, make sure it's enabled */ 569 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 570 pgtblctl |= 1; 571 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 572 573 gatt->ag_physical = pgtblctl & ~1; 574 } 575 576 if (0) 577 agp_i810_dump_regs(dev); 578 579 return 0; 580} 581 582static int 583agp_i810_detach(device_t dev) 584{ 585 struct agp_i810_softc *sc = device_get_softc(dev); 586 int error; 587 588 error = agp_generic_detach(dev); 589 if (error) 590 return error; 591 592 /* Clear the GATT base. */ 593 if ( sc->chiptype == CHIP_I810 ) { 594 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0); 595 } else { 596 unsigned int pgtblctl; 597 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); 598 pgtblctl &= ~1; 599 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); 600 } 601 602 /* Put the aperture back the way it started. */ 603 AGP_SET_APERTURE(dev, sc->initial_aperture); 604 605 if ( sc->chiptype == CHIP_I810 ) { 606 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP); 607 } 608 free(sc->gatt, M_AGP); 609 610 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res); 611 612 return 0; 613} 614 615/** 616 * Sets the PCI resource size of the aperture on i830-class and below chipsets, 617 * while returning failure on later chipsets when an actual change is 618 * requested. 619 * 620 * This whole function is likely bogus, as the kernel would probably need to 621 * reconfigure the placement of the AGP aperture if a larger size is requested, 622 * which doesn't happen currently. 623 */ 624static int 625agp_i810_set_aperture(device_t dev, u_int32_t aperture) 626{ 627 struct agp_i810_softc *sc = device_get_softc(dev); 628 u_int16_t miscc, gcc1; 629 630 switch (sc->chiptype) { 631 case CHIP_I810: 632 /* 633 * Double check for sanity. 634 */ 635 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { 636 device_printf(dev, "bad aperture size %d\n", aperture); 637 return EINVAL; 638 } 639 640 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 641 miscc &= ~AGP_I810_MISCC_WINSIZE; 642 if (aperture == 32 * 1024 * 1024) 643 miscc |= AGP_I810_MISCC_WINSIZE_32; 644 else 645 miscc |= AGP_I810_MISCC_WINSIZE_64; 646 647 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); 648 break; 649 case CHIP_I830: 650 if (aperture != 64 * 1024 * 1024 && 651 aperture != 128 * 1024 * 1024) { 652 device_printf(dev, "bad aperture size %d\n", aperture); 653 return EINVAL; 654 } 655 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 656 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 657 if (aperture == 64 * 1024 * 1024) 658 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 659 else 660 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 661 662 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); 663 break; 664 case CHIP_I855: 665 case CHIP_I915: 666 case CHIP_I965: 667 case CHIP_G33: 668 return agp_generic_set_aperture(dev, aperture); 669 } 670 671 return 0; 672} 673 674/** 675 * Writes a GTT entry mapping the page at the given offset from the beginning 676 * of the aperture to the given physical address. 677 */ 678static void 679agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical, 680 int enabled) 681{ 682 struct agp_i810_softc *sc = device_get_softc(dev); 683 u_int32_t pte; 684 685 pte = (u_int32_t)physical | 1; 686 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) { 687 pte |= (physical & 0x0000000f00000000ull) >> 28; 688 } else { 689 /* If we do actually have memory above 4GB on an older system, 690 * crash cleanly rather than scribble on system memory, 691 * so we know we need to fix it. 692 */ 693 KASSERT((pte & 0x0000000f00000000ull) == 0, 694 (">4GB physical address in agp")); 695 } 696 697 switch (sc->chiptype) { 698 case CHIP_I810: 699 case CHIP_I830: 700 case CHIP_I855: 701 bus_write_4(sc->sc_res[0], 702 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte); 703 break; 704 case CHIP_I915: 705 case CHIP_G33: 706 bus_write_4(sc->sc_res[1], 707 (offset >> AGP_PAGE_SHIFT) * 4, pte); 708 break; 709 case CHIP_I965: 710 bus_write_4(sc->sc_res[0], 711 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte); 712 break; 713 } 714} 715 716static int 717agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical) 718{ 719 struct agp_i810_softc *sc = device_get_softc(dev); 720 721 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 722 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries); 723 return EINVAL; 724 } 725 726 if ( sc->chiptype != CHIP_I810 ) { 727 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 728 device_printf(dev, "trying to bind into stolen memory"); 729 return EINVAL; 730 } 731 } 732 733 agp_i810_write_gtt_entry(dev, offset, physical, 1); 734 735 return 0; 736} 737 738static int 739agp_i810_unbind_page(device_t dev, int offset) 740{ 741 struct agp_i810_softc *sc = device_get_softc(dev); 742 743 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 744 return EINVAL; 745 746 if ( sc->chiptype != CHIP_I810 ) { 747 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 748 device_printf(dev, "trying to unbind from stolen memory"); 749 return EINVAL; 750 } 751 } 752 753 agp_i810_write_gtt_entry(dev, offset, 0, 0); 754 755 return 0; 756} 757 758/* 759 * Writing via memory mapped registers already flushes all TLBs. 760 */ 761static void 762agp_i810_flush_tlb(device_t dev) 763{ 764} 765 766static int 767agp_i810_enable(device_t dev, u_int32_t mode) 768{ 769 770 return 0; 771} 772 773static struct agp_memory * 774agp_i810_alloc_memory(device_t dev, int type, vm_size_t size) 775{ 776 struct agp_i810_softc *sc = device_get_softc(dev); 777 struct agp_memory *mem; 778 779 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 780 return 0; 781 782 if (sc->agp.as_allocated + size > sc->agp.as_maxmem) 783 return 0; 784 785 if (type == 1) { 786 /* 787 * Mapping local DRAM into GATT. 788 */ 789 if ( sc->chiptype != CHIP_I810 ) 790 return 0; 791 if (size != sc->dcache_size) 792 return 0; 793 } else if (type == 2) { 794 /* 795 * Type 2 is the contiguous physical memory type, that hands 796 * back a physical address. This is used for cursors on i810. 797 * Hand back as many single pages with physical as the user 798 * wants, but only allow one larger allocation (ARGB cursor) 799 * for simplicity. 800 */ 801 if (size != AGP_PAGE_SIZE) { 802 if (sc->argb_cursor != NULL) 803 return 0; 804 805 /* Allocate memory for ARGB cursor, if we can. */ 806 sc->argb_cursor = contigmalloc(size, M_AGP, 807 0, 0, ~0, PAGE_SIZE, 0); 808 if (sc->argb_cursor == NULL) 809 return 0; 810 } 811 } 812 813 mem = malloc(sizeof *mem, M_AGP, M_WAITOK); 814 mem->am_id = sc->agp.as_nextid++; 815 mem->am_size = size; 816 mem->am_type = type; 817 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE)) 818 mem->am_obj = vm_object_allocate(OBJT_DEFAULT, 819 atop(round_page(size))); 820 else 821 mem->am_obj = 0; 822 823 if (type == 2) { 824 if (size == AGP_PAGE_SIZE) { 825 /* 826 * Allocate and wire down the page now so that we can 827 * get its physical address. 828 */ 829 vm_page_t m; 830 831 VM_OBJECT_LOCK(mem->am_obj); 832 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY | 833 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY); 834 VM_OBJECT_UNLOCK(mem->am_obj); 835 mem->am_physical = VM_PAGE_TO_PHYS(m); 836 } else { 837 /* Our allocation is already nicely wired down for us. 838 * Just grab the physical address. 839 */ 840 mem->am_physical = vtophys(sc->argb_cursor); 841 } 842 } else { 843 mem->am_physical = 0; 844 } 845 846 mem->am_offset = 0; 847 mem->am_is_bound = 0; 848 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link); 849 sc->agp.as_allocated += size; 850 851 return mem; 852} 853 854static int 855agp_i810_free_memory(device_t dev, struct agp_memory *mem) 856{ 857 struct agp_i810_softc *sc = device_get_softc(dev); 858 859 if (mem->am_is_bound) 860 return EBUSY; 861 862 if (mem->am_type == 2) { 863 if (mem->am_size == AGP_PAGE_SIZE) { 864 /* 865 * Unwire the page which we wired in alloc_memory. 866 */ 867 vm_page_t m; 868 869 VM_OBJECT_LOCK(mem->am_obj); 870 m = vm_page_lookup(mem->am_obj, 0); 871 VM_OBJECT_UNLOCK(mem->am_obj); 872 vm_page_lock_queues(); 873 vm_page_unwire(m, 0); 874 vm_page_unlock_queues(); 875 } else { 876 contigfree(sc->argb_cursor, mem->am_size, M_AGP); 877 sc->argb_cursor = NULL; 878 } 879 } 880 881 sc->agp.as_allocated -= mem->am_size; 882 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link); 883 if (mem->am_obj) 884 vm_object_deallocate(mem->am_obj); 885 free(mem, M_AGP); 886 return 0; 887} 888 889static int 890agp_i810_bind_memory(device_t dev, struct agp_memory *mem, 891 vm_offset_t offset) 892{ 893 struct agp_i810_softc *sc = device_get_softc(dev); 894 vm_offset_t i; 895 896 /* Do some sanity checks first. */ 897 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 || 898 offset + mem->am_size > AGP_GET_APERTURE(dev)) { 899 device_printf(dev, "binding memory at bad offset %#x\n", 900 (int)offset); 901 return EINVAL; 902 } 903 904 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 905 mtx_lock(&sc->agp.as_lock); 906 if (mem->am_is_bound) { 907 mtx_unlock(&sc->agp.as_lock); 908 return EINVAL; 909 } 910 /* The memory's already wired down, just stick it in the GTT. */ 911 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 912 agp_i810_write_gtt_entry(dev, offset + i, 913 mem->am_physical + i, 1); 914 } 915 agp_flush_cache(); 916 mem->am_offset = offset; 917 mem->am_is_bound = 1; 918 mtx_unlock(&sc->agp.as_lock); 919 return 0; 920 } 921 922 if (mem->am_type != 1) 923 return agp_generic_bind_memory(dev, mem, offset); 924 925 if ( sc->chiptype != CHIP_I810 ) 926 return EINVAL; 927 928 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 929 bus_write_4(sc->sc_res[0], 930 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3); 931 } 932 933 return 0; 934} 935 936static int 937agp_i810_unbind_memory(device_t dev, struct agp_memory *mem) 938{ 939 struct agp_i810_softc *sc = device_get_softc(dev); 940 vm_offset_t i; 941 942 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 943 mtx_lock(&sc->agp.as_lock); 944 if (!mem->am_is_bound) { 945 mtx_unlock(&sc->agp.as_lock); 946 return EINVAL; 947 } 948 949 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 950 agp_i810_write_gtt_entry(dev, mem->am_offset + i, 951 0, 0); 952 } 953 agp_flush_cache(); 954 mem->am_is_bound = 0; 955 mtx_unlock(&sc->agp.as_lock); 956 return 0; 957 } 958 959 if (mem->am_type != 1) 960 return agp_generic_unbind_memory(dev, mem); 961 962 if ( sc->chiptype != CHIP_I810 ) 963 return EINVAL; 964 965 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 966 bus_write_4(sc->sc_res[0], 967 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0); 968 } 969 970 return 0; 971} 972 973static device_method_t agp_i810_methods[] = { 974 /* Device interface */ 975 DEVMETHOD(device_identify, agp_i810_identify), 976 DEVMETHOD(device_probe, agp_i810_probe), 977 DEVMETHOD(device_attach, agp_i810_attach), 978 DEVMETHOD(device_detach, agp_i810_detach), 979 980 /* AGP interface */ 981 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture), 982 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture), 983 DEVMETHOD(agp_bind_page, agp_i810_bind_page), 984 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page), 985 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb), 986 DEVMETHOD(agp_enable, agp_i810_enable), 987 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory), 988 DEVMETHOD(agp_free_memory, agp_i810_free_memory), 989 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory), 990 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory), 991 992 { 0, 0 } 993}; 994 995static driver_t agp_i810_driver = { 996 "agp", 997 agp_i810_methods, 998 sizeof(struct agp_i810_softc), 999}; 1000 1001static devclass_t agp_devclass; 1002 1003DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0); 1004MODULE_DEPEND(agp_i810, agp, 1, 1, 1); 1005MODULE_DEPEND(agp_i810, pci, 1, 1, 1); 1006