agp_i810.c revision 159981
1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * Copyright (c) 2000 Ruslan Ermilov 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org> 30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org> 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/agp/agp_i810.c 159981 2006-06-27 14:05:11Z anholt $"); 35 36#include "opt_bus.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46#include <sys/proc.h> 47 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <pci/agppriv.h> 51#include <pci/agpreg.h> 52 53#include <vm/vm.h> 54#include <vm/vm_object.h> 55#include <vm/vm_page.h> 56#include <vm/vm_pageout.h> 57#include <vm/pmap.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63MALLOC_DECLARE(M_AGP); 64 65#define READ1(off) bus_space_read_1(sc->bst, sc->bsh, off) 66#define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off) 67#define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) 68#define WRITEGTT(off,v) bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v) 69 70#define CHIP_I810 0 /* i810/i815 */ 71#define CHIP_I830 1 /* 830M/845G */ 72#define CHIP_I855 2 /* 852GM/855GM/865G */ 73#define CHIP_I915 3 /* 915G/915GM */ 74 75struct agp_i810_softc { 76 struct agp_softc agp; 77 u_int32_t initial_aperture; /* aperture size at startup */ 78 struct agp_gatt *gatt; 79 int chiptype; /* i810-like or i830 */ 80 u_int32_t dcache_size; /* i810 only */ 81 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */ 82 device_t bdev; /* bridge device */ 83 84 struct resource *regs; /* memory mapped GC registers */ 85 bus_space_tag_t bst; /* bus_space tag */ 86 bus_space_handle_t bsh; /* bus_space handle */ 87 88 struct resource *gtt; /* memory mapped GATT entries */ 89 bus_space_tag_t gtt_bst; /* bus_space tag */ 90 bus_space_handle_t gtt_bsh; /* bus_space handle */ 91 92 void *argb_cursor; /* contigmalloc area for ARGB cursor */ 93}; 94 95/* For adding new devices, devid is the id of the graphics controller 96 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the 97 * second head should never be added. The bridge_offset is the offset to 98 * subtract from devid to get the id of the hostb that the device is on. 99 */ 100static const struct agp_i810_match { 101 int devid; 102 int chiptype; 103 int bridge_offset; 104 char *name; 105} agp_i810_matches[] = { 106 {0x71218086, CHIP_I810, 0x00010000, 107 "Intel 82810 (i810 GMCH) SVGA controller"}, 108 {0x71238086, CHIP_I810, 0x00010000, 109 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"}, 110 {0x71258086, CHIP_I810, 0x00010000, 111 "Intel 82810E (i810E GMCH) SVGA controller"}, 112 {0x11328086, CHIP_I810, 0x00020000, 113 "Intel 82815 (i815 GMCH) SVGA controller"}, 114 {0x35778086, CHIP_I830, 0x00020000, 115 "Intel 82830M (830M GMCH) SVGA controller"}, 116 {0x35828086, CHIP_I855, 0x00020000, 117 "Intel 82852/5"}, 118 {0x25728086, CHIP_I855, 0x00020000, 119 "Intel 82865G (865G GMCH) SVGA controller"}, 120 {0x25828086, CHIP_I915, 0x00020000, 121 "Intel 82915G (915G GMCH) SVGA controller"}, 122 {0x25928086, CHIP_I915, 0x00020000, 123 "Intel 82915GM (915GM GMCH) SVGA controller"}, 124 /* XXX: I believe these chipsets should work, but they haven't been 125 * tested yet. 126 */ 127 /* 128 {0x27728086, CHIP_I915, 0x00020000, 129 "Intel 82945G (945G GMCH) SVGA controller"}, 130 {0x27A28086, CHIP_I915, 0x00020000, 131 "Intel 82945GM (945GM GMCH) SVGA controller"}, 132 */ 133 {0, 0, 0, NULL} 134}; 135 136static const struct agp_i810_match* 137agp_i810_match(device_t dev) 138{ 139 int i, devid; 140 141 if (pci_get_class(dev) != PCIC_DISPLAY 142 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA) 143 return NULL; 144 145 devid = pci_get_devid(dev); 146 for (i = 0; agp_i810_matches[i].devid != 0; i++) { 147 if (agp_i810_matches[i].devid == devid) 148 break; 149 } 150 if (agp_i810_matches[i].devid == 0) 151 return NULL; 152 else 153 return &agp_i810_matches[i]; 154} 155 156/* 157 * Find bridge device. 158 */ 159static device_t 160agp_i810_find_bridge(device_t dev) 161{ 162 device_t *children, child; 163 int nchildren, i; 164 u_int32_t devid; 165 const struct agp_i810_match *match; 166 167 match = agp_i810_match(dev); 168 devid = match->devid - match->bridge_offset; 169 170 if (device_get_children(device_get_parent(device_get_parent(dev)), 171 &children, &nchildren)) 172 return 0; 173 174 for (i = 0; i < nchildren; i++) { 175 child = children[i]; 176 177 if (pci_get_devid(child) == devid) { 178 free(children, M_TEMP); 179 return child; 180 } 181 } 182 free(children, M_TEMP); 183 return 0; 184} 185 186static void 187agp_i810_identify(driver_t *driver, device_t parent) 188{ 189 190 if (device_find_child(parent, "agp", -1) == NULL && 191 agp_i810_match(parent)) 192 device_add_child(parent, "agp", -1); 193} 194 195static int 196agp_i810_probe(device_t dev) 197{ 198 device_t bdev; 199 const struct agp_i810_match *match; 200 201 if (resource_disabled("agp", device_get_unit(dev))) 202 return (ENXIO); 203 match = agp_i810_match(dev); 204 if (match == NULL) 205 return ENXIO; 206 207 bdev = agp_i810_find_bridge(dev); 208 if (!bdev) { 209 if (bootverbose) 210 printf("I810: can't find bridge device\n"); 211 return ENXIO; 212 } 213 214 /* 215 * checking whether internal graphics device has been activated. 216 */ 217 if (match->chiptype == CHIP_I810) { 218 u_int8_t smram; 219 220 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1); 221 if ((smram & AGP_I810_SMRAM_GMS) 222 == AGP_I810_SMRAM_GMS_DISABLED) { 223 if (bootverbose) 224 printf("I810: disabled, not probing\n"); 225 return ENXIO; 226 } 227 } else if (match->chiptype == CHIP_I830 || 228 match->chiptype == CHIP_I855) { 229 unsigned int gcc1; 230 231 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1); 232 if ((gcc1 & AGP_I830_GCC1_DEV2) == 233 AGP_I830_GCC1_DEV2_DISABLED) { 234 if (bootverbose) 235 printf("I830: disabled, not probing\n"); 236 return ENXIO; 237 } 238 } else if (match->chiptype == CHIP_I915) { 239 unsigned int gcc1; 240 241 gcc1 = pci_read_config(bdev, AGP_I915_DEVEN, 4); 242 if ((gcc1 & AGP_I915_DEVEN_D2F0) == 243 AGP_I915_DEVEN_D2F0_DISABLED) { 244 if (bootverbose) 245 printf("I915: disabled, not probing\n"); 246 return ENXIO; 247 } 248 } 249 250 if (match->devid == 0x35828086) { 251 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { 252 case AGP_I855_GME: 253 device_set_desc(dev, 254 "Intel 82855GME (855GME GMCH) SVGA controller"); 255 break; 256 case AGP_I855_GM: 257 device_set_desc(dev, 258 "Intel 82855GM (855GM GMCH) SVGA controller"); 259 break; 260 case AGP_I852_GME: 261 device_set_desc(dev, 262 "Intel 82852GME (852GME GMCH) SVGA controller"); 263 break; 264 case AGP_I852_GM: 265 device_set_desc(dev, 266 "Intel 82852GM (852GM GMCH) SVGA controller"); 267 break; 268 default: 269 device_set_desc(dev, 270 "Intel 8285xM (85xGM GMCH) SVGA controller"); 271 break; 272 } 273 } else { 274 device_set_desc(dev, match->name); 275 } 276 277 return BUS_PROBE_DEFAULT; 278} 279 280static int 281agp_i810_attach(device_t dev) 282{ 283 struct agp_i810_softc *sc = device_get_softc(dev); 284 struct agp_gatt *gatt; 285 const struct agp_i810_match *match; 286 int error, rid; 287 288 sc->bdev = agp_i810_find_bridge(dev); 289 if (!sc->bdev) 290 return ENOENT; 291 292 error = agp_generic_attach(dev); 293 if (error) 294 return error; 295 296 match = agp_i810_match(dev); 297 sc->chiptype = match->chiptype; 298 299 /* Same for i810 and i830 */ 300 if (sc->chiptype == CHIP_I915) 301 rid = AGP_I915_MMADR; 302 else 303 rid = AGP_I810_MMADR; 304 305 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 306 RF_ACTIVE); 307 if (!sc->regs) { 308 agp_generic_detach(dev); 309 return ENODEV; 310 } 311 sc->bst = rman_get_bustag(sc->regs); 312 sc->bsh = rman_get_bushandle(sc->regs); 313 314 if (sc->chiptype == CHIP_I915) { 315 rid = AGP_I915_GTTADR; 316 sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 317 RF_ACTIVE); 318 if (!sc->gtt) { 319 bus_release_resource(dev, SYS_RES_MEMORY, 320 AGP_I810_MMADR, sc->regs); 321 agp_generic_detach(dev); 322 return ENODEV; 323 } 324 sc->gtt_bst = rman_get_bustag(sc->gtt); 325 sc->gtt_bsh = rman_get_bushandle(sc->gtt); 326 } 327 328 sc->initial_aperture = AGP_GET_APERTURE(dev); 329 330 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 331 if (!gatt) { 332 agp_generic_detach(dev); 333 return ENOMEM; 334 } 335 sc->gatt = gatt; 336 337 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; 338 339 if ( sc->chiptype == CHIP_I810 ) { 340 /* Some i810s have on-chip memory called dcache */ 341 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 342 sc->dcache_size = 4 * 1024 * 1024; 343 else 344 sc->dcache_size = 0; 345 346 /* According to the specs the gatt on the i810 must be 64k */ 347 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0, 348 0, ~0, PAGE_SIZE, 0); 349 if (!gatt->ag_virtual) { 350 if (bootverbose) 351 device_printf(dev, "contiguous allocation failed\n"); 352 free(gatt, M_AGP); 353 agp_generic_detach(dev); 354 return ENOMEM; 355 } 356 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t)); 357 358 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); 359 agp_flush_cache(); 360 /* Install the GATT. */ 361 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 362 } else if ( sc->chiptype == CHIP_I830 ) { 363 /* The i830 automatically initializes the 128k gatt on boot. */ 364 unsigned int gcc1, pgtblctl; 365 366 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); 367 switch (gcc1 & AGP_I830_GCC1_GMS) { 368 case AGP_I830_GCC1_GMS_STOLEN_512: 369 sc->stolen = (512 - 132) * 1024 / 4096; 370 break; 371 case AGP_I830_GCC1_GMS_STOLEN_1024: 372 sc->stolen = (1024 - 132) * 1024 / 4096; 373 break; 374 case AGP_I830_GCC1_GMS_STOLEN_8192: 375 sc->stolen = (8192 - 132) * 1024 / 4096; 376 break; 377 default: 378 sc->stolen = 0; 379 device_printf(dev, "unknown memory configuration, disabling\n"); 380 agp_generic_detach(dev); 381 return EINVAL; 382 } 383 if (sc->stolen > 0) 384 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 385 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 386 387 /* GATT address is already in there, make sure it's enabled */ 388 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 389 pgtblctl |= 1; 390 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 391 392 gatt->ag_physical = pgtblctl & ~1; 393 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) { /* CHIP_I855 */ 394 unsigned int gcc1, pgtblctl, stolen; 395 396 /* Stolen memory is set up at the beginning of the aperture by 397 * the BIOS, consisting of the GATT followed by 4kb for the BIOS 398 * display. 399 */ 400 if (sc->chiptype == CHIP_I855) 401 stolen = 132; 402 else 403 stolen = 260; 404 405 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); 406 switch (gcc1 & AGP_I855_GCC1_GMS) { 407 case AGP_I855_GCC1_GMS_STOLEN_1M: 408 sc->stolen = (1024 - stolen) * 1024 / 4096; 409 break; 410 case AGP_I855_GCC1_GMS_STOLEN_4M: 411 sc->stolen = (4096 - stolen) * 1024 / 4096; 412 break; 413 case AGP_I855_GCC1_GMS_STOLEN_8M: 414 sc->stolen = (8192 - stolen) * 1024 / 4096; 415 break; 416 case AGP_I855_GCC1_GMS_STOLEN_16M: 417 sc->stolen = (16384 - stolen) * 1024 / 4096; 418 break; 419 case AGP_I855_GCC1_GMS_STOLEN_32M: 420 sc->stolen = (32768 - stolen) * 1024 / 4096; 421 break; 422 case AGP_I915_GCC1_GMS_STOLEN_48M: 423 sc->stolen = (49152 - stolen) * 1024 / 4096; 424 break; 425 case AGP_I915_GCC1_GMS_STOLEN_64M: 426 sc->stolen = (65536 - stolen) * 1024 / 4096; 427 break; 428 default: 429 sc->stolen = 0; 430 device_printf(dev, "unknown memory configuration, disabling\n"); 431 agp_generic_detach(dev); 432 return EINVAL; 433 } 434 if (sc->stolen > 0) 435 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 436 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 437 438 /* GATT address is already in there, make sure it's enabled */ 439 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 440 pgtblctl |= 1; 441 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 442 443 gatt->ag_physical = pgtblctl & ~1; 444 } 445 446 return 0; 447} 448 449static int 450agp_i810_detach(device_t dev) 451{ 452 struct agp_i810_softc *sc = device_get_softc(dev); 453 int error; 454 455 error = agp_generic_detach(dev); 456 if (error) 457 return error; 458 459 /* Clear the GATT base. */ 460 if ( sc->chiptype == CHIP_I810 ) { 461 WRITE4(AGP_I810_PGTBL_CTL, 0); 462 } else { 463 unsigned int pgtblctl; 464 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 465 pgtblctl &= ~1; 466 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 467 } 468 469 /* Put the aperture back the way it started. */ 470 AGP_SET_APERTURE(dev, sc->initial_aperture); 471 472 if ( sc->chiptype == CHIP_I810 ) { 473 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP); 474 } 475 free(sc->gatt, M_AGP); 476 477 if (sc->chiptype == CHIP_I915) { 478 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GTTADR, 479 sc->gtt); 480 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR, 481 sc->regs); 482 } else { 483 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR, 484 sc->regs); 485 } 486 487 return 0; 488} 489 490static u_int32_t 491agp_i810_get_aperture(device_t dev) 492{ 493 struct agp_i810_softc *sc = device_get_softc(dev); 494 uint32_t temp; 495 u_int16_t miscc; 496 497 switch (sc->chiptype) { 498 case CHIP_I810: 499 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 500 if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32) 501 return 32 * 1024 * 1024; 502 else 503 return 64 * 1024 * 1024; 504 case CHIP_I830: 505 temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 506 if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 507 return 64 * 1024 * 1024; 508 else 509 return 128 * 1024 * 1024; 510 case CHIP_I855: 511 return 128 * 1024 * 1024; 512 case CHIP_I915: 513 temp = pci_read_config(dev, AGP_I915_MSAC, 1); 514 if ((temp & AGP_I915_MSAC_GMASIZE) == 515 AGP_I915_MSAC_GMASIZE_128) { 516 return 128 * 1024 * 1024; 517 } else { 518 return 256 * 1024 * 1024; 519 } 520 } 521 522 return 0; 523} 524 525static int 526agp_i810_set_aperture(device_t dev, u_int32_t aperture) 527{ 528 struct agp_i810_softc *sc = device_get_softc(dev); 529 u_int16_t miscc, gcc1; 530 u_int32_t temp; 531 532 switch (sc->chiptype) { 533 case CHIP_I810: 534 /* 535 * Double check for sanity. 536 */ 537 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { 538 device_printf(dev, "bad aperture size %d\n", aperture); 539 return EINVAL; 540 } 541 542 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 543 miscc &= ~AGP_I810_MISCC_WINSIZE; 544 if (aperture == 32 * 1024 * 1024) 545 miscc |= AGP_I810_MISCC_WINSIZE_32; 546 else 547 miscc |= AGP_I810_MISCC_WINSIZE_64; 548 549 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); 550 break; 551 case CHIP_I830: 552 if (aperture != 64 * 1024 * 1024 && 553 aperture != 128 * 1024 * 1024) { 554 device_printf(dev, "bad aperture size %d\n", aperture); 555 return EINVAL; 556 } 557 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 558 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 559 if (aperture == 64 * 1024 * 1024) 560 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 561 else 562 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 563 564 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); 565 break; 566 case CHIP_I855: 567 if (aperture != 128 * 1024 * 1024) { 568 device_printf(dev, "bad aperture size %d\n", aperture); 569 return EINVAL; 570 } 571 break; 572 case CHIP_I915: 573 temp = pci_read_config(dev, AGP_I915_MSAC, 1); 574 temp &= ~AGP_I915_MSAC_GMASIZE; 575 576 switch (aperture) { 577 case 128 * 1024 * 1024: 578 temp |= AGP_I915_MSAC_GMASIZE_128; 579 break; 580 case 256 * 1024 * 1024: 581 temp |= AGP_I915_MSAC_GMASIZE_256; 582 break; 583 default: 584 device_printf(dev, "bad aperture size %d\n", aperture); 585 return EINVAL; 586 } 587 588 pci_write_config(dev, AGP_I915_MSAC, temp, 1); 589 break; 590 } 591 592 return 0; 593} 594 595static int 596agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical) 597{ 598 struct agp_i810_softc *sc = device_get_softc(dev); 599 600 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 601 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries); 602 return EINVAL; 603 } 604 605 if ( sc->chiptype != CHIP_I810 ) { 606 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 607 device_printf(dev, "trying to bind into stolen memory"); 608 return EINVAL; 609 } 610 } 611 612 if (sc->chiptype == CHIP_I915) { 613 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, physical | 1); 614 } else { 615 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1); 616 } 617 618 return 0; 619} 620 621static int 622agp_i810_unbind_page(device_t dev, int offset) 623{ 624 struct agp_i810_softc *sc = device_get_softc(dev); 625 626 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 627 return EINVAL; 628 629 if ( sc->chiptype != CHIP_I810 ) { 630 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 631 device_printf(dev, "trying to unbind from stolen memory"); 632 return EINVAL; 633 } 634 } 635 636 if (sc->chiptype == CHIP_I915) { 637 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, 0); 638 } else { 639 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0); 640 } 641 642 return 0; 643} 644 645/* 646 * Writing via memory mapped registers already flushes all TLBs. 647 */ 648static void 649agp_i810_flush_tlb(device_t dev) 650{ 651} 652 653static int 654agp_i810_enable(device_t dev, u_int32_t mode) 655{ 656 657 return 0; 658} 659 660static struct agp_memory * 661agp_i810_alloc_memory(device_t dev, int type, vm_size_t size) 662{ 663 struct agp_i810_softc *sc = device_get_softc(dev); 664 struct agp_memory *mem; 665 666 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 667 return 0; 668 669 if (sc->agp.as_allocated + size > sc->agp.as_maxmem) 670 return 0; 671 672 if (type == 1) { 673 /* 674 * Mapping local DRAM into GATT. 675 */ 676 if ( sc->chiptype != CHIP_I810 ) 677 return 0; 678 if (size != sc->dcache_size) 679 return 0; 680 } else if (type == 2) { 681 /* 682 * Type 2 is the contiguous physical memory type, that hands 683 * back a physical address. This is used for cursors on i810. 684 * Hand back as many single pages with physical as the user 685 * wants, but only allow one larger allocation (ARGB cursor) 686 * for simplicity. 687 */ 688 if (size != AGP_PAGE_SIZE) { 689 if (sc->argb_cursor != NULL) 690 return 0; 691 692 /* Allocate memory for ARGB cursor, if we can. */ 693 sc->argb_cursor = contigmalloc(size, M_AGP, 694 0, 0, ~0, PAGE_SIZE, 0); 695 if (sc->argb_cursor == NULL) 696 return 0; 697 } 698 } 699 700 mem = malloc(sizeof *mem, M_AGP, M_WAITOK); 701 mem->am_id = sc->agp.as_nextid++; 702 mem->am_size = size; 703 mem->am_type = type; 704 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE)) 705 mem->am_obj = vm_object_allocate(OBJT_DEFAULT, 706 atop(round_page(size))); 707 else 708 mem->am_obj = 0; 709 710 if (type == 2) { 711 if (size == AGP_PAGE_SIZE) { 712 /* 713 * Allocate and wire down the page now so that we can 714 * get its physical address. 715 */ 716 vm_page_t m; 717 718 VM_OBJECT_LOCK(mem->am_obj); 719 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY | 720 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY); 721 VM_OBJECT_UNLOCK(mem->am_obj); 722 mem->am_physical = VM_PAGE_TO_PHYS(m); 723 } else { 724 /* Our allocation is already nicely wired down for us. 725 * Just grab the physical address. 726 */ 727 mem->am_physical = vtophys(sc->argb_cursor); 728 } 729 } else { 730 mem->am_physical = 0; 731 } 732 733 mem->am_offset = 0; 734 mem->am_is_bound = 0; 735 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link); 736 sc->agp.as_allocated += size; 737 738 return mem; 739} 740 741static int 742agp_i810_free_memory(device_t dev, struct agp_memory *mem) 743{ 744 struct agp_i810_softc *sc = device_get_softc(dev); 745 746 if (mem->am_is_bound) 747 return EBUSY; 748 749 if (mem->am_type == 2) { 750 if (mem->am_size == AGP_PAGE_SIZE) { 751 /* 752 * Unwire the page which we wired in alloc_memory. 753 */ 754 vm_page_t m; 755 756 VM_OBJECT_LOCK(mem->am_obj); 757 m = vm_page_lookup(mem->am_obj, 0); 758 VM_OBJECT_UNLOCK(mem->am_obj); 759 vm_page_lock_queues(); 760 vm_page_unwire(m, 0); 761 vm_page_unlock_queues(); 762 } else { 763 contigfree(sc->argb_cursor, mem->am_size, M_AGP); 764 sc->argb_cursor = NULL; 765 } 766 } 767 768 sc->agp.as_allocated -= mem->am_size; 769 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link); 770 if (mem->am_obj) 771 vm_object_deallocate(mem->am_obj); 772 free(mem, M_AGP); 773 return 0; 774} 775 776static int 777agp_i810_bind_memory(device_t dev, struct agp_memory *mem, 778 vm_offset_t offset) 779{ 780 struct agp_i810_softc *sc = device_get_softc(dev); 781 vm_offset_t i; 782 783 /* Do some sanity checks first. */ 784 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 || 785 offset + mem->am_size > AGP_GET_APERTURE(dev)) { 786 device_printf(dev, "binding memory at bad offset %#x\n", 787 (int)offset); 788 return EINVAL; 789 } 790 791 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 792 mtx_lock(&sc->agp.as_lock); 793 if (mem->am_is_bound) { 794 mtx_unlock(&sc->agp.as_lock); 795 return EINVAL; 796 } 797 /* The memory's already wired down, just stick it in the GTT. */ 798 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 799 u_int32_t physical = mem->am_physical + i; 800 801 if (sc->chiptype == CHIP_I915) { 802 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4, 803 physical | 1); 804 } else { 805 WRITE4(AGP_I810_GTT + 806 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 807 physical | 1); 808 } 809 } 810 agp_flush_cache(); 811 mem->am_offset = offset; 812 mem->am_is_bound = 1; 813 mtx_unlock(&sc->agp.as_lock); 814 return 0; 815 } 816 817 if (mem->am_type != 1) 818 return agp_generic_bind_memory(dev, mem, offset); 819 820 if ( sc->chiptype != CHIP_I810 ) 821 return EINVAL; 822 823 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 824 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 825 i | 3); 826 } 827 828 return 0; 829} 830 831static int 832agp_i810_unbind_memory(device_t dev, struct agp_memory *mem) 833{ 834 struct agp_i810_softc *sc = device_get_softc(dev); 835 vm_offset_t i; 836 837 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 838 mtx_lock(&sc->agp.as_lock); 839 if (!mem->am_is_bound) { 840 mtx_unlock(&sc->agp.as_lock); 841 return EINVAL; 842 } 843 844 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 845 vm_offset_t offset = mem->am_offset; 846 847 if (sc->chiptype == CHIP_I915) { 848 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4, 849 0); 850 } else { 851 WRITE4(AGP_I810_GTT + 852 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 0); 853 } 854 } 855 agp_flush_cache(); 856 mem->am_is_bound = 0; 857 mtx_unlock(&sc->agp.as_lock); 858 return 0; 859 } 860 861 if (mem->am_type != 1) 862 return agp_generic_unbind_memory(dev, mem); 863 864 if ( sc->chiptype != CHIP_I810 ) 865 return EINVAL; 866 867 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 868 WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0); 869 870 return 0; 871} 872 873static device_method_t agp_i810_methods[] = { 874 /* Device interface */ 875 DEVMETHOD(device_identify, agp_i810_identify), 876 DEVMETHOD(device_probe, agp_i810_probe), 877 DEVMETHOD(device_attach, agp_i810_attach), 878 DEVMETHOD(device_detach, agp_i810_detach), 879 880 /* AGP interface */ 881 DEVMETHOD(agp_get_aperture, agp_i810_get_aperture), 882 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture), 883 DEVMETHOD(agp_bind_page, agp_i810_bind_page), 884 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page), 885 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb), 886 DEVMETHOD(agp_enable, agp_i810_enable), 887 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory), 888 DEVMETHOD(agp_free_memory, agp_i810_free_memory), 889 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory), 890 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory), 891 892 { 0, 0 } 893}; 894 895static driver_t agp_i810_driver = { 896 "agp", 897 agp_i810_methods, 898 sizeof(struct agp_i810_softc), 899}; 900 901static devclass_t agp_devclass; 902 903DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0); 904MODULE_DEPEND(agp_i810, agp, 1, 1, 1); 905MODULE_DEPEND(agp_i810, pci, 1, 1, 1); 906