adwmcode.h revision 40024
140024Sgibbs/* 240024Sgibbs * Exported interface to downloadable microcode for AdvanSys SCSI Adapters 340024Sgibbs * 440024Sgibbs * $Id: advmcode.h,v 1.4 1998/09/15 07:03:34 gibbs Exp $ 540024Sgibbs * 640024Sgibbs * Obtained from: 740024Sgibbs * 840024Sgibbs * Copyright (c) 1995-1998 Advanced System Products, Inc. 940024Sgibbs * All Rights Reserved. 1040024Sgibbs * 1140024Sgibbs * Redistribution and use in source and binary forms, with or without 1240024Sgibbs * modification, are permitted provided that redistributions of source 1340024Sgibbs * code retain the above copyright notice and this comment without 1440024Sgibbs * modification. 1540024Sgibbs */ 1640024Sgibbs 1740024Sgibbs#ifndef _ADMCODE_H_ 1840024Sgibbs#define _ADMCODE_H_ 1940024Sgibbs 2040024Sgibbsextern u_int16_t adw_mcode[]; 2140024Sgibbsextern u_int16_t adw_mcode_size; 2240024Sgibbsextern u_int32_t adw_mcode_chksum; 2340024Sgibbs 2440024Sgibbs/* 2540024Sgibbs * Fixed LRAM locations of microcode operating variables. 2640024Sgibbs */ 2740024Sgibbs#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 2840024Sgibbs#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */ 2940024Sgibbs#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 3040024Sgibbs#define ADW_MC_STACK_BEGIN 0x002E /* microcode stack begin */ 3140024Sgibbs#define ADW_MC_STACK_END 0x0030 /* microcode stack end */ 3240024Sgibbs#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */ 3340024Sgibbs#define ADW_MC_VERSION_NUM 0x003A /* microcode number */ 3440024Sgibbs#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 3540024Sgibbs#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 3640024Sgibbs#define ADW_MC_HALTCODE 0x0094 /* microcode halt code */ 3740024Sgibbs#define ADW_MC_CALLERPC 0x0096 /* microcode halt caller PC */ 3840024Sgibbs#define ADW_MC_ADAPTER_SCSI_ID 0x0098 /* one ID byte + reserved */ 3940024Sgibbs#define ADW_MC_ULTRA_ABLE 0x009C 4040024Sgibbs#define ADW_MC_SDTR_ABLE 0x009E 4140024Sgibbs#define ADW_MC_TAGQNG_ABLE 0x00A0 4240024Sgibbs#define ADW_MC_DISC_ENABLE 0x00A2 4340024Sgibbs#define ADW_MC_IDLE_CMD 0x00A6 4440024Sgibbs#define ADW_MC_IDLE_PARA_STAT 0x00A8 4540024Sgibbs#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC 4640024Sgibbs#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE 4740024Sgibbs#define ADW_MC_DEFAULT_MEM_CFG 0x00B0 4840024Sgibbs#define ADW_MC_DEFAULT_SEL_MASK 0x00B2 4940024Sgibbs#define ADW_MC_RISC_NEXT_READY 0x00B4 5040024Sgibbs#define ADW_MC_RISC_NEXT_DONE 0x00B5 5140024Sgibbs#define ADW_MC_SDTR_DONE 0x00B6 5240024Sgibbs#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0 5340024Sgibbs#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0 5440024Sgibbs#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100 5540024Sgibbs#define ADW_HSHK_CFG_WIDE_XFR 0x8000 5640024Sgibbs#define ADW_HSHK_CFG_RATE_MASK 0x0F00 5740024Sgibbs#define ADW_HSHK_CFG_RATE_SHIFT 8 5840024Sgibbs#define ADW_HSHK_CFG_PERIOD_FACTOR(cfg_val) \ 5940024Sgibbs((((((cfg_val) & ADW_HSHK_CFG_RATE_MASK) >> ADW_HSHK_CFG_RATE_SHIFT) \ 6040024Sgibbs * 25) + 50)/4) 6140024Sgibbs#define ADW_HSHK_CFG_OFFSET 0x001F 6240024Sgibbs#define ADW_MC_WDTR_ABLE 0x0120 /* Wide Transfer TID bitmask. */ 6340024Sgibbs#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 6440024Sgibbs#define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */ 6540024Sgibbs#define ADW_MC_WDTR_DONE 0x0124 6640024Sgibbs#define ADW_MC_HOST_NEXT_READY 0x0128 /* Host Next Ready RQL Entry. */ 6740024Sgibbs#define ADW_MC_HOST_NEXT_DONE 0x0129 /* Host Next Done RQL Entry. */ 6840024Sgibbs 6940024Sgibbs/* 7040024Sgibbs * LRAM RISC Queue Lists (LRAM addresses 0x1200 - 0x19FF) 7140024Sgibbs * 7240024Sgibbs * Each of the 255 Adv Library/Microcode RISC queue lists or mailboxes 7340024Sgibbs * starting at LRAM address 0x1200 is 8 bytes and has the following 7440024Sgibbs * structure. Only 253 of these are actually used for command queues. 7540024Sgibbs */ 7640024Sgibbs#define ADW_MC_RISC_Q_LIST_BASE 0x1200 7740024Sgibbs#define ADW_MC_RISC_Q_LIST_SIZE 0x0008 7840024Sgibbs#define ADW_MC_RISC_Q_TOTAL_CNT 0x00FF /* Num. queue slots in LRAM. */ 7940024Sgibbs#define ADW_MC_RISC_Q_FIRST 0x0001 8040024Sgibbs#define ADW_MC_RISC_Q_LAST 0x00FF 8140024Sgibbs 8240024Sgibbs/* RISC Queue List structure - 8 bytes */ 8340024Sgibbs#define RQL_FWD 0 /* forward pointer (1 byte) */ 8440024Sgibbs#define RQL_BWD 1 /* backward pointer (1 byte) */ 8540024Sgibbs#define RQL_STATE 2 /* state byte - free, ready, done, aborted (1 byte) */ 8640024Sgibbs#define RQL_TID 3 /* request target id (1 byte) */ 8740024Sgibbs#define RQL_PHYADDR 4 /* request physical pointer (4 bytes) */ 8840024Sgibbs 8940024Sgibbs/* RISC Queue List state values */ 9040024Sgibbs#define ADW_MC_QS_FREE 0x00 9140024Sgibbs#define ADW_MC_QS_READY 0x01 9240024Sgibbs#define ADW_MC_QS_DONE 0x40 9340024Sgibbs#define ADW_MC_QS_ABORTED 0x80 9440024Sgibbs 9540024Sgibbs/* RISC Queue List pointer values */ 9640024Sgibbs#define ADW_MC_NULL_Q 0x00 9740024Sgibbs#define ADW_MC_BIOS_Q 0xFF 9840024Sgibbs 9940024Sgibbs/* ADW_SCSI_REQ_Q 'cntl' field values */ 10040024Sgibbs#define ADW_MC_QC_START_MOTOR 0x02 /* Issue start motor. */ 10140024Sgibbs#define ADW_MC_QC_NO_OVERRUN 0x04 /* Don't report overrun. */ 10240024Sgibbs#define ADW_MC_QC_FIRST_DMA 0x08 /* Internal microcode flag. */ 10340024Sgibbs#define ADW_MC_QC_ABORTED 0x10 /* Request aborted by host. */ 10440024Sgibbs#define ADW_MC_QC_REQ_SENSE 0x20 /* Auto-Request Sense. */ 10540024Sgibbs#define ADW_MC_QC_DOS_REQ 0x80 /* Request issued by DOS. */ 10640024Sgibbs 10740024Sgibbs/* 10840024Sgibbs * Microcode idle loop commands 10940024Sgibbs */ 11040024Sgibbstypedef enum { 11140024Sgibbs ADW_IDLE_CMD_COMPLETED = 0x0000, 11240024Sgibbs ADW_IDLE_CMD_STOP_CHIP = 0x0001, 11340024Sgibbs ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002, 11440024Sgibbs ADW_IDLE_CMD_SEND_INT = 0x0004, 11540024Sgibbs ADW_IDLE_CMD_ABORT = 0x0008, 11640024Sgibbs ADW_IDLE_CMD_DEVICE_RESET = 0x0010, 11740024Sgibbs ADW_IDLE_CMD_SCSI_RESET = 0x0020 11840024Sgibbs} adw_idle_cmd_t; 11940024Sgibbs 12040024Sgibbstypedef enum { 12140024Sgibbs ADW_IDLE_CMD_FAILURE = 0x0000, 12240024Sgibbs ADW_IDLE_CMD_SUCCESS = 0x0001 12340024Sgibbs} adw_idle_cmd_status_t; 12440024Sgibbs 12540024Sgibbs 12640024Sgibbs#endif /* _ADMCODE_H_ */ 127