1139749Simp/*- 240024Sgibbs * Exported interface to downloadable microcode for AdvanSys SCSI Adapters 340024Sgibbs * 450477Speter * $FreeBSD$ 540024Sgibbs * 640024Sgibbs * Obtained from: 740024Sgibbs * 856979Sgibbs * Copyright (c) 1995-1999 Advanced System Products, Inc. 940024Sgibbs * All Rights Reserved. 1040024Sgibbs * 1140024Sgibbs * Redistribution and use in source and binary forms, with or without 1240024Sgibbs * modification, are permitted provided that redistributions of source 1340024Sgibbs * code retain the above copyright notice and this comment without 1440024Sgibbs * modification. 1540024Sgibbs */ 1640024Sgibbs 1740024Sgibbs#ifndef _ADMCODE_H_ 1840024Sgibbs#define _ADMCODE_H_ 1940024Sgibbs 2056979Sgibbsstruct adw_mcode 2156979Sgibbs{ 2256979Sgibbs const u_int8_t* mcode_buf; 2356979Sgibbs const u_int32_t mcode_chksum; 2456979Sgibbs const u_int16_t mcode_size; 2556979Sgibbs}; 2640024Sgibbs 2756979Sgibbsextern const struct adw_mcode adw_asc3550_mcode_data; 2856979Sgibbsextern const struct adw_mcode adw_asc38C0800_mcode_data; 2956979Sgibbs 3040024Sgibbs/* 3140024Sgibbs * Fixed LRAM locations of microcode operating variables. 3240024Sgibbs */ 3340024Sgibbs#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 3440024Sgibbs#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */ 3540024Sgibbs#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 3640024Sgibbs#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */ 3740024Sgibbs#define ADW_MC_VERSION_NUM 0x003A /* microcode number */ 3840024Sgibbs#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 3940024Sgibbs#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 4056979Sgibbs#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 4156979Sgibbs#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 Bytes) */ 4256979Sgibbs#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 4356979Sgibbs#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 4456979Sgibbs#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 4556979Sgibbs#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 4656979Sgibbs#define ADW_MC_CHIP_TYPE 0x009A 4756979Sgibbs#define ADW_MC_INTRB_CODE 0x009B 4856979Sgibbs#define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 4956979Sgibbs#define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected Bus Reset. */ 5056979Sgibbs#define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure.*/ 5156979Sgibbs#define ADW_ASYNC_HOST_SCSI_BUS_RESET 0x80 /* 5256979Sgibbs * Host Initiated 5356979Sgibbs * SCSI Bus Reset. 5456979Sgibbs */ 5556979Sgibbs#define ADW_MC_WDTR_ABLE_BIOS_31 0x0120 5656979Sgibbs#define ADW_MC_WDTR_ABLE 0x009C 5740024Sgibbs#define ADW_MC_SDTR_ABLE 0x009E 5840024Sgibbs#define ADW_MC_TAGQNG_ABLE 0x00A0 5940024Sgibbs#define ADW_MC_DISC_ENABLE 0x00A2 6056979Sgibbs#define ADW_MC_IDLE_CMD_STATUS 0x00A4 6140024Sgibbs#define ADW_MC_IDLE_CMD 0x00A6 6256979Sgibbs#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8 6340024Sgibbs#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC 6440024Sgibbs#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE 6540024Sgibbs#define ADW_MC_DEFAULT_MEM_CFG 0x00B0 6640024Sgibbs#define ADW_MC_DEFAULT_SEL_MASK 0x00B2 6740024Sgibbs#define ADW_MC_RISC_NEXT_READY 0x00B4 6840024Sgibbs#define ADW_MC_RISC_NEXT_DONE 0x00B5 6940024Sgibbs#define ADW_MC_SDTR_DONE 0x00B6 7040024Sgibbs#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0 7140024Sgibbs#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0 7240024Sgibbs#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100 7340024Sgibbs#define ADW_HSHK_CFG_WIDE_XFR 0x8000 7456979Sgibbs#define ADW_HSHK_CFG_RATE_MASK 0x7F00 7540024Sgibbs#define ADW_HSHK_CFG_RATE_SHIFT 8 7640024Sgibbs#define ADW_HSHK_CFG_OFFSET 0x001F 7740024Sgibbs#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 7840024Sgibbs#define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */ 7940024Sgibbs#define ADW_MC_WDTR_DONE 0x0124 8056979Sgibbs#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 8156979Sgibbs#define ADW_MC_ICQ 0x0160 8256979Sgibbs#define ADW_MC_IRQ 0x0164 8340024Sgibbs 8456979Sgibbs/* ADW_SCSI_REQ_Q 'cntl' field values */ 8556979Sgibbs#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */ 8656979Sgibbs#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 8756979Sgibbs#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 8856979Sgibbs#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 8956979Sgibbs#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXXTBD */ 9056979Sgibbs 9156979Sgibbs#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 9256979Sgibbs#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 9356979Sgibbs#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request.*/ 9456979Sgibbs#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 9556979Sgibbs#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request.*/ 9640024Sgibbs/* 9756979Sgibbs * Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or 9856979Sgibbs * ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 9940024Sgibbs */ 10056979Sgibbs#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 10156979Sgibbs#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 10240024Sgibbs 10356979Sgibbsstruct adw_carrier 10456979Sgibbs{ 10556979Sgibbs u_int32_t carr_offset; /* Carrier byte offset into our array */ 10656979Sgibbs u_int32_t carr_ba; /* Carrier Bus Address */ 10756979Sgibbs u_int32_t areq_ba; /* SCSI Req Queue Bus Address */ 10856979Sgibbs u_int32_t next_ba; 10956979Sgibbs#define ADW_RQ_DONE 0x00000001 11056979Sgibbs#define ADW_CQ_STOPPER 0x00000000 11156979Sgibbs#define ADW_NEXT_BA_MASK 0xFFFFFFF0 11256979Sgibbs}; 11340024Sgibbs 11440024Sgibbs/* 11540024Sgibbs * Microcode idle loop commands 11640024Sgibbs */ 11740024Sgibbstypedef enum { 11840024Sgibbs ADW_IDLE_CMD_COMPLETED = 0x0000, 11940024Sgibbs ADW_IDLE_CMD_STOP_CHIP = 0x0001, 12040024Sgibbs ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002, 12140024Sgibbs ADW_IDLE_CMD_SEND_INT = 0x0004, 12240024Sgibbs ADW_IDLE_CMD_ABORT = 0x0008, 12340024Sgibbs ADW_IDLE_CMD_DEVICE_RESET = 0x0010, 12456979Sgibbs ADW_IDLE_CMD_SCSI_RESET_START = 0x0020, 12556979Sgibbs ADW_IDLE_CMD_SCSI_RESET_END = 0x0040, 12656979Sgibbs ADW_IDLE_CMD_SCSIREQ = 0x0080 12740024Sgibbs} adw_idle_cmd_t; 12840024Sgibbs 12940024Sgibbstypedef enum { 13040024Sgibbs ADW_IDLE_CMD_FAILURE = 0x0000, 13140024Sgibbs ADW_IDLE_CMD_SUCCESS = 0x0001 13240024Sgibbs} adw_idle_cmd_status_t; 13340024Sgibbs 13440024Sgibbs 13540024Sgibbs#endif /* _ADMCODE_H_ */ 136