adwlib.c revision 241588
1/*- 2 * Low level routines for Second Generation 3 * Advanced Systems Inc. SCSI controllers chips 4 * 5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32/*- 33 * Ported from: 34 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 35 * 36 * Copyright (c) 1995-1998 Advanced System Products, Inc. 37 * All Rights Reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that redistributions of source 41 * code retain the above copyright notice and this comment without 42 * modification. 43 */ 44 45#include <sys/cdefs.h> 46__FBSDID("$FreeBSD: head/sys/dev/advansys/adwlib.c 241588 2012-10-15 15:26:00Z jhb $"); 47 48#include <sys/param.h> 49#include <sys/conf.h> 50#include <sys/lock.h> 51#include <sys/mutex.h> 52#include <sys/systm.h> 53#include <sys/bus.h> 54#include <sys/rman.h> 55 56#include <machine/bus.h> 57 58#include <cam/cam.h> 59#include <cam/cam_ccb.h> 60#include <cam/cam_sim.h> 61#include <cam/cam_xpt_sim.h> 62#include <cam/scsi/scsi_all.h> 63 64#include <dev/advansys/adwlib.h> 65 66const struct adw_eeprom adw_asc3550_default_eeprom = 67{ 68 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 69 0x0000, /* cfg_msw */ 70 0xFFFF, /* disc_enable */ 71 0xFFFF, /* wdtr_able */ 72 { 0xFFFF }, /* sdtr_able */ 73 0xFFFF, /* start_motor */ 74 0xFFFF, /* tagqng_able */ 75 0xFFFF, /* bios_scan */ 76 0, /* scam_tolerant */ 77 7, /* adapter_scsi_id */ 78 0, /* bios_boot_delay */ 79 3, /* scsi_reset_delay */ 80 0, /* bios_id_lun */ 81 0, /* termination */ 82 0, /* reserved1 */ 83 0xFFE7, /* bios_ctrl */ 84 { 0xFFFF }, /* ultra_able */ 85 { 0 }, /* reserved2 */ 86 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */ 87 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 88 0, /* dvc_cntl */ 89 { 0 }, /* bug_fix */ 90 { 0, 0, 0 }, /* serial_number */ 91 0, /* check_sum */ 92 { /* oem_name[16] */ 93 0, 0, 0, 0, 0, 0, 0, 0, 94 0, 0, 0, 0, 0, 0, 0, 0 95 }, 96 0, /* dvc_err_code */ 97 0, /* adv_err_code */ 98 0, /* adv_err_addr */ 99 0, /* saved_dvc_err_code */ 100 0, /* saved_adv_err_code */ 101 0 /* saved_adv_err_addr */ 102}; 103 104const struct adw_eeprom adw_asc38C0800_default_eeprom = 105{ 106 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 107 0x0000, /* 01 cfg_msw */ 108 0xFFFF, /* 02 disc_enable */ 109 0xFFFF, /* 03 wdtr_able */ 110 { 0x4444 }, /* 04 sdtr_speed1 */ 111 0xFFFF, /* 05 start_motor */ 112 0xFFFF, /* 06 tagqng_able */ 113 0xFFFF, /* 07 bios_scan */ 114 0, /* 08 scam_tolerant */ 115 7, /* 09 adapter_scsi_id */ 116 0, /* bios_boot_delay */ 117 3, /* 10 scsi_reset_delay */ 118 0, /* bios_id_lun */ 119 0, /* 11 termination_se */ 120 0, /* termination_lvd */ 121 0xFFE7, /* 12 bios_ctrl */ 122 { 0x4444 }, /* 13 sdtr_speed2 */ 123 { 0x4444 }, /* 14 sdtr_speed3 */ 124 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 125 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 126 0, /* 16 dvc_cntl */ 127 { 0x4444 } , /* 17 sdtr_speed4 */ 128 { 0, 0, 0 }, /* 18-20 serial_number */ 129 0, /* 21 check_sum */ 130 { /* 22-29 oem_name[16] */ 131 0, 0, 0, 0, 0, 0, 0, 0, 132 0, 0, 0, 0, 0, 0, 0, 0 133 }, 134 0, /* 30 dvc_err_code */ 135 0, /* 31 adv_err_code */ 136 0, /* 32 adv_err_addr */ 137 0, /* 33 saved_dvc_err_code */ 138 0, /* 34 saved_adv_err_code */ 139 0, /* 35 saved_adv_err_addr */ 140 { /* 36 - 55 reserved */ 141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 142 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 143 }, 144 0, /* 56 cisptr_lsw */ 145 0, /* 57 cisprt_msw */ 146 /* 58-59 sub-id */ 147 (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32, 148}; 149 150#define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0 151#define ADW_MC_SDTR_OFFSET_ULTRA2 1 152#define ADW_MC_SDTR_OFFSET_ULTRA 2 153const struct adw_syncrate adw_syncrates[] = 154{ 155 /* mc_sdtr period rate */ 156 { ADW_MC_SDTR_80, 9, "80.0" }, 157 { ADW_MC_SDTR_40, 10, "40.0" }, 158 { ADW_MC_SDTR_20, 12, "20.0" }, 159 { ADW_MC_SDTR_10, 25, "10.0" }, 160 { ADW_MC_SDTR_5, 50, "5.0" }, 161 { ADW_MC_SDTR_ASYNC, 0, "async" } 162}; 163 164const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]); 165 166static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr); 167static void adw_eeprom_write_16(struct adw_softc *adw, int addr, 168 u_int data); 169static void adw_eeprom_wait(struct adw_softc *adw); 170 171int 172adw_find_signature(struct adw_softc *adw) 173{ 174 if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE 175 && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD) 176 return (1); 177 return (0); 178} 179 180/* 181 * Reset Chip. 182 */ 183void 184adw_reset_chip(struct adw_softc *adw) 185{ 186 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET); 187 DELAY(1000 * 100); 188 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG); 189 190 /* 191 * Initialize Chip registers. 192 */ 193 adw_outw(adw, ADW_SCSI_CFG1, 194 adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN); 195} 196 197/* 198 * Reset the SCSI bus. 199 */ 200int 201adw_reset_bus(struct adw_softc *adw) 202{ 203 adw_idle_cmd_status_t status; 204 205 if (!dumping) 206 mtx_assert(&adw->lock, MA_OWNED); 207 status = 208 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0); 209 if (status != ADW_IDLE_CMD_SUCCESS) { 210 xpt_print_path(adw->path); 211 printf("Bus Reset start attempt failed\n"); 212 return (1); 213 } 214 DELAY(ADW_BUS_RESET_HOLD_DELAY_US); 215 status = 216 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0); 217 if (status != ADW_IDLE_CMD_SUCCESS) { 218 xpt_print_path(adw->path); 219 printf("Bus Reset end attempt failed\n"); 220 return (1); 221 } 222 return (0); 223} 224 225/* 226 * Read the specified EEPROM location 227 */ 228static u_int16_t 229adw_eeprom_read_16(struct adw_softc *adw, int addr) 230{ 231 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr); 232 adw_eeprom_wait(adw); 233 return (adw_inw(adw, ADW_EEP_DATA)); 234} 235 236static void 237adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data) 238{ 239 adw_outw(adw, ADW_EEP_DATA, data); 240 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr); 241 adw_eeprom_wait(adw); 242} 243 244/* 245 * Wait for and EEPROM command to complete 246 */ 247static void 248adw_eeprom_wait(struct adw_softc *adw) 249{ 250 int i; 251 252 for (i = 0; i < ADW_EEP_DELAY_MS; i++) { 253 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0) 254 break; 255 DELAY(1000); 256 } 257 if (i == ADW_EEP_DELAY_MS) 258 panic("%s: Timedout Reading EEPROM", 259 device_get_nameunit(adw->device)); 260} 261 262/* 263 * Read EEPROM configuration into the specified buffer. 264 * 265 * Return a checksum based on the EEPROM configuration read. 266 */ 267u_int16_t 268adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf) 269{ 270 u_int16_t *wbuf; 271 u_int16_t wval; 272 u_int16_t chksum; 273 int eep_addr; 274 275 wbuf = (u_int16_t *)eep_buf; 276 chksum = 0; 277 278 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN; 279 eep_addr < ADW_EEP_DVC_CFG_END; 280 eep_addr++, wbuf++) { 281 wval = adw_eeprom_read_16(adw, eep_addr); 282 chksum += wval; 283 *wbuf = wval; 284 } 285 286 /* checksum field is not counted in the checksum */ 287 *wbuf = adw_eeprom_read_16(adw, eep_addr); 288 wbuf++; 289 290 /* Driver seeprom variables are not included in the checksum */ 291 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN; 292 eep_addr < ADW_EEP_MAX_WORD_ADDR; 293 eep_addr++, wbuf++) 294 *wbuf = adw_eeprom_read_16(adw, eep_addr); 295 296 return (chksum); 297} 298 299void 300adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf) 301{ 302 u_int16_t *wbuf; 303 u_int16_t addr; 304 u_int16_t chksum; 305 306 wbuf = (u_int16_t *)eep_buf; 307 chksum = 0; 308 309 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE); 310 adw_eeprom_wait(adw); 311 312 /* 313 * Write EEPROM until checksum. 314 */ 315 for (addr = ADW_EEP_DVC_CFG_BEGIN; 316 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) { 317 chksum += *wbuf; 318 adw_eeprom_write_16(adw, addr, *wbuf); 319 } 320 321 /* 322 * Write calculated EEPROM checksum 323 */ 324 adw_eeprom_write_16(adw, addr, chksum); 325 326 /* skip over buffer's checksum */ 327 wbuf++; 328 329 /* 330 * Write the rest. 331 */ 332 for (addr = ADW_EEP_DVC_CTL_BEGIN; 333 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++) 334 adw_eeprom_write_16(adw, addr, *wbuf); 335 336 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE); 337 adw_eeprom_wait(adw); 338} 339 340int 341adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1) 342{ 343 u_int8_t biosmem[ADW_MC_BIOSLEN]; 344 const u_int16_t *word_table; 345 const u_int8_t *byte_codes; 346 const u_int8_t *byte_codes_end; 347 u_int bios_sig; 348 u_int bytes_downloaded; 349 u_int addr; 350 u_int end_addr; 351 u_int checksum; 352 u_int scsicfg1; 353 u_int tid; 354 355 /* 356 * Save the RISC memory BIOS region before writing the microcode. 357 * The BIOS may already be loaded and using its RISC LRAM region 358 * so its region must be saved and restored. 359 */ 360 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++) 361 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr); 362 363 /* 364 * Save current per TID negotiated values if the BIOS has been 365 * loaded (BIOS signature is present). These will be used if 366 * we cannot get information from the EEPROM. 367 */ 368 addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM; 369 bios_sig = biosmem[addr] 370 | (biosmem[addr + 1] << 8); 371 if (bios_sig == 0x55AA 372 && (adw->flags & ADW_EEPROM_FAILED) != 0) { 373 u_int major_ver; 374 u_int minor_ver; 375 u_int sdtr_able; 376 377 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM; 378 minor_ver = biosmem[addr + 1] & 0xF; 379 major_ver = (biosmem[addr + 1] >> 4) & 0xF; 380 if ((adw->chip == ADW_CHIP_ASC3550) 381 && (major_ver <= 3 382 || (major_ver == 3 && minor_ver <= 1))) { 383 /* 384 * BIOS 3.1 and earlier location of 385 * 'wdtr_able' variable. 386 */ 387 adw->user_wdtr = 388 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31); 389 } else { 390 adw->user_wdtr = 391 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE); 392 } 393 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE); 394 for (tid = 0; tid < ADW_MAX_TID; tid++) { 395 u_int tid_mask; 396 u_int mc_sdtr; 397 398 tid_mask = 0x1 << tid; 399 if ((sdtr_able & tid_mask) == 0) 400 mc_sdtr = ADW_MC_SDTR_ASYNC; 401 else if ((adw->features & ADW_DT) != 0) 402 mc_sdtr = ADW_MC_SDTR_80; 403 else if ((adw->features & ADW_ULTRA2) != 0) 404 mc_sdtr = ADW_MC_SDTR_40; 405 else 406 mc_sdtr = ADW_MC_SDTR_20; 407 adw_set_user_sdtr(adw, tid, mc_sdtr); 408 } 409 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE); 410 } 411 412 /* 413 * Load the Microcode. 414 * 415 * Assume the following compressed format of the microcode buffer: 416 * 417 * 253 word (506 byte) table indexed by byte code followed 418 * by the following byte codes: 419 * 420 * 1-Byte Code: 421 * 00: Emit word 0 in table. 422 * 01: Emit word 1 in table. 423 * . 424 * FD: Emit word 253 in table. 425 * 426 * Multi-Byte Code: 427 * FD RESEVED 428 * 429 * FE WW WW: (3 byte code) 430 * Word to emit is the next word WW WW. 431 * FF BB WW WW: (4 byte code) 432 * Emit BB count times next word WW WW. 433 * 434 */ 435 bytes_downloaded = 0; 436 word_table = (const u_int16_t *)adw->mcode_data->mcode_buf; 437 byte_codes = (const u_int8_t *)&word_table[253]; 438 byte_codes_end = adw->mcode_data->mcode_buf 439 + adw->mcode_data->mcode_size; 440 adw_outw(adw, ADW_RAM_ADDR, 0); 441 while (byte_codes < byte_codes_end) { 442 if (*byte_codes == 0xFF) { 443 u_int16_t value; 444 445 value = byte_codes[2] 446 | byte_codes[3] << 8; 447 adw_set_multi_2(adw, ADW_RAM_DATA, 448 value, byte_codes[1]); 449 bytes_downloaded += byte_codes[1]; 450 byte_codes += 4; 451 } else if (*byte_codes == 0xFE) { 452 u_int16_t value; 453 454 value = byte_codes[1] 455 | byte_codes[2] << 8; 456 adw_outw(adw, ADW_RAM_DATA, value); 457 bytes_downloaded++; 458 byte_codes += 3; 459 } else { 460 adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]); 461 bytes_downloaded++; 462 byte_codes++; 463 } 464 } 465 /* Convert from words to bytes */ 466 bytes_downloaded *= 2; 467 468 /* 469 * Clear the rest of LRAM. 470 */ 471 for (addr = bytes_downloaded; addr < adw->memsize; addr += 2) 472 adw_outw(adw, ADW_RAM_DATA, 0); 473 474 /* 475 * Verify the microcode checksum. 476 */ 477 checksum = 0; 478 adw_outw(adw, ADW_RAM_ADDR, 0); 479 for (addr = 0; addr < bytes_downloaded; addr += 2) 480 checksum += adw_inw(adw, ADW_RAM_DATA); 481 482 if (checksum != adw->mcode_data->mcode_chksum) { 483 device_printf(adw->device, "Firmware load failed!\n"); 484 return (EIO); 485 } 486 487 /* 488 * Restore the RISC memory BIOS region. 489 */ 490 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++) 491 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]); 492 493 /* 494 * Calculate and write the microcode code checksum to 495 * the microcode code checksum location. 496 */ 497 addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR); 498 end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR); 499 checksum = 0; 500 adw_outw(adw, ADW_RAM_ADDR, addr); 501 for (; addr < end_addr; addr += 2) 502 checksum += adw_inw(adw, ADW_RAM_DATA); 503 adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum); 504 505 /* 506 * Tell the microcode what kind of chip it's running on. 507 */ 508 adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip); 509 510 /* 511 * Leave WDTR and SDTR negotiation disabled until the XPT has 512 * informed us of device capabilities, but do set the desired 513 * user rates in case we receive an SDTR request from the target 514 * before we negotiate. We turn on tagged queuing at the microcode 515 * level for all devices, and modulate this on a per command basis. 516 */ 517 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]); 518 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]); 519 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]); 520 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]); 521 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb); 522 for (tid = 0; tid < ADW_MAX_TID; tid++) { 523 /* Cam limits the maximum number of commands for us */ 524 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid, 525 adw->max_acbs); 526 } 527 adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0); 528 529 /* 530 * Set SCSI_CFG0 Microcode Default Value. 531 * 532 * The microcode will set the SCSI_CFG0 register using this value 533 * after it is started. 534 */ 535 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0, 536 ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG| 537 ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id); 538 539 /* 540 * Tell the MC about the memory size that 541 * was setup by the probe code. 542 */ 543 adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG, 544 adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK); 545 546 /* 547 * Determine SCSI_CFG1 Microcode Default Value. 548 * 549 * The microcode will set the SCSI_CFG1 register using this value 550 * after it is started below. 551 */ 552 scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1); 553 554 /* 555 * If the internal narrow cable is reversed all of the SCSI_CTRL 556 * register signals will be set. Check for and return an error if 557 * this condition is found. 558 */ 559 if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 560 device_printf(adw->device, "Illegal Cable Config!\n"); 561 device_printf(adw->device, "Internal cable is reversed!\n"); 562 return (EIO); 563 } 564 565 /* 566 * If this is a differential board and a single-ended device 567 * is attached to one of the connectors, return an error. 568 */ 569 if ((adw->features & ADW_ULTRA) != 0) { 570 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0 571 && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) { 572 device_printf(adw->device, "A Single Ended Device is " 573 "attached to our differential bus!\n"); 574 return (EIO); 575 } 576 } else { 577 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) { 578 device_printf(adw->device, 579 "A High Voltage Differential Device " 580 "is attached to this controller.\n"); 581 device_printf(adw->device, 582 "HVD devices are not supported.\n"); 583 return (EIO); 584 } 585 } 586 587 /* 588 * Perform automatic termination control if desired. 589 */ 590 if ((adw->features & ADW_ULTRA2) != 0) { 591 u_int cable_det; 592 593 /* 594 * Ultra2 Chips require termination disabled to 595 * detect cable presence. 596 */ 597 adw_outw(adw, ADW_SCSI_CFG1, 598 scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV); 599 cable_det = adw_inw(adw, ADW_SCSI_CFG1); 600 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1); 601 602 /* SE Termination first if auto-term has been specified */ 603 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) { 604 605 /* 606 * For all SE cable configurations, high byte 607 * termination is enabled. 608 */ 609 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H; 610 if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0 611 || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) { 612 /* 613 * If either cable is not present, the 614 * low byte must be terminated as well. 615 */ 616 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L; 617 } 618 } 619 620 /* LVD auto-term */ 621 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0 622 && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) { 623 /* 624 * If both cables are installed, termination 625 * is disabled. Otherwise it is enabled. 626 */ 627 if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0 628 || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) { 629 630 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD; 631 } 632 } 633 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV; 634 } else { 635 /* Ultra Controller Termination */ 636 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) { 637 int cable_count; 638 int wide_cable_count; 639 640 cable_count = 0; 641 wide_cable_count = 0; 642 if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) { 643 cable_count++; 644 wide_cable_count++; 645 } 646 if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0) 647 cable_count++; 648 649 /* There is only one external port */ 650 if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) { 651 cable_count++; 652 wide_cable_count++; 653 } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0) 654 cable_count++; 655 656 if (cable_count == 3) { 657 device_printf(adw->device, 658 "Illegal Cable Config!\n"); 659 device_printf(adw->device, 660 "Only Two Ports may be used at a time!\n"); 661 } else if (cable_count <= 1) { 662 /* 663 * At least two out of three cables missing. 664 * Terminate both bytes. 665 */ 666 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H 667 | ADW_SCSI_CFG1_TERM_CTL_L; 668 } else if (wide_cable_count <= 1) { 669 /* No two 16bit cables present. High on. */ 670 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H; 671 } 672 } 673 } 674 675 /* Tell the user about our decission */ 676 switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) { 677 case ADW_SCSI_CFG1_TERM_CTL_MASK: 678 printf("High & Low SE Term Enabled, "); 679 break; 680 case ADW_SCSI_CFG1_TERM_CTL_H: 681 printf("High SE Termination Enabled, "); 682 break; 683 case ADW_SCSI_CFG1_TERM_CTL_L: 684 printf("Low SE Term Enabled, "); 685 break; 686 default: 687 break; 688 } 689 690 if ((adw->features & ADW_ULTRA2) != 0 691 && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0) 692 printf("LVD Term Enabled, "); 693 694 /* 695 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 696 * set 'scsicfg1'. The TERM_POL bit does not need to be 697 * referenced, because the hardware internally inverts 698 * the Termination High and Low bits if TERM_POL is set. 699 */ 700 if ((adw->features & ADW_ULTRA2) != 0) { 701 term_scsicfg1 = ~term_scsicfg1; 702 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK 703 | ADW2_SCSI_CFG1_TERM_CTL_LVD; 704 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK 705 |ADW2_SCSI_CFG1_TERM_CTL_LVD 706 |ADW_SCSI_CFG1_BIG_ENDIAN 707 |ADW_SCSI_CFG1_TERM_POL 708 |ADW2_SCSI_CFG1_DEV_DETECT); 709 scsicfg1 |= term_scsicfg1; 710 } else { 711 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK; 712 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK; 713 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL; 714 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE; 715 } 716 717 /* 718 * Set SCSI_CFG1 Microcode Default Value 719 * 720 * The microcode will set the SCSI_CFG1 register using this value 721 * after it is started below. 722 */ 723 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1); 724 725 /* 726 * Only accept selections on our initiator target id. 727 * This may change in target mode scenarios... 728 */ 729 adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK, 730 (0x01 << adw->initiator_id)); 731 732 /* 733 * Tell the microcode where it can find our 734 * Initiator Command Queue (ICQ). It is 735 * currently empty hence the "stopper" address. 736 */ 737 adw->commandq = adw->free_carriers; 738 adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba); 739 adw->commandq->next_ba = ADW_CQ_STOPPER; 740 adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba); 741 742 /* 743 * Tell the microcode where it can find our 744 * Initiator Response Queue (IRQ). It too 745 * is currently empty. 746 */ 747 adw->responseq = adw->free_carriers; 748 adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba); 749 adw->responseq->next_ba = ADW_CQ_STOPPER; 750 adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba); 751 752 adw_outb(adw, ADW_INTR_ENABLES, 753 ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR); 754 755 adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR)); 756 757 return (0); 758} 759 760void 761adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr) 762{ 763 adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid); 764 adw->user_sdtr[ADW_TARGET_GROUP(tid)] |= 765 mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid); 766} 767 768u_int 769adw_get_user_sdtr(struct adw_softc *adw, u_int tid) 770{ 771 u_int mc_sdtr; 772 773 mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)]; 774 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid); 775 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid); 776 return (mc_sdtr); 777} 778 779void 780adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr) 781{ 782 u_int mc_sdtr_offset; 783 u_int mc_sdtr; 784 785 mc_sdtr_offset = ADW_MC_SDTR_SPEED1; 786 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2; 787 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset); 788 mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid); 789 mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid); 790 adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr); 791} 792 793u_int 794adw_get_chip_sdtr(struct adw_softc *adw, u_int tid) 795{ 796 u_int mc_sdtr_offset; 797 u_int mc_sdtr; 798 799 mc_sdtr_offset = ADW_MC_SDTR_SPEED1; 800 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2; 801 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset); 802 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid); 803 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid); 804 return (mc_sdtr); 805} 806 807u_int 808adw_find_sdtr(struct adw_softc *adw, u_int period) 809{ 810 int i; 811 812 i = 0; 813 if ((adw->features & ADW_DT) == 0) 814 i = ADW_MC_SDTR_OFFSET_ULTRA2; 815 if ((adw->features & ADW_ULTRA2) == 0) 816 i = ADW_MC_SDTR_OFFSET_ULTRA; 817 if (period == 0) 818 return ADW_MC_SDTR_ASYNC; 819 820 for (; i < adw_num_syncrates; i++) { 821 if (period <= adw_syncrates[i].period) 822 return (adw_syncrates[i].mc_sdtr); 823 } 824 return ADW_MC_SDTR_ASYNC; 825} 826 827u_int 828adw_find_period(struct adw_softc *adw, u_int mc_sdtr) 829{ 830 int i; 831 832 for (i = 0; i < adw_num_syncrates; i++) { 833 if (mc_sdtr == adw_syncrates[i].mc_sdtr) 834 break; 835 } 836 return (adw_syncrates[i].period); 837} 838 839u_int 840adw_hshk_cfg_period_factor(u_int tinfo) 841{ 842 tinfo &= ADW_HSHK_CFG_RATE_MASK; 843 tinfo >>= ADW_HSHK_CFG_RATE_SHIFT; 844 if (tinfo == 0x11) 845 /* 80MHz/DT */ 846 return (9); 847 else if (tinfo == 0x10) 848 /* 40MHz */ 849 return (10); 850 else 851 return (((tinfo * 25) + 50) / 4); 852} 853 854/* 855 * Send an idle command to the chip and wait for completion. 856 */ 857adw_idle_cmd_status_t 858adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter) 859{ 860 u_int timeout; 861 adw_idle_cmd_status_t status; 862 863 if (!dumping) 864 mtx_assert(&adw->lock, MA_OWNED); 865 866 /* 867 * Clear the idle command status which is set by the microcode 868 * to a non-zero value to indicate when the command is completed. 869 */ 870 adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0); 871 872 /* 873 * Write the idle command value after the idle command parameter 874 * has been written to avoid a race condition. If the order is not 875 * followed, the microcode may process the idle command before the 876 * parameters have been written to LRAM. 877 */ 878 adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter); 879 adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd); 880 881 /* 882 * Tickle the RISC to tell it to process the idle command. 883 */ 884 adw_tickle_risc(adw, ADW_TICKLE_B); 885 886 /* Wait for up to 10 seconds for the command to complete */ 887 timeout = 5000000; 888 while (--timeout) { 889 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS); 890 if (status != 0) 891 break; 892 DELAY(20); 893 } 894 895 if (timeout == 0) 896 panic("%s: Idle Command Timed Out!", 897 device_get_nameunit(adw->device)); 898 return (status); 899} 900